Microprocessor

(for Embedded Systems)

06. GPIO Management
Huỳnh Việt Thắng
Faculty of Electronic & Telecommunication Engineering
Danang University of Science and Technology
[email protected]
<Danang, Feb 2019>
 Course contents
• Introduction
• Number systems and data formats (review)
• Microcomputer organization
• Introduction to ARM based processors
• Introduction to STM32 MCUs
• Interfacing with STM32 MCU
peripherals
– GPIO Management
• Applications
 Main reference
1. Carmine Noviello, Mastering STM32, 2018
2. RM0383 Reference manualSTM32F411xC/E
advanced Arm®-based 32-bit MCUs
3. Datasheet STM32F411xC STM32F411xE
4. STM32F411VE Website:
https://www.st.com/content/st_com/en/products/microcontrollers/st
m32-32-bit-arm-cortex-mcus/stm32-high-performance-
mcus/stm32f4-series/stm32f411/stm32f411ve.html
 Lecture Outline
• STM32 Peripherals Mapping
• GPIO main features and functional description
• GPIO configuration
• Driving a GPIO
• De-initialize a GPIO
 Memory and Bus Architecture
(open the STM32F411 reference manual and STM32F411 datasheet)
In STM32F411xC/E, the main system consists of 32-bit multilayer AHB
bus matrix that interconnects:
• Six masters:
– Cortex®-M4 with FPU core I-bus, D-bus and S-bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus

• Five slaves:
– Internal Flash memory ICode bus
– Internal Flash memory DCode bus
– Main internal SRAM
– AHB1 peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals

The bus matrix provides access from a master to a slave, enabling

concurrent access and efficient operation even when several high-
speed peripherals work simultaneously.
This architecture is shown in Figure 1 (see next slide).
 Memory and Bus Architecture
Ref: STM32F411 reference manual
 STM32F411 Memory Map
Ref: STM32F411 datasheet
(Section 5. Memory Mapping)
 STM32F411 Memory Map
Ref: STM32F411 reference manual
 GPIO main features (1)
• Up to 16 I/Os under control (tối đa 16 chân I/O mỗi cổng)

• Output states: push-pull or open drain + pull-up/down

• Output data from output data register (GPIOx_ODR) or

peripheral (alternate function output)

• Speed selection for each I/O

• Input states: floating, pull-up/down, analog

• Input data to input data register (GPIOx_IDR) or

peripheral (alternate function input)
 GPIO main features (2)
• Bit set and reset register (GPIOx_BSRR) for bitwise
write access to GPIOx_ODR

• Locking mechanism (GPIOx_LCKR) provided to freeze

the I/O configuration Analog function

• Alternate Function input/output selection registers (at

most 16 AFs per I/O)

• Fast toggle capable of changing every two clock cycles

• Highly flexible pin multiplexing allows the use of I/O pins

as GPIOs or as one of several peripheral functions
 GPIO functional description
Subject to the specific hardware characteristics of each I/O port listed in the
datasheet, each port bit of the general-purpose I/O (GPIO) ports can be
individually configured by software in several modes:
• Input floating (ngõ vào thả nổi)
• Input pull-up (ngõ vào kéo lên)
• Input-pull-down (ngõ vào kéo xuống)
• Analog (ngõ vào tín hiệu tương tự)
• Output open-drain with pull-up or pull-down capability (ngõ ra cực máng hở
với điện trở kéo lên hoặc kéo xuống)
• Output push-pull with pull-up or pull-down capability (ngõ ra đẩy-kéo với
điện trở kéo lên hoặc kéo xuống)
• Alternate function push-pull with pull-up or pull-down capability
• Alternate function open-drain with pull-up or pull-down capability
 HAL_GPIO handlers
• HAL = Hardware Abstraction Layer
• Every time we need to configure a peripheral that uses MCU pins,
we need to configure its corresponding GPIOs using the HAL_GPIO
module.
• The HAL is designed so that it abstracts from the specific peripheral
memory mapping. But, it also provides a general and more user-
friendly way to configure the peripheral, without forcing the
programmers to now how to configure its registers in detail.
 GPIO_TypeDef Struct
• GPIO_TypeDef Struct
GPIO_InitTypeDef Struct
Pin mode
 GPIO registers (các thanh ghi liên quan GPIO)
• I/O port control registers (các thanh ghi điều khiển)
– Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os.
– The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog).
– The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type
(push-pull or open-drain) and speed (the I/O speed pins are directly connected to the
corresponding GPIOx_OSPEEDR register bits whatever the I/O direction).
– The GPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O
direction.

• I/O port data registers (các thanh ghi dữ liệu)

– Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.

• I/O data bitwise handling

– The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
GPIO register map

Ref: STM32F411 reference manual

(page 163)
 Basic structure of an I/O port pin

Note: this is a 5 V tolerant I/O port bit

 GPIO port pin mode (1)
• GPIO_MODE_INPUT
– The output buffer is disabled.
– The Schmitt trigger input is activated.
– The pull-up and pull-down resistors are activated depending on the value of the Pull field.
– Data present on the I/O pin are sampled into the input data register every AHB clock cycle.
– A read access to the input data register provides the I/O state.
 GPIO port pin mode (2)
• GPIO_MODE_ANALOG
– The output buffer is disabled.
– The Schmitt trigger input is deactivated, providing zero consumption for every analog value
of the I/O pin.
– The weak pull-up and pull-down resistors are disabled by hardware.
– Read access to the input data register gets the value 0.
 GPIO port pin mode (3)
• GPIO_MODE_OUTPUT
– The output buffer is enabled as follow:
• if mode is GPIO_MODE_OUTPUT_OD: A 0 in the Output register (ODR)
activates the N-MOS whereas a 1 leaves the port in Hi-Z (the P-MOS is
never activated);
• if mode is GPIO_MODE_OUTPUT_PP: A 0 in the ODR activates the N-MOS
whereas a 1 activates the P-MOS.
– The Schmitt trigger input is activated.
– The pull-up and pull-down resistors are activated depending on the
value of the Pull field.
– The data present on the I/O pin are sampled into the input data register
every AHB clock cycle.
– A read access to the input data register gets the I/O state.
– A read access to the output data register gets the last written value.
 GPIO port pin mode (4)
• GPIO_MODE_AF (Alternative Function)
– The output buffer is enabled as follow:
• if mode is GPIO_MODE_OUTPUT_OD: A 0 in the Output register (ODR)
activates the N-MOS whereas a 1 leaves the port in Hi-Z (the P-MOS is
never activated);
• if mode is GPIO_MODE_OUTPUT_PP: A 0 in the ODR activates the N-MOS
whereas a 1 activates the P-MOS.
– The Schmitt trigger input is activated.
– The pull-up and pull-down resistors are activated depending on the
value of the Pull field.
– The data present on the I/O pin are sampled into the input data register
every AHB clock cycle.
– A read access to the input data register gets the I/O state.
– A read access to the output data register gets the last written value.
 GPIO port pin mode (5)
• The GPIO modes GPIO_MODE_EVT_* are related to sleep modes. When
an I/O is configured to work in one of these modes, the CPU will be woken
up (when placed in sleep mode with a WFE instruction) if the corresponding
I/O is triggered, without generating the corresponding interrupt
• The GPIO modes GPIO_MODE_IT_* modes are related to interrupts
management
 HAL Handlers for Driving a GPIO
• GPIO ports clock enable
__HAL_RCC_GPIOx_CLK_ENABLE();
• Initialize a GPIO
HAL_GPIO_Init (GPIOx, &GPIO_InitStruct)
• Read status of an I/O
HAL_GPIO_ReadPin (GPIOx, GPIO_Pin)
• Write an I/O
HAL_GPIO_WritePin (GPIOx, GPIO_Pin, PinState)
• Invert I/O state
HAL_GPIO_TogglePin (GPIOx, GPIO_Pin)
• Lock configuration
HAL_GPIO_LockPin (GPIOx, GPIO_Pin)
• De-initialize a GPIO
HAL_GPIO_DeInit (GPIOx, GPIO_Pin)
**Note: GPIOx is in {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOH}
 Examples on STM32F411 EDiscovery board (1)
• Example 1: LED Blinking
• Link video: https://dutudn-
my.sharepoint.com/:v:/g/personal/thanghv_dut_u
dn_vn/EZ55Uz-
tBC5FrXjufsT7kqkBjGx14x7_PLTLCDP7lJ5weg
?e=U3yNiF
 Examples on STM32F411 EDiscovery board (2)
• Example 2: Read user push-button (Blue button) state
and change the way of LED Blinking
CubeMX Clock Configuration
Summary