Chapter 2
Chapter 2
Logic Gates
Aziz Qaroush
Basic Definitions
Boolean Algebra defined with a set of elements, a set of
operators and a number of axioms ( )البديهياتor postulates
()المسلمات.
A set if a collection of objects having a common property
Elements
x is an element of set S
x y x.y x y x+y x x’
0 0 0 0 0 0
0 1
0 1 0 0 1 1
1 0 0 1 0 1 1 0
1 1 1 1 1 1
Two-valued Boolean Algebra
but
thus
and
x y xy x+xy
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1
DeMorgan's Theorem
(𝑥 + 𝑦)′ = 𝑥′ 𝑦′ Can be verified
(𝑥 𝑦)′ = 𝑥′ + 𝑦′ Using a Truth Table
Example 1
Example 2
Example 3
Example 5
Answer: 𝑓′ = (𝑥 + 𝑦 ′ + 𝑧)(𝑥 ′ + 𝑦 + 𝑧)
= 𝒙′ + 𝒚𝒛′ + 𝒚′ 𝒛
Complement of a function
Find the complement of the following functions by taking
their duals and complementing each literal
The dual
Complement each literal
The dual
Combinational
𝑛 inputs 𝑚 outputs
Circuit
Example of a Simple Combinational Circuit
𝑥
𝑦 𝑓
Truth Table
x y z f
0 0 0 0
What is the logic expression of 𝑓?
0 0 1 0
0 1 0 1
0 1 1 1 What is the gate implementation of 𝑓?
1 0 0 0
1 0 1 1 To answer these questions, we need
1 1 0 0
to define Minterms and Maxterms
1 1 1 1
Minterms and Maxterms
Minterms are AND terms with every variable present in either
true or complement form
Maxterms are OR terms with every variable present in either
true or complement form
Minterms and Maxterms for 2 variables 𝑥 and 𝑦
x y index Minterm Maxterm
0 0 0 𝑚0 = 𝑥′𝑦′ 𝑀0 = 𝑥 + 𝑦
0 1 1 𝑚1 = 𝑥′𝑦 𝑀1 = 𝑥 + 𝑦′
1 0 2 𝑚2 = 𝑥𝑦′ 𝑀2 = 𝑥′ + 𝑦
1 1 3 𝑚3 = 𝑥𝑦 𝑀3 = 𝑥′ + 𝑦′
For Minterms:
‘1’ means the variable is Not Complemented
For Maxterms:
‘0’ means the variable is Not Complemented
𝑓 = 𝑥 ′ 𝑦𝑧 ′ + 𝑥 ′ 𝑦𝑧 + 𝑥𝑦 ′ 𝑧 + 𝑥𝑦𝑧
Examples of Sum-Of-Minterms
𝑓 𝑎, 𝑏, 𝑐, 𝑑 = 𝑚2 + 𝑚3 + 𝑚6 + 𝑚10 + 𝑚11
𝑔 𝑎, 𝑏, 𝑐, 𝑑 = 𝑚0 + 𝑚1 + 𝑚12 + 𝑚15
𝑓(𝑎, 𝑏, 𝑐, 𝑑) = 𝑀1 ∙ 𝑀3 ∙ 𝑀11
𝑓(𝑎, 𝑏, 𝑐, 𝑑) = 𝑎 + 𝑏 + 𝑐 + 𝑑′ 𝑎 + 𝑏 + 𝑐 ′ + 𝑑′ (𝑎′ + 𝑏 + 𝑐 ′ + 𝑑 ′ )
𝑔 𝑎, 𝑏, 𝑐, 𝑑 = ς(0, 5, 13)
𝑔(𝑎, 𝑏, 𝑐, 𝑑) = 𝑀0 ∙ 𝑀5 ∙ 𝑀13
𝑓(𝑎, 𝑏, 𝑐, 𝑑) = 𝑎 + 𝑏 + 𝑐 + 𝑑 𝑎 + 𝑏 ′ + 𝑐 + 𝑑 ′ (𝑎′ + 𝑏′ + 𝑐 + 𝑑′ )
Conversions between Canonical Forms
The same Boolean function 𝑓 can be expressed in two ways:
Sum-of-Minterms 𝑓 = 𝑚0 + 𝑚2 + 𝑚3 + 𝑚5 + 𝑚7 = σ(0, 2, 3, 5, 7)
Product-of-Maxterms 𝑓 = 𝑀1 ∙ 𝑀4 ∙ 𝑀6 = ς(1, 4, 6)
Truth Table
x y z f Minterms Maxterms
0 0 0 1 𝑚0 = 𝑥 ′ 𝑦′𝑧′
0 0 1 0 𝑀1 = 𝑥 + 𝑦 + 𝑧′ To convert from one canonical
0 1 0 1 𝑚2 = 𝑥 ′ 𝑦𝑧′ form to another, interchange
0 1 1 1 𝑚3 = 𝑥 ′ 𝑦𝑧
the symbols and and list
1 0 0 0 𝑀4 = 𝑥′ + 𝑦 + 𝑧
those numbers missing from
1 0 1 1 𝑚5 = 𝑥𝑦′𝑧
1 1 0 0 𝑀6 = 𝑥′ + 𝑦′ + 𝑧 the original form.
1 1 1 1 𝑚7 = 𝑥𝑦𝑧
Function Complement
Truth Table Given a Boolean function 𝑓
For a Boolean function, given the list of Minterm indices one can
determine the list of Maxterms indices (and vice versa)
F BC AB AC
Standard Forms
48
BC ( A A)
AC ( B B )
F AC ( B B) AB(C C ) BC ( A A)
F AC AB BC
F ( A C )( A B)( B C )
Two-Level Gate Implementation
𝑓1 = 𝑥𝑦′ + 𝑥𝑧 𝑓2 = 𝑦 + 𝑥𝑦′𝑧
𝑥 𝑦
𝑦′
𝑓1 𝑓2
𝑥
𝑥 𝑦′
𝑧 AND-OR 𝑧 3-input AND gate
implementations
𝑓3 = (𝑥 + 𝑧)(𝑥 ′ + 𝑦 ′ ) 𝑓4 = 𝑥(𝑥 ′ + 𝑦 ′ + 𝑧)
𝑥 𝑥
𝑧
𝑓3 𝑓4
𝑥′
𝑥′ 𝑦′
𝑦′ OR-AND 𝑧 3-input OR gate
implementations
Two-Level vs. Three-Level Implementation
ℎ = 𝑎𝑏 + 𝑐𝑑 + 𝑐𝑒 (6 literals) is a sum-of-products
ℎ may also be written as: ℎ = 𝑎𝑏 + 𝑐(𝑑 + 𝑒) (5 literals)
However, ℎ = 𝑎𝑏 + 𝑐(𝑑 + 𝑒) is a non-standard form
ℎ = 𝑎𝑏 + 𝑐(𝑑 + 𝑒) is not a sum-of-products nor a product-of-sums
𝑥 𝑥
𝑥·𝑦 𝑥+𝑦 𝑥 𝑥′
𝑦 𝑦
AND gate OR gate NOT gate (inverter)
𝑥 ′ 𝑥
𝑥·𝑦 (𝑥 + 𝑦)′ 𝑥 𝑥
𝑦 𝑦
NAND gate NOR gate Buffer
𝑐
𝑥 𝑥
𝑥⊕𝑦 (𝑥 ⊕ 𝑦)′ 𝑥 𝑓
𝑦 𝑦
XOR gate XNOR gate 3-state gate
NAND Gate
The NAND gate has the following symbol and truth table
NAND represents NOT AND
The small bubble circle represents the invert function
𝑥 x y NAND
𝑥·𝑦 ′ = 𝑥′ + 𝑦′
𝑦 0 0 1
NAND gate 𝑥 0 1 1
𝑥′ + 𝑦′
𝑦 1 0 1
Another symbol for NAND 1 1 0
𝑥 x y NOR
𝑥+𝑦 ′ = 𝑥′ · 𝑦′
𝑦 0 0 1
NOR gate 𝑥 0 1 0
𝑥′ · 𝑦′
𝑦 1 0 0
Another symbol for NOR 1 1 0
′ ′ ′
𝑥 NOR (𝑦 NOR 𝑧) = 𝑥 + 𝑦 + 𝑧 = 𝑥 + 𝑦′𝑧′ = 𝑥′(𝑦 + 𝑧)
Extension to multiple inputs
Demonstrating the nonassociativity of the NOR operator: x y z x y z
Multiple-Input NAND / NOR Gates
NAND/NOR gates can have multiple inputs, similar to AND/OR gates
𝑥 𝑤
𝑥 𝑦 ′ 𝑥 𝑤·𝑥·𝑦·𝑧 ′
𝑥·𝑦 ′ 𝑥·𝑦·𝑧 𝑦
𝑦 𝑧 𝑧
2-input NAND gate 3-input NAND gate 4-input NAND gate
𝑥 𝑤
𝑥 𝑦 ′ 𝑥 𝑤+𝑥+𝑦+𝑧 ′
𝑥+𝑦 ′ 𝑥+𝑦+𝑧 𝑦
𝑦 𝑧 𝑧
2-input NOR gate 3-input NOR gate 4-input NOR gate
Note: a 3-input NAND is a single gate, NOT a combination of two 2-input gates.
The same can be said about other multiple-input NAND/NOR gates.
Extension to multiple inputs
Multiple‐input and cascaded NOR and NAND gates
Exclusive OR / Exclusive NOR
Exclusive OR (XOR) is an important Boolean operation used
extensively in logic circuits
x y XOR x y XNOR
0 0 0 0 0 1
0 1 1 0 1 0 XNOR is also known
1 0 1 1 0 0 as equivalence
1 1 0 1 1 1
𝑥 𝑥
𝑥⨁𝑦 (𝑥 ⨁ 𝑦)′
𝑦 𝑦
XOR gate XNOR gate
XOR / XNOR Functions
The XOR function is: 𝑥 ⨁ 𝑦 = 𝑥𝑦′ + 𝑥′𝑦
The XNOR function is: (𝑥 ⨁ 𝑦)′ = 𝑥𝑦 + 𝑥′𝑦′
XOR and XNOR gates are complex
Can be implemented as a true gate, or by
Interconnecting other gate types
XOR and XNOR gates do not exist for more than two inputs
For 3 inputs, use two XOR gates
The cost of a 3-input XOR gate is greater than the cost of two XOR gates