Lab Manual

EE-227L
Computer Organization and
Architecture Lab

Department of Electrical Engineering

School of Engineering
University of Management and Technology
CII, Johar Town Lahore
http:/www.umt.edu.pk
 University of Management & Technology

School of Engineering

Department of Electrical Engineering

EE227L Computer Organization & Architecture Lab

List Of Experiments

Week Experiments

1 Getting Familiar with PCSpim/QtSpim

2 Converting Higher Level Language to Lower Level Language

3 Learning the Use of System Calls

4 Getting familiar with Variables , Frame pointers & Recursion

5 MIPS Linking

6 Introduction to Basic Syntax of Verilog and Gate-level-Modeling Using Xilinx ISE tools

7 Simulation of Full and 4-Bit Ripple Carry Adder in Gate Level Abstraction

8 Introduction to Data Flow Level Programming in Verilog

9 Implementation of Different types of Adders in Data Flow Modeling

10 Implementation of Various Combinational Circuits on Verilog at behavioral level

11 Simple Arithmetic Logic Unit using Xilinx ISE tools

12 Complex Arithmetic Logic Unit using Xilinx ISE tools

13 To Understand the codes of Data Memory, Instruction Memory, Register file, ALU and
Address Generator of The Single Cycle MIPS Machine

14 Complete Data path and Control of The Single Cycle MIPS Machine

15 Verification of the Single Cycle MIPS Machine

Computer Organization And Architecture LAB 1

Roll #:_____________________________

Getting Familiar with PCSpim

1.1 Introduction
PCSpim is a personal computer simulator for MIPS. It helps in learning the
language without having to buy a MIPS-based computer. It also provides
debugging features such as setting breakpoints, executing instructions in steps
and viewing register and memory contents during the execution of the
program. PCSpim does not come with an editor or a word processor, so, we
shall be using Notepad for writing the programs.

1.2 PCSpim Message Window

A snapshot of the PCSpim messages window is shown below:

This window is called the registers window. It contains information about the
Program Counter (PC) and General, Single and Double Floating Point Registers.
Each of these is thirty-two in number.

This window displays the contents of the text segment. Recall that the text
segment is the portion of the memory that contains the instructions to be executed.
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The first column contains the address of the instruction. The second one is the
instruction expressed in Hex form (a topic for next class on Monday); the third is
the actual machine language instruction to be executed while the last contains the
original instruction.

This window displays the contents of the data segment. Data segment
reserves the space for declarations (int, char etc)) that you do while writing the
program. It also shows the contents of the stack.

This window shows the messages generated by PCSpim.

1.3 EXAMPLE # 1
Open Notepad and type in the following code: (Note that .data portion is optional
and not needed here)
Note that it is case sensitive, all program in lower case except labels.

main:
addi $s0, $zero, 100
addi $s1, $zero, 200
addi $s2, $zero, -300

add $t0, $s0, $s1

sub $t1, $s1, $s2
add $t2, $t0, $t1
or $t3, $s0, $s1
xor $t4, $s0, $s2
slt $t5, $s0, $s1
slti $t6, $s2, -400
Save this code as “FirstProgram.s” in your Z drive. Do not forget to use inverted
commas to preserve extension.

1.3.1 Running the Simulator

Load PCSpim by clicking its icon present on the desktop. Pull down the File menu
and select Open. Open the file FirstProgram from where you have saved it earlier.

To run the program in single steps press F10 for each instruction. Keep pressing
F10 till you reach the instruction at address 0x00400024 (shown on left side in test
window). This is where you program starts and here you will be able to see your
program in widow as mentioned above. These instruction corresponds to the
instructions of your program. All the instructions before this address are added by
PCSPIM.

Note that at this point notice that all register contain 0000 0000 (they are displayed
in HEX by default.)

1.3.2 Viewing the registers in Hex/Decimal Form

To view register values in decimal, select Settings in Simulator menu and uncheck
View General Registers in Hex.
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Computer Organization And Architecture LAB 1
Single step your program using F10 and fill the following table from register
window. You can also use window’s calculator as needed, but be informed that
Windows built-in calculator is 64-bit and our PCSPIM is 32-bit.
What is the value of $s0 after executing the first statement? ____________, Hex,
______________
What is the value of $s1 after executing the second statement? __________, Hex:
_______________
What is the value of $s2 after executing the third statement? ____________,
Hex:__________________
What is the value of $t0 after executing the fourth statement? ____________,
Hex:__________________
What is the value of $t1 after executing the fifth statement? ______________,
Hex:__________________
What is the value of $t2 after executing the sixth statement? _______________,
Hex:___________________
What is the value of $t3 after executing the 7th statement? ______________,
Hex:__________________
What is the value of $t4 after executing the 8th statement? _______________,
Hex:___________________
What is the value of $t5 after executing the 9th statement? ______________,
Hex:__________________
What is the value of $t6 after executing the 10th statement? _______________,
Hex:___________________

You shall be required to provide all the answers in hex form. However, you should
view registers in decimal form to confirm your answers. For $t3, $t4, do the
calculations in 32-bit binary (by directly converting hex values of s0 and s1
given above) on the back of this page to verify your answer.

1.4 Exercise # 1: Summing the First Ten Integers using Control Instruction
The following code sums the first ten positive integers. Figure out the missing parts
and run the program.

main:
addi $s0, $zero, 10 #counter
addi $t0, $zero, 0 #sum/accumulator initialized to 0
loop1: # fill missing values
add ______, ______, ______
addi ______, ______, -1
bnez ______, ______
nop
nop

After executing the last instruction in the loop and before executing the nop (No
Operation) instruction, what is the value of $t0? _______. Show the program to
your Teacher _______

1.5 More Logical Operations

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1.5.1 Shift Operations
srl and sll shift the number by specified number of bits. Recall that shifting
a number in binary is equivalent to multiplying or dividing the number with powers
of 2, e.g.
sll $t1, $t1, 4 multiplies the number in the register $t1 by 16.
srl $t1, $t1, 4 divides the number in the register $t1 by 16.

1.5.2 Bit Wise operation (Masking)

and, or, andi, and ori are bitwise operations available in MIPS.
Masking can be used to extract bits from a given number, e.g.
Andi $t1, $t0, 32 extracts the 6th bit from $t0 and saves it in $t1. All other bits
become zero.
Andi $t1, $t0, 7 extracts the last (least significant) three bits from $t0 and saves
them in $t1.

1.5.2.1 Exercise # 1
Write a program to load the value 223 in $t0 register. Shift it left by 5, then shift it
right by 7 and then shift it left by 2.
Show your program to Teacher: _____________ Run the program.
What is the Hex value of 223 load in $t0:___________
What is value of $t0 after it is shifted left by 5? ___________. Why?
___________________
What is value of $t0 after it is shifted right by 7? ___________.
Why?__________________
What is value of $t0 after it is shifted left by 2? ___________. Why?
____________________
Is the final result different from 223: Why?
__________________________________________

1.5.2.2 Exercise # 2
Write a program to load 220 in $s0. Mask $s0 using and operation to obtain least
significant five bits of $s0 and store them in $s1. Find the sum of 8*$s1 and $s1/8
using shift operations. Show your program to Teacher. _____________
What is the sum? _________

1.5.2.3 Exercise # 3
Recall that immediate field in addi can hold 16 bits. We learned how to load a 32-
bit value in a register. Let us try that.
Remember the method is: 1. Load upper (most significant) 16 bits in a register. 2.
Shift it left by 16 places. 3. Add lower (least significant) 16 bits.

Using the abovementioned method, load the value 0x12345678 in $t0. You can
load hex values using 0x notation,
e.g. addi $t0, $zero, 0x1234. Show your code to the Teacher _______.

1.5: Learning to Use the Assembler Directives

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Assembler directives give a programmer the ability to establish some initial data
structures that will be accessed by the computer at “run time”. Some directives
we have learned in the class are:
.data All the items following this directive are stored in the data segment.
.globl main Declare that the label main is global so it can be referenced by operating
system.
.text All the items following this directive are stored in the text segment or the code of the
program.
.word w1,…,wn Store the n 32-bit quantities in successive memory words.

1.5.1: Summing the Elements of an Array

Write a program that sums the integers in an array of 10 and then saves the result in data
segment. Starting code is given below:

.data
myData: .word 2, 12, -5, 7, 4, -2, 3, -7, 89, 4
sum: .word 0 # this will contain the sum
.globl main
.text
main:
la $s0, myData #load address of myData
add $t2, $zero, $zero #initialize to save the sum
<Write you code here to do sum of myData array. Do not use any branch instruction but
hard code for each element.

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Computer Organization And Architecture LAB 1
la $s0, sum
sw $t2, 0($s0)

You need to show the program and its working to the Teacher. What is value of sum:
_______
What is the address of first element of array in data segment: _______________. Check this
after you run first instruction of the program that $s0 is indeed loaded with that correct
address using special assembler generated instruction. We will not discuss la (load
address instruction) any further.
What address is loaded for sum _____________ and why ___________________. (How can you
calculate this address)
What value is stored at the address of sum __________ (see data memory to answer this,
before and after stepping through the last instruction)

1.5.2: Finding the Sum Using Branch Instruction

Repeat exercise 5 but this time using branch instruction and for 15 values

.data
myData: .word 200, -1299, -5000, 7123, 4, -2, 3, -7, 89, 4, -1000, 11, 0, 14, -1
sum: .word 0 # this will contain the sum
.globl main
.text
main:
la $s0, myData #load address of myData
li $t1, 9 #counter , you may initialize to 10 not 9
add $t2, $zero, $zero #initialize to save the sum
loop:
<Write you code here to do sum of myData array using beq or bneq instruction>

exit:
la $s0, sum

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sw $t2, 0($s0)

Show the program and its working to the Teacher.

Write values in data memory AFTER the sum is stored.

0x10010000: _____________
0x10010004: _____________0x10010008: _____________
0x1001000C: _____________

0x10010010:_____________
0x10010014:_____________0x10010018:_____________
0x1001001C:_____________

0x10010020:_____________
0x10010024:_____________0x10010028:_____________
0x1001002C:_____________

0x10010030:_____________
0x10010034:_____________0x10010038:_____________
0x1001003C:_____________

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Observations/Comments/Explanation of Results

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Computer Organization And Architecture LAB 1

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Computer Organization And Architecture LAB 2
Roll #:_____________________________

Converting Higher Level Language to Lower Level Language

Following is the last exercise from the last lab. It finds sum of 10 numbers stored in an array
myData[10]. Remember index goes from 0 to 9 in C.

.data

myData: .word 200, -1299, -5000, 7123, 4, -2, 3, -7, 89, 4

sum: .word 0 # place to hold the final sum

.globl main

.text

main:

la $s0, myData #load address of myData (pointer to array)

la $s1, sum #load address of sum, (pointer to sum)

li $t1, 10 #counter initialized to 10

add $t2, $zero, $zero #initialize to zero to save the sum, t2

assigned to sum

loop:

lw $t3, 0($s0) #load a number from array

add $t2,$t2,$t3 # add array element to sum.

sw $t2, 0($s1) # store the sum, could’ve stored once outside the loop

addi $s0, $s0, 4 # increment the base address

addi $t1,$t1, -1 #decrement counter

bne $t1, $t0, loop

exit:

nop #end of program

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Computer Organization And Architecture LAB 2
nop

nop

Type and run this program and show its working to the Teacher.

Exercise 2.

Write equivalent C code for the code above.

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Computer Organization And Architecture LAB 2
Exercise 3. We have seen the C code and Assembly code. Now let us create a processor
picture for the above code.

Fill the missing boxes (*) in the following Memory Map and write values in SUM data
memory AFTER the sum is stored.

You can watch how sum changes in each loop iteration.

Memory 32-bit HEX Assembled Code/ Your Assembly Comments

Address Instruction oror data value in dec Instruction

data

[0x7fffeffc] 0x00000000 Stack area.

●●●

●●●

●●●

[0x1001002c]

[0x10010028] * * Place to store SUM

Confirm the result

[0x10010024] * *

[0x10010020] * *

[0x1001001c] * *

[0x10010018] * *

[0x10010014] * *

[0x10010010] 0x00000004 *

[0x1001000c] 0x00001bd3 *

[0x10010008] 0xffffec78 *

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Computer Organization And Architecture LAB 2
[0x10010004] 0xfffffaed -1299 Use calculator to confirm
that

this 32-bit number is -

1299

[0x10010000] 0x000000c8 200 myData[0] base address

Data Starts here

●●●

●●●

●●●

[0x00400054] 0x00000000 Nop Nop

[0x00400050] 0x00000000 Nop Nop Code ends here

[0x0040004c] * * * ***
[0x00400048] * * *
[0x00400044] * * * **
[0x00400040] * * *
[0x0040003c] * * * **
[0x00400038] * * *
[0x00400034] 0x00005020 add $10, $0, $0 add $t2, $zero, $zero **

[0x00400030] 0x3409000a ori $9, $0, 10 li $t1, 10

[0x0040002c] 0x3431003c ori $17, $1, 60[sum] Here confirm that $s0 and

$s1 has the address of

[0x00400028] 0x3c011001 lui $1, 4097 [sum] la $s1, sum myData

And sum respectively

[0x00400024] 0x3c101001 lui $16, 4097 [myData]la $s0, myData Your program code starts
here

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Computer Organization And Architecture LAB 2
** On back of the page use 32-bit hex code to prove that this the right instruction in
assembly.

*** This is branch instruction. What the branch offset ____________________,

Why____________________

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Computer Organization And Architecture LAB 2

Observations/Comments/Explanation of Results

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Computer Organization And Architecture LAB 2

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Computer Organization And Architecture LAB 3

Roll #:_____________________________

Learning the Use of System Calls

System call is used to communicate with the system for reading from
keyboard or writing to screen. System call require some parameter to be
passed in a particular register and a request number (or service code) to be
passed in another register $v0.

STEPS FOR USING SYSTEM CALLS

1. Load system call code into Register $v0. Codes (Value of $V0 to be
loaded) are given in the table below.
2. Load arguments (if any) into registers $a0, $a1
3. use syscall
4. Results are returned in registers $v0.

Exercise 0: Printing your name using SYSCALL.

Use the following code to print your name in an output screen.

.data

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Computer Organization And Architecture LAB 3
mesg1: .asciiz “My Name is ………. \n“

.text

.globl main

main:

li $v0, 4 # Load immediate vi with value 4

la $a0, mesg1 # a0 points to base address of string array mesg1

syscall

li $v0, 10 # prepare to exit

syscall

Using table above explain:

1. What does the first SYSCALL do?__________________________

2. What is contained by $a0_________________________________

3. What is purpose of second SYSCALL _________________

4. Modify the above program to print an integer, say 1234.

a. What should be the value of a0 before you make a syscall __________

b. What should be the value of v0 before you make a syscall __________

Exercise 1: Sum of Integers

Type the code given on the last page to find the sum of N integers and run for N =
100, N= 200, N= 1000.

What is the answer in each case?

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Computer Organization And Architecture LAB 3
___________, _______________, _______________, _____________

For what value of N we get a wrong answer and why? ________________

Change the first instruction after label Loop to (add unsigned):

addu $t0, $t0, $v0

Now for what value of N you start getting wrong answers, can you explain the wrong
answer.

Do you get exceptions this time____, why not?__________

What happens if you give a very large N, say 100000. Can you explain the answer
now _____________.

EXERCISE 2: Using JAL instruction

Let say we have the following function that returns 0 if the value passed is greater
than 255, 0 otherwise. Convert the following C program to MIPS assembly.

int check255(int x)

int result;

if (x > 255) {

result = 0;

else {

result = 1;

return result;

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Computer Organization And Architecture LAB 3
Here is a template for the program that uses check255 function. The template
shows how to call a function. In addition, it shows how to read from the keyboard
and write answer to the screen using SPIM system calls.

# Using a function in main

.text

.globl main

main:

# get input

addi $v0, $zero, 5 # Use system call 5 (read integer)

syscall # Invoke system call (int is returned in $v0)

add $a0, $zero, $v0 # put int into $a0, the argument register for

parameter passing

jal check255 # call check255

# print output

add $a0, $zero, $v0 # put return value into $a0

addi $v0, $zero, 1 # Use system call 1 (print integer)

syscall # Invoke system call

addi $v0, $zero, 10 # Use system call 10 (exit)

syscall # Invoke system call

check255:

# put your code here function check255

# make sure the return value is in $v0

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Computer Organization And Architecture LAB 3

jr $ra # go back to main

What is value stored in $ra when jal check255 is executed ________, Why
________________

Finding Sum of Positive and Negative Numbers

.data

array: .word -5, 4, -10, -22, 20, 12

msg1: .asciiz “\n The sum of the positive numbers is = “

msg2: .asciiz “\n The sum of the negative numbers is = “

.globl main

.text

main:

li $v0, 4 # system call to print a string

la $a0, msg1 # a0 has address of message 1

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Computer Organization And Architecture LAB 3
syscall

la $a0, array # a0 has base address of array

li $a1, 6 # load immediate ,a1 = 6,total data size is 6

jal sum # call sum function.On return v0 will have some of pos nos

move $a0, $v0 # a0 has integer to be printed (sum of pos numbers)

li $v0, 1 # System call for printing a integer

syscall

li $v0, 4 # system call to print a string

la $a0, msg2 # a0 has address of message 2

syscall

move $a0, $v1 # a0 has sum of negative numbers

li $v0, 1 # System call for printing a integer

syscall

li $v0, 1 0 # System call program exit

syscall

sum:

li $v0,0

li $v1,0

Loop:

blez $a1, Return #a1 has N, if N is less than 0 return from function

addi $a1, $a1, -1 # Decrement loop counter

lw $t0, 0($a0) # get a value from array

addi $a0, $a0, 4 # increment base pointer

bltz $t0, Negative

add $v0, $v0, $t0

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Computer Organization And Architecture LAB 3
b Loop

Negative:

add $v1, $v1, $t0 # sum negative numbers in $v1

b Loop

Return:

jr $ra

######################################################

# Program Name: Sum of Integers

# Programmer: YOUR NAME

# Date last modified:

#######################################################

# Functional Description:

# A program to find the sum of the integers from 1 to N, where N is a value

# Read in from the keyboard

# Pseudocode description of algorithm:

# main: count << “\n Please input a value for N = “

# cin >> v0

# If ( v0 > 0 )

# {t0 = 0;

# while (v0 > 0 ) do

# {t0 = t0 + v0;

# v0 = v0 – 1}

# count << “ The sum of the integers from 1 to N is “, t0;

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Computer Organization And Architecture LAB 3
# jump to main

# }

# else /*User can input any negative number to terminate this program */

# cout << “\n **** Bye Bye – Have good day ****”

####################################################################
##

# Cross References:

# v0: N, t0: Sum

####################################################################
#### .data

Prompt: .asciiz “\n Please Input a value for N = “

Result: .asciiz “The sum of the integers from 1 to N is”

Bye: .asciiz “\n **** Adios Amigo – Have a good day****”

.glob1 main

.text

main:

li $v0, 4 # system call code for print string

la $a0, Prompt # load address of prompt into $a0

syscall # print the prompt message

li $v0, 5 # system call code for Read Integer

syscall # reads the value of N into $v0

blez $v0, End # branch to end if $v0 < = 0

li $t0, ) # clear register $t0 to 0

Loop:

add $t0, $t0, $v0 # sum of integers in register $t0

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Computer Organization And Architecture LAB 3
addi $v0, $v0, -1 # summing integers in reverse order

bnez $v0, Loop # branch to loop if $v0 is != 0

li $v0, 4 # system call code for Print String

la $a0, Result # load address of message into $a0

syscall # print the string

li $v0, 1 # system call code for Print Integer

move $a0, $t0 # move value to be printed to $a0

syscall # print sum of integers

b # branch to main

End: li $v0, 4 # system call code for Print String

la $a0, Bye # load address of msg. into $a0

syscall # print the string

li $v0, 10 # terminate program run and

syscall # return control to system

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[ Computer Organization And Architecture] [lab 3]

Observations/Comments/Explanation of Results

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Computer Organization And Architecture LAB 4

Roll #:_____________________________

Getting familiar with Variables , Frame pointers & Recursion

Experiment 1:
using loop perform the following task
(the compute should ask the user to enter digits as shown and should
display the sum
Enter digit 1
Enter digit 2
Enter digit 3
Enter digit 4
Enter digit 5
The sum is _____
Note: it should not just ask you to enter digit,it should ask you to give
1st,2nd,3rd,4th,5th digit as shown above and use onlyi loop.
Bonus:(you can try this at the end of lab session,you can submit it till next
lab for bonus marks)

Experiment 2:
What does the following program calculates ?
.text
.globl main
main:
li $v0,5
syscall
add $a0,$zero,$v0

li $v0,5
syscall
add $a1,$zero,$v0

li $v0,5
syscall
add $a2,$zero,$v0

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Computer Organization And Architecture LAB 4
li $v0,5
syscall
add $a3,$zero,$v0

jal abc

li $v0,1
add $a0,$zero,$s2
syscall

li $v0,10
syscall

abc:
add $s0,$a0,$a1
add $s1,$a2,$a3
sub $s2,$s0,$s1
jr $ra

Experiment3:

why is the given program not giving the correct value. Debug !
.text
.globl main
main:
li $v0,5
syscall
add $a0,$zero,$v0

li $v0,5
syscall
add $a1,$zero,$v0

li $v0,5
syscall
add $a2,$zero,$v0

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Computer Organization And Architecture LAB 4

li $v0,5
syscall
add $a3,$zero,$v0

jal sum

li $v0,1
add $a0,$zero,$s0
syscall

li $v0,10
syscall

sum:
addi $sp,$sp,-12
sw $t0,8($sp)
sw $t1,4($sp)
sw $s0,0($sp)

add $t0,$a0,$a1
add $t1,$a2,$a3
sub $s0,$t0,$t1

lw $t0,8($sp)
lw $t1,4($sp)

lw $s0,0($sp)

addi $sp,$sp,12

jr $ra

Experiment4:
following function opens the console ,user enters the digit and by running
the program all the way through, calculates its factorial.

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Computer Organization And Architecture LAB 4
main:

li $v0,5
syscall

add $a0,$zero,$v0
jal fact
add $a0,$zero,$v0
li $v0,1
syscall
li $v0,10
syscall

fact:
addi $sp,$sp,-8
sw $ra,4($sp)
sw $a0,0($sp)

slti $t0,$a0,1
beq $t0,$zero,l1

addi $v0,$zero,1
addi $sp,$sp,8
jr $ra

l1: addi $a0,$a0,-1

jal fact

lw $a0,0($sp)
lw $ra,4($sp)
addi $sp,$sp,8
mul $v0,$a0,$v0
jr $ra

lab tasks:
make the program more refined

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Computer Organization And Architecture LAB 4

>display on console, the system should ask you to enter the digit whose
factorial you want to find.

Lab Assignment:

>the caculated factorial should be displayed as the (factorial of "x" is "y")

where y is the calculated facorial. and x is the digit you entered.note:you
may need two arrays for this purpose..think about it!
>Write a function which ask the user to enter temp in centigrade and
returns corresponding Fahrenheit value.

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Computer Organization And Architecture LAB 4

Observations/Comments/Explanation of Results

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Computer Organization And Architecture LAB 5
Roll #:_____________________________

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Computer Organization And Architecture LAB 5

2.

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Computer Organization And Architecture LAB 5

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Computer Organization And Architecture LAB 5

3. Load Lab5-part1.s into QTSPIM. Use “Reinitialize and Load Program”. Then use “Load File” to
load lab5-part2.s

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Computer Organization And Architecture LAB 5

Observations/Comments/Explanation of Results

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Computer Organization And Architecture LAB 6

Roll #:_____________________________

Introduction to Basic Syntax of Verilog and Gate-level-Modeling

Using Xilinx ISE tools

Objectives:

Identifying the components of a Verilog module definition

Understanding how to define the port list for a module and declare it in

Verilog.

Familiarization with the logic gate primitives provided in Verilog

Understanding instantiation of gates and construction of a Verilog

description from the logic diagram of the circuit

Hierararchical Design in Verilog

Reference:

Chapter 4 and Chapter 5

BOOK : Verilog HDL by Samir Palnitkar

Chapter 4

BOOK : Advanced Digital Design with the Verilog HDL

Procedure:

1. Launch the Xilinx ISE 7.1 software as follows:

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Start >> Programs >> Xilinx ISE 7.1 >> Project Navigator

2. Start a new project as follows:

File >> New Project

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3. Give the project name as : Half_Adder

Select the project location as follows:

C:\COMParch\Your ID

Select the top level module type as : HDL

4. Click Next.

5. In the next window of ‘Select Device and Design Flow for the Project’:
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Select the simulator as : ISE simulator and don’t worry about the rest of the options for
the time being. We shall look at them in greater detail afterwards.

6. Click Next.

7. In the next window of ‘Create a new source’:

Simply click Next. We shall not use this option for the time being.

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8. In the next window of ‘Add Existing Sources’:

Simply click Next. We shall not use this option for the time being.

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9. In the next window, click Finish.

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10. Select Project >> New Source

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11. In the ‘New Source’ window:

Select ‘Verilog module’ out of different options available in the

left hand column. Give the file name as: half_adder

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12. In the next window of ‘Define Verilog Source’:

Simply click Next. We shall not use this option for the time being.

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13. In the next window, click Finish.

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14. You will see something like this:-

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15. Enter the following Verilog Code in half_adder.v file and save the file:

module half_adder(sum , carry, in1, in2);

output sum;

output carry;

input in1;

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input in2;

xor x1(sum, in1, in2);

and a1(carry, in1, in2);

endmodule

Follow carefully the instructor’s explanation of the basic syntax of a

Verilog module, port list and Verilog’s gate level statements.

In the ‘Processes Window’, located 2nd from the top on the left hand side, locate
the “Synthesize-XST” process and expand it by clicking on the small box
containing + sign alongside it. Now, in the options available inside the
“Synthesize-XST” process, locate the “Check Syntax” step and click on it.

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16. Make the Gate-level Diagram of the half and full adder. Show proper working and table.

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17. Make sure that your Verilog Code is free of any Syntax errors and the Check Syntax process
does not give any error.( of course we are talking about half-adder you just made. )

18. Moving on to simulating the Verilog module for half adder:

Select Project>> New Source

19. In the New Source Window, select the ‘Test Bench Waveform’ out of different options available
in the left hand column and give the file name as “half_adder_tb”.

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20. Click Next.

21. In the next window, you have to associate this testbench waveform with a particular verilog
module of your design to which you want to apply this waveform and check the results. As we
have only one module, half_adder, in our design, select half_adder and then click Next.

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22. In the next ‘New Source Information’ window, simply click Finish.

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23. You will see something like this:

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24. In the right hand side portion named ‘Clock Information’, select ‘Combinational (or Internal
Clock)’ option.

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25. Then, select OK.

26. The screen will take the form as shown below:

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27. In this Waveform window, you can see that outputs are indicated with yellow colour and
inputs are indicated with light green colour.

28. You can click the input signal waveform area to decide what waveform you want to apply to
the inputs of your module and then in the next step, you will be able to simulate and see the
results of applying that particular input in the form of output waveforms.

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29. Click the save icon in order to save this TestBenchWaveform file named half_adder_tb.tbw.

30. In the ‘Sources in the Project’ window on the top left hand side, select the Test Bench
Waveform file named ‘half_adder_tb’. Then, click on the ‘Process View’ tab, located at the
bottom of the 2nd window from the top on the left hand side.

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31. Clicking the ‘Process View’ for half_adder_tb file will result in the screen as shown below:

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32. Expand the “Xilinx ISE Simulator” options in the Processes Window and double click on the
“Simulate Behavioral Model” option.

33. This will start the simulation process and you will end up with something like this:

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34. Out of the four tabs available at the bottom of the main window, select the second from the
right hand side named half_adder_tb_isim. This will show you the results of simulating the
Verilog module half_adder.v by applying it the input waveform mentioned in the file
half_adder_tb.tbw.

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35. Assignment:

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36.
Write down the module statement and port list for the following Block diagram:

( You are not expected to write the whole programme just the first couple of statements )

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Observations/Comments/Explanation of Results

Roll #:_____________________________
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Simulation of Full and 4-Bit Ripple Carry Adder in Gate Level

Abstraction

Objective:

Understanding gate level coding techniques in Verilog

Full Adder:

Following the steps described in the manual 5 simulate full adder . ( I mean the so many
steps you just did , do them again and get used to them . They are your friends!!! )
Gate level code for the full adder module:

module full_adder(sum ,carry_out, in1, in2, carry_in);

output sum;

output carry_out;

input in1;

input in2;

input carry_in;

wire c, d, e;

xor x1(c,in1,in2);

xor x2(sum, c, carry_in);

and a1(d, in1, in2);

and a2(e, c, carry_in);

or o1(carry_out, d, e);

endmodule

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Note the difference of Verilog code for the full adder and the code of half adder employed in
the last couple of steps . Note the use of “wire c,d,e;” in order to handle the intermediate
connections between the gates.

1. Enter this code and then, simulate it using the steps described above

2. Following is the full adder diagram implemented as a combination of half adders:

The use of the smaller blocks to design a larger block is known as “Hierarchical Design”.
This sort of hierarchical design can be implemented in Verilog as well through the concept
of “Instantiating” a smaller module in some larger module .Following is the Verilog Code for
the full adder using this hierarchical approach, by “Instantiating” the half_adder module

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module full_adder (sum ,carry_out, in1, in2, carry_in);

output sum;

output carry_out;

input in1;

input in2;

input carry_in;

wire c, d, e;

half_adder h1(s1,c1,in1,in2);

half_adder h2( x2(sum, c2, s1, carry_in);

or o1(carry_out, c1, c2);

endmodule

3. Enter this code and then, simulate it using the steps described above.

4-Bit Ripple Carry Adder:

Previously you had been asked to write the Verilog Code of a 4 bit Ripple Carry Adder
which consisted of 4 full adders that you had previously designed. Now, you will again
write the Verilog Code for this Ripple Carry Adder but this time the inputs and outputs
will be handled differently using the concept of “Vectors” in Verilog.

1. Following is the Diagram for that Ripple Carry Adder using this new approach.

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2. Following is the Verilog code for the Ripple Carry Adder defining the inputs and
outputs as Vectors.

module full_adder_4(sum, carry_out, a, b, carry_in);

output [3:0] sum;

output carry_out;

input [3:0] a,b;

input carry_in;

wire c1, c2, c3;

full_adder fa0(sum[0], c1, a[0], b[0], carry_in);

full_adder fa1(sum[1], c2, a[1], b[1], c1);

full_adder fa2(sum[2], c3, a[2], b[2], c2);

full_adder fa3(sum[3], carry_out, a[3], b[3], c3);

endmodule

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Roll #:_____________________________

Introduction to Data Flow Level Programming in Verilog

Objectives:

Understanding data flow level coding in Verilog

Types of Verilog Modelling:

As it had been mentioned in the first lab that in Verilog we have different levels of
abstraction available to us like:

a. Gate level
b. Dataflow level
c. Behavioral level

In the first few labs, we have looked at the Gate level coding.

Now, we shall take a look at the

Dataflow level Coding:

In the manual techniques of designing any digital logic circuit, we start from the truth
table, generate a separate Boolean Equation for each output column of the truth table,
then these Boolean equations are simplified using different techniques and finally, these
simplified Boolean equations are translated into gate level diagram.

In Gate level coding, we basically translate the gate level diagram of a circuit into
statements

While in Dataflow level coding, we can directly translate the Boolean equations of a circuit into
statements. So, you can easily see that Dataflow level coding is at a higher level of abstraction
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as compared to Gate level coding. While describing Boolean equations in the form of Dataflow
statements, we use logical operators like negation (~), and (&), or(|), xor(^), xnor(^~),etc.

Besides describing Boolean equations at Dataflow level, we can even move on to a higher level
of abstraction and use other type of operators as well like arithmetic operators(+,-)

Dataflow Operators:

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Concatenation and Replication Operators:

wire[3:0] x, y;

wire[7:0] z, q, w, t;

wire[31:0] m, n;

assign x = 4’b1100;

assign y = 4’b0101;

assign z = {x, x}; // z is 8’b11001100

assign q = {x, y}; // q is 8’b11000101

assign w = {4’b1101, y}; // w is 8’b11010101

assign t = {2{x}}; // same as {x, x}

assign m = {{4{x}}, {2{q}}};

// m is 32’b11001100110011001100010111000101

A Dataflow MUX Version-1 :

module mux21(q, sel, a, b);

input sel, a, b;

output q;

assign q = (~sel & a) | (sel & b);

endmodule

A Dataflow MUX Version-2 :

module mux21(q, sel, a, b);

input sel, a, b;
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output q;

assign q = sel ? b : a;

endmodule

Data Flow Code For Half Adder:

module half_adder(sum , carry, X, Y);

output sum;

output carry;

input X;

input Y;

assign sum = X ^ Y;

assign carry = X & Y;

endmodule

See the results of Designed module using ISE Simulator.

2:4 Decoder:

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module decode24(q, a);

output[3:0] q;

input[1:0] a;

assign q = (4’b0001) << a;

endmodule

A Dataflow MUX – Multi-Bit:

module mux21(q, sel, a, b);

input sel;

input[15:0] a, b;

output[15:0] q;

assign q = sel ? b : a;

endmodule

A Dataflow MUX – Parameterized Width:

module mux21n(q, sel, a, b);

parameter WID = 16;

input sel;

input[WID-1:0] a, b;

output[WID-1:0] q;

assign q = sel ? b : a;

endmodule

• By default, this is now a 16-bit wide MUX.

• When instantiating, the default value of 16 can be overridden

4:1 MUX – Method 1:

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module mux41n(q, sel, a, b, c, d);

parameter WID=16;

input[1:0] sel;

input[WID-1:0] a, b, c, d;

output[WID-1:0] q;

wire[WID-1:0] tmp1, tmp2;

mux21n #(WID) M0(tmp1, sel[0], a, b);

mux21n #(WID) M1(tmp2, sel[0], c, d);

mux21n #(WID) M2(q, sel[1], tmp1, tmp2);

endmodule

If the mux21n cells are parameterizable for bit-width this works…

If not, it doesn’t work…

Assignment:

Write down the code for 8to 1 Multiplexer in data flow level coding.

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Observations/Comments/Explanation of Results

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Roll #:_____________________________

Implementation of Different types of Adders in Data Flow Modeling

Objectives:
After this lab you’ll be able to

 To write Verilog module for adders at data flow level

Half Adder:

module half_adder(sum , carry, X, Y);

output sum;

output carry;

input X;

input Y;

assign sum = X ^ Y;

assign carry = X & Y;

endmodule

See the results of Designed module using ISE Simulator.

Now write down the Boolean Equations for full adder:

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Use the following dataflow level code.

module full_adder(sum , carry, X, Y, Z);

output sum;

output carry;

input X,Y,Z;

assign sum = X ^ Y ^ Z;

assign carry = (X & Y) | (Z & (X ^ Y));

endmodule

See the results of designed module using ISE Simulator.

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Assignment:

Write the code for a 4 bit adder using data flow modelling.

See the results of designed module using ISE Simulator.

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Observations/Comments/Explanation of Results

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Roll #:_____________________________

Implementation of Various Combinational Circuits on Verilog at

behavioral level

Objectives
After this lab you’ll be able to

 To write verilog module for digital circuits at behavioral level

 To use case statements in Verilog HDL.
 To use if else statements in Verilog HDL.
 To write verilog module for Decoders.
 To write verilog module for Priority Encoders.
 To write verilog module for Multiplexers.

Introduction

A number of standard combinational logic functions have been developed for digital circuits that
represent many of the useful tasks that can be performed with digital circuits.

Decoders detect the presence of particular binary states and can activate other circuits based on their
input values or can convert an input code to a different output code.

Encoders generate a binary or binary coded decimal (BCD) code corresponding to an active input.

Multiplexers and de-multiplexers are used for data routing. They select a transmission path for
incoming or outgoing data, based on a selection made by a set of binary-related inputs.

Decoders

The general function of a decoder is to activate one or more circuit outputs upon detection of a
particular digital state. The simplest decoder is a single logic gate, such as a NAND or AND, hose
output activates when all its inputs are HIGH. When combined with one or more inverters, a NAND or
AND can detect any unique combination of binary input values. An extension of this type of decoder
is a device containing several such gates, each of which responds to a different input state. Usually, for
an n-bit input, there are 2n logic gates, each of which decodes a different combination of input
variables. Some types of decoders translate binary inputs to other forms, such as the decoders that

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drive seven-segment numerical displays. The decoder has one output for every segment in the display.
These segments illuminate in unique combinations for each input code

Figure 1 2-line-to-4-line Decoder with Enable

Figure 1 shows the logic circuit of a 2-line-to-4-line decoder. The circuit detects the presence of a
particular state of the 2-bit input D1D0, as shown by the truth table in Table 1. One and only one
output is HIGH for any input combination, provided the enable input G is LOW.

G(activelow) D0 D1 Y0 Y1 Y2 Y3

0 0 0 1 0 0 0

0 0 1 0 1 0 0

0 1 0 0 0 1 0

0 1 1 0 0 0 1

1 X X 0 0 0 0

Table1 Truth Table of a 2-to-4 Decoder with Enable

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Task1:

A verilog module is shown below. Create a new project using Xilinx ISE.Add this module to
project and verify it by simulating its behavior .

Verilog Module for 3 to 8 decoder

module v_decoders_1 (sel, res);

input [2:0] sel;

output [7:0] res;

reg [7:0] res;

always @(sel or res)

begin

case (sel)

3'b000 : res = 8'b00000001;

3'b001 : res = 8'b00000010;

3'b010 : res = 8'b00000100;

3'b011 : res = 8'b00001000;

3'b100 : res = 8'b00010000;

3'b101 : res = 8'b00100000;

3'b110 : res = 8'b01000000;

default : res = 8'b10000000;

endcase

end

endmodule

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What is the purpose of using case statement in module for 3 to 8 decoder?

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Explain and record results for above verilog module?

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Draw results from Test bench for 3 to 8 decoder? Indicate Input & Output signals?

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Task2:

A verilog module is shown below. Create a new project using Xilinx ISE.Add this module to
project and verify it by simulating its behavior.

module v_decoders_2 (sel, res);

input [2:0] sel;

output [7:0] res;

reg [7:0] res;

always @(sel)

begin

case (sel)

3'b000 : res = 8'b11111110;

3'b001 : res = 8'b11111101;

3'b010 : res = 8'b11111011;

3'b011 : res = 8'b11110111;

3'b100 : res = 8'b11101111;

3'b101 : res = 8'b11011111;

3'b110 : res = 8'b10111111;

default : res = 8'b01111111;

endcase

end

endmodule

What is the difference between module v_decoders_2 and module v_decoders_1?

______________________________________________________________________________
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______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Explain and record results for above verilog module? How this module will be
implemented at hardware level?

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Draw results from Test bench for 3 to 8 decoder? Indicate Input & Output signals?

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Observations/Comments/Explanation of Results

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Roll #:_____________________________

Simple Arithmetic Logic Unit using Xilinx ISE tools

After this lab you’ll be able to

 To write verilog module for ALU at behavioral level

 To use casex statement in Verilog

Introduction

The arithmetic logic unit (ALU) carries out the logic operations (such as comparisons) and arithmetic
operations (such as add or subtract) required during the program execution. Generally

an ALU has two data inputs and one data output. Operations performed in the ALU often affect bits in
the status register (bits are set to indicate actions such as whether an overflow has occurred). The ALU
knows which operations to perform because it is controlled by signals from the control unit.

ALU in Verilog HDL

Table below shows pin description for ALU

Signal I/O Number of Bits

op_a; Input 4

op_b; Input 4

Func Input 2

alu_out Output 4

module alu_simp(op_a, op_b, func, alu_out);

input [3:0] op_a;

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input [3:0] op_b;

input [1:0] func;

output reg [3:0] alu_out;

always @ (op_a or op_b or func)

begin

case(func)

2'd0: alu_out = op_a + op_b;

2'd1: alu_out = op_a - op_b;

2'd2: alu_out = op_a & op_b;

2'd3: alu_out = op_a | op_b;

endcase

end

endmodule

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Task1:

Create a project in Xilinx ISE .Add this file to the project .Now simulate this file using ISE Simulator.
Next synthesize this file using XST.

Now Answer following Questions

What is the purpose of func line in above verilog module?

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Draw results from Test bench for ALU IN FIGURE 2? Indicate Input & Output
signals?

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Figure 2 Test Bench waveform for ALU

Signal I/O Number of Bits

op_a; Input 4

op_b; Input 4

Func Input 3

alu_out Output 4

Objective of this task is to write a verilog module for a complex ALU which can add,subtract ,compare
and shift and rotate operands.

Before writing module for complex ALU first answer following questions

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Write statements in Verilog HDL that can compare two operands each of 4 bits?

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

How you can shift and rotate data at behavioral level ?

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Read verilog module for complex ALU called alu_cmplx .Explain its operation
without using Xilinx ISE?

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

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Observations/Comments/Explanation of Results

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Roll #:_____________________________

Complex Arithmetic Logic Unit using Xilinx ISE tools

After this lab you’ll be able to

 To write verilog module for complex ALU at behavioral level

Without using synthesizer tool draw hardware diagram for complex ALU from
module given below?

Complex ALU in Verilog HDL

module alu_cmplx(op_a, op_b, func, alu_out);

input [3:0] op_a;

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input [3:0] op_b;

input [2:0] func;

output reg [3:0] alu_out;

always @ (op_a or op_b or func)

begin

casex({func, op_b})

//Logic operations:

//And, Or, Xor, Not

7'b000_xxxx: alu_out = op_a & op_b;

7'b001_xxxx: alu_out = op_a | op_b;

7'b010_xxxx: alu_out = op_a ^ op_b;

7'b011_xxxx: alu_out = ~op_a;

//Aritmetic operations:

//Addition, Subtration, Comparison, Shifting&Rotation

7'b100_xxxx: alu_out = op_a + op_b;

7'b101_xxxx: alu_out = op_a - op_b;

//Comparator

//alu_out[3] = 0, alu_out[2] = G;

//alu_out[1] = E, alu_out[0] = L;

7'b110_xxxx: begin

if (op_a > op_b)

alu_out = 4'b0100;

if (op_a == op_b)

alu_out = 4'b0010;

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if (op_a < op_b)

alu_out = 4'b0001;

end

//Shifter Rotator

//cases for shift left

7'b111_0000: alu_out = op_a;

7'b111_0001: alu_out = {op_a[2:0], 1'b0 };

7'b111_0010: alu_out = {op_a[1:0], 2'b00 };

7'b111_0011: alu_out = {op_a[0] , 3'b000};

//cases for shift right

7'b111_0100: alu_out = op_a;

7'b111_0101: alu_out = {1'b0 , op_a[3:1]};

7'b111_0110: alu_out = {2'b00 , op_a[3:2]};

7'b111_0111: alu_out = {3'b000, op_a[3] };

//cases for rotate left

7'b111_1000: alu_out = op_a;

7'b111_1001: alu_out = {op_a[2:0], op_a[3] };

7'b111_1010: alu_out = {op_a[1:0], op_a[3:2]};

7'b111_1011: alu_out = {op_a[0] , op_a[3:1]};

//cases for rotate right

7'b111_1100: alu_out = op_a;

7'b111_1101: alu_out = {op_a[0] , op_a[3:1]};

7'b111_1110: alu_out = {op_a[1:0], op_a[3:2]};

7'b111_1111: alu_out = {op_a[2:0], op_a[3] };

endcase

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end

endmodule

Draw results from Test bench for ALU IN Figure 3? Indicate Input & Output
signals? Verify that each function of ALU is being performed.

Figure 3 Test Bench waveform for complex ALU

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Observations/Comments/Explanation of Results

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Roll #:_____________________________

To Understand the codes of Data Memory, Instruction Memory,

Register file, ALU and Address Generator of The Single Cycle MIPS
Machine

Objectives

The target of today's experiment in to develop a Verilog module which will serve as the interconnect
module for all the elements present in Single Cycle MIPS machine proposed by Hennessey and
Patterson in your textbook.

Figure 5 shows datapath for single cycle machine.

Figure 5 Data path for Single Cycle MIPS Machine

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Code Listing

Below is code listing for Single Cycle Machine.

module Data_Memory(clk, write, read, address, data_in, data_out);

input clk, write, read;

input [31:0] address, data_in;

output [31:0] data_out;

reg [31:0] data_out;

reg [31:0] data_mem [255:0];

always @ (read or write or address or data_in)

if (read == 1'b1)

data_out = data_mem[address];

always @ (negedge clk)

if (write == 1'b1)

data_mem[address] = data_in;

endmodule

module Instruction_Memory(address, out);

input [31:0] address;

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Computer Organization And Architecture LAB 12

output [31:0] out;

reg [7:0] mem [255:0];

assign out = {mem[address], mem[address + 1],mem[address + 2],

mem[address + 3]};

endmodule

module Register_File(clk, write, add_opa, add_opb, add_write,

data_in, op_a, op_b);

input clk, write;

input [4:0] add_opa, add_opb, add_write;

input [31:0] data_in;

output [31:0] op_a, op_b;

reg [31:0] rf [31:0];

assign op_a = rf[add_opa];

assign op_b = rf[add_opb];

always @ (negedge clk)

if(write==1'b1)

rf[add_write] = data_in;

endmodule

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Computer Organization And Architecture LAB 12

module ALU(opa, opb, alu_control, alu_out, zero_flag);

input [31:0] opa, opb;

input [3:0] alu_control;

output [31:0] alu_out;

reg [31:0] alu_out;

output zero_flag;

reg zero_flag;

always @ (alu_out)

if (alu_out == 32'd0)

zero_flag = 1'b1;

else

zero_flag = 1'b0;

always @ (opa or opb or alu_control)

case(alu_control)

4'b0000: alu_out = opa & opb;

4'b0001: alu_out = opa | opb;

4'b0010: alu_out = opa + opb;

4'b0110: alu_out = opa - opb;

4'b0111: if(opa < opb)

alu_out = 32'd1;

else

alu_out = 32'd0;

4'b1100: alu_out = ~(opa | opb);

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Computer Organization And Architecture LAB 12

endcase

endmodule

module address_generator(pc, offset, branch_sel,clk);

input branch_sel, clk;

input [31:0] offset;

output [31:0] pc;

reg [31:0] pc;

initial

pc = 0;

always @ (negedge clk)

if (branch_sel == 1'b0)

pc = pc + 4;

else

pc = pc + 4 + {offset[29:0], 2'b0};

endmodule

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Computer Organization And Architecture LAB 12

Observations/Comments/Explanation of Results

Page | 105
Computer Organization And Architecture LAB 13

Roll #:_____________________________

Complete Data path and Control of The Single Cycle MIPS Machine

Objectives

The target of today's experiment in to develop a Verilog module which will serve as the interconnect
module for all the elements present in Single Cycle MIPS machine proposed by Hennessey and
Patterson in your textbook.

Code Listings:

module add_gen(pc, offset, branch_sel, clk);

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Computer Organization And Architecture LAB 13

input branch_sel, clk;

input [31:0] offset;

output [31:0] pc;

wire [31:0] pc_out, m_out, incremented_address,

jump_address, shifted_offset;

assign pc = pc_out;

pcreg P(clk, m_out, pc_out);

shiftleft2 sl2(offset, shifted_offset);

add_4 a4(pc_out, incremented_address);

add_offset ao(incremented_address, shifted_offset, jump_address);

Mux2to1_32bit m32(incremented_address, jump_address, branch_sel,

m_out);

endmodule

module add_offset(in, offset, out);

input [31:0] in;

input [31:0] offset;

output [31:0] out;

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Computer Organization And Architecture LAB 13

assign out = in + offset;

endmodule

module add_4(in, out);

input [31:0] in;

output [31:0] out;

assign out = in + 4;

endmod-ule

module shiftleft2(in, out);

input [31:0] in;

output [31:0] out;

assign out = {in[29:0], 2'b0};

endmodule

module pcreg(clk, in, out);

input clk;

input [31:0] in;

output [31:0] out;

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Computer Organization And Architecture LAB 13

reg [31:0] out;

always @ (negedge clk)

out = in;

endmodule

module Sign_Extend(in, out);

input [15:0] in;

output [31:0] out;

assign out = {in[15], in[15], in[15], in[15],

in[15], in[15], in[15], in[15],

in[15], in[15], in[15], in[15],

in[15], in[15], in[15], in[15],

in};

endmodule

module Mux2to1_5bit(in1, in2, sel, out);

input [4:0] in1, in2;

input sel;

output [4:0] out;

reg [4:0] out;

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Computer Organization And Architecture LAB 13

always @ (in1 or in2 or sel)

case(sel)

1'b0: out = in1;

1'b1: out = in2;

endcase

endmodule

module Mux2to1_32bit(in1, in2, sel, out);

input [31:0] in1, in2;

input sel;

output [31:0] out;

reg [31:0] out;

always @ (in1 or in2 or sel)

case(sel)

1'b0: out = in1;

1'b1: out = in2;

endcase

endmodule

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Computer Organization And Architecture LAB 13

module Control(opcode, RegDst, ALUSrc, MemtoReg, RegWrite,

MemRead, MemWrite, Branch, ALUOp1, ALUOp0);

input [5:0] opcode;

output RegDst, ALUSrc, MemtoReg, RegWrite, MemRead,

MemWrite, Branch, ALUOp1, ALUOp0;

reg [8:0] cont;

initial

cont = 9'd0;

assign RegDst = cont[8];

assign ALUSrc = cont[7];

assign MemtoReg = cont[6];

assign RegWrite = cont[5];

assign MemRead = cont[4];

assign MemWrite = cont[3];

assign Branch = cont[2];

assign ALUOp1 = cont[1];

assign ALUOp0 = cont[0];

always @ (opcode)

case(opcode)

6'b000000: cont = 9'b100100010;

6'b100011: cont = 9'b011110000;

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Computer Organization And Architecture LAB 13

6'b101011: cont = 9'bx1x001000;

6'b000100: cont = 9'bx0x000101;

endcase

endmodule

module alu_control(func_field, alu_op, operation);

input [5:0] func_field;

input [1:0] alu_op;

output [3:0] operation;

reg [3:0] operation;

always @ (func_field or alu_op)

casex({func_field, alu_op})

8'bxxxxxx00: operation = 4'b0010;

8'bxxxxxxx1: operation = 4'b0110;

8'bxx00001x: operation = 4'b0010;

8'bxx00101x: operation = 4'b0110;

8'bxx01001x: operation = 4'b0000;

8'bxx01011x: operation = 4'b0001;

8'bxx10101x: operation = 4'b0111;

endcase

endmodule

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Computer Organization And Architecture LAB 13

Task:

Create a project in Xilinx ISE .Add all of the modules written above to the project.

Develop a Verilog module which will serve as the interconnect module for all the elements present in
Single Cycle MIPS machine proposed by Hennessey and Patterson in your textbook.

Page | 113
Computer Organization And Architecture LAB 13

Observations/Comments/Explanation of Results

Page | 114
Computer Organization And Architecture LAB 14

Roll #:_____________________________

Verification of the Single Cycle MIPS Machine

Objectives

The target of today's experiment in to verify the data path of single machine that was implemented
in previous lab.

Implement the code given below.

Figure 6 Data path for Single Cycle MIPS Machine

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Computer Organization And Architecture LAB 14

Code:

module processor(clk,result);

input clk;

output[5:0] result;

wire [31:0] ins;

wire [31:0] offset;

wire branch_signal;

wire [31:0] pc;

wire RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite,

Branch,ALUOp1, ALUOp0;

wire zero_flag;

wire [3:0] alu_control;

wire [4:0] out_M1;

wire [31:0] out_M2, out_M3, op_a, op_b, immi,alu_out, data_out;

assign offset = immi;

assign branch_signal = zero_flag & Branch;

address_generator AG(pc, offset, branch_signal, clk);

///////////////////////////////////////////////////////////

Instruction_Memory IM(pc, ins);

///////////////////////////////////////////////////////////

Control C(ins[31:26], RegDst, ALUSrc, MemtoReg, RegWrite,

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Computer Organization And Architecture LAB 14

MemRead, MemWrite, Branch, ALUOp1, ALUOp0);

////////////////////////////////////////////////////////

Mux2to1_5bit M1(ins[20:16], ins[15:11], RegDst, out_M1);

///////////////////////////////////////////////////////////

Register_File RF(clk, RegWrite, ins[25:21], ins[20:16], out_M1,

out_M3, op_a, op_b);

///////////////////////////////////////////////////////////

Mux2to1_32bit M2(op_b, immi, ALUSrc, out_M2);

///////////////////////////////////////////////////////////

alu_control AC(ins[5:0], {ALUOp1, ALUOp0}, alu_control);

///////////////////////////////////////////////////////////

ALU A(op_a, out_M2, alu_control, alu_out, zero_flag);

///////////////////////////////////////////////////////////

Data_Memory DM(clk, MemWrite, MemRead, alu_out, op_b, data_out);

///////////////////////////////////////////////////////////

Mux2to1_32bit M3(alu_out, data_out, MemtoReg, result);

///////////////////////////////////////////////////////////

endmodule

module Data_Memory(clk, write, read, address, data_in, data_out);

input clk, write, read;

input [31:0] address, data_in;

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Computer Organization And Architecture LAB 14

output [31:0] data_out;

reg [31:0] data_out;

reg [31:0] data_mem [255:0];

initial

begin

data_mem[4] = 7;

data_mem[65] = 56;

data_mem[67] = 43;

end

always @ (read or write or address or data_in)

if (read == 1'b1)

data_out = data_mem[address];

always @ (negedge clk)

if (write == 1'b1)

data_mem[address] = data_in;

endmodule

module Instruction_Memory(address, out);

input [31:0] address;

output [31:0] out;

reg [7:0] mem [255:0];

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Computer Organization And Architecture LAB 14

initial

begin

//r-format addition

mem[0] = 8'h00;

mem[1] = 8'h01;

mem[2] = 8'h10;

mem[3] = 8'h20;

//r-format subtraction

mem[4] = 8'h00;

mem[5] = 8'h82;

mem[6] = 8'h10;

mem[7] = 8'h22;

//r-format addition-----accumulation

mem[8] = 8'h00;

mem[9] = 8'h44;

mem[10] = 8'h10;

mem[11] = 8'h10;

mem[12] = 8'h00;

mem[13] = 8'h44;

mem[14] = 8'h10;

mem[15] = 8'h10;

mem[16] = 8'h00;

mem[17] = 8'h44;

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Computer Organization And Architecture LAB 14

mem[18] = 8'h10;

mem[19] = 8'h10;

mem[20] = 8'h00;

mem[21] = 8'h44;

mem[22] = 8'h10;

mem[23] = 8'h10;

//sw

mem[24] = 8'hAC;

mem[25] = 8'h20;

mem[26] = 8'h00;

mem[27] = 8'h00;

//sw with offset

mem[28] = 8'hAC;

mem[29] = 8'h22;

mem[30] = 8'h00;

mem[31] = 8'h41;

//lw with offest

mem[32] = 8'h8C;

mem[33] = 8'h24;

mem[34] = 8'h00;

mem[35] = 8'h41;

end

assign out = {mem[address] , mem[address + 1],

mem[address + 2], mem[address + 3]};

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Computer Organization And Architecture LAB 14

endmodule

module Register_File(clk, write, add_opa, add_opb,

add_write, data_in, op_a, op_b);

input clk, write;

input [4:0] add_opa, add_opb, add_write;

input [31:0] data_in;

output [31:0] op_a, op_b;

reg [31:0] rf [31:0];

initial

begin

rf[0] = 2;

rf[1] = 4;

rf[2] = 65;

rf[3] = 3;

rf[4] = 21;

rf[5] = 5;

rf[6] = 78;

rf[7] = 5;

rf[8] = 3;

rf[9] = 11;

end

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Computer Organization And Architecture LAB 14

assign op_a = rf[add_opa];

assign op_b = rf[add_opb];

always @ (negedge clk)

if(write==1'b1)

rf[add_write] = data_in;

endmodule

module Mux2to1_5bit(in1, in2, sel, out);

input [4:0] in1, in2;

input sel;

output [4:0] out;

reg [4:0] out;

always @ (in1 or in2 or sel)

case(sel)

1'b0: out = in1;

1'b1: out = in2;

endcase

endmodule

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Computer Organization And Architecture LAB 14

module Mux2to1_32bit(in1, in2, sel, out);

input [31:0] in1, in2;

input sel;

output [31:0] out;

reg [31:0] out;

always @ (in1 or in2 or sel)

case(sel)

1'b0: out = in1;

1'b1: out = in2;

endcase

endmodule

module Control(opcode, RegDst, ALUSrc, MemtoReg, RegWrite,

MemRead, MemWrite, Branch, ALUOp1, ALUOp0);

input [5:0] opcode;

output RegDst, ALUSrc, MemtoReg, RegWrite, MemRead,

MemWrite, Branch, ALUOp1, ALUOp0;

reg [8:0] cont;

initial

cont = 9'd0;

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Computer Organization And Architecture LAB 14

assign RegDst = cont[8];

assign ALUSrc = cont[7];

assign MemtoReg = cont[6];

assign RegWrite = cont[5];

assign MemRead = cont[4];

assign MemWrite = cont[3];

assign Branch = cont[2];

assign ALUOp1 = cont[1];

assign ALUOp0 = cont[0];

always @ (opcode)

case(opcode)

6'b000000: cont = 9'b100100010;

6'b100011: cont = 9'b011110000;

6'b101011: cont = 9'bx1x001000;

6'b000100: cont = 9'bx0x000101;

endcase

endmodule

module alu_control(func_field, alu_op, operation);

input [5:0] func_field;

input [1:0] alu_op;

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Computer Organization And Architecture LAB 14

output [3:0] operation;

reg [3:0] operation;

always @ (func_field or alu_op)

casex({func_field, alu_op})

8'bxxxxxx00: operation = 4'b0010;

8'bxxxxxxx1: operation = 4'b0110;

8'bxx00001x: operation = 4'b0010;

8'bxx00101x: operation = 4'b0110;

8'bxx01001x: operation = 4'b0000;

8'bxx01011x: operation = 4'b0001;

8'bxx10101x: operation = 4'b0111;

endcase

endmodule

module ALU(opa, opb, alu_control, alu_out, zero_flag);

input [31:0] opa, opb;

input [3:0] alu_control;

output [31:0] alu_out;

reg [31:0] alu_out;

output zero_flag;

reg zero_flag;

always @ (alu_out)

if (alu_out == 32'd0)

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Computer Organization And Architecture LAB 14

zero_flag = 1'b1;

else

zero_flag = 1'b0;

always @ (opa or opb or alu_control)

case(alu_control)

4'b0000: alu_out = opa & opb;

4'b0001: alu_out = opa | opb;

4'b0010: alu_out = opa + opb;

4'b0110: alu_out = opa - opb;

4'b0111: if(opa < opb)

alu_out = 32'd1;

else

alu_out = 32'd0;

4'b1100: alu_out = ~(opa | opb);

endcase

endmodule

module address_generator(pc, offset, branch_sel,clk);

input branch_sel, clk;

input [31:0] offset;

output [31:0] pc;

reg [31:0] pc;

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Computer Organization And Architecture LAB 14

initial

pc = 32'h00000000;

//always @ (negedge clk)

//if (branch_sel == 1'b0)

//pc = pc + 4;

//else

//pc = pc + 4 + {offset[29:0], 2'b0};

endmodule

Task:

1. Create a project in Xilinx ISE .Add the above code in it. Make the testbench of it and determine
what the code is doing.

2. Make changes in the above code to implement Load Instruction.

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 Observations/Comments/Explanation of Results

The End

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