Final Lecture 1
Final Lecture 1
Final Lecture 1
Learning Outcomes
1. Familiarize to Zener and Transistor parameters
2. Knowing Zener and Transistor Biasing condition
3. See and observed the biasing condition of a regulator and emitter
biased.
4. Experiencing to plot and sketch characteristics curve of a zener and
transistor.
Zener Diode Voltage Regulator
Ex1.) Vrec=25V, VRL = 9V, VZ=6V. Find: Output Regulated Voltage?
Vo = unregulated output voltage from 6V to 9V to 25V.
RECTIFIER
Step 1: Find an exact value of Resistor(Rs) to exceed that Vin concerning
VRL. Then apply Thevenin’s theorem. VRL = 9V. Therefore Vo = 6V.
I-V Characteristic
KVL
KVL
Input
Outp
ut
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Formulae for Zener Regulator
Circuit
Rs establishes the zener bias current, IZT:
Vi − VZ Vi − VZ
Rs = =
I Rs I ZT + I L
For fixed Vi, but variable RL:
VZ RsVZ
min . RL = =
I Rs Vi − VZ
VZ VZ
max . RL = =
I L (min) I Rs − I ZM
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Formulae (cont’d)
For fixed RL, but variable Vi:
RL + Rs
min .Vi = VZ
RL
max .Vi = I R (max) Rs + VZ
where I R (max) = I ZM + I L
• Darlington amplifier
• Two transistors used
together
• Gain is multiplicative
Transistor Series Voltage
Regulator
The simple zener regulator
can be markedly improved
by adding a transistor.
Since VBE = VZ - VL any
tendency for VL to decrease
or increase will be negated
by an increase or decrease in IE. The dc currents for the
circuit are: VL VZ − VBE Vi − VZ
IL = = ; IR =
RL RL R
IL = hFEIB; IZT = IR - IB
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Transistor Shunt Voltage
Regulator
Since VBE = VL - VZ,
any tendency for VL
to increase or decrease
will result in a
corresponding increase or decrease in IRs. This will
oppose any changes in VL because VL = Vi - IRsRs.
VL VZ + VBE Vi − (VZ + VBE )
IL = = ; I Rs =
RL RL RS
IE = IRs + IL = hFEIZT
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