Microprocessor systems: DEEP/T 3. EE department RVIST. Trainer: Mr. Kongo S.

Microprocessor systems

Table of Contents
1.0 COMPUTER PRINCIPLES ............................................................................................................................. - 4 -
1.1 MICROCOMPUTER ARCHITECHTURE ........................................................................................................ - 5 -
1.1.1 THE MICROPROCESSOR...................................................................................................................... - 5 -
1.1.2 ARITHMETIC AND LOGIC UNIT ........................................................................................................... - 7 -
1.1.3 TIMING AND CONTROL ...................................................................................................................... - 8 -
1.1.4 THE BUS STRUCTURE.......................................................................................................................... - 8 -
3.0 8085 MICROPROCESSOR ......................................................................................................................... - 35 -
3.1 8085 PIN DIAGRAM ............................................................................................................................. - 35 -
3.2 8085 MICROPROCESSOR FUNCTIONAL BLOCK DIAGRAM .................................................................. - 37 -
3.3 INSTRUCTION SETS AND ASSEMBLY LANGUAGE PROGRAMMING..................................................... - 40 -
3.4 8085 INSTRUCTION SET........................................................................................................................... - 42 -
SUMMARIZED 8080/8085 INSTRUCTION SET ............................................................................................... - 79 -
3.5 ADDRESSING MODES OR ADDRESSING METHODS ................................................................................. - 80 -
4.0 TOOLS USED IN ASSEMBLY LANGUAGE PROGRAMMING ....................................................................... - 84 -
5.0 INTERRUPTS............................................................................................................................................. - 91 -
5.1 8085 interrupts.................................................................................................................................... - 93 -
6.0 INTERFACES ............................................................................................................................................. - 97 -
6.1 FORMATS FOR DATA TRANSFER.......................................................................................................... - 98 -
6.2 8156/8155 PIO .................................................................................................................................. - 103 -
8085-8156 INTERFACE......................................................................................................................... - 104 -

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 Microprocessor systems: DEEP/T 3. EE department RVIST. Trainer: Mr. Kongo S.

6.2.1 PORTS ......................................................................................................................................... - 104 -

PROGRAMMING THE PORTS ................................................................................................................... - 105 -
PROGRAMMING THE TIMER ................................................................................................................... - 109 -
7.0 I/O TECHNIQUES.................................................................................................................................... - 113 -
7.1 I/O-MAPPED I/O ................................................................................................................................ - 113 -
7.2 MEMORY-MAPPED I/O...................................................................................................................... - 114 -
7.3 METHODS OF I/O DATA TRANSFER ................................................................................................... - 116 -
Direct Memory Access (DMA) ............................................................................................................. - 117 -
8.0 SUBROUTINES........................................................................................................................................ - 119 -
Introduction ............................................................................................................................................ - 119 -
8.1 Nested subroutines ........................................................................................................................... - 123 -
8.2 Parameter passing............................................................................................................................. - 124 -
9.0 FAULT DIAGNOSIS ................................................................................................................................ - 126 -
9.1 TROUBLE SHOOTING TREE ................................................................................................................ - 126 -
9.2 TYPICAL FAULTS IN MICROCOMPUTER BASED SYSTEMS .................................................................. - 127 -
9.3 FAULT FIINDING TECHNIQUES........................................................................................................... - 128 -
REVISION QUESTIONS AND ANSWERS ........................................................................................................ - 134 -
REVISION QUESTIONS (WITH ANSWERS) .................................................................................................... - 153 -

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 Microprocessor systems: DEEP/T 3. EE department RVIST. Trainer: Mr. Kongo S.

1.0 COMPUTER PRINCIPLES

A digital computer utilizes the very high speed execution of each machine instruction by
automatically executing each instruction in a sequence called a program. This stored program
capacity enables a computer to be much more flexible in the range of operations possible.
In performing a program, a computer goes through a methodical process. The computer fetches an
instruction from memory and then executes this instruction. The next instruction is fetched and then
executed. This process is continued, each fetch/execute cycle takes a few microseconds for a typical
microprocessor based system. The details of this fetch/execute cycle vary greatly from computer to
computer. We will be using the Intel 8085 microprocessor for the study of microprocessor in this
course.
The computers instructions are normally located in its memory in sequence. Knowing the location of
the last-fetched instruction allows the processor to find the next one. To start a program we must
simply indicate the location of the first instruction to the processor.
Computer memory is composed of a large collection of individual data storage locations. Each
location has a number assigned to it, called an address. No two locations have the same address.
As far as the processor is concerned, the address numbers and hence the address locations normally
occur in sequence. Sometimes the addresses occur in blocks, however the addresses occur in
sequence within the blocks.
The complete set of instructions that a given microprocessor can perform is called the processors
instruction set. Commonly, the microprocessors from the same manufacturer will have similar
instruction sets.
A computer does three kinds of operations internally, it stores program instructions and data
manipulates data and changes its operations based on data. The latter is referred to as decision
making. Processor decision making instructions allow the computer to alter its path though a
program based on available data. This deviation from the sequences of executing instructions is
known as branching. The process of using a branch to repeat a sequence of instructions is called
polling.
Instruction consists of a group of binary digits or bits forming a digital word. When the
microprocessor receives these bits as an instruction, it sets various internal switches so that the
instruction will be executed.
For many common microprocessors the instruction and data word are 8-bits long and an address is
16-bits long. The 8-bit binary number is called a byte.

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 Microprocessor systems: DEEP/T 3. EE department RVIST. Trainer: Mr. Kongo S.

A 4-bit binary number is called a nibble. The term “word” generally refers to a group of binary
numbers that contain some information. It is sometimes reserved for 16-bit binary numbers.
The information stored in a microprocessor‟s memory amounts to groups of related binary bits. This
groups or words are coded as data in various forms. One common form of computer data is of
course the machine instructions. Secondly the data may represent various forms of numbers e.g.
Binary coded Decimal (BCD). Another common form of data is a standardized method of
representing letters and symbols called ASCII (American Standard Code for Information
Interchange). Most exchanges between such items as keyboards, displays, printers etc are done in
ASCII.

1.1 MICROCOMPUTER ARCHITECHTURE

Microproc- ROM RAM Input / Input devices

Output
essor unit ports Output devices
(MPU)

Address bus
Data bus
Control bus

1.1.1 THE MICROPROCESSOR

A simplified view of a microprocessor is shown below;

Registers

ALU

Timing &
control

To external
BUS devices

The bus connects the microprocessor to its memory and to its I/O devices which are used to
communicate with the outside world.

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 Microprocessor systems: DEEP/T 3. EE department RVIST. Trainer: Mr. Kongo S.

Registers
A register is a temporary data storage location within the processor whose contents may be moved or
manipulated during each machine cycle. Because they are resident in the microprocessor, they can
be manipulated rapidly without selecting external chips. Although the details of the internal register
architecture vary from machine to machine, certain register types are very common.

1. PC (Program counter)
Once a program has been developed for a particular task, it is loaded into memory and is then
executed. To remember which program instruction is to be executed next; the processor uses a
register called the program counter (PC). The contents of the PC identify the address of the next
instruction to be fetched and executed. It is said to “point” to the next instruction. It contains the
address of the next instruction to be fetched. Its size determines the range of memory in which
program instructions can be located. For many common machines e.g. the 8080, 8085, Z80, 6502 or
6800 this is a 16-bit number and gives a range of 65,536 possible locations.

2. Accumulator (A)
It is used extensively for data manipulations. Although exceptions occur, addition, subtractions and
similar instructions commonly use the accumulator for data to initiate the operation and as the
destination for the result.

3. Flag Register (F)

It contains various bits of status information. If for example the last operation resulted in a zero
value, a zero flag might be set, by this we mean that a specific bit of the flag register word will be set
to a one. Other common flags are a carry flag for addition, a borrow flag for subtraction, a sign flag
auxiliary carry flag and parity flag. The flag register is often given other names e.g. condition code
register, processor status register or simply status register.

4. Instruction Register (IR)

It is used as the destination of the instruction during the fetch cycle. The program cannot directly
manipulate this register. Such a register is said to be invisible.
The instruction therefore contains the operation code (op-code) of the instruction currently under
execution.

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 Microprocessor systems: DEEP/T 3. EE department RVIST. Trainer: Mr. Kongo S.

5. Stack
In some microprocessors a special set of a registers is arranged in what is called a stack. These
registers are connected in such a way that when a word is stored in the first register, the data
previously contained in this register are transferred to the next register down the stack. The previous
contents of the second register are transferred to the third, the third to the fourth and so on. Storing
data this way is known as pushing the stack. When a read operation is performed, the word that is
retrieved is the last word pushed into the stack. This kind of stack is therefore called a last-in first
out (LIFO) stack. The read operation is called poping the stack.
A LIFO stack can also be implemented by using memory locations. Here a portion of RAM is
reserved for use as a stack. A CPU register is designed as a stack pointer (SP) and contains the
address of the free memory location (top of the stack). When the stack is to be pushed the data are
stored in the location pointed to by the SP and the pointer is stepped. Popping the stack involves the
reverse operation. The advantage of this type of stack is that many more storage locations become
available. The disadvantage is that stack operations may take longer because the data transfers occur
external to the CPU.
NB
The stack is a LIFO memory in the sense that items or data that goes in last will come out first. The
address of the top of the stack is contained in a register called stack pointer. Two instructions PUSH
and POP or are usually available with the stack.
PUSH operation is defined as writing to the top or bottom of the stack. Some microprocessors access
the stack from the top while others access via bottom. When the stack is accessed from the bottom
the stack pointer is incremented after a PUSH and decremented after a POP operation on the other
hand if the stack is accessed from the top the stack pointer is decremented after a push and
incremented after a pop

1.1.2 ARITHMETIC AND LOGIC UNIT

The arithmetic logic unit (ALU) and “timing and control” blocks form the central control features of
the computer system. The ALU can generally do addition and subtraction along with various logic
operations such as AND, OR, exclusive OR etc.
The ALU is physically composed of dedicated logic circuits. It rarely provides a multiplication or
addition capability for basic 8-bit systems because of the complexity, involved. These operations are

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 Microprocessor systems: DEEP/T 3. EE department RVIST. Trainer: Mr. Kongo S.

generally done by programming multiple additions or subtraction. Another approach is to use an

external chip called a math processor which carries out such complex operations.

1.1.3 TIMING AND CONTROL

Timing and control refers to the rather complex set of logic functions that synchronize the machine
and direct various operations. A high frequency oscillator provides the basis for timing. During the
first cycles of this clock, after the start of the fetch cycle;
1. The memory address of the first program instructions (usually address location zero) is used
to excite the memory address lines.
2. An indication is sent that the processor is ready to receive the instruction from this address.
3. The instruction word is moved from memory to the instruction register (which is connected
to an instruction decoder).
4. Finally, the memory is told that the instruction has been received.

This shows that a number of critical timing conditions must be met if data transmission is to be
properly co-coordinated.
The timing and control block decodes instructions and directs the execute cycle. For example, the
instruction word 10001010 (8AH) is decoded by 8085 as “add register D with carry to the
accumulator. This instruction causes the timing and control block to command the ALU to add the
contents of the accumulator t the contents of register D and add to this sum a one if the carry flag is a
one. The ALU will then store the result in the accumulator erasing the old accumulator data. The
various flags will be changed based on the result of this operation. A gain the function of the timing
and control is to coordinate this activity. The timing and control block also provides a reset function
to initialize the CPU along with other components in the computer system.

1.1.4 THE BUS STRUCTURE

A bus is a set of conductors over which data, address, control signals or other information can be
transmitted. A classic 8-bit microprocessor system would include an 8-bit (that is 8 wire) data bus, a
16-bit address bus and 6 to 8-bit control bus as shown in figure 1.
 The data bus/lines are used to carry data and instructions from one unit to another e.g. carries
data to be stored or read from a memory location to the microprocessor.
 Address bus/lines carry the address word i.e. the address of the memory location where data
is to be stored or read from.

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 The control bus however is used to transmit of timing and control signals for co-ordinating
data transfers.

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3.0 8085 MICROPROCESSOR

INTRODUCTION
The very first microprocessor was introduced by Intel Corporation in 1971. Intel introduced the 4-bit
4004 and the 8-bit 8008 in that year. In 1974, Intel introduced the 8080 microprocessor, which
handles 8-bit data words and has a 16-bit address line and a 16-bit stack pointer. The 8080 became
one of the most widely used general-purpose microprocessors in the industry. The Intel 8085
microprocessor is an enhancement of the 8080 unit. It integrates the clock, system control, and
interrupt prioritization within the microprocessor IC, thereby reducing the number of ICs used in
most systems. The 8085 also operates on single +5V power supply. The 8085 MPU uses all the same
instructions as the 8080, thereby making them program compatible.

3.1 8085 PIN DIAGRAM

The Intel 8085 8-bit microprocessor is housed in a 40-pin dual-in-line package (DIP). The pin
diagram for the 8085 MPU is reproduced in figure below.

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The 8085 microprocessor is capable of transmitting 16-bit addresses, which means that 216 = 65,536
memory locations can be addressed directly. The data bus is of 8- bits which means that eight bits of
data can be transferred to and from the microprocessor.
The CPU sets the state of both the address and the control buses for the read or write operations.
However the state of the data bus may be established either by a memory location or by the CPU.
Thus both the CPU and the memory must be able to:
1. Drive a data bus line to a 1
2. Drive a data bus line to a 0
3. Allow a data bus line to be driven by other devices.
A device that can achieve these three states is said to be a three state device/driver called a buffer.
The control bus defines whether the device is to produce data (the first two states) or be passive (the
high impedance state) by some form of read/write select as shown in figure below.

Logic  0 or 1 when select is 1

input
 High impedance when
select is 0

select

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3.2 8085 MICROPROCESSOR FUNCTIONAL BLOCK DIAGRAM
Figure below shows the functional block diagram of Intel‟s 8085 microprocessor. It is actually the
internal architecture.

The 8-bit internal data bus, which is bi-directional, carries the instructions and data between the
different registers. At the bottom right are the external address and data bus.
1. Program counter (PC)
 Is a 16 – bit register which holds the address of the next instruction to be executed.
 The PC goes through a step-by-step counting sequence and causes the processor to read
successive instructions previously stored in memory.
2. Instruction register (IR)
 Holds the operation code (op-code) byte of the instruction currently under execution by the
processor.
3. Control and timing unit

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  Examines the instruction byte in the IR and implements it by sending out timing and control
signals to other parts of the processor and beyond.
4. Work registers
 Used to hold data items that are processed within instructions.
 There are seven work registers namely A (accumulator), B, C, D, E, H and L.
 The Accumulator is an 8-bit register used for operations such as arithmetic, logic, load, store
and I/O instructions. It is the principal work register.
 Registers B, C, D, E, H and L are also 8-bit and are called general purpose registers. They
are used as six 8-bit registers or as three 16-bit register pairs i.e. BC, DE and HL
5. ALU
 Used whenever arithmetic processing or logical operations are required.
 The results of such ALU operations are normally placed in the Accumulator.
6. Flag register or Status register.
 It contains 5 status bits (or flags) used to indicate different states of the ALU.
 The five flags found in 8085 processor are:
(i) Sign flag (S)
 Is set to the condition of the most significant bit of the accumulator following the execution
of an arithmetic or logical instruction. These instruction use the MSB of data to represent the
sign of the number contained in the accumulator.
 A set sign flag (S = 1) represents a negative number whereas a reset sign flag
(S = 0) means a positive number
(ii) Auxiliary carry flag (AC)
 Indicates an overflow or carry out of bit 3 of the accumulator in the same manner a carry flag
indicates an overflow from bit 7.
 AC = 1 means a carry from bit 3 occurred while AC = 0 means no carry from bit 3
 This flag is commonly used in BCD arithmetic
(iii) Parity flag (P)
 Tests for the number of 1 bits in the accumulator
 If the accumulator holds an even number of 1„s, it is said that even parity exists and the flag
is set to 1 (P = 1).
 However if the accumulator holds an odd number of 1 s ( called odd parity ) the parity flag
is reset to 0 (P = 0)
(iv) Carry flag (CY)

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  Is set or reset by arithmetic operations.
 An overflow from an 8-bit addition will result in the carry flag bit being set to 1.
 In subtraction the carry flag acts as a „borrow‟ flag, indicating the minuend is less than the
subtrahend if the flag is set.
(v) Zero flag (Z)
 Used to indicate whether the results of the last operation is zero or not.
 The zero flag is set to 1 (Z=1) if the result is zero and reset (Z = 0) if the result is non-zero.

The flag/status register

B7 B6 B5 B4 B3 B2 B1 B0

S Z AC P CY

SIGN ZERO PARITY CARRY

AUXILLIARY
FLAG FLAG FLAG FLAG
CARRY FLAG

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3.3 INSTRUCTION SETS AND ASSEMBLY LANGUAGE PROGRAMMING
Essentially, there are three levels of programming namely;
1. Machine language
2. Assembly (low level) language
3. High level language
Machine language
 Is a list of or string of binary numbers (0’s and 1’s) which makes µP the instruction for the
process required. The microprocessor works in machine codes.
 This form of coding is tedious and error-prone for human operations. Therefore, machine
code programs are usually written in hexadecimal codes or by using symbolic notation
known as assembly language.
Assembly language
 Is a collection of mnemonics which represent the machine code instructions.
 Mnemonics are English-like commands which describe the action of each instruction in an
abbreviated form.
 These mnemonics are far more understandable to the human programmer e.g. MOV A, C
means move the data held in register C to register A.
 A computer programmer would normally write the whole of the proposed program in
mnemonic form and afterwards this would be coded into hexadecimal codes (machine codes)
for use by the computer as instructions.
 The process of converting the mnemonics into hexadecimal codes is called assembling the
program. Most microprocessors have an in built assembler.
High level language
 They are designed to be more readable by the person who is programming.
 They make use of statements as opposed to mnemonics (abbreviations). Examples are
BASIC, FORTRAN, PASCAL, COBOL etc.
 Before a high level language can be executed by the computer, it must be converted into a
suitable machine code. Two programs can be used to achieve this;

i) An interpreter
ii) A compiler

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Interpreter
This is a language translator that translates each high level instruction into the appropriate machine
code instruction as the program is running. It is common in BASIC.
Compiler
This translates the whole set of instructions into a machine code before the program runs.

INSTRUCTION SET
An instruction set is a collection of all the instructions available for a certain microprocessor.
Therefore when designing a program, the programmer is restricted to use the instructions provided
for that particular machine. Each microprocessor has its own unique set of instructions.
An instruction set provides information concerning each instruction which may be of use to the
programmer. This includes the following items;
1. Mnemonics: Abbreviations representing each instruction in the set.
2. Symbolic notation: A short hand method of representing the effect of executing an
instruction.
3. Op-codes: The actual machine codes for each instruction.
4. Flags: Shows which flags are affected and how they change in response to the execution of
each instruction.
5. Number of bytes: Allows programmer to determine the length of the program.
6. T-states: Gives the number of clock cycles required to execute each instruction.

Instruction format
Each instruction consists of two parts, an operation code (op-code)/mnemonic and an operand and
adopts the following general format;
Mnemonic operand1, operand2
Mnemonic/op-code consists of 2-6 characters which describe the action of each instruction in
abbreviated form.
An operand identifies data or the location of data that will be processed by the instruction and is
separated from the mnemonic by one or more spaces.
In principle, all instructions require two operands; one to define the source of data prior to
processing and the second to define the destination of the processed data.
e.g. MOV A, B

Mnemonic destination source

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 Instruction fields

Name/label Op-code (mnemonic) Operand Comment field

field field field
e.g. e.g.
START: MOV A, B ; Move the contents of register B to
register A
1-6 2-6
characters Characters As required

NB
The semicolon before the comment helps to recognize that what comes next is a comment. If the
semicolon (;) appears in the label field, the whole line is treated as a comment.

3.4 8085 INSTRUCTION SET

The 8085 microprocessor instruction set consists of 246 instructions. Intel Corporation groups these
instructions into the following functional categories;
1. Data transfer group
2. Arithmetic group
3. Logic group
4. Branch group
5. Stack, I/O, and machine control group
 The data transfer group of instructions moves data between registers or between memory
locations and registers. Included are moves, loads, stores, and exchanges.
 The arithmetic group of instructions performs adds, subtracts, increments, or decrements on
data in registers or memory.
 The logic group of instructions performs ANDs, ORs, XORs, compares,
rotates, or complements on data in registers or between memory and a register.
 The branch group of instructions initiates conditional or unconditional jumps, calls, returns,
and restarts.

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  The stack, I/O, and machine control group includes instructions for maintaining the stack,
reading from input ports, writing to output ports, setting and reading interrupt masks, and
setting and clearing flags.

1
3.4.1 8085 DATA TRANSFER INSTRUCTIONS
• A summary of the 8080/8085 microprocessor’s data
transfer instructions is shown in Fig. 8-17.
• These instructions include move, exchange, load, and
store operations.
• Figure 8-17 gives only the mnemonic and
hexadecimal op code for these 84 instructions.
• Data transfer instructions are among the most widely
used of all microprocessor instructions.
1

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2

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3

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5

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8

10

13

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11

15

12

17

19

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14

21

15

23

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1 3.4.2 8085 ARITHMETIC INSTRUCTIONS

• A summary of the 8080/8085 microprocessor’s

arithmetic instructions is shown in Fig. 8-22.

• These instructions include add, add with carry,

subtract, subtract with borrow, increment, decrement,
and decimal adjust accumulator operations.

• Only the mnemonic and op codes for the arithmetic

instructions are given in Fig. 8-22.
1

2
• This group of instructions performs arithmetic
operations on data in registers and memory.
• Unless indicated otherwise, all instructions in this
group affect the zero (Z), sign (S), parity (F), carry
(CY), and auxiliary carry (AC) flags.
• All subtraction operations are performed via 2s
complement arithmetic and set the carry flag to 1 to
indicate a borrow and clear it to indicate no borrow.
• Refer to Fig. 8-18 for meanings of abbreviations used
in the following descriptions from the Intel User‟s 2

Manual.

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3
FIG. 8-22 SUMMARY OF 8080/8085 ARITHMETIC INSTRUCTIONS

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5
e.g. ADD B

(B) + (A) = (A)

IF;
B = F5H = 1111 0101
A = C2H = 1100 0010
THEN, AFTER ADD B INSTRUCTION WE HAVE;
F5 + C2 = 1 B7H = 1 1011 0111
HENCE, A = 1011 0111
AND CY = 1
5

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 ADI F5H
(A ) + DATA
8 (A) + F5 = (A)
IF A = 23H = 0010 0011
THEN ADI F5H
= 23H + F5H
= 1 18H
A = 18H = 0001 1000
CY = 1
10

10
ADC B
e.g. (A) + (B) + (CY)
If
A = 25H, B = 3DH, CY = 1
= 25+3D+1
= 64H

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11

11

12

12

13

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14

15

15

16

SUI 57H

• (A) – DATA
• (A) – 57H = (A)

17

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17

18

18

21

19

22

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20
INR C
IF C = 65H
THEN
INR C
C = 66H

23

21

25

24
e.g. INX B
Means:
(BC) + 1
LET BC = FF05H
i.e. B =FF, C= 05
AFTER INX B
THEN BC = FF06H
i.e. B = FF, C = 06
28

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26

29

27

30

28
e.g.
1. DAD B
This means;
(HL) + (BC)

2. DAD D
Means;
(HL) + (DE)

31

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 32

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1
3.4.3 8085 BRANCH INSTRUCTIONS
• A summary of the 8080/8085 microprocessor’s branch
instructions is shown in Fig. 8-32.
• These include jump, call, return, and restart
instructions. Only Intel’s mnemonics and op-codes are
listed for each instruction in Fig. 8-32.
• This group of instructions alters the normal sequential
program flow.
• The two types of branch instructions are unconditional
and conditional.
• Unconditional transfers simply perform the specified
operation on the program counter.
• Conditional transfers examine the status of one of the
four MPU flags to determine whether the specified
branch is to be executed.
• The conditions that may be specified are listed in the
Intel User’s Manual as follows:

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4

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6

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8

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10

11

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1 3.4.4 8085 LOGICAL INSTRUCTIONS
• A summary of the 8080/8085 microprocessor’s logical
instructions is shown in Fig. 8-28. These includes AND,
OR, XOR, compare, rotate, and complement
instructions.
• Only Intel’s mnemonics and op-codes are listed for each
instruction in Fig. 8-28. As in the previous section, the
Logical group of instructions will be detailed using Intel’s
corporationown format.
• This group of instructions performs logical (Boolean)
operations on data in registers and memory and on
flags. Refer to Fig. 8-18 for meanings of abbreviations
used in the following descriptions from the Intel User’s
Manual.

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4 …………………………………………………
…………………………………………………
…………………………………………………
…………………………………………………
…………………………………………………
…………………………………………………
…………………………………………………
…………………………………………………
………………………………………………….

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7

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10

11

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12

13

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14

15

16

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17

18

19

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1
3.4.5 8085 STACK, I/0 AND MACHINE CONTROL
INSTRUCTIONS
• A summary of the 8080/8085 microprocessor’s stack, I/O,
and machine control instructions is shown in Fig. 8-37.
• These include push and pop, input and output, exchange,
interrupt enables and disables, no operation and halts, and
multiple-purpose read and set interrupt mask instructions.
• As in the previous sections, the stack, I/O, and machine
control group of instructions will be detailed using Intel
Corporation’s own format.
• This group of instructions performs inputs and outputs,
manipulates the stack, and alters internal control flags.
• Refer to Fig. 8-18 for meanings of abbreviations used in the
following descriptions from the Intel User’s Manual.

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2

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4

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5

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9

10

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11

12

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13

14

15

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SUMMARIZED 8080/8085 INSTRUCTION SET
OP OP OP OP OP OP
CODE MNEMONIC CODE MNEMONIC CODE MNEMONIC CODE MNEMONIC CODE MNEMONIC CODE MNEMONIC

00 NOP 2B DCX H 56 MOV D, M 81 ADD C AC XRA H D7 RST 2

01 LXI B, D16 2C INR L 57 MOV D, A 82 ADD D AD XRA L D8 RC
02 STAX 2D DCR L 58 MOV E, B 83 ADD E AE XRA M D9 -
03 INX B 2E MVI L, DB 59 MOV E, C 84 ADD H AF XRA A DA JC Adr
04 INR B 2F CMA 5A MOV E, D 85 ADD L B0 ORA B DB IN D8
05 DCR B 30 SIM 5B MOV E, E 86 ADD M B1 ORA C DC CC Adr
06 MVI B, DB 31 LXI SP, D16 5C MOV E, H 87 ADD A B2 ORA D DD -
07 RLC 32 STA Adr 5D MOV E, L 88 ADC B B3 ORA E DE SBI D8
08 -- 33 INX SP 5E MOV E, M 89 ADC C B4 ORA H DF RST 3
09 DAD B 34 INR M 5F MOV E, A 8A ADC D B5 ORA L E0 RPO
0A LDAX B 35 DCR M 60 MOV H, B 8B ADC E B6 ORA M E1 POP H
0B DCX B 36 MVI M, D8 61 MOV H, C 8C ADC H B7 ORA A E2 JPO Adr
0C INR C 37 STC 62 MOV H, D 8D ADC L B8 CMP B E3 XTHL
0D DCR C 38 -- 63 MOV H, E 8E ADC M B9 CMP C E4 CPO Adr
0E MVI C, D8 39 DAD SP 64 MOV H, H 8F ADC A BA CMP D E5 PUSH H
0F RRC 3A LDA Adr 65 MOV H, L 8G SUB B BB CMP E E6 ANI D8
10 -- 3B DCX SP 66 MOV H, M 91 SUB C BC CMP H E7 RST 4
11 LXI D, D16 3C INR A 67 MOV H, A 92 SUB D BD CMP L E8 RPE
12 STAX 3D DCR A 68 MOV L, B 93 SUB E BE CMP M E9 PCHL
13 INX D 3E MVI A, DB 69 MOV L, C 94 SUB H BF CMP A EA JPE Adr
14 INR D 3F CMC 6A MOV L, D 95 SUB L C0 RNZ EB XCHG
15 DCR B 40 MOV B, B 6B MOV L, E 96 SUB M C1 POP B EC CPE Adr
16 MVI B, DB 41 MOV B, C 6C MOV L, H 97 SUB A C2 JNZ Adr ED -
17 RAL 42 MOV B, D 6D MOV L, L 98 SBB B C3 JNP Adr EE XRI D8
18 -- 43 MOV B, E 6E MOV L, M 99 SBB C C4 CNZ Adr EF RST 5
19 DAD D 44 MOV B, H 6F MOV L, A 9A SBB D C5 PUSH B F0 RP
1A LDAX D 45 MOV B, L 70 MOV M, B 9B SBB E C6 ADI D8 F1 POP PSW
1B DCX D 46 MOV B, M 71 MOV M, C 9C SBB H C7 RST 0 F2 JP Adr
1B INR E 47 MOV B, A 72 MOV M, D 9D SBB L C8 RZ F3 DI
1D DRC E 48 MOV C, B 73 MOV M, E 9E SBB M C9 RET Adr F4 CP Adr
1E MVI E, D8 49 MOV C, C 74 MOV M, H 9F SBB A CA JZ F5 PUSH PSW
1F RAR 4A MOV C, D 75 MOV M, L A0 ANA B CB - F6 ORI D8
20 RIM 4B MOV C, E 76 HLT A1 ANA C CC CZ Adr F7 RST 6
21 LXI H, D16 4C MOV C, H 77 MOV M, A A2 ANA D CD CALL Adr F8 RM
22 SHLD Adr 4D MOV C, L 78 MOV A, B A3 ANA E CE ACI D8 F9 SPHL
23 INX H 4E MOV C, M 79 MOV A, C A4 ANA H CF RST 1 FA JM Adr
24 INR H 4F MOV C, A 7A MOV A, D A5 ANA L D0 RNC FB EI
25 DCR H 50 MOV D, B 7B MOV A, E A6 ANA M D1 POP D FC CM Adr
26 MVI H, D8 51 MOV D, C 7C MOV A, H A7 ANA A D2 JNC Adr FD -
27 DAA 52 MOV D, D 7D MOV A, L A8 XRA B D3 OUT D8 FE CPI D8
28 -- 53 MOV D, E 7E MOV A, M A9 XRA C D4 CNC Adr FF RST 7
29 DAD H 54 MOV D, H 7F MOV A, A AA XRA D D5 PUSH D
2A LHLD Adr 55 MOV D, L 80 ADD B AB XRA E D6 SUI D8

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3.5 ADDRESSING MODES OR ADDRESSING METHODS
Addressing modes refers to methods of specifying the address of the data to be used in an
instruction. Popular addressing modes include;
1. Immediate
2. Implied
3. Direct
4. Page zero
5. Register
6. Indirect
7. Indexed
8. Relative
Immediate addressing
Description: The data to be operated on is specified in the instruction itself. The data is stored in the
memory location immediately after the op-code byte.
Example:
1. MVI A, data
Memory
Content Address

3E 2000H

data 2001H

2. LXI H, data
Memory
Content Address

21 2000H
Lower order
data byte 2001H

Higher order 2002H

data byte

Length: Instructions employing immediate addressing are either 2-bytes long (e.g. MVI A, data) or
3-bytes long (e.g. LX H, data) i.e.
MVI A, data OR LXI H, data

Op-code destination 1-byte data

Op-code destination 2-bytes data

Note
In cases where an „X‟ appears in the middle of an instruction (mnemonic), it should be interpreted as
meaning „register pair‟.

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Implied addressing or inherent addressing
Description: The instructions using this mode have no operands. The op-code itself specifies or
implies the required address.
Example: STC
Length: instructions using this mode are 1-byte long
e.g. STC – op-code 37

Direct/Extended/Absolute addressing
Description: Instructions using this mode specify the address of an operand in the instruction itself
i.e. the address is part of the instruction.
Example:
1. LDA, 20BCH - Load the accumulator with the contents of memory location 20BCH.
(A) (20BC)

2. STA 20BDH - Store the contents of the accumulator in the memory location 20BDH
(20BD) (A)

3. LHLD 20ABH - Load H and L registers from the two consecutive memory locations
(L) (20AB)
beginning at 20ABH.
(H) (20AC)

Length: Instructions using this mode are 3-bytes long, with the first byte as the op-code and the
second and third bytes giving the address (the low-order byte of the address is byte 2 and the high-
order address byte is byte 3) e.g. LDA, 2035H.

Memory
Content Address

BYTE 1 3A 2000

BYTE 2 35 2001

20 2002
BYTE 3

Page zero addressing:

Description: Page zero is the first page of the memory of a computer. Thus page zero starts at 0000H
and ends at 00FFH. Hence the most significant byte of an address in page zero is 00H. To address
any location on page zero (using page zero addressing), it is only necessary to specify the least
significant byte of the address. Thus an instruction using page zero addressing is only 2-bytes long
(the first byte being the op-code and the second byte being the address within page zero).

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Example:
STA 2CH - Store the contents of the accumulator in the memory location 002CH.
Length: Instructions using page zero are only 2-bytes long. Since this type of instruction is one byte
shorter than equivalent direct addressing instructions, it takes µP less memory space and is faster in
execution.
Register addressing/register direct addressing
Description: This mode of addressing specifies a register or register pair that contains data. It is
generally the same as direct addressing except that the location referred to in the instruction is a
register other than a memory location.
Example:
1. MOV B, C
2. ADD D
3. SBB E
Length: Instructions using this mode are 1-byte long.

Indirect addressing
Description: In this mode of addressing, the address of the data rather than the data itself is in the
memory location specified by the instruction. There are several ways of implementing indirect
addressing and the 8085 microprocessor uses register indirect addressing.
Register indirect addressing.
In this mode of addressing, the address referred to in the instruction is either contained in a 16-bit
register or in a register pair i.e. the instruction contains a register or register pair which stores the
address of data.
Example:
1. LDAX B - Load the accumulator with the contents of the memory location specified by
the contents of the register pair B and C.
2. STAX D - Store the contents of the accumulator in the memory location whose address
is specified by the contents of register pair D and E.
Length: Instructions using this mode are 1-byte long

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Indexed addressing mode
Description: In this mode, a base address is stored in an index register within the register array of the
CPU (8085 does not have an index register but Z80, 6502, 6800 and many others do). The location
referred to by the instruction (known as the effective address) is displaced from the base address by
an amount known as the displacement or offset. The displacement is an 8-bit number represented in
2‟s complement form. This allows the effective address to be displaced from the base address either
by a positive amount in the range 00H to 7FH (corresponding to 0 to +127 in decimal) or by a
negative number in the range FFH to 80H (corresponding to -1 to -128 in decimal). The
displacement is added to the low byte of the index register and carry produced by the addition is
ignored.
Example:
If the index register stores address 2005H and the displacement is 09H, the effective address
referred to by the instruction is:
2005H + 09H = 200EH
If the displacement is FCH (i.e. -4 in decimal) the effective address is;
2005H + FCH = 2001H
Note
The carry produced by the lower byte of the above addition is ignored i.e. 05H + FCH = 01H plus
carry which is ignored.
Relative addressing
Description: this is similar to indexed addressing but the base address to which the displacement is
added to give the effective address is the contents of the program counter (PC) i.e. the effective
address is given by;
Content of PC + displacement
Note
This addressing mode is not available in the 8085 microprocessor but is found in many other
microprocessors including the Z80 and 6502.

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4.0 TOOLS USED IN ASSEMBLY LANGUAGE PROGRAMMING

1] THE ASSEMBLER
An assembly language program cannot be executed by a machine directly as it is not in binary form
[machine language]. Usually we refer to such a program as a source program. A program is needed
in order to translate an assembly language [source] program into the object code executable by the
machine. The program that does all this is called an assembler.
Several types of assemblers are available the most common are;
1] One-pass assemble
2] two-pass assemble
3] Macro assemble
4] Cross-assemble
5] Resident assemble
6] Meta assemble

One-pass assembler.
In one pass assembler the source code is processed only once. As the source code is processed, any
labels encountered are given an address and stored in a table. Therefore when the label is
encountered again the assembler may look backwards to find the address of the label. If the label
has not been defined yet the assembler issues an error message.
Since only one pass is used to translate the source code a one-pass assembler is very fast.

Two-Pass Assembler
The two-pass assembler is similar in operation to the one pass with one major difference i.e the first
pass made through the source code is specifically for the purpose of assigning an address to all
labels. When the labels have been stored in a table with the appropriate addresses a second pass is
made to actually translate the source code into machine code.

Macro-Assembler
A macro assembler is a type of two pass assembler that allows the programmer to write the source
code in a macro. Conditional assembly is also included in macro assemblers.

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Cross-Assembler
A cross assembler may be of any type already mentioned. The distinguishing feature of across
assembler is that it is not written in the same language used by the processor that will execute the
machine code generated by the assembler. Cross assemblers are usually written in high level
languages e.g. FORTRAN and then the assembler may be executed on another machine e.g.
Motorola 6800.

Resident-Assembler
Is almost the complete opposite of cross-assembler. It is written to run on the same machine that
will execute the source code.

Meta-Assembler
The most powerful assembler is the Meta assembler because it will support many micro-processors.
The programmer merely specifies at the start of the source code which microprocessor. The
assembler will translate the source code to the correct machine code.
NB
The output file from most assemblers is an object file is a code that may be confirmed to execute at
any address.

2] EDITOR
This is the program used to modify and create the files contain your own program and document A
good editor is display oriented i.e. a cursor that shows or marks your place in the file the editor has
commands to change ,delete or insert lines or character The two type of editors currently;

1] Line-Oriented editor
2] Character-Oriented editor

The main difference between the two is that line editor do not display any change in the file whereas
character editors will display the change. Character oriented editor are also called screen editor or
display editor.

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3] DEBUGGER
This is a program that removes the bugs/errors out of your program. The debugger provides an
interactive method of executing and debugging the program one or a few instructions at a time.
Debugging Techniques
Debugging a microprocessor based system may be divided into two categories:
(i) Software debugging
(ii) Hardware debugging
Both debugging processes are usually carried out separately from each other because software
debugging can be carried out on an emulator without having the final system hardware.
In a single-board microcomputer, techniques commonly used in debugging are:
i) Single-stepping technique
ii) Breakpoint technique
iii) Register examine/simulator program
a) Single step
A single-stepper facility makes use of a single-step key on a keyboard and allows the user to execute
the program being debugged one instruction at a time. Generally, a single step facility is built with a
hardwired logic circuit. As the single-step key is pushed, it is possible to observe addresses and
codes as they are executed. During debugging, it is usually helpful to examine the state of the data
bus, the address bus, the control bus and the status flags. By the single step technique, one can be
able to detect program faults such as;
i. Incorrect addresses
ii. Incorrect jumps
iii. Incorrect data
iv. Erroneous op-codes etc
The single step technique is useful for short programs.
b) Breakpoint
A breakpoint facility allows the user to execute a program in sections. The breakpoint can be set in a
program by using the RST instructions. When the execute key is pushed, the program is exeuted
until the breakpoint. The registers can then be examined for expected results. If that segment of the
program is found to be satisfactory, a second breakpoint can be set at another memory address to
debug the next segment of the program. With the breakpoint facility, you can isolate the segment of
the program with errors. Then that segment of the program can be debugged with single-step facility.

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There are two types of breakpoint systems:
(i) Hardware
(ii) Software
Hardware breakpoint
The hardware breakpoint uses hardware to monitor the system address bus and detect when the
system reaches the desired breakpoint location. When the breakpoint is detected, the hardware uses
the processor control lines to either halt the processor for inspection or cause the processor to
execute an interrupt to a breakpoint routine. Hardware breakpoints can be used to debug both ROM
and RAM based programs.
Software breakpoints
Software breakpoints only operate on a system with the program in RAM because the breakpoint
instruction must be inserted into the program that is to be executed.
Note
Most debuggers combine single-stepper and breakpoint facilities to provide a complete package. The
user may insert a breakpoint at a desired point and let the program execute until that point. When the
program stops at the breakpoint, the user may use a single stepper to examine it one instruction at a
time.
c) Register examine/simulator
A simulator is a program that allows the execution of a program while observing the contents of the
registers of the target processor. When appropriate keys are pressed, the contents of the registers can
be displayed. The simulator operates by taking one instruction at a time and then simulating all
actions that the target processor would perform for that instruction.
Simulators are usually very large programs which will include all the software debugging tools
(single-stepper, breakpoint etc) necessary in a complete software development program.

4] LINKER, RELOCATORS AND LOADER.

Large programs are best broken down into „modules‟ i.e. separate parts that can be edited ,assembled
or compiled and debugged separately. A linker is a program that gets together all the modules
contained in a program. Once the modules are put together a program called a relocator assigns a
location in memory to each module and then a loader gets it into memory.

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5] LABLES
When a programmer is writing a program containing jump instruction, he does not always know the
absolute address in memory where the instruction is stored. Therefore it is usual for a programmer to
use „symbolic address name‟ or „labels‟ to indicate the intended addresses of the destination
instruction and it is only during the translation process that these are converted to absolute addresses
as shown below.

ADDRESSES: SYMBOLIC INSTRUCTION

(Assigned during translation process)
LAB 1:Destination Instruction
JMP LAB 1 ; Branch to instruction with
; address (symbolic) LAB 1
JMP LAB 2 ; Branch to instruct with
; Symbolic address LAB 2
LAB 2: Destination instruction

Normally the symbolic names used for labels are a mix of alpha – numeric names by the
programmer e.g. REPEAT, START, RESULT, BEGIN, LOOP, SUM, NUM etc

6] ASSEMBLY DIRECTIVES (Pseudo instructions)

An assembly language program can‟t be executed by a machine directly as it is not in binary form.
Usually we refer to an assembly language program as a source program. An assembler is needed in
order to translate an assembly language program into the object code executable by the machine.
Pseudo instructions (pseudo codes) are instructions which are not directly translated into machine
language (object code) but are used as special instructions to the assembler (directives) to perform
special function.
The assembler will recognize pseudo instructions that assign memory space, assign addresses to
labels, format the pages of the source code etc. The pseudo instruction is usually placed in the op-
code field. If any label or data are required by the pseudo instruction, they are placed in the label or
operand field as necessary.

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Common pseudo instructions
a) Origin (ORG)
The ORG instruction is used by the programmer when it is necessary to place the program in a
particular location in memory. It informs the assembler about the start address or origin of the
program.
For example, if it is desired to have a subroutine at a particular location in memory such as 2000H,
the ORG statement would be placed immediately before the subroutine to direct the assembler to
alter the program counter.
ORG 2000H ; set program counter to 2000H.
SUB: MVI A, 05H ; subroutine puts 05H in A.
RET ; return to caller.
Note
Most assemblers will assume a starting address of 0000H if no ORG statement is given in the source
code.
b) Equate (EQU)
The EQU instruction is used to assign the data value or address in the operand field to the label in
the label field. The EQU instruction is important because it allows the programmer to write the
source code in symbolic form and be concerned with the numeric value needed. In some cases, the
programmer develops a program without knowing the actual address or data required by the
hardware. The program may be written and debugged in symbolic form and the actual data added at
a later time.
Using the EQU instruction is also helpful when a data value is used several times in a program. If for
example a counter value was loaded at ten different locations in a program, a symbolic label (such as
„COUNT‟) could be used and the label „COUNT‟ defined at the end of the program.
Example.
PORT A: EQU 00 ; assign a dummy value
PORT B: EQU 00 ; another dummy value
MVI A, FFH ; data to be sent to output
OUT PORT A ; send data to port A
OUT PORT B ; and port B too
NOTE: In the above example, the programmer does not know the hardware address of output ports
A and B, but may still write the program. When the port addresses are known, they may be used to
replace 00 in the EQU instruction.

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c) Define byte (DB)
The DB instruction is used to set a memory location to a specific data value. The DB instruction is
usually used to create data tables or to presser a flag value used in the program. As the name implies,
the DB instruction is used to create an 8-bit value
For example, if a table of four values 45H, 34H, 25H and D3H is to be created at address 2000H, the
following code could be written.
ORG 2000H ; set table address
TABLE: DB 44H, 34H, 25H, D3H ; preset table values

NOTE
The commas are necessary for the assembler to differentiate between data values. When the code is
assembled, the machine code would appear as follows;
2000…….44
2001…….34
2002…….25
2003…….D3
d) Define storage (DS)
This instruction reserves or allocates memory locations for storage of temporary data
e.g. ORG 1800H
TEMP1: DS 2
This reserves 2 bytes of memory at locations starting from 1800H

7] MACRO
A macro is a sequence of instruction that the programmer gives a name. Whenever the programmer
wishes to duplicate the sequence of instruction, the macro name is inserted in the source code. The
macro routine is not the same as a subroutine „call‟ in assembly language. An assembly language
call is a function of the microprocessor. When a macro is used it is a function of the assembler and
not the micro-processor. Every time the macro name is encountered in the source file a block of
instructions (macro) is assembled.

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5.0 INTERRUPTS
An interrupt is a signal (which may either be generated by the computer hardware or produced by an
instruction) that causes the computer to temporarily suspend or interrupt the normal sequence of
operations and transfer control to an „‟ interrupt routine‟‟ (see purpose of interrupt)
There two forms of interrupt namely:
1. Non – mask able interrupts
2. Mask able interrupts

Non – mask able interrupt

Is one that cannot be „‟disabled‟‟ by means of an instruction in the program. This type of interrupt is
used to handle situations of the highest priority e.g. power supply failure situations. It is received on
the processor‟s NMI pin (in the case of the 8085 CPU this is the TRAP pin or RST 4.5).
When a non- maskable interrupt occurs, the CPU interrupts the operation of the main program and
transfers control to an interrupt routine (which has the same general form as a subroutine ) which
deals with the interrupt. In case of a power supply interrupt the CPU „saves „ the contents of vital
locations in RAM that has battery back- µP. This ensures that the data is retained until the power
supply is restored

Maskable interrupt
Is one that can be “masked out‟‟ by means of an instruction in the program. Maskable interrupts
usually handle situations that are less catastrophic than those associated with non- maskable
interrupts. The 8085 has three maskable hardware interrupt lines on the chip – RST 7.5, RST 6.5 and
RST 5.5. It has 8 other maskable interrupts (which may be either software or hardware ) – RST 0 ,
RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7.

NB
A maskable interrupt is received on the processors INTR pin. The processor does not recognize a
maskable interrupt unless the interrupt flag (IF) is set or enabled. In 8085it is the EI (enable
interrupt) instruction (op-code FBH) that enables the IF. However, if either the interrupt flag has not
been set or if the interrupt flag has been disabled by means of a DI (disable interrupt) or if the
interrupt has been masked out by means of an instruction in the program the interrupt is ignored.

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Typical Interrupt Handling Sequence
When an interrupt request is made by a peripheral on one of the interrupt pins on the CPU chip the
following takes place:
1. The interrupt flag is disabled – This prevents the interrupt routine from being interrupted. At
the same time the return address to the main program is pushed on to the stack:
2. The address of the first instruction in the interrupt routine is transferred to the program
counter – This ensures that the next instruction to be executed is the first instruction in the
interrupt routine
3. The CPU executes the program in the main interrupt routine.
4. After execution of the interrupt routine the interrupts are enabled again. This is where the
interrupt flag is re- enabled by means of EI (Enabled Interrupt) instruction.
5. Unconditional Return is made by means of RET instruction it results in the return address
(which was pushed into the stack) being popped into the program counter. This ensures an
orderly return to the main program

Main program
Save CPU status

InterrµPt here Join interrµPt

routine

Restore CPU status

Main program
continues

Re-enable interrµPts

Return from interrµPt

- 66 -
5.1 8085 interrupts
The interrupt instructions are known as restart instructions (RST) since the interrupt causes the CPU
to be restarted at a specific vectored address as shown in the table below.
Interrupt Op-code Vector address
RST 0 C7 0000H
RST 1 CF 0008H
RST 2 D7 0010H
RST 3 DF 0018H
RST 4 E7 0020H
RST 4.5 (TRAP) Hardware 0024H
RST 5 EF 0028H
RST 5.5 Hardware 002CH
RST 6 F7 0030H
RST 6.5 Hardware 0034H
RST 7 FF 0038H
RST 7.5 Hardware 003CH

8085 has a total of four hardware interrupts and eight software interrupts. Each of the software
interrupts RST 0,1,2,3,4,5,6 and 7 can be accessed either by means of a software instruction having
the op-code listed in table above, or can be accessed when a logic „1‟ signal is applied by an
interrupting device on the INTR ( interrupt request) pin of the CPU. When the signal is received by
the CPU it sends out a logic „0‟ on the INTA (interrupt acknowledge) control bus line to
acknowledge the interrupt request. In response to the logic „0‟ on the INTA line the interrupting
device places the op-code of required RST instruction on to the data bus. For example if the
interrupting device wishes to vector the CPU to the address corresponding to the RST 6 interrupt it
places the hex value F7 on to the data bus at this time This causes the CPU to transfer control or to
vector control to address 0030H.
Purpose of Interrupts
The purpose of an interrupt is to allow peripheral devices to suspend the CPU operations in an
orderly manner and force the CPU to start peripheral service routine. Usually the service routine is
involved in the exchange of data or status and control of information between the CPU and
peripheral. Once the service routine is completed, the CPU return to operations from it was
interrupted

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N.B.
1. Servicing means identifying what kind of signals or operations are required
2. The ability to interrupt can be disabled

Events occurring during interrupt

a) There is an interrupt request signal by the I/O device
b) Interrupt acknowledgement: signal to the peripheral device after completing the current
instruction
c) Status saving: the mp saves the program counter (PC) contents for next instruction in the
main program
d) Peripheral identification: the mp must identify the requesting interrupting device
e) Servicing the peripheral: depending on the peripheral it is serviced by going to a service
routine
f) Restoration: the mp reloads back registers to their original values
g) Resumes main program

Multiple Interrupt (Identifying the interrupting device)

Two design issues arise in implementing interrupt I/O. First because there will be multiple I/O
devices how does the processor determine which device issued the interrupt secondly if multiple
interrupts occurs how does the processor decide which one to process several techniques are used to
accomplish this.

1. Multiple interrupt lines

2. Software pull
3. Daisy chain (hard ware pull vectored)

Multiple Interrupt Lines

 In this technique multiple interrupt lines are provided between the processor and the I/O
device.
 However it is impractical to dedicate many bus lines or processor pins to interrupt lines
consequently even if multiple lines are used it is likely that each line will have several I/O
devices attached to it.
 Thus one of the other techniques must be used on each line

- 68 -
Software Polling
 In this technique when the processor detects an interrupt it branches to an interrupt service
routine whose job is to poll each I/O device to determine which device caused the interrupt.
 During software polling the processor reads the status register of each I/O module to identify
the interrupting device
 Once the correct module is identified the processor branches to a specific service routine for
that device.

Advantage of polling
1] Require less interfacing hardware
2] It is synchronous because it is under program

Disadvantage
1] It requires extensive software
2] It is time consuming i.e. waste MPU time
3] If many devices must be polled it takes a lot of time to respond to an I/O device in
need of service.

Daisy Chain
 This is in effect a hardware poll.
 All I/O modules share a common interrupt request line.
 The interrupt acknowledge line is daisy chained through the modules.
 When the processor senses an interrupt it sends out an interrupt acknowledge signal. This
signal is propagated through a series of I/O modules unit it gets to a requesting module. The
requesting module responds by placing a word on the data bus. This word is referred to as
a vector the processor uses this vector as a pointer to the device.
 This technique is called a vectored interrupt.

Advantage of daisy chain over polling

1] They have fast response time
2] They have better usage of MPU time
3] They require less software.

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Disadvantage
1] They are asynchronous in operation
2] They require more extensive hardware

Interrupt PRIORITIZATION
- With multiple lines the processor just picks the interrupt line with the highest priority.
- With soft ware polling the order in which modules are polled determines their priority.
- On a daisy chain the order of the device /modules determines their priority.

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6.0 INTERFACES
Input /output data transfer movement always requires interrelated hardware and software facilities.
The hardware facility allows the microprocessor to be interfaced to the outside world. An interface is
a device dividing two zones operating under different conditions. Interfacing is therefore a matching
function. In a complete microprocessor system, the interface device connects the microprocessor
system to the peripheral world and organizes the data transferred to and from the peripheral devices
so that it may be assimilated by the computer system.
An interface is a special circuitry which fits into the gap between the processor and the peripheral.
The interface is connected to the processor‟s data bus, address bus and control bus and passes
information between the processor and the peripheral.
The interface unit has both an input and an output port. These ports are made µP of data storage
registers that hold the information being transferred to or from the peripheral device. Each port has
it‟s own address which is determined by the address decoding logic.

Functions performed by the interfaces

d) Address decoding or I/O selection.
This means that the interface must respond in a desired fashion when it is addressed by the processor
and not respond at any other time. This is accomplished by use of logic gates connected to the
address bus. These gates generate a signal which is used to access an interface whenever its
identifying address appears on the bus. The interface itself must include an enable input to which
this signal is connected.
e) Speed matching.
The interface must match the speed of the microprocessor with that of the peripheral. The
microprocessor operates on a sub-microsecond scale while most peripherals operate in a much
slower time frame. This matching is accomplished with flip-flops and registers contained within the
interface chip.
f) Level conversion.
The interface matches the microprocessor‟s signal characteristics to the requirements of the
peripheral. The peripheral may need a different voltage from that the processor provides or it may
present a large load to be driven directly by the processor.
The processor in turn requires a very specific range of input signals from the peripheral if it is to
operate properly. The interface must satisfy these needs by converting between the two categories of
signals.

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N.B.
Other functions include:
g) Analog-to-digital and digital-to-analog conversion,
h) Converting between the microprocessors parallel signals and an external serial signals,
i) Detecting errors etc.

6.1 FORMATS FOR DATA TRANSFER

When data is transferred between the computer and a peripheral it may be transmitted in two
different ways;
1] Parallel data transfer
2] Serial data transfer

1] PARALLEL DATA TRANSFER

The bits are transferred simultaneously often one byte at a time.

The parallel format is used when a high data transfer rate is desired.
A parallel peripheral device provides a path for transferring binary information in parallel.

Peripheral data bus

Computer Peripheral address bus Peripheral

Device
Peripheral control bus

I/O bus
When the peripherals are relatively close to the processor say within a few meters of it, the

interconnecting cables between the computer and the peripheral are short and their cost is small
however when the peripheral are a great distance from the processor this cost may become very high
and an alternative approach may be used.

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Parallel peripheral interface
It consists of ports. Each port has two registers an 8- bit I/O bus and a pair of lines called handshake
lines.

Data
Data bus buffers
Port A data register I/O bus

Port A control register Handshake lines

bus
Internal
Port B data register I/O bus

Port B control register Handshake lines

The information stored in the control register specifies the ports mode of operation. The port data
register is used for transferring data to and from the data bus and I/O bus. The microprocessor
initializes each port by transferring appropriate bits into a control register so as to define the mode of
operation of the port. In most cases each port can be placed in an input or output mode. In addition,
the port can be made to function in a variety of operating modes. Three operating modes found in
most interface chips are:

1. Direct transfer without handshake lines

2. Transfer with handshaking
3. Transfer with handshaking using interrupt.

Direct transfer mode

An interface is placed in a direct –transfer mode of operation when the device attached to the I/O bus
is always ready to transfer information. The handshake lines are not used in this case.
The direct transfer can operate in an input or output mode. In the input mode, a read operation
transfers the contents of the I/O bus to the microprocessor data bus. In the output mode, a write
operation transfers the contents of the data bus to the selected port data register.
Direct transfers are useful only if valid data can reside in the I/O bus for a long time. If I/O data can
be valid only for a short time, the interface must operate in the handshake mode.

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Handshaking mode
Handshaking refers to exchange of signals. Handshake lines are used to control the transfer between
two devices operating asynchronously with each other i.e. when they do not share a common clock.
The transfer with handshaking depends on whether the port is in an output or input mode.
In the output mode, the microprocessor writes a byte into the interface port data register. The
interface then enables output handshake line to inform the external device that a valid byte is
available on the I/O bus. When the external device accepts the byte from the I/O bus, it enables the
input handshake line. This sets a flag bit in the control register. The microprocessor reads the register
containing the flag bit to determine if the transfer was completed. If so, the microprocessor can write
a new byte into the data register of the interface chip.
In the input handshake mode, the external device places a byte on the I/O bus and enables the
interface input handshake line. The interface transfers the byte into its data register and also sets a
flag bit in the control register. The microprocessor reads the register containing the flag bit to
determine if an input transfer is requested. If the flag bit is set, the microprocessor reads the byte
from the port data register and clears the flag bit. The interface then informs the device attached to
the I/O bus, through the output handshake line that a new byte can now be accepted.

Interrupt mode
In the handshake mode, the microprocessor must periodically read the control register to check the
status of the flag bit. If there are a number of ports attached to the microprocessor it would be
necessary to poll them in succession to determine the ones that require a transfer. This is a time
consuming operation. It can be avoided by initializing the interface to operate in the interrupt mode.
Most commercial units provide a separate interrupt line for each port in the interface. Every time a
flag is set in the port, the interrupt request belonging to the port is automatically enabled to inform
the microprocessor that a transfer is to be initiated. The microprocessor responds to the interrupt
signal from the port that requested the action and transfers data to or from the interface port data
register.
NB
Special integrated circuits are available to support any peripheral device which one my need to
incorporate into a system for parallel data transfer. These IC‟s are called programmable interface
chips. They are programmable in order to make them universally useful e.g. Intel 8155 PIO
(programmable input-output), Motorola MC 6522 PIA (peripheral interface adapter) e.t.c

- 74 -
2] SERIAL DATA TRANSFER
When the high data transfer rate associated with the parallel format is not necessary, or when a
peripheral is a great distance from the computer, then a serial format may be used. With this format
data is transferred one bit at a time, over a single data line. Thus the interconnecting cables between
the peripheral and the computers are fewer than the corresponding cables required with the parallel
format. However, data transfers rate is considerably slower.
A practical serial transmission requires that the receiver be in synchronism with the transmitter in
order to sort out the message bits. Two timing problems must be resolved with serial data
transmission. The first is that of bit synchronization (the identification and separation of each
individual bit in the data stream). The other is that of word boundary identification, or the separation
of the individual bit-groups in the data stream. These problems are handled in either of the following
two ways.
1. Synchronous approach
2. Asynchronous approach

Synchronous mode
In the synchronous serial mode, the transmitter and receiver share a common clock. A
synchronizing agent between the receiver and transmitter called sync character is chosen. This is
accomplished by reserving a unique 8-bit pattern and assigning it as the sync character, when the
transmitter starts sending 8-bit characters, it sends a few sync characters first and then sends the
actual message with each clock pulse, the receiver checks the last eight bits received. If they do not
match the bits of the sync character, the receiver accepts one more bit, rejects the previous high
order bit, and checks again the last 8-bit received until a synch character is recognized. From here
on, the receiver counts every eight bits and accepts them as a single character. Moreover, when the
transmitter does not have any message characters to send, it sends a continuous string of sync
characters in this case the two units maintain synchronism while no meaningful message is being
communicated.

Asynchronous mode
The character transmitter and receiver do not share a common clock. At least two additional bits are
sent with each character. These additional bits are called start and stop bits e.g. a teletype unit
using an 8-byte character code sends 11 bits for each characters transmitted. The first bit is the start
bit. This is followed by the 8-bits of the character and then two stop bits. The first bit is always „0‟

- 75 -
and represents the start bit to indicate the beginning of a character. The receiver can detect the start
bit when the line goes from 1 to 0. After the 8-bits of he characters are received, the receiver checks
for two stop bits which are usually in the 1 state. After the two stop bits have been transmitted, the
line may go to 0, indicating a start bit for a new character. The line will stay in the 1-state if no
character follows immediately.

1 0 0 1 1 0 1 0
8-bit information
Start 2 stop bits
bit

Serial communication interface

Data bus Bus

buffers Transmitter Shift Transmitted
register register data

Control Transmitter Transmitter

Internal bus

register control & clock clock

Status Receiver control Receiver

register & clock clock

Receiver Shift Received data

register register

It functions both as a transmitter and receiver and can be programmed to function in a variety of
modes. The interface is initialized for a particular serial transfer mode by means of a control byte
which is loaded into its control register. The transmitter register accepts a data byte from the
microprocessor through the data bus. This byte is transferred to a shift register for serial
transmission. The receiver portion receives serial information into another shift register for serial
transmission. When a complete data byte is accumulated, it is transferred to the receiver register. The
microprocessor can select the receiver register to read the byte through the data bus. The bits in the
status register are used to set input and output flags and to detect certain errors that may occur during
the transmission.

- 76 -
6.2 8156/8155 PIO
 The 8156 PIO has a 2048 (2k) bit static RAM organized as 256 words of 8 bits each. This means
it can store 256 bytes.
 The PIO has three ports that can be programmed to act as input or output ports.
 The address-data pins of the 8155/8156 PIO (AD0-AD7) are connected to the address-data bus
of the 8085 microprocessor.
Note
The only difference between 8155 and 8156 PIOs is that in 8155, the chip enable (CE) signal is low
while in 8156, the CE is high.

8156 PIN DIAGRAM

PC3 1 40 VCC
PC4 2 39 PC2

TIMER 3 38 PC1
RESE 4 37 PC0
PC5 5 36 PB7
6 35 PB6
IO/ 7 34 PB5
CE 8 33 PB4
9 32 PB3
10 8156 31 PB2
11 30
ALE PIO PB1
AD0 12 29 PB0
AD1 13 28 PA7
AD2 14 27 PA6
AD3 15 26 PA5
AD4 16 25 PA4
AD5 17 24 PA3
AD6 18 23 PA2
AD7 19 22 PA1
VSS 20 21 PA0

PORT A - 8 Data bus (PA0 – PA7)

PORT B - 8 Data bus (PB0 – PB7)

PORT C - 6 Data bus (PC0 – PC5)

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8085-8156 INTERFACE
IO/ IO/

A13 CE

8085 AD AD 8156
microprocessor
AD1 AD1

AD0 AD0

ALE ALE

AD3-AD7 AD3-AD7

Address-data bus AD0-AD7 is the same as A8-A15. Thus AD0-AD2 will be A8-A10. These are
used for decoding the port addresses. A13 is used as a chip enable while A11, A12, A14 and A15 are
unused (don‟t care- assume zero).
Therefore port addresses are;

A15 A14 A13 A12 A11 A10 A9 A8 PORT SELECTED ADDRESS

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

0 0 1 0 0 0 0 0 CSR 20H
0 0 1 0 0 0 0 1 PORT A 21H
0 0 1 0 0 0 1 0 PORT B 22H
0 0 1 0 0 0 1 1 PORT C 23H
0 0 1 0 0 1 0 0 TIMER LOWER PORT 24H
0 0 1 0 0 1 0 1 TIMER HIGHER PORT 25H

6.2.1 PORTS
8156 has three ports (Port A, Port B and Port C). To read data or write into these ports, IO/ must
be high. Each port has an internal register (PA, PB and PC) that latches data during an I/O operation.
Port A and Port B can latch 8-bit data each. Port C can however latch only 6-bit data. This is because
Port C is typically used for serial I/O or as a 6-bit parallel control port for handshaking to support
data transfer between the 8085 and an external device via Ports A and B.
Note
Handshaking means data transfer via exchange of control signals. Two bits (bits 2 and 3) of the CSR
are required t configure port C.

- 78 -
When using IN and OUT instructions, we have to include an immediate byte that specifies the port
address (port number) e.g. OUT 21H.
When IN or OUT instruction is executed, the 8085 duplicates the port number on the address bus
and on the address-data bus e.g. during OUT 21H, we have;
AD7 – AD0 = 0010 0001
A15 – A8 = 0010 0001
Besides ports A, B and C, 8156 contains a command and status register (CSR) and a timer. The CSR
determines whether the ports act as input or output ports (command word). It also contains
information about the status of the ports (status word). The timer is a 14-bit down counter used for
counting input pulses.

PROGRAMMING THE PORTS

The 8156 ports can be programmed as input or outputs by sending a command word to the command
and status register (CSR).
Command word
B B B B B B B B

PORT A definition 0 – Input

1 - Output
PORT B definition

PORT C definition

Enable PORT A 0 – Disable

1 - Enable
Enable PORT B interrupt
TIMER control

Timer control
B7 Effect
B6
00 No effect on timer
01 Stop timer if running
10 Stop timer immediately terminal count is reached
11 Start timer immediately

- 79 -
 Port c definition
B3 B2 Effect
00 Defines port C as an input port
11 Defines port C as an output port
Defines;
PC0 as port A interrupt
01 PC1 as port A buffer full
PC2 as port A strobe
PC3-PC5 as output bits
Defines;
PC0 as port A interrupt
PC1 as port A buffer full
10 PC2 as port A strobe
PC3 as port B interrupt
PC4 as port B buffer full
PC5 as port B strobe

Note
To send a command word to the command and status register, we use OUT 20H e.g. suppose we
want port A to be in input port and port B to be an output port. Then B0 must be 0 and B1 must be 1
and the rest can be zeros. To load the command register with this word, we use;
MVI A, 02H
OUT 20H
If we want port A to be input port and ports B and C to be output ports, we can initialize 8156 PIO
with the following instructions.
MVI A, 0EH
OUT 20H

Handshaking
Port C is complicated because it can act as an input, output or a handshaking port. When bits B3 and
B2 are 0 and 1 respectively, half of port C is used as a handshaking port and the other half as an
output port. When B3 and B2 is 1 and 0 respectively, port C provides handshaking for ports A and
B. Three handshaking bits are used for each port i.e. an interrupt, a buffer full and a strobe. This
allows the use of interrupt O/I with handshaking.

- 80 -
Status word
The CSR can be read using an IN 20H instruction. This transfers the content of the status register to
the accumulator. Figure below shows the bits of status word.
INTR INTE BF INTR INTE BF INTR
X TIMERR B B A
B A A

Interrupt pending at port A

Buffer full at port A

Interrupt enabled at port A

Interrupt pending at port B

Buffer full at port B

Interrupt enabled at port B

Interrupt TIMER
Don‟t care

e.g. suppose the execution of IN 20H produces accumulator contents of A = X1000111.

This means;
 A high terminal count has been reached
 Port B interrupt enabled
 Port B buffer empty
 No pending interrupt at port B
 Port A interrupt enabled
 Port A buffer full (valid data latched at port A awaiting an I/O transfer)
 A pending port A interrupt

Example 1
Show the instructions needed to make port A an input port, B an input port and C a full handshaking
port. The A and B interrupts should be enabled and the timer bits reset to 00.
Solution
We need a command word of;
00111010 =3AH
This will reset the timer bits to 00(bits 7 and 6), enable the A and B interrupts (bits 5 and 4), provide
hand shaking for A and B (bits 2 and 3), make B an output port (bit1) and A an output port (bit0). To
send this command to the command register, we use;
MVI A, 3AH
OUT 20H

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Example 2
Show an interrupt driven input circuit that handshakes with port A.

Solution
(a)
8085 8156
Peripheral
data data device
AD0 - PA0 - PA7
AD7

INTR BF A
A

(b)

BF A

INTR A

In figure (a), the peripheral device sends data (PA0-PA7) to port A of the 8156 which then sends the
data (AD0-AD7) to the 8085. Port C provides the handshaking bits (INTR A, BF A and )
Figure (b) is the timing diagram. First the peripheral device sends a low to the 8156. This
loads the peripheral data into port A via PA0-PA7 bus. The 8156 acknowledges receiving this data
by sending a high BF A back to the peripheral device.
A little later, the 8156 is ready to transfer data, so it sends a high INTR A to the RST 5.5 pin of the
8085. After the 8085 recognizes this interrupt, it branches to a service routine that includes the
instruction IN 22H. During the execution of this instruction, goes low, this transfers the data in
port A to the accumulator via the address-data bus. Then the remainder of the service routine is
completed.
Example 3
Show an interrupt driven output circuit that handshakes with port B.
Solution
(a)
8085 8156
Peripheral
data data device
AD0 - PA0 - PA7

INTR BF B
B

- 82 -
(b)
INTR B

BF

Figure (a) is the circuit while figure (b) is the timing diagram. The action begins when the 8156
sends a high INTR B to the 8085. After this has been recognized, the 8085 branches to a subroutine
that includes an OUT 22H instruction. During the execution of this instruction, goes low, this
transfers data from the accumulator to port B via the address-data bus. The INTR B then goes low,
indicating that the data has been received.
A little later, the 8186 sends a high BF B to the peripheral device. This transfers the data from port B
to the peripheral device via PB0-PB7 bus. To indicate that it has been received the data, the
peripheral device returns a low

PROGRAMMING THE TIMER

The timer is a 14-bit presettable down counter that counts the incoming TIMER IN pulses (pin 3). It
can be preset with any number between 0002H to 3FFFH. This preset number is called terminal
count. For instance, if the timer is preset with 00FFH, it will reach the terminal count after 255
pulses have been received at the TIMER IN pin.
Presetting the terminal count
As shown earlier, port 24H corresponds to the lower 8 bits of the timer while port 25H corresponds
to the upper 6 bits of the timer and the timer mode.

T7 T6 T5 T4 T3 T2 T1 T0 PORT 24H

LOWER 8

T7 T6 T5 T4 T3 T2 T1 T0 PORT 25H

UPPER 6

TIMER

- 83 -
Suppose we want to preset the terminal count to 00FFH, then these are the initializing instructions;
MVI A, FFH
OUT 24H
MVI A, 00H
OUT 25H
The first two instructions loads FFH to the lower 8 bits of the timer while the last two instructions
loads 00H to the upper 6 bits and the timer mode.
Timer mode
The output signal (pin 6) depends on the timer mode M2M1 as show in table below.

M2 M1 Effect

0 0 Single square wave

0 1 Continuous square wave

1 0 Single pulse

1 1 Continuous pulse

Figure below shows how the signals appear after each mode.

Start Terminal Terminal Terminal Terminal Terminal

count count count count count count

Mode 00

Mode 01

Mode 10

Mode 11

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Timer Command
Bits b7 and b6 of the command and status register (CSR) control the starting and stopping of the
timer as shown in table below.
B7 B6 Effect
0 0 No effect on timer
0 1 Stop timer immediately
1 0 Stop timer after terminal count is
reached
1 1 Start timer

For instance, suppose we want to start the timer, enable the port interrupts, make C and B output
ports and A an input port. Then we need a command word of;
Command word = 1111 1110
The initializing instructions are;
MVI A, FEH
OUT 20H
Example
The system clock is connected to the TIMER IN input of the 8156. The clock has a frequency of
3MHz. show a program segment that produces a continuous square wave with a frequency of 1 kHz.
Include a start timer command, disable the port interrupts, make C and B output and A an input port.
Solution
We have to divide the clock frequency by 3000 which is equivalent to OBB8H. By setting the
terminal count equal to 0BBH, we will get one square wave for cycle out for each 3,000 clock pulses
in. Therefore, the lower 8 bits of the terminal count are;
1011 1000
This is the lower byte to be loaded into port 24H.
The upper 6 bits of the terminal count are;
00 1011
The timer mode bits for a continuous square wave are;
M2M1 = 01
Therefore, port 25H must be loaded with;
0100 1011
The command word we need for port 20H is;

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 1100 1110

1 0 1 1 1 0 0 0 PORT 24H

0 1 0 0 1 0 1 1 PORT 25H

1 1 0 0 1 1 1 0 PORT 25H

Here is the program segment;

MVI A, B8H
OUT 24H
MVI A, 4BH
OUT 25H
MVI A, CEH
OUT 20H

- 86 -
7.0 I/O TECHNIQUES
The I/O operation is defined as transfer of data between the microcomputer system and the external
world. Whatever the application, a microprocessor system must be able to accept data from an input
peripheral device and transfer data processed within the CPU to an output peripheral e.g. printer.
This input /output data transfer movement will always require interrelated hardware and software
facilities. The interface unit has both an input and an output port. These ports are made µP of data
storage registers that holds the information being transferred to or from the peripheral device.
There two ways of addressing an I/O Port
1] Standard I/O (I/O-mapped I/O or isolated I/O)
2] Memory-mapped I/O.

7.1 I/O-MAPPED I/O

This refers to a configuration in which the I/O circuitry has it’s own address space separate from
that of the memory. The number of I/O location in any computer system is very much smaller than
the memory locations. So the I/O address space is always smaller than the memory address space.
The I/O-mapped I/O typically utilizes a control pin on the processor chip commonly called the M/IO
control signal. A high on this pin indicates a memory operation whereas a low indicates an I/O
operation.

Address bus

Data bus

M/IO MEMORY
MPU
I/O

R/W

MEM MEM Interface 1 Interface

1 N N

Peripheral Peripheral
device 1 device N

- 87 -
7.2 MEMORY-MAPPED I/O
In this form of accessing the interface the I/O circuit shares the same address space of the processor
with the memory. This approach is illustrated in the figure below.

Address bus

Data bus

MPU

R/W

MEM MEM Interface 1 Interface

1 N N

Peripheral Peripheral
device 1 device N

Since the interface circuit look exactly like memory locations to the processor any of the regular
instruction which operate upon the contents of memory location can be brought to bear upon the I/O
device.

Advantages of memory –mapped I/O

 Since the I/O addresses are configured as memory address, one can use all the processor
instructions that reference memory address for the I/O port. This means that one can perform
arithmetic and logic operation and many other functions on port data.

Disadvantages of memory I/O

 Memory mapped I/O interface circuits occupy apportion of the memory address space which
would be available for memory. This reduces the size of memory.
 In memory mapped I/O 3-byte instruction are used namely LDA and STA as follows;
LDA address; 3-byte instruction for inputting a byte into accumulator.
STA address; 3-byte instruction for outputting data from accumulator into a specified
port.

- 88 -
Advantages of I/O-mapped I/O
 Typically uses 2-byte instructions namely IN and OUT as follows;
IN port; 2-byte instruction for inputting data from specified port into accumulator.
OUT port; 2 byte instruction for outputting data from accumulator into specified I/O port.

Disadvantages
 In order to perform operation on port data one must move the data into accumulator first.

- 89 -
7.3 METHODS OF I/O DATA TRANSFER
Typically there are three main ways of transferring data between microcomputer and the external
device.
1] Programmed I/O
2] Interrupt I/O
3] Direct memory access.

Programmed I/O
Using this technique the processor executes a program to perform all data transfer between the
computer system and the external devices via the I/O port the program tell the peripheral interface
exactly what to do and when to do it. The main characteristic is that the external device carries out
the function as dictated by the program inside the computer system i.e. the microprocessor
completely controls all the transfer.
Program control is the slowest although it requires the least amount of interface logic to implement
with this method the programmer has complete control over the entire process hence it is also easiest
method to test and debug.

Interrupt I/O
In programmed I/O when peripheral is not ready for data transfer then the processor must wait. In
system with several peripherals of this type, the time spent waiting is often not tolerable. There may
be other more important things which the processor should be doing rather than waiting for
peripherals. In such cases an alternative is to use interrupt I/O.
With interrupt I/O, the peripheral initiates the transfer of data. It does this by signaling to the
processor its readiness through a special input to the processor called an interrupt pin (INT). The
external I/O device is connected to this pin. When the device wants to communicate with
microprocessor, it makes the signal on the interrupt pin HIGH or LOW (depending on the
microprocessor). In response the microprocessor completes the current instruction and pushes the
current contents of the PC into the stack so that the processor will know where to return after
completion of the I/O operation.
The processor then turns off the interrupt system so that it can execute instructions with no
additional interrupt occurring. Then it branches to the beginning of a special program written by user
the called an interrupt service routine.

- 90 -
The interrupt service routine is the program the external device wants the microprocessor to execute
in order to transfer data. The interrupt service routine transfers data or otherwise services the
peripheral in accordance with it‟s needs. Upon completion of the service routine, the processor POPs
the address which was saved/pushed into the stack onto the PC.

Direct Memory Access (DMA)

Programmed I/O and interrupt I/O provide data transfer between the processor and external devices.
However there are various instance when data must be moved between memory and external device
e.g. between a mass storage device and RAM. This can be handled in two ways:
The first method uses programmed I/O where the computer can be programmed to input data from
an I/O device. This means that the processor must fetch and execute instructions in order to carry out
the transfer. Thus the processor is involved in the data transfer.
The second method is called direct memory access [DMA] where data is transferred directly
between the peripheral and the memory (through the interface) without involving the micro-
processor.
With DMA, the peripheral device initiates the transfer by signaling the processor that it wishes to
take over control of the address and data buses. This signaling takes place over a special line called
bus request or DMA request (DMARQ). When the processor reaches a place in its sequence where it
can do so, it stops fetching and executing instructions. It then releases control of the buses and signal
the peripheral that it may now use them. The peripheral (through its interface) takes over the busses,
placing the required address and data on them and controls the transfer of data directly with memory
with no intervention from the processor. After completion of data transfer, it transfers control of the
system busses to the microprocessor.

Most processors support several alternatives for the timing of a DMA data transfer. These are:

1] Block Transfer (Burst Mode)

The peripheral takes over the buses for the duration of the transfer of an entire block of data. This is
the most common type of DMA used with microprocessor. This may result in large gaps of time
during which the processor is not executing instructions.

- 91 -
2] Cycle Stealing
The processor gives µP the bus for a memory cycle of DMA or at most a few such cycles. In this
technique the DMA controller transfers a byte of data between the peripheral and the memory by
„stealing‟ a clock cycle of the microprocessor. This is accomplished by not providing a clock signal
to the microprocessor. An INHIBIT signal is used for this purpose. This INHIBIT signal is normally
HIGH and is logically ANDed with the system clock to generate the microprocessors clock. The
DMA controller stops the microprocessor by lowering the INHIBIT signal to LOW. The DMA
controller then takes over the system buses for the time microprocessor is stopped.

3] Interleaved DMA (Transparent Mode)

Using this technique the DMA controller take over the system buses when the processor is not using
them e.g. when the microprocessor is doing ALU operations. One of the main characteristics of
interleaved DMA is that data transfer occurs without stopping the microprocessor.

- 92 -
8.0 SUBROUTINES
Introduction
When writing a program it is frequently necessary to repeat an operation which was performed in
another part of the program e.g. a time delay. The simplest solution to this problem would be to
repeat the entire routine on each occasion it is required. This is a rather wasteful approach, resulting
in a program which is larger than necessary and which contains several almost identical sections of
codes. A better approach would be to write each routine once only and call the function when
required. This may be achieved by writing the function as a subroutine.
Definition
A subroutine is a special program which performs some repetitive/ repeatedly needed tasks such as
searching, sorting etc and which may be called from any part of the main program.

If a commonly used function such as a time delay is coded as a subroutine, the time delay may be
accessed from any part of the program simply by calling the subroutine. This results in a shorter
program. Typically a subroutine can be written, assembled and tested separately.

Subroutine operation

Main program
Start of subroutine

Call
Subroutine body
subroutine

End of subroutine
Main
program
continues

 The execution of the program proceeds normally until the call subroutine instruction is
encountered.
 At this point, the address of the subroutine is placed into the program counter (PC) register,
causing a jump to the subroutine start address.
 At the same time, the microprocessor makes a note of the position reached in the main
program for later reference.

- 93 -
  The subroutine is then executed causing the required operation to be completed.
 The last instruction in the subroutine causes the microprocessor to return to the main program
at the point previously reached. This is called a RETurn Instruction (RET).
 The address of the instruction immediately following the subroutine is then placed back into
the program counter. This causes the main program to resume at the point previously
reached.
NOTE
Since the subroutine may be called from anywhere in the program, the microprocessor must keep a
record of the subroutine return address. This is the address of the next instruction after the call
subroutine instruction. The microprocessor uses a special area of RAM called the stack to store this
information.

EXAMPLE
For the 8085 microprocessor demonstrate how a simple time delay subroutine may be called from
the main program. Use a trace table to study the detailed operation of the program.

; Main program
ORG 4000H
CALL DELAY
HLT
; Subroutine
ORG 5000H
DELAY: MVI A, 03H
DCR A
JNZ LOOP
RET

 The (incomplete) main program contains a subroutine call to the label DELAY, which is
stored at address 5000H.
 The subroutine loads a start value (03H) into the accumulator which is then repeatedly
decremented.
 The RET instruction then returns control to the main program at which point the HALT
instruction is encountered.

- 94 -
Trace table
Address (PC) Instruction A
4000 CALL DELAY -
5000 MVI A , 03H 03
5002 DCR A 02
5003 JNZ LOOP 02
5002 DCR,A 01
5003 JNZ LOOP 01
5002 DCR A 00
5003 JNZ LOOP 00
5006 RET 00
4003 HLT 00

Advantages of using subroutines

1. Each subroutine may be individually tested and proved to work reliably. A library of
these proven subroutines may be built-µP and used in new projects.
2. The use of subroutines encourages modular program design; the problem may be broken
down into a series of sub tasks, which may then be further sub-divided. Many of these
tasks may be coded as subroutines, which since they can be individually tested, lead to a
more reliable final program. A program which has been developed in a modular fashion
may also be easier to read and understand.
3. As will be seen latter, it is possible to pass one or more parameters to a subroutine and
the subroutine may optionally return a result. This allows general purpose subroutines to
be developed e.g. a multiplication subroutines.
4. Since the subroutine exists only once in memory, this avoids the repetition of similar
sections of the program. The final program would be shorter and requires less storage
space.
Stack operations during a subroutine
 When a jump to a subroutine is made, the return address to the main program is stored onto
the stack. This is the address of the instruction immediately following the subroutine call.
 The return address is a 16-bit number which is stored in two memory locations on the stack.
The most significant byte is stored first followed by the least significant byte.

- 95 -
  When the return from subroutine is encountered this causes the two bytes on the top of the
stack to be removed and placed into the program counter. The least significant byte is
removed first followed by the most significant byte. This is illustrated below with reference
to the example above.
Before subroutine.
PC 4000 Stack (Empty)

During subroutine
PC 5000 Stack (return address) 03 LSB
40 MSB
After subroutine
PC 4003 Stack (Empty)
Subroutine calls and return from subroutine are usually handled by two special instructions namely
CALL and RET respectively. When the CALL instruction is executed, the current contents of the
PC are saved in the stack and the PC is loaded with the address of the first instruction in the
subroutine.
NOTE
 The current contents of the PC provide the address of the instruction that immediately
follows the CALL instruction. It is also called return address because this is the point where
execution of the calling program resumes after exiting the subroutine. Thus the CALL
instruction is equivalent to the following instruction sequence.
PUSH PC ; save return address in stack
JP ADDRESS ; branch to subroutine
 The RET instruction is usually the last instruction of the subroutine. When this instruction is
executed the return address previously saved in the stack is retrieved and is loaded into the
PC. Thus the control is transferred to the calling program. In concept, the RET instruction is
functionally equivalent to POP PC.

- 96 -
8.1 Nested subroutines
This is where one subroutine calls another subroutine as illustrated by figure below.

Main program
Subroutine Subroutine
“SUB1” “SUB2”

Call SUB1 Call SUB2

Return from
Return from Subroutine “SUB2”
Main program Subroutine “SUB1”
continues

In the above example the main program executes normally until a subroutine call to “SUB1” is
encountered. The return address to the main program is then stored into the stack and the first
subroutine begins to run.
At some point, a subroutine call to “SUB2” occurs which causes the return address to the first
subroutine to be stored in the stack. The return address to the first subroutine is the most recently
saved and is therefore on the top of the stack.
When the second subroutine finishes, the return from subroutine instruction causes the top two bytes
on the stack to be placed into the program counter. This causes the first subroutine to resume at the
instruction following the second subroutine call.
On completion of the first subroutine, the remaining two bytes are removed from the stack and
placed on to the program counter. At this point the main program resumes immediately after the first
subroutine call.
Figure below shows the content of the stack at each point in the nested subroutine.

SUB2

SUB1 SUB1 SUB1

MAIN PROGRAM (Before call SUB2) SUB1 (After SUB2) MAIN PROGRAM

(Before call SUB1) MAIN MAIN MAIN (After SUB1)

Empty MAIN MAIN MAIN Empty

- 97 -
NB
1. A subroutine must be called from the main program using a call subroutine or jump to
subroutine instruction e.g. CALL 3000H (means jump to subroutine at memory location
3000H)
2. The last instruction executed by the subroutine must be a return from subroutine (RET).
3. In order to implement subroutine nesting we need to retrieve the return addresses exactly in
the reverse order in which they were saved since the stack is a LIFO data structure.

8.2 Parameter passing

As mentioned before, subroutines are written to handle a specific task. One effective use of
subroutine calls is a method of transferring data from the calling program to the subroutine and vice
versa. This aspect is often referred to as the parameter or argument passing. For example, a time
delay subroutine which could produce several different delays based on an externally supplied
parameter. Some subroutines such as mathematical functions may also return a result tot the main
program.
There are several possible methods of passing parameters to and from subroutines.
1. Using registers: The main program may load the required parameters into one or more
registers before calling the subroutine. On completion of the subroutine, the result if any
could also be left in a register.
2. Using memory: An area of RAM called parameter block may be used by the main program
and the subroutine. The main program would write the required data in to the parameter
block before calling the subroutine. The subroutine would in turn place any results into the
parameter block for later use by the main program.
3. Using stack: Some applications such as high level languages may place parameters onto the
stack before calling a subroutine. The subroutine returns any result by placing them on the
stack before returning to the main program.

NB
Whichever of the above method is used, the program documentation must give adequate details of
any parameters used or returned by subroutine.

- 98 -
Example
For the 8085 microprocessor, write a double loop time delay program which accepts its start value
using a parameter. The parameter should be passed using one of the microprocessors registers. On
completion, the subroutine should return to the main program leaving all the data registers in their
initial state.
Solution
Assume that the subroutine will accept the parameters in register C and that it will use register B
internally. The program is therefore;
ORG 4000H ; origin is 4000H
MVI C, 05H ; parameter = 5
CALL DELAY ; jump to subroutine
HALT
DELAY: PUSH BC ; store B & C in the stack
LOOP1: MVI B, FFH ; inner loop
LOOP2: DCR B ; outer loop
JNZ LOOP2
DCR C
JNZ LOOP1
POP BC ; restore B & C
RET
 The above example includes a short main program. In this program, a parameter (5) is loaded
into register C before the subroutine is called.
 The subroutine uses registers B and C internally and so the BC register pair is PUSHed into
the stack before the main time delay starts. The original register contents are restored when
the BC register pair is POPed from the stack just before the return instruction.
 The inner loop repeatedly decrements register B while the outer loop decrements register C
which is the parameter passed by the main program. Once B and C are zero, the main
program resumes.

- 99 -
9.0 FAULT DIAGNOSIS
9.1 TROUBLE SHOOTING TREE

Start

Problem? NO
Leave it alone

YES

Indicator NO
Check Power supply
line ON?

YES

Indicator NO Check reset, Hold and

CoenOtiN
lin n?ue ready lines

YES

Free Run System

YES

Address NO Check faulty bus line

pattern
correct?

YES

continue
- 100 -
9.2 TYPICAL FAULTS IN MICROCOMPUTER BASED SYSTEMS
i) Chip failure
ii) Open circuit interconnection
iii) Short Circuit interconnection
iv) Externally Included interface
v) Software Bugs.

1. Chip Failure
Common failures include;
a) Input(s) open circuit
b) Input(s) shorted to ground
c) Two or more inputs shorted together
d) Output stuck high
e) Incorrect or partial operation due to internal open or short circuit
f) Sequential logic faults (wrong count, wrong reset etc)

2. Open Circuit interconnection

These faults cause a break in any signal or power. Typically sources of such faults include the
following;
a) Unsoldered or faulty soldered joints
b) Fracture of a printed circuit board
c) Faulty contact n a connector e.g. edge connector
d) Breaks in cables particularly at their point of attachment to the circuit and cable
Connector.

NOTE
Connectors are often a weak link in the chain particularly if of poor quality, subject to abuse or if
equipment is dismantled.

3. Bridging or short circuit Interconnection

Printed circuit tracks and assorted connections are much closer proximity to one with the result that
it becomes very easy to form bridging contacts. A major source of such unwanted contacts is surplus
solder.

- 101 -
4. Extremely induced interference
Since the signals in a microprocessor consists of sequence of pulses, it follows that any externally
induced pulses affect its operation, causing programs to “crash” since these pulse will be interpreted
by the system as valid signals. A practical solution to this problem is to remove such spikes before
they can enter the system by fitting filters in series with power supply to a microprocessor

5. Software Bugs
Bugs are logic errors. These errors may go undetected for months or even year only to become
apparent when a particular set of inputs or operating conditions are established which hitherto have
not been used. In fact when writing very complex programs it may not be feasible to test for every
possible combination of operating conditions and feedback from the software user become essential.

9.3 FAULT FIINDING TECHNIQUES

1. Visual Inspection
2. D.C Test
3. Oscilloscope

Visual Inspection
It may reveal the source of a fault and is certainly worth carrying out before attempting further
investigations. Simple faults such as loose connectors, ICs loose in their sockets or cracked PCB‟s
etc can easily be identified or noticed by visual inspection. Sometimes the temperature of a
component helps to isolate a fault e.g. voltage regulator which runs too hot or cool may indicate a
fault.
D.C Test
A multimeter is used to measure dc voltages or resistances. It is of limited use in microprocessor
based systems but may be satisfactory for checking power supplies to each device, short or open
inference circuit etc.
Oscilloscope
It is limited to those applications in which signals can be obtained e.g. Clock signals. Most of the
signals from the microprocessor are not and depend upon program being executed at that time. It‟s
applicable only when a microprocessor is made to generate repetitive signals e.g. by free running it
or running very short looping programs.
Examples of fault finding equipments in this technique are:

- 102 -
 i) Logic Probe
ii) Logic Pulser
iii) Logic Analyzer
iv) Logic comparator
v) Signature Analyzer
vi) Emulator
vii) Current tracer

LOGIC PROBE
This is a hand-held instrument which is used and detects „high‟ and „low‟ logic levels in types of
circuits including TTL and CMOS logic probes should be capable of detecting indicating „bad‟ logic
levels, open circuits and inputs. The method of indicating the detected levels varies. Some probes
e.g. HP 545A use a near the logic tip to give the following indications:
OFF - Below logic „o‟ threshold
DIM - A bad logic level or open – circuit
BRIGHT - above logic 1 threshold
FLASHING - pulsating input

lamp

Other types of logic probes use three different types of colored LEDs typically RED, YELLOW &
GREEN which gives the following indications;
GREEN - below logic „0 ‟threshold
RED only - above logic „1‟ threshold
RED & YELLOW - pulsing 1 to 0
GREEN & YELLOW - pulsing 0 to 1
RED, GREEN & YELLOW - square waves.

- 103 -
Logic pulser
It is used to stimulate digital circuits by injection of controlled pulses. A logic probe is often used to
determine the effect of stimulating a circuit as shown below:

CURRENT TRACER
It is used to locate the source of a low impedance path without the necessity of removing
components from the circuit. The tip is magnetically sensitive and is used to detect the magnetic
field which surrounds a conductor when carrying a current tracer must first be aligned with the
printed circuit track where tracing is to begin and its sensitivity control is adjusted so that the
indicator lamp glows.
The current tracer tip is then moved along the tracks and along all branches including off the track
until the source of abnormal current flow is detected.

LOGIC COMPARATOR
Needed for checking faulty nodes in digital circuits, often associated with faulty ICs .It compares a
known good or reference with the one suspected of being faulty.
The reference IC is connected in parallel with the faulty IC input pins. Each output of the reference
IC is Ex-ORed with the corresponding output of the IC under test.
A difference between only two corresponding outputs generates a logical 1level on the Ex-OR gate
output and this is used to activate an error indicator LED.
The main advantage is that testing is carried out at normal operating speeds without need to remove
the suspected IC from the circuit.

LOGIC ANALYZER
One problem associated with checking the operation of a microprocessor based system is that data
on the bus and control lines changes rapidly as the program is executed. Since the bus signals are
repetitive, a signal event may occur within one or two micro processor cycle and go undetected.

- 104 -
A logic analyzer allows the logic states of a bus and control signals to be captured at specified times
and stored in a first –in first –out (FIFO) format/memory.

a) Trigger word
The point in a program where data capture starts or finishes must be selected by the user. This is
achieved by setting up a “trigger word” in the logic analyzer which is compared with the incoming
data. The trigger word may contain „don‟t cares‟(x) which enable data with unknown elements to be
specified. Once a match is found between the incoming the trigger word, data capture continues for a
predetermined number of clock pulses and is then terminated. This arrangement allows the user to
study events leading up to the trigger point as well as those immediately following it.

b) FIFO Memory
The data storage provided by logic analyzers organized as a first-in-first-out (FIFO) memory which
has typically 1024 to 2048 storage locations each 32 bits wide. Some logic analyzer allows this
memory to store be re-figured by the user to obtain a larger number of storage but of reduced width.
Each of the 32 bits of a word used to store the instantaneous logic state of a bus FIFO
simultaneously using either internally generated or externally derived clock signals.
As each data word is clocked into the FIFO, all previously captured data is shifted one place to make
room new data. The data word shifted out from the opposite end of the FIFO is lost. Therefore at any
instant, the FIFO contains a record of the logic states on the bus and control lines during the last
1024 or 2048 clock periods.

c) Clock signals
A logic analyzer may be told at which instants to capture data from the bus and control lines.
Therefore a clock signals is used data into the FIFO memory. A high speed asynchronous clock
signal with user selectable frequencies may be generated by the logic analyzer itself. This type of
clock can operate at much higher frequencies than are used in the system under test, thus enabling a
logic analyzer to perform high speed sampling of signals for solving hardware, logic and timing
problems.
A low speed synchronous clock is obtained from the system under test using such signals such as
RD, WR, MREQ, IORQ etc as the source. This type of clock signal is useful for debugging software
and the user may select which edge of the clock is used to transfer data into the memory.

- 105 -
d) Display Format
The output from the FIFO memory may be formatted by a logic analyzer to provide one of the
following user selectable displays
i) List or state
ii) Timing
iii) Disassembly

i) State Display
A list or state display shows the contents of a logic analyzer memory as a sequence of binary, octal,
decimal or hexadecimal codes. Often display of ASCII equivalent is provided for easier
identification of certain words.
ii) Timing Display
A timing display allows data captured from a limited number of channels to be displayed in correct
time as sequence as digital waveforms. Since the waveforms are constructed from the data stored in
memory, they do not represent the true shape of the original waveforms and are used for timing
comparisons only.
iii) Disassembly
Many logic analyzers allow captured data to be displayed as disassembled assembly language
mnemonics. For each different type of microprocessor supported, a logic analyzer requires addition
of a personality module or and through installation of associated software. The pod simply clips into
the microprocessor making all the necessary connections.

SIGNATURE ANALYZER
Signature analysis is a technique designed to simplify fault location on complex microprocessor
based systems. With the location on complexities of modern equipments, a manufacturer may often
adapt a modular form of construction in order to simplify testing and subsequent fault location. The
major advantage of this approach is that it requires a large number of connectors which add to the
cost of equipment and provide additional source of possible faults.
A circuit provided is marked up with appropriate waveforms and voltages obtained from the
equipment under test may b compared with those on the circuit diagram until discrepancy is found,
thus enabling the faulty component to be located.

- 106 -
Deriving Signatures
Signatures are digital information t any point in the circuit. They are taken at different points of the
act and are compared with the correct signature which is printed on the circuit diagram. Any
discrepancies should lea the technician to the sources of the trouble.

The bit sequences being measured are added into the feedback before being clocked into the shift
register. The effect of this is that some bits are inverted before being clocked into the shift register
depending on what has happened previously. The bit stream may be any length but only the residue
in the shift register at the end of the measurement is used. These 16 bits displayed in hexadecimal
are the signature of the measured data stream.
For the 1st eight periods (0-7), the circuit performs as an ordinary shift register but at period 7, the
1st „1‟ of the sequence has reached the ist tap of the shift register. The result of this is that the next
input bit which s a logical „0‟ is inverted before being clocked into the shift register. This process
continues until the end of the measurement when the 16- bit residue remaining is
1101100101010011

Taking Signature
In order to take signatures, a signature analyzer requires START and STOP signals. A Clock signals
is also required, and those signals are obtained from the circuit under test. At points defined in the
service manual. Typical points for obtaining these START and STOP signals are the high order
address lines while the clock may be obtained from the „RED‟ or „WRITE‟ lines or from chip
selects.

- 107 -
REVISION QUESTIONS AND ANSWERS

1. What is the size of the memory address space for the microprocessors given in Table 12.1

Table 12.1

Microprocessor Data bus Width Address bus Width

8030A 8-bit 16-bit

6800 8-bit 16-bit
8086 16-bit 20-bit
9900 16-bit 16-bit
Z8000 16-bit 23-bit

SOLUTION
The memory address space is given by
M = 2p
Where, P is the address bus width.
The memory address space for the µPs is given in Table 12.2

Table 12.2

Microprocessor Memory address space

8080A 64Kbytes
6800 64K bytes
8086 1M bytes
9900 64K bytes
Z8000 8M bytes

2. How many different instructions are possible in an 8-bit microprocessor? Compare this
number with the number of instructions of 8085.

SOLUTION

The number of distinct combination of 8 bits

Words = 28 = 256

Therefore, the total number of instruction codes, assuming single byte op code = 256

The total number of instruction codes in 8085µP is 246

- 108 -
3. For a particular 8085 microprocessor based system it is required to use 2K bytes of
EPROM and 4K bytes of RAM. Assume 2142 RAMs and 2716 EPROMs are available.

a) Find the number of RAM and EPROM chips required.

b) Connect the memory chips to the microprocessor and show all the connections clearly. Make
suitable assumptions whenever required.
c) Find the addresses of EPROMs and RAMs and express them in hex notation.

SOLUTION

(a) 2142 is a 1024 x 4 bits RAM

Therefore 4 K bytes = 4 K x 8 bits
= (1K x 4) x (4 x 2)bits
=4x2
= 8 chips
2716 is a 2K x 8 bits EPROM. Therefore, only one 2716 chip is required.

(b) Let the first 2K bytes be in EPROM and next 4K bytes be in the RAMs.
The relevant connections are shown in the Fig. 12.1. Other connections are indicated
below;
A0-A10 from µP to A0-A10 of 2716

A0-A9 from µP to A0-A9 of each of 2142

CS2 of each 2142 to Vcc

WR from µP to WE of each 2142

RD from µP to OD of each 2142

A8-A15

WR
A10 A0 0
8085 RD TO CS 0F 2716
A11 A1
A12 A2 1
AD0-AD7

2 TO CS 0F RAM SET

ALE TO CS OF RAM SET 2

3
8205
8212 TO CS 0F RAM SET 3
4
TO CS 0F RAM SET 4
CLR
5
DS2 MD
A13 E1
A14 E2 6

DS1
A15 E3
7

(a) (b)

+vcc
Fig 12.1

- 109 -
(c) The address of various chips are given in table 12.3.

Table 12.3
Memory chips Starting address Last address
EPROM 0000H 07FFH
RAM pair 1 0800H 0BFFH
RAM pair 2 0C00H 0FFFH
RAM pair 3 1000H 13FFH
RAM pair 4 1400H 17FFH

4. It is desired to clear the accumulator of 8085. Explain the possible instructions for this purpose.

SOLUTION

(i) MVI A, 00H ;Load accumulator with Zero

(ii) SUB A, ;Subtract A from A
(iii) ANI 00H ;AND A with Zero
(iv) XRA A ;A EX- OR A

5. Write a set of instructions to check a register pair of 8085 µP for Zero content.

SOLUTION

Let us consider the B-C pair. The following set of instructions will set the Zero flag if the
content of B-C pair is Zero.

MOV A, C
ORA B ; OR C with B
JZ TEST ; Jump to TEST if Z=1

6. Write a program for 8085 to complement the bytes stored in locations 0F00H through 0FFFH
and store them in locations starting from 1F00H.

SOLUTION

Let D-E and H-L pair be pointers to source and destination memory locations respectively.
The program is given below:

LXI D, 0F00 H ; Initialise source pointer

LXI H, 1F00 H ; Initialise destination pointer
LXI B, 100H ; Initialize counter
LOOP: LDAX D ; Load A with contents of source memory
CMA ; Complement A
MOV M, A ; store in destination memory
INX D ; increment pointers
INX H
DCX B ; Decrement counter
MOV A, C ; Check counter for Zero
ORA B
JNZ LOOP
- 110 -
 HLT
7. Calculate the memory requirement for the program of Q6.

SOLUTION
From instruction set, we obtain the number of bytes for each instruction. The total bytes
required are:
Bytes = 3+3+3+1+1+1+1+1+1+1+1+3+1 = 21

8. Calculate the time required to execute of Program of Q6. Assume T state time as 320 ns.

SOLUTION

From instruction set, we obtain the number of T states for each instruction.
The total number of T states, TS, is given by;

TS =10+10+10+N x (7+4+7+6+6+6+4+4) + (N-1) x 10+7+5

Where N is the number of times the instructions in the Do loop are executed. It is 100H=256
in this case. The JNZ condition is true for (N-1) times and during Nth time the control comes
out of LOOP, where the numbers of T states are 10 and 7 respectively

Therefore, Ts =30+256 x 44+255 x10+7+5= 13856

The total time = Number of T states x Time of 1 T state
=13856 x 320ns
=4433920ns

9. Write a program for 8085 to find the larger of the two numbers stored in the locations 0A02H and
0A01H and store it in memory location 0A02H.

SOLUTION

The program is given below:

LXI H, 0A02H ; Store destination address in H-L pair

LDA 0A00H ; Load A with first number
MOV B, A ; Transfer to B
LDA 0A00H ; Load A with first number
CMP B ; Compare A and B
JZ FINIS ; Go to FINISH if the two numbers are equal
JC GREAT ; If CY=1, (A) < (B)
MOV M, A ; Otherwise (A) > (B)
JMP FINIS
GREAT: MOV M, B
FINISH: HLT

10. Write a program to clear memory location 01A0H in an 8085 microprocessor system.

SOLUTION
The following instructions will clear the memory location.
LXI H, 01A0H
- 111 -
 MVI M, 00H
11. Write a program to find the smallest element in a block of 8–bit unsigned binary data, whose
number is stored in memory location A001H, and the data are stored in memory locations
beginning from A002H. Store the smallest number in memory locations FF00H. The µP used is
8085;

SOLUTION
LXI H, A001H ; Initialize pointer
MOV C, M ; Get the number of bytes in C
INX H ; Increase Pointer by 1
START: MOV A, M ; get a byte of data in A
REP: DCR C
JZ STOP ; stop at the end of data
INX H
CMP M ; Compare
JC REP ; If (A) < (M), try next number
JMP START
STOP: STA FF00H ; Store the smallest element
END

12. It is desired to mask (set to 0) the most significant four bits in the accumulator.
Suggest an instruction to accomplish this in an 8085µP system.

SOLUTION

ANI OFH

13. An 8085 program is given below. Find the task performed by this program.

START: LXI H, BUFR

MVI C, 0BH
LOOP: DCR C
JZ FINIS
MOV M, A
INX H
JMP LOOP
FINIS: MOV B, A

SOLUTION
The operation performed by each instruction is given below:
START: LXI H, BUFR ; Initialize H-L pair with address BUFR
MOV C, OBH ; Initialize counter with decimal 11
LOOP: DCR C ; Decrease counter by one
JZ FINIS ; Go to FINIS if counter=0
IN DATA ; Input a byte from a DATA port
MOV M, A ; Move the byte to memory location pointed to by H-L
INX H ; Advantage the pointer by one
JMP LOOP ; Go to loop
FINISH: MOV B, A ; Move the contents of A to B

- 112 -
 The operation performed by the program is to input 10 bytes from input port ‘DATA’ and
store them in memory location starting from BUFR.
14. Find the memory requirement of the 8085 µP program below:

LXI B, 2475H
LXI D, 3794H
LDAX B
MOV L, A
LDAX D
STAX B
MOV A, L
STAX D

SOLUTION

From instruction set, we obtain, the number of bytes as

N = 3+3+1+1+1+1+1+1=12 bytes

15. Assume that the accumulator contains 08H and register B contains 93H (both in BCD format).
Find the contents of the accumulator after ADD B instruction is executed. Is the result a valid
BCD number? If not, what should be done to obtain the result in BCD format? Explain clearly.

SOLUTION

(A) = 0000 1000

(B) = 1001 0011

ADD, B 1001 1011

The result is not a valid BCD number. ADD B instruction must be followed by DAA
instruction. The effect of this is given below:

1001 1011
0000 0110 ; Add 06H because the least significant bits do not represent a valid BCD digit

10000 0001 = 101H

16. The contents of some memory locations of an 8085 µP based system are shown in the fig 12.2
What will be the content of H-L pair after the execution of the program given below:

LHLD 3000H
MOV E, M
INX H
MOV D, M
LDAX D
MOV L,A
INX D
LDAX D
MOV H, A

- 113 -
 Memory address memory contents
(Hex) (Hex)

3000 02
3001 30
3002 00
3003 30

Fig. 12.2

 The first instruction will load L & H registers 02H and 30H respectively.
 The second instruction will copy the contents of the memory location 3002H in register E, i.e.
register E will be loaded with 00.
 The third and fourth instruction will load the D register with 30H (the contents of memory
location 3003H). Now the DE pair contains 3000H.
 The instruction LDAX D will load the accumulator with 02H and the next instruction will
change the contents of the register L to 02H.
 The last three instructions will make the contents of H register 30H, i.e. the contents of H
register will remain the same. Therefore, now the H-L pair contains 3002H.

17. The first four instructions of an interrupt service subroutine are

PUSH B
PUSH D
PUSH H
PUSH PSW

What will be the last six instructions of the subroutine? Explain clearly.

SOLUTION

The last six instructions will be;

POP PSW
POP H
POP D
POP B
EI
RET

Here it is assumed that the interrupts are kept disabled during the execution of the subroutines.

18. Write an 8085program to convert a decimal digit in memory location 00F0H to an ASCII
character and store it in memory location 00F1H. If the memory location 00F0H does not
contain a decimal digit an ASCII question mark should be placed in the memory location

- 114 -
 00F1H.

SOLUTION

The ASCII code for decimal 0 is 0110000 and for ? is 0111111. The program is given below;

LXL H, 00F1H
LDA 00F0H
CPI 0AH
JNC QUE
ADI 30B
MOV M, A
JMP STOP
QUE: MVI M, 3FH
STOP: END

19. Consider a keypad with eight keys marked 0 through 7. It is interfaced with an 8085µP based
controller. Each key is associated with a function that the controller carries out when the key is
pressed. Whenever any key is pressed, an encoder associated with the key pad gives an 8-bit
binary output corresponding with the key pressed, for example, when key number 4 is pressed,
the output of the encoder is 00000100. Assume the address of the port to which the key pad is
connected AH. Write the program segment to implement it.

SOLUTION

Assume a table containing bytes in contiguous memory location starting from address
TABLE. This table contain the eight branching addresses corresponding to eight
functions. The required program segment is given below.

LXI H, TABLE ; Load H-L pair (pointer) to the start of table

IN 0AH ; Input encoded binary number
RLC ; Multiply by two
MOV C, A ; Create offset Corresponding
MVI B, 0 ; to the key pressed
DAD B ; Add offset
MOV E, M ; Transfer the address
INX H ; of jump location
MOV D. M ; to D.E pair
XCHG ; Exchange H-L and D-E pairs
PCHL ; Jump to the function routine

20.It is required to ascertain whether a 2 K x 8 EPROM is completely erased or not after it is

exposed to UV radiation. When erased, the contents of the EPROM are logic 1. An LED display
should be ON to indicate complete erasure and another LED should be ON in case it is not
completely erased. Write a routine to perform this task. Use 8085 µP.

SOLUTION

- 115 -
 Let the EPROM under test to be plugged into a socket with 2K (2048 =0800H) locations
starting at address ‘EPROM’. Let the two LEDs be connected to port DISP at bit 0 and 1
locations respectively to indicate complete erasure or incomplete erasure. The program is
given below:

START: XRA A ; Clear accumulator

OUT DISP ; Clear LED display
LXI H, EPROM ; Load H-L with starting EPROM address
LXI B, 0800H ; initialise counter for 2K
TEST: MVI A, FFH ; Load with one’s
CMP M
JNZ NER ; If not equal, test is complete
INX H
DCX B
MOV A, C ; test to a certain whether
ORA B ; All the locations have been tested
JNZ TEST
MVI A, 01H ; test Complete
JMP ERASE
NER: MVI A, O2H ; Set display to indicate not erased
ERASE: OUT DISP ; set display to indicate not erased erasure

21. Write a subroutine to create a delay of 2 ms using 8085 µP with T = 320 ns.

SOLUTION

The program is given below:

DELAY: LXI B, N ; initialise B-C

LOOP : DCX B
MOV A, B
ORA C
JNZ LOOP
OUT:

The value of N is to be calculated as follows:

The time required to execute this routine = [10 + N x (6+4+4) + (N-1) x10+7] x 320 ns

= (24N+7) x 320 x 10-9 = 2 m s

N = 260

22. Prepare a flow chart and write an ALP for 8085 µP which inputs 500 bytes from I/O device
connected to port 0AH and stores them in memory location starting from 2A00H if the data is
positive and from 3A00H if the data is negative.

SOLUTION

- 116 -
The flow-chart is given in Fig 12.3 and the assembly language program is given below.
Start

Initialize
registers

Input byte
from port

NO
Is
Byte
Positive?

YES
Store byte
Store byte

Increment
Increment address
address

Decrement
counter

NO Is
counter
= 0?

YES

End

Fig 12.3

BEGIN: LXI H, 500 ; move 500 H-L pair, which will be used as a counter
LXI B, 2A00H
LXI D, 3A00H ; move 3A00H to D-E pair
LOOP: IN 0AH ; Input byte from port OAH
ORA A ; Check its sign
JP PLUS ; If possible go to plus
STAX D ; store the contents of A at address specified by DE pair
INX D ; increment D-E pair by one
JMP CHECK ; Jump to CHECK
PLUS: STAX B ; Store the contents of A at address specified by BC pair
INX B ; Increment B-C pair by one
CHECK: DCX H ; Decrement H-L pair by 1
MOV A, H ; move contents of H to A
ORA L ; OR the contents with contents of L
JNZ LOOP ; If not Zero, jump to LOOP

- 117 -
 END ; END of mainline

23. Write a subroutine to shift left the contents of H-L pair by 1 bit as shown in figure below.
Write ALP using this subroutine to multiply an 8-bit number by 16. Assume 8085 µP.

CY H L 0

SOLUTION

SHIFT: STC ; Set the carry flag

CMC ; and reset it
MOV A, L ; Move the contents of L to A
RAL ; Rotate accumulator left through carry
MOV L, A ; Move the contents of A to L
MOV A, H ; Move the contents of A to H
RAL ; Rotate accumulate left through carry
MOV H, A ; Move contents of A to H
RET ; Return to maintain
END ; End of the subroutine

Let the 8-bit number be X. The multiplication program is given below.

BEGIN: MVI L, X ; Move the number to L

MVI H, 00H ; Clear H
CALL SHIFT ; 4 Bits left shift is equivalent to
CALL SHIFT ; multiplying the number by 16
CALL SHIFT
CALL SHIFT
END ; End of program

The result is in H-L pair

24 Write an ALP for 8085 µP to find the series SUM (SUM = 1+ 2 + 3 +…+ 10 ).Using;
(a) INR instruction and no DCR instruction and
(b) DCR instruction and no INR instruction.

SOLUTION

(a) SUM: DS 1 ; reserve one byte for the result

MVI B, 01H ; Initialise B to 1
MVI C, 00H ; Initialize C to 0
LOOP: MOV A, C
ADD B
INR B
MOV C, A
MOV A, B
CPI OBH
JNZ LOOP
MOV A, C
- 118 -
 STA SUM
END
(b) SUM: DS 1
MVI A,00H
MVI B,0AH
AGAIN: ADD B
DCR B
JZ OUT
JMP AGAIN
OUT: STA SUM
END

25. Memory assemble the program of 24 (a) starting from memory location 2000H store in RAM
of 8085 µP kit and execute. Verify the validity of the program.

SOLUTION

Refer Appendix D.2 for the codes of various instructions. The program is hand assembled
and the codes are shown in table 12.4. The last code is for RST 1 which is used to transfer
control to the monitor. These codes are stored in the memory and the program is executed
starting from the memory location 2001H. The contents of memory location 2000H after
execution of the program = 37H = 5510

Table 12.4

Memory Location (Hex,) Codes (Hex.)

2000 -
2001 06
2002 01
2003 0E
2004 00
2005 79
2006 80
2007 04
2008 4F
2009 78
200A FE
200B 0B
200C C2
200D 05
200E 20
200F 79
2010 32
2011 00
2012 20
2013 CF

- 119 -
26. Execute the program of 25 in single step mode and observe the contents of PC registers
A,B,C and the flags after the execution of each instruction. Verify the effect of each
instruction on PC, A,B,C, and the flags. Find the contents of memory location 2000H at the
end of the execution of the program.

SOLUTION

The program is executed in single-step mode starting at address 2001H. The contents of PC,
A, B, C, flag (F) are examined after every step and are given in Table 12.5 in hexadecimal
format.

Table 12.5
Flags

PC A B C F S Z AC P CY
2000 - - -
2003 00 01 00 undefined .
2005 00 01 00 undefined no change .
2006 00 01 00 undefined no change .
2007 01 01 00 00 0 0 0 0 0
2008 01 02 00 00 0 0 0 0 0
2009 01 02 01 00 0 0 0 0 0
200A 02 02 01 00 0 0 0 0 0
200C 02 02 01 A1 1 0 0 0 1
2005 02 02 01 A1 1 0 0 0 1
2006 01 02 01 A1 1 0 0 0 1
2007 03 02 01 04 0 0 0 1 0
2008 03 03 01 04 0 0 0 1 0
2009 03 03 03 04 0 0 0 1 0
200A 03 03 03 04 0 0 0 1 0
200C 03 03 03 A1 1 0 0 0 1
2005 03 03 03 A1 1 0 0 0 1
2006 03 03 03 A1 1 0 0 0 1
2007 06 03 03 04 0 0 0 1 0
2008 06 04 03 00 0 0 0 0 0
2009 06 04 06 00 0 0 0 0 0
200A 04 04 06 00 0 0 0 0 0
200C 04 04 06 A5 1 0 0 1 1
2005 04 04 06 A5 1 0 0 1 1
2006 06 04 06 A5 1 0 0 1 1
2007 0A 04 06 04 0 0 0 1 0
2008 0A 05 06 04 0 0 0 1 0
2009 0A 05 0A 04 0 0 0 1 0
200A 05 05 0A 04 0 0 0 1 0
200C 05 05 0A 05 1 0 0 1 1
2005 05 05 0A 05 1 0 0 1 1
2006 0A 05 0A A5 1 0 0 1 1
2007 0F 05 0A 04 0 0 0 1 0

- 120 -
2008 0F 06 0A 04 0 0 0 1 0
2009 0F 06 0F 04 0 0 0 1 0
200A 06 06 0F 04 0 0 0 1 0
200C 06 06 0F A1 1 0 0 0 1
2005 06 06 0F A1 1 0 0 0 1
2006 0F 06 0F A1 1 0 0 0 1
2007 15 06 0F 10 0 0 1 0 0
2008 15 07 0F 00 0 0 0 0 0
2009 15 07 15 00 0 0 0 0 0
200A 07 07 15 00 0 0 0 0 0
200C 07 07 15 A5 1 0 0 1 1
2005 07 07 15 A5 1 0 0 1 1
2006 15 07 15 A5 1 0 0 1 1
2007 1C 07 15 00 0 0 0 0 1
2008 1C 08 15 00 0 0 0 0 0
2009 1C 08 1C 00 0 0 0 0 0
200A 08 08 1C 00 0 0 0 0 0
200C 08 08 1C A1 1 0 0 0 1
2005 08 08 1C A1 1 0 0 0 1
2006 1C 08 1C A1 1 0 0 0 1
2007 24 08 1C 14 0 0 1 1 0
2008 24 09 1C 04 0 0 0 1 0
2009 24 09 24 04 0 0 0 1 0
200A 09 09 24 04 0 0 0 1 0
200C 09 09 24 A1 1 0 0 0 1
2005 09 09 24 A1 1 0 0 0 1
2006 24 09 24 A1 1 0 0 0 1
2007 2D 09 24 04 0 0 0 1 0
2008 2D 0A 24 04 0 0 0 1 0
2009 2D 0A 2D 04 0 0 0 1 0
200A 0A 0A 2D 04 0 0 0 1 0
200C 0A 0A 2D A5 1 0 0 1 1
2005 0A 0A 2D A5 1 0 0 1 1
2006 2D 0A 2D A5 1 0 0 1 1
2007 37 0A 2D 10 0 0 1 0 0
2008 37 0B 2D 00 0 0 0 0 0
2009 37 0B 37 00 0 0 0 0 0
200A 0B 0B 37 00 0 0 0 0 0
200C 0B 0B 37 54 0 1 1 1 0
200F 0B 0B 37 54 0 1 1 1 0
2010 37 0B 37 54 0 1 1 1 0
2013 37 0B 37 54 0 1 1 1 0

The contents of the memory location 2000H=37H

- 121 -
27. Write an assembly location in the accumulator. Assume that the result doesn‟t exceed 8-bit (in 2‟s
complement format).

SOLUTION

The following subroutine does multiplication by repeated addition.

MULT8: MVI D, 00H; ; Initialise reg. D to keep track

MVI A, V ; Get Y In A
ADI 00H ; check for Zero n sign
JZ OVER ; If zero jump to OVER
JP GETX ; If negative obtain 2’s complement
CMA
ADI 01H
INR D ; increment reg. D
GETX: MOV B, A ; store Y in the reg. B
MVI A, X ; Get X in A
ADO 00H , check for zero and sign
JZ OVER ; If zero jump to over
JP THERE ; if negative obtains 2’s comp.
CMA
ADI 01H
INR D ; increment reg. D
THERE: MOV C,A ; store X in C
AGAIN: DCR B
JZ FINIS
ADD C ; Add reg. C to A till reg. B is zero
JMP AGAIN
FINIS: DCR D ; check signs
JNZ OVER ; Reg. D non-zero means positive result
CMA ; Otherwise the result is negative
ADI 01H
OVER: RET

28. Hand assemble the subroutine of 27 starting from memory location 2000H.
Assume X=FOH and Y=08H

SOLUTION

Table 12.6 gives the codes to be stored in various memory location.

- 122 -
 Table 12.6

Memory Loc.(H) Code(H) Memory location(H) Code(H)

2000 16 2018 F2
2001 00 2019 1F
2002 3E 201A 20
2003 08 201B 2F
2004 C6 201C C6
2005 00 201D 01
2006 CA 201E 14
2007 2F 201F 4F
2008 20 2030 05
2009 F2 2021 CA
200A 10 2022 28
200B 20 2023 20
200C 2F 2024 81
200D CF 2025 C3
200E 01 2026 20
200F 14 2027 20
2010 47 2028 15
2011 3E 2029 C2
2012 F0 202A 2F
2013 C6 202B 20
2014 00 202C 2F
2015 CA 202D C6
2016 2F 202E 01
2017 20 202F C9

29. Assemble the following program starting from memory location 203FH. Set SP = 20FFH

CALL MULT8
RST 1

Use an 8085 kit and store the MULT8 subroutine of Q28 and the above program and execute the
program. Examine the contents of register A and verify that this gives the product of X and Y.

SOLUTION

Men. Loc. (H) Data (H)

203F CD
2040 00
2041 20
2042 CF

The subroutine and the program are loaded in RAM and program executed.

The contents of A = (A) = 80H

- 123 -
 Since X = F0H = 11110000 = - 00010000 = - 1610
And Y = 08H = 00001000 = 810
Therefore, X*Y = -16*8 = -128 = 10000000
= 80H

30. Given 2 positive 8 bit values X and Y, write an assembly language subroutine for 8085 µP, which
divides X by Y leaving the quotient in A and remainder in B. In case Y is Zero, FFH is left in A
and B registers.

SOLUTION

DIV8: MVI A,Y

ADI 00H
JZ ERROR
MOV B, A
MVI A, X
MVI C, 00
AGAIN: CMP B
JC OUT
SUB B
INR C
JMP AGAIN
OUT: MOV B, A
MOV A, C
RET
ERROR: MVI A, FFH
MOV B, A
RET

31. An 8085 µP based system has the program stored in memory as given in table 12.7. Write this
program in the assembly language.

Table 12.7

Memory location contents

Hex. Hex.

0000 0E
0001 FF
0002 21
0003 41
0004 00
0005 46
0006 11
0007 51
0008 00
0009 23

- 124 -
 000A 13
000B 1A
000C BE
000D CA
000E 16
000F 00
0010 05
0011 C2
0012 09
0013 00
0014 05
0015 00
0016 79
0017 32
0018 40
0019 00
001A 76

SOLUTION

The first code i.e. the contents of the memory location 0000H must be an op-code. Identified to be
the op-code for the instruction MVI C data (Refer to instruction set). Therefore, the next byte is the
data byte. In this way we go on identifying the codes and write the instructions. The complete
program is given below:

MVI C, 0FFH
LXI H, 0041H
MOV B, M
LXI D, 0051H
LOOP: INX H
INX D
LDAX D
CMP M
JZ OVER
DCR B
JNZ LOOP
MVI C, 00H
MOV A, C
STA 0040C
HLT

- 125 -
Supplementary questions

32. Find the address bus width for the µPs, which can address the following memory locations.

(a) 1 K bytes
(b) 64 K bytes
(c) 1 M bytes
(d) 8 Mbytes

33. Specify the word size of following µPs:

(a) 8085
(b) 8086
(c) 6502
(d) 6800
(e) Z80
(f) 68000
(g) Z8000

34. It is desired to use 16 K bytes of EPROM and 48 K bytes of DRAM.The available EPROM‟s
are 27256 (32 K x 8) and DRAM‟s are 2186A (8192 x 8). Find the number of chips required for
RAM and EPROMs.

- 126 -
REVISION QUESTIONS (WITH ANSWERS)
R12.1 When did the microprocessors come into existence?

Ans. The term microprocessor came into existence in 1971 when the Intel Corporation of
America developed the first microprocessor (INTEL 4004), which is a 4-bit
microprocessor (µP).

R12.2 What is a Microprocessor?

Ans. It is a digital circuit consisting of thousands of components on a silicon chip with

capabilities similar to the central processing unit (CPU) of a Computer.

R12.3 What is meant by µP based system?

Ans. A system with a µP as an integral part is known as a µP based system.

R12.4 What is a microcomputer?

Ans. It is an µP -based computer which has a µP as its CPU.

R12.5 How is a µP specified?

Ans. It is specified by its word size. For example 8-bit,16-bit,etc.

R12.6 What is meant by „word size‟ of µP?

Ans. It specifies the number of bits of data that is processed by the µP as a unit. For
example, an 8-bit µP performs various operation on 8-bit data. It also specifies the
width of the bus.

R12.7 Differentiate between a microcomputer (µC) and a µP?

Ans. A µC consist of input/output and memory in addition to µP which acts as CPU.

R12.8 What are the functions of address bus of a µP?

Ans. It allows the µP to address any memory location or I/O device.

R12.9 What are the functions of the data bus of a µP?

Ans. It is used to transfer the information (instruction or data) between the µP and the
memory, between the µP and the I/O devices.

R12.10 Is the address bus of a µP unidirectional or bi-directional?

Ans. It unidirectional. The address information is always given by the µP to address a

memory or I/O device

- 127 -
R12.11. Is the data bus of a µP unidirectional or bi-directional?

Ans. It is bi-directional since the same bus is used for transfer of data between µP and the
memory or I/O device in both the same direction.

R12.12. Name some 8-bit and 16-bit microprocessors.

Ans. 8-bit microprocessors: 8085A, 6800, Z80, and 6502

16-bit microprocessors: 8086, 68000, and Z8000.

R12.13. What is meant by a „dedicated‟ bus.

Ans. A bus used only for one specific purpose is known as a dedicated bus. For example
the address bus in some microprocessors is used to transmit only the address in some
microprocessors is only used to transmit only the address information where as in
some other microprocessors a bus is used to transmit address information as well as
for transfer of data the first one is a dedicated bus.

R12.14. Why multiplexing of buses i.e. using a bus for more than one function is preferred in µPs

Ans. It saves number of pins in µP chips

R12.15. What is meant by „handshaking‟ operation of µP based system?

Ans. The communication protocol between the µP and the I/O devices in which an I/O
device makes a request and then waits for the response from the µP is known as
handshaking.

P12.16. How are the I/O devices interfaced with the µPs?

Ans. The I/O devices are interfaced with the µPs though the ports.

P12.17. What does I/O stand for?

Ans. It stands for input and output devices. There are many situations in which a device is
used as input device for some functions and as output device for some other function.
Therefore these devices are usually represented by one term i.e. I/O.

P12.18. What is referenced while using the word input or output?

Ans. It is always with reference to the µP for example if a keyboard is used for entering
data /instruction it is an input device.

P12.19. What is meant by „program‟ in computer and µP based system?

Ans. The set of instructions to perform the desired operation is known as a program.

P12.20 . What is the language in which instructions are given to any computer or µP based system?

- 128 -
 Ans. The instructions are coded in binary form and this is the only language that a
computer or µP based system understands. It is known as the machine language.

P12.21. What is assembly language

Ans. This is another way of coding instruction in computers and µP based system.
In this names are assigned to instructions, registers, data and memory locations.
These names are usually the abbreviations of the name or descriptions of the
instruction (mnemonics), addresses, or data and are used to aid the designers memory.

P12.22. What is an Assembler?

Ans. It is a program which translate the assembly language program into an equivalent
machine language program.

P12.23. How does a µP differentiates between the instruction code and data/address?

Ans. It executes instructions step by step and depending upon the time at which a digital
information is received by a µP it will automatically interpret it as instruction code,
data or address.

R12.24. What is meant by higher-level language?

Ans. For ease of programming, a program can be written in statements form called higher
level language, such as, FORTRAN, BASIC, PASCAL, etc.

R12.25. What is a Compiler?

Ans. Is it a program that translate programs from higher level language into machine
Language. It translates the whole program first before it is executed.

R12.26. What is instruction set?

Ans. Is a collection of all the instruction that a specific µP can execute.

R12.27. Define the terms „Hardware‟ and „Software‟

Ans. The electronic components and circuit which makes a computer or a µP based system
is known as hardware whereas the programs are called software.

R12.28. What are the basic operations performed by the µP?

Ans. There are two basic operations (i) Fetch an instruction from memory and (ii) Execute
the instruction.

R12.29. Explain the fetch operation

Ans. The various steps performed during fetch operation are:

(a) The µP places the address of the first byte of instruction on the address bus a
long with a control signal to read from the addressed memory location.

- 129 -
 (b) The µP get this byte on the data bus. This byte is known as op code and this operation is
known as op code fetch
(c) The op code is decoded and the necessary control signals are generated.
(d) If the instruction is a multi-byte instruction the second and the subsequent bytes are
fetched from the memory one by one by the following steps similar to (a) and (b)

R12.30. Explain the execute operation.

Ans. After the fetching of an instruction is completed, the µP performs the operation that is
specified by the instruction. This operation is known as the execute operation.

R12.31. What is the function of an ALU in a µP?

Ans. It performs arithmetic operations such as, addition , subtraction , etc, and logical
operation such as, AND, OR, EX-OR, etc. it is in fact the heart of the µP.

R12.32. What is meant by „Scratch card registers‟?

Ans. These are general purpose register in the µP used to store temporary address/data.

R12.33. How many general purpose registers are there in 8085 µP?

Ans. There are six 8-bit general purpose register B, C, D, E, H and L

R12.34. Is there any special registration of H and L registers in 8085 µP? Explain

Ans. Registers H and L is used as a pair to store 16-bit address of a memory location. The
register H and L is meant for higher and lower bytes respectively.

R12.35. What is a program counter?

Ans. It is binary µP counter which holds the address of either the first byte of the next
instruction to be fetched for execution or the address of the next byte of a multi-byte
of instruction which has not yet been completely fetched in either case it gets
automatically increment one by one as the instruction bytes gets fetched.

R12.36. What is the content of the program counter (PC) of an 8085 µP after its reset?

Ans. The program counter sets to Zero.

R12.37. How can a user have access to the general-purpose registers of the µP?

Ans. These are not accessible physically and can be accessed only through instruction.

R12.38. What is meant by „stack‟?

Ans. Stack is a portion of RAM used for saving the contents of PC and general purpose
registers etc whenever required.

R12.39. ROM cannot be used to implement the stack. Why?

- 130 -
 Ans. Since it is not possible to write into the ROM, therefore it cannot be used as stack

R12.40. What is a „Stack pointer‟?

Ans. It is a special purpose register in the µP, which holds the address of the ‘Top’ of the
stack.

R12.41. What are the instructions meant to store in and retrieve from the stack in 8085 µP based
system?

Ans. PUSH instruction pushes the contents of the specified registers on to the stack and the
POP instruction retrieves the contents of the stack.

R12.42. Does the stack pointer get increment or decrement after PUSH instruction is executed in
8085 µP?

Ans. It gets decremented i.e. the stack grows in the downward direction.

R12.43. What are the minimum components/subsystems required in a µP based system?

Ans. µP memory I/O devices.

R12.44. What is meant by „flag‟ in a µP?

Ans. Flags are single-bits of a register in µP used to store certain conditions which arise
as a result of execution of certain instructions.

R12.45. What does the Zero flag signifies?

Ans. If the result of arithmetic or a logical operation is zero, it is set (i.e. Z=1) otherwise it
is a reset (i.e. Z=0).

R12.46. What are the various flags in 8085 µP?

Ans. Carry (CY,) Zero (Z,) Sign (S), Parity (P) and Auxiliary carry (AC).

R12.47. What is meant by an interrupt?

Ans. A µP executes instructions in sequence. Sometimes it may become necessary to

postpone the routine job that the µP is doing in order to attend to some urgent task.
The signal that causes the µP to do this is called an interrupt signal. For example a
µP based system may be used for monitoring the temperature and pressure of a
process. If the temperature and/or pressure goes beyond a prescribed safe limit the
µP should be able to initiate proper action to avoid any damage to life and
equipment.

R12.48. What is meant by priorities of interrupt?

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 Ans. Different I/O may be required to interrupt the µP. In such situation a priority is
defined for each of the interrupting devices i.e. which device will be attended to first
in case they both interrupt the µP at the same time.

R12.49. What are the various interrupts in 8085 µP?

Ans. These are known as TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. TRAP is the highest
priority interrupt and INTR is the lowest priority interrupt.

P12.50 What is meant by non-maskable interrupt?

Ans. An interrupt, which can never masked, i.e. disable is known as non-maskable
interrupt. For example TRAP in 8085and NMI in 6800 are non-maskable interrupts.

P12.51 What does DMA stands for? Explain.

Ans. It means direct memory access. For normal operation there is no direct transfer of
data between the I/O devices and memory. All data transfer takes place through the
µP. This is very time consuming process in case a large quantity of data transfer is
required between the I/O devices and the memory. The DMA operation helps in direct
transfer of data between the I/O devices and the memory.

R12.52. What type of memory will you prefer for program storage while developing a µP based
system and why?

Ans. An erasable programmable type of memory is best suited for this because is non-
volatile and therefore, is not erased when power is off. At the same time it is possible
to modify the program by erasing and programming again.

R12.53. What type of memory will you prefer for program storage for a µP based system required in
very large numbers?

Ans. Mask-programmed ROM will be the best suited for this because of its low cost for
high volume production.

R12.54. What type of memory will be best suited for program storage for a low µP based system?

Ans. PROM will be best suited for this because of its low cost for low volume and there is
no risk of loosing the program even by accident.

R12.55. Specify the type of memory, which you will prefer for permanent data and for temporary
data.

Ans. ROM for permanent data and RAM for temporary data.

R12.56. What does the term „burning‟ mean?

Ans. Burning means programming of programmable ROMs. This term has become popular
because of burning of fusible links in PROMs for data storage.

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R12.57. Is the meaning of programming same for computers and read only memories? Explain.

Ans. No. programming a computer means preparing a set of instructions to perform a task,
whereas programming a read only memory means entering information init.

R12.58. What is meant by memory address space?

Ans. It is the maximum possible memory size, which can be used with a µP.

R12.59. What is meant by I/O address space?

Ans. It is the maximum possible number of I/O devices, which can be interfaced with a µP?

R12.60. Is it necessary for a µP to have separate address spaces for memory and I/O ? Explain

Ans. No in case separate address spaces are not available, the I/O device are connected as
the memory locations. This arrangement is known as memory mapped I/O.

R12.61. What is meant by „standard I/O?

Ans. When separate address is available for I/O devices, the I/O devices are connected
using this space. This arrangement is known as standard I/O or I/O mapped I/O.

R12.62. What are the address spaces in 8085 µP?

Ans. It has 16-bit address bus for memory addressing and 8-bit address bus for I/O
addressing. The corresponding address spaces are 216 = 64 K byte and 28 = 256 for
memory and I/O devices respectively.

R12.63. It is possible to use I/O mapped I/O in 6800 µP?

Ans. No. Since no separate address space is available for I/O. Therefore, only memory
mapped I/O is possible.

R12.64. 8085 µP has an 8-bit bus (AD0- AD7) known as address/data bus and another 8-bit bus
(A8 -A15) known as address bus. Explain the function of these buses.

Ans. The AD0 – AD7 bus is used for transfer of data (data bus) for lower order eight bits of
memory address, and for I/O address. The A bus is used on higher order eight bits of
memory address and duplicate the I/O address.

R12.65. In a 8085 µP based system, how do the I/O device and memory know for whom the address
is meant at any time.

Ans. In 8085 µP there is an output pin designated as IO/M. If it is HIGH, the address is
meant for the I/O and if it is LOW the address is meant for the memory.

R12.66. What happens if the memory locations are selected simultaneously for reading by a µP?

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 Ans. Data from two locations will cause bus contention. It is never allowed.

R12.67. What happens if the memory location and an I/O or two I/O devices are addressed
simultaneously by a µP?

Ans. This will also cause bus contention and is therefore never allowed.

R12.68. What can be the possible number of distinct op codes in a µP if eight bits are used for op
code?

Ans. The maximum possible number of distinct op codes will be 28 = 256 for an 8-bit op
code.

R12.69. What is the semiconductor technology used for the fabrication of 8085 µP?

Ans. NMOS technology

R12.70. How many transistors are there in 8085 µP and what is the size of the chip?

Ans. 8085 µP consist of approximately 6,200 transistors (MOS) on a 164x222 mil chip
container in a 40-pin DIP

R12.71. What is the international clock frequency of 8085µP if a crystal of 6.25 MHz is used?

Ans. It is half of the crystal frequency, i.e. 3.125 MHz.

R12.72. Define the term „Machine cycle‟

Ans. It is the time required for fetching one byte of instruction or for reading from or
writing into one memory location.

R12.73. What is meant by instruction cycle‟?

Ans. It is the time required for fetching and executing one instruction.

R12.74. What is meant by „Wait state‟?

Ans. Usually the I/O device, which are usually electromechanical device, are slower in
speed than µP and so they require the µP to wait till they are ready for data transfer.
For these purpose the µP has to generate wait states.

R12.75. What are the various schemes used for data transfer between µP and I/O devices?

Ans. (i) Synchronous data transfer.

(ii) Asynchronous data transfer
(iii) Interrupt driven data transfer.

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SOME REGISTER FUNCTIONS

1 MEMORY ADDRESS REGISTER (MAR)

This is a register that is used to contain address which must be changed while the program is
running when a program refers to a location in memory to retrieve or store an item of data it often
does so by fist assembly the appropriate address in a register it then directs to the processor to
use the content of this register to identify and access the memory location a register which is used
for this purpose is called a MAR whatever the source of the address it must be placed into memory
address register.

2 MEMORY BUFFER REGISTER

This register is used to temporarily a word of data before it is fed into the ALU. Whatever the
contents of memory location being read it is being decoded prior to execution.

3 DATA REGISTER
The data register contains the actual data being outputted or inputed from the processor a data
register serves a role similar to that of an accumulator in that it may be used in arithmetic/logic
input /output and load /store operation.

4 DATA DIRECTION REGISTER

Data direction register identifies each line of an I/O port as being used only as an input or an
output port the data direction register configures each bit or out put addressing the DDT and
lording it with O‟S configures the port line as outputs in some I/O chips there is only one DOR
known as the control register for configuring all port as either input or output as shown.

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