A Tutorial on Logic Synthesis for Lookup-Table Based FPGAs

Robert J. Francis

Department of Electrical Engineering, University of Toronto

Abstract node represents a local function of the global functions

represented by its immediate fanin nodes. For exam-
The ability to shorten development cycles has made ple, in the DAG illustrated in Figure 2a the local func-
Field-Programmable Gate Arrays (FPGAs) an attrac- tion at the node z is z = wxy, and the global function
tive alternative to Standard Cells an,d Mask Pro- is z = ((abc) + (def))(g + h)(i + j).
grammed Gate Arrays for the realization of ASICs. The netlist describing a circuit of LUTs can be rep-
One important class of FPGAs are those that use resented by a similar DAG. In this case, each node rep-
lookup tables (L UTs) to implement combinational resents a smgle LUT and the node’s local function spec-
logic. The ability of a K-input LUT to implement any ifies the function implemented by the LUT. Figure 2b
Boolean function of Ii- variables di$eren,tiates the syn- illustrates a circuit of 5-input LUTs implementing the
thesis of LUT circuits from synthesis for conventional function illustrated in Figure 2a. The dotted bound-
ASIC technologies. The major difference occurs dur- aries in Figure 2b indicate the local function imple-
ing the technology mapping phase of logic synthesis. mented by each LUT. The local function implemented
For values of I( greater th,an 3, th.e large number of by the LUT t is z = (u + (def))t. Unless stated other-
functions that can be implemented by a K-input LUT wise, all examples in the remainder of this tutorial will
makes it impractical to use conventional library-based use 5-input LUTs.
technology mapping. However, the completeness of Combinational logic synthesis can be conceptually
the set of functions th.at can be implemented by a LlJT divided into two phases; technology-independent logic
eliminates the need for a library of separate junctions. optimization, and technology mapping [2]. Logic
In addition, this completeness can be leveraged to op- optimization restructures the original network, without
timize the final circuit. changing the function of its primary outputs, and tech-
nology mapping implements the optimized network us-
ing the circuit elements available in the given ASIC
1 Introduction

Field-Programmable Gate Arrays (FPGAs) now

nrovide an alternative to Standard Cells and Mask Pro- x = ab + bc
grammed Gate Arrays for the realization of ASICs. An 0
FPGA consists of an array of logic blocks that imple-
ment combinational and sequential functions, a,nd a
user-programmable routing network that provides con-
nections between the logic blocks. User-programability
allows for rapid and inexpensive prototype develop-
ment [l]. This tutorial discusses combinational logic
synthesis for FPGAs that use lookup tables (LUTs)
to implement combinational logic, and focuses on is-
sues that differentiate LUT synthesis from conven- a) Truth Table
tional logic synthesis.
A K-input lookup table is a digital memory that abc
can implement any Boolean function of K variables.
The I< inputs are used to address a 2K by l-bit digi-
tal memory that stores the truth table of t,he Boolean
function. For example, Figure la illustrates the truth
table for the function 2 = ab + zc, and Figure lb il-
lustrates the st,ructure of a 3-input LUT implementing S lo 1 multiDlexer
this function. The truth table is stored in an 8 by l-bit, i“....“........”“._........I ......_I............. /.. “.....” ...........“. I.._..._......
memory, and an 8 to 1 multiplexer, controlled by the
variables a, b, and c, selects the output value z. x
The goal of combinational logic synthesis is to pro-
duce an optimized circuit implementing a given combi- b) 3-Input LUT
national function. The original function can be repre-
sented by a Directed Acyclic Graph (DAG) where each Figure 1: A LUT Implementing z = ub + zc

40
O-8186-3010-8/92 $03.00 0 1992 IEEE
 abc def gh i j ab
, , f de df

” ” x Y

”
w

x Y
Y
z
a) Boolean Network
a) Boolean Network

g” i j

abc

de f
‘
”

b) Circuit of 5-input LUTs

Figure 3: Common Sub-Expression Elimination

b) Circuit of S-input LUTs

Figure 2: Network a.nd Circuit on the longest path. To illustrate the issues that dif-
ferentiate LUT synthesis from conventional logic syn-
thesis, this tutorial will focus on the minimization of
the total number of LUTs in the final circuit. The fol-
technology. lowing section discusses the limitations of conventional
The modifications performed by logic optimization library-based synthesis when applied to LUT circuits,
typically include redundancy removal and common and Section 3 discusses approaches to logic synthesis
sub-expression elimination. The intention is to im- that deal specifica.lly with LUT circuits.
prove the final circuit by simplifying the underlying
network. For example, consider the network shown
in Figure 3a. The common sub-expression e + f can 2 Library-Based Synthesis
be factored out of the functions x and g leading to the
simplified network covered by the circuit shown in Fig-
ure 3b. Conventional techniques for logic optimization Standard Cells and Mask Programmed Gate Ar-
can be effective for LUT circuits particularly at a level rays both implement. combinational functions using a
of granularity where factors ha.ve more t,han AVinputs. limited set of simple gates. The most successful ap-
These techniques have been summarized in [2] and will proach t,o synthesis for these ASIC technologies has
not be discussed here. used library-based technology ma.pping [3]. This ap-
Technology mapping selects sub-networks of the op- proach traverses the network from the primary inputs
timized network to be implemented by the available to the primary outputs, and at each node the local
circuit elements. In the case of LUT-based FPGAs, structure of the network is m.adched against a library
any sub-network wit.11 at most K inputs can be im- of patterns representing the set of available gates. For
plemented by a K-input LUT. The final circuit must each successful match, the cost of the circuit using that
include a LUT implementing each of the primary out- gate is calculated from the cost of the gate, and the cost
puts and all of the LUT input,s t,hat a.re not primary of t,he previously constructed circuits implementing the
inputs. input,s to the gate. The minimum cost circuit among
The optimization goa. for the synthesis of LUT cir- all the matches is then retained.
cuits is typically the minimiza.tion of the t.ot.al munber The major obstacle to applying library-based tech-
of LUTs, t,he number of ferlels of LUTs, or bot,h. Min- nology mapping to LUT circuits is the large number
imizing the number of LUTs in the circuit increases of different functions that a K-input LUT can imple-
the size of designs that can fit into the fixed number ment. The function implemented by a K-input LUT is
of LUTs availa.ble in a given FPGA. The minimiza- determined by the values stored in its 2K memory bits.
tion of the number of levels of LUTs can improve the Since each bit ca.n independently be either 0 or 1, there
performance of the circuit by reducing the number of are 2-7K different Boolean functions of li’ variables. For
logic block delays and programmable routing delays values of li’ greater than 3 the library required to rep-

41
 without with with fanout nodes in the original network.
I< permutations permut,ations permutations
and inversions and inversions
2 1G 12 4 3.1 Decomposition of Infeasible Nodes
3 25G 80 14
4 65536 3984 232 The general stra.tegy for the decomposition of infea-
sible nodes is to decompose each infeasible node into
Table 1: Number of Patt,erns for a K-Input LUT sub-functi’ons that use fewer inputs than the original
infeasible node. Any sub-function that uses no more
t,han K inputs is feasible and is decomposed no further.
resent a K-input LUT becomes impractically large. Any sub-function that has more tha.t Ii’ inputs is recur-
The size of the libra.ry can be reduced by noting sively decomposed. Eventually the original infeasible
that some pa,tterns are equivalent after a. permutation node is decomposed into a set of feasible nodes. Four
of inputs [4]. The inversion of outputs or inputs, which methods tl1a.t have been proposed for the decompo-
is trivially accomplished with a LUT, ca.n also produce sition of infeasible nodes are; disjoint decomposition,
equivalent ‘patterns. Table 1 lists the number of differ- algebraic factorization, AND-OR decomposition, and
ent patterns, with and without permutations and in- Shannon cofactoring.
versions, for IC = 2, 3, and 4. To match a. sub-network
against a pattern in the reduced library it may be nec- 3.1.1 Disjoid Decomposition
essary to permute or invert the sub-network. Ha.shing
functions have been proposed to simplify the matching A disjoint deconlposition is based on a pa.rtition of the
of permuted patterns [5]! but the increased complexity inputs to the infeasible node into two disjoint sets re-
of pattern matching limits the benefits of the reduced ferred to as the bound sef and the free set. One or more
library. functions of the bound set are extracted from the in-
Another alternative is to use a partial library tuned feasible node, and the infeasible node is replaced by a
to take advantage of the network structure likely to be function of the outputs of the extracted functions and
produced by technology independent logic optimiza- the inputs in the free set. The attraction of a disjoint
tion [6]. The limitation of this approach is that it pre- decomposition is that the number of inputs in the each
cludes some opportunities for optimization of the final of the t.wo sets must be less than the number of inputs
circuit. The following section discusses approaches to t,o the infeasible node.
LUT synthesis that exploit the full functiona.lity of a Disjoint decompositions can be found by searching
K-input LUT to obtain improved result,s. through all possible pa.rtitions of t,he inputs to the in-
feasible node, alld using well known methods such as
residues [19], t.o determine if each ea.& partition leads
3 LUT-Specific Synthesis t,o a disjoint decomposition. A residue function is ob-
t.ained by repla.cing the inputs in the free set with con-
There has been a great, deal of recent, work on lo .ic sta.nt values. If the set of all possible residue functions
synthesis that deals specifically with LUT circuits. BG , for a given partition consists of the constants 0 or 1,
71 PI P WI, Pll, 1121,
[’181. The
[13], P41, P51, 161, P7 ,
‘G ey to all of these approaches is t Ile ability
1 or a single function h of the bound variables, or its in-
verse SE,then the partition is a disjoint decomposition,
of a K-input LUT to implement ~11functions of Ii with one extracted function. For example, consider the
variables. This complelen.ess simplifies the ma.tching of 4-input function f = ab + c&d + 7ib? + Tibz shown in
a sub-network t.o a LUT. To determine if a sub-network Figure 4a, and t,he pa,rtition of its inputs into the free
matches a. K-input, LUT it is not, necessary t,o matc!l set. (0, b} a.nd the bound set {c? d}. The set of residue
the sub-network a.gainst, a. library of sepamte palterns, functions for this partition, shown in Figure 4b, con-
as described in the preceding sect,ion. It is sufficient sists of the constants 0 and 1, a.nd the function cd and
to count the number of inputs t’o the sub-network, and
verify that the number of inputs does not exceed the its inverse (cd). Therefore, this partition leads to the
constraint K. disjoint, decomposition of the function f, shown in Fig-
Technology mapping optimizes the final circuit by ure 4c.
selecting which sub-networks are covered by LUTs. If The number of partitions grows exponentially with
the original network includes nodes with more than K number of inputs to the infeasible node, and the search
inputs, referred to as infeasible nodes., it may not be for disjoint decompositions can become prohibitively
possible to find a circuit of LUTs covermg the network. expensive if the infeasible node has a large number of
In many mapping algorithms, t.o ensure that a circuit inputs.
covering the network exists, each infeasible node is de-
composed into a set of feasible nodes, each wit,h at most 3.1.2 Algebraic Decomposition
I< inputs. In addition, the decomposition of bot,h fea-
sible and infeasible nodes present,s an opportunity to Algebmic factoriza.tion techniques developed for tech-
optimize the final circuit. nology independent logic opt,imization can also be used
The next section discusses the decomposition of in- for the decomposition of infeasible nodes [7]. For ex-
feasible nodes, Section 3.2 discusses how decomposition ample, she function CC= UC+ bc + bd + ce ca.n be alge-
and covering can be combined to improve the final cir- bra.ica.lly factored into the fa.ctor y = a + b + e, and the
cuit, and Section 3.3 describes how covering can exploit remainder ;c = cv + bd. Since the va.riable b is nsed by

42
 ab abed abc abd

a) Original circuit, 4 LUTs

a) An infeasible function for A’ = 3
b cdeg

cd b hc,d
0 01 0

b) Residues for t,he partition {CL,6)) {c, d)

cd
‘r
i . . . . . . . . . . q.“-“..-:
i

b) With Shannon cofactoring, 3 LUTs

Figure 5: Shannon Cofactoring

3.1.4 Shannon Cofactoring

f
Another form of decomposition that. will always suc-
c) The disjoint decomposition cessfully decompose an infeasible node is Shannon co-
factoring [‘ZO]. A n infeasible function of n. variables,
f(z1 . . . ~j . x,,), is decomposed into the three func-
Figure 4: Identifying Disjoint Decompositions tions fX, = f(rl . . l...z,), f- = f(Xl...O...X,)
and f = zjfE, +qfq. The func?on f now depends on
the three inputs ~j, frj, and fq, and can therefore be
both the factor y a.nd the remainder z this is a. not a implemented by a single K-input LUT for Ir’ >_3. The
disjoint decomposition. functions fZ,, and fq, each depend on at most n - 1
variables. If n - 1 equals I< then the completeness of a
K-input L17T ensures that these functions can be im-
3.1.3 AND-OR Decomposition plemented by a single LUT. Otherwise, the functions
f Q3’ and fq, ca,n be recursively decomposed. For ex-
Disjoint decompositions a,nd algebraic factorization are ample, t,he G input function f = a.bcd+%eg+Z~eg can
not sufficient. to decompose all infeasible nodes. For ex- be covered by the 4 LUT circuit shown in Figure 5a.
ample, the majority function z = a6 + UC+ bc. has no This function can be cofactored ab_out the vqiable_a to
disjoint decomposition. AND-OR decomposition ca,n produce the cofact,ors fa = bcd+~@, fx = beg+Efi,
be used to ensure that any infeasible node is clecom- and the 3 LUT circuit shown in Figure 5b.
posed into a set of feasible nodes. The AND OR)
operator is associative and commutat,ive, which aI lows
an AND (OR) node to be divided into smaller AND 3.2 Decomposition and Covering
(OR) nodes using any partition of its inputs. An in-
feasible node is represented as a sub-graph of AND An important observation is that the decomposition
and OR nodes, each of which is then decomposed us- of feasible nodes, as well as infeasible nodes, can lead
ing AND-OR decomposition. For example, the above to a superior circuit. For example, in the circuit shown
3-input majority function can be decomposed into the in Figure 6a the AND and OR nodes in the underlying
2-input functions ‘v = ab, w = ac, x = bc, y = v + w, network are all feasible, and four 5-input LUTs are
and t = y+s. needed to cover the network. In Figure Gb the original
AND-OR decomposition can also be used to decom- 4-input OR node has been decomposed into a 2-input
pose large infea.sible nodes into infeasible nodes that and a S-input OR node a.nd only 2 LUTs are needed
are small enough t.o ma.ke an exhaust,ive search for dis- to cover the network.
joint decompositions practical [9]. The AND-OR decomposition of feasible, and infea-

43
 4 Original 4-input, OR node, 4 LUTs a) Fanin LUTs

r ...... ...
1
i
IV 1
: ........ . -...........

b) OR node decomposed, 3 LUTs b) After bin packing

Figure G: Decomposition of a Feasible Node - . ...I...

1
sible nodes, can be combined with a covering algorithm
similar to the library-based approach described in Sec- ...... 1I ......._..
~.~~~~~~~.~.~.,~~
tion 2 to optimize the final circuit [lo]. The original
network consists of AND and OR nodes, and is tra-
I’...- i
versed from the primary inputs to the primary outputs. ! I
A circuit implementing each node is constructed from
the circuits implementing its immediate fanin nodes. % I._......... JI,...
.,............_..._
.....
This circuit is optimized to minimize the total number
of LUTs, and to minimize the number of inputs used by i
its root LUT. This increases the number of unused in-
I
puts available at the root, LUT, and these may reduce
the number of LUTs required to implement a subse-
quent node.
7 i..I.._..I. z
At each node, the root LUTs of the fanin circuits
are referred to as the funin. L UTs. For example, Figure c) The final circuit
7a illustrates the fanin LUTs for the node z. In this
example, the LUTs preceding the fanin LUTs are not Figure 7: Decomposition and Covering
shown, and the functions implemented by the fanin
LUTs are simple AND gates. In general, the fanin
LUTs can implement more complex functions. completeness of K-input LUTs ensures that any group
At each node’, a tree of LUTs replacing the fanin of fanin LUTs that together have no more than K in-
LUTs and implementing a decomposition of the node puts can be implement,ed by a single LUT. This allows
being mapped is constructed in two st,eps. The first the minimization of the number of packed LUTs to be
step selects decompositions, as shown in Figure 7b, rest.ated and solved as a bin packing problem.
that allow several fanin LUTs to be packed together The goal of the bin packing problem is to find the
into a single LUT. The second step comiects these minimum number of fixed capacity bins into which a
LUTs to form the circuit implemeuting the node being given set of arbitrary sized boxes can be packed. In
mapped, as shown in Figure 7c. The following sections this case, the boxes are the fanin LUTs and the bins
describe these two steps. are the LUTs into which they are packed. The size
of each box is the number of inputs used by the fanin
3.2.1 Decomposition Using Bin Packing LUT and the capacity of each bin is K. In Figure 7a
the boxes have sizes 3, 2, 2, 2, and 2.
The objective of the first step is the minimization of Bin packing is a well known combinational optimiza-
the number of LUTs into which the fanin LUTs are t,ion problem, and there exists several effective algo-
packed. To determine if a group of fanin LUTs can rithms for its solution [21]. In particular, the First Fit
be packed into a single LUT it is sufficient to count Decreasing (FFD) algorithm is optimal for boxes and
the total number of inputs used by this group. The bins with integer sizes less than equal to 6 [22]. The

44
FFD algorithm begins with an empty list of bins. The
boxes are sorted by size and then each box, beginning
with the largest, is packed into the first bin in ‘the list
into which it fits. If the box does not fit int.o any bin
then it is packed into a new bin added to t,he end of
the list. In Figure 7b the FFD algorit.hm has packed
the fanin LUTs from Figure 7a into LUTs having filled
capacities of 5, 4, and 2. Note that packing boxes into
bins implies decomposition of the node being mapped.

3.2.2 Completing the Circuit

After the fanin LUTs have been packed into the bins,
the final circuit, shown in Figure 7c, is formed by sort-
ing the bins by filled capacity and then connecting the a) Reconvergent paths covered separately, 3 LUTs
output of each bin to an unused input, of one of the
following bins. If no unused inputs are available then
a new LUT is added to the root of circuit. Connect-
ing the bins alters the decomposition of the node being
mapped, however, the completeness of a K-input LUT
ensures that each sub-function can be implemented by
a single LUT. In addition to minimizing the number
of LUTs in the circuit, this approach minimizes the
number of inputs used a.t the root LUT of the circuit.
This is an important consideration, since the root LUT
becomes a box when the following node is mapped.
Smaller boxes ca.n reduce the number of bins required
by the bin packing step and lead to a superior circuit.

3.2.3 Optimality b) Reconvergent paths covered together, 2 LUTs

If the original network is a fallout-free t,ree then t,he
above approach constructs the circuit containing t,he Figure 8: Covering Reconvergent Paths
minimum number of K-input LUTs for values of Ii’ 5
5. A similar approach can map fallout-free trees into
the the minimum depth circuit for values of I< 5 G [14]. has at most K distinct inputs, as shown in Figure 8b,
The mapping of trees can be used as part of a divide then the completeness of a K-input LUT ensures that
and conquer strategy to map arbitrary networks by t,he paths can be covered by a single LUT with only
partitioning the network at, fa.nout nodes int,o a forest one input connected to the fanout. node. The reduc-
of trees that are then mapped separately. tion in the number of inputs connected to the fanout
node can lead to a superior circuit, as shown in Figure
8b. However, it is not always advantageous to cover
3.3 Covering of Fanout Nodes reconvergent. paths wit,11 a single LUT. For example, in
the circuit shown in Figure 9a the reconvergent paths
While separate trees can be mapped effectively using originating from the node a are realized within a single
the approach described in the previous section, general LUT, and 4 LUTs cover the network. This network can
networks containing fanout nodes present additional be covered with a circuit of 3 LUTs, as shown in Fig-
challenges and opportunities. The following two sec- ure 9b if the reconvergent paths are covered separately.
tions describe the opportunities presented by reconver- The challenge for LUT synthesis is to determine when
gent paths and the replication of logic at fanout nodes, reconvergent paths should be covered by a single LUT.
and Section 3.3.3 describes an a.pproach to LUT tech-
nology mapping that takes adva.ntage of these oppor-
tunities. 3.3.2 Replication of Logic at Fauout Nodes
The replication of logic at fanout nodes a,lso presents
3.3.1 Covering Reconvergent Paths an opportunity t,o improve the final circuit. For ex-
ample, in t,he 3 LUT circuit shown in Figure 10a the
In some networks sepa.rate paths tha.t originate a.t a fanout node L is explicitly implemented as the out-
fanout node reconverge at a subsequent node. For ex- put of a LUT. Replicat,ing t,he function of this LUT
ample, in Figure Sa, there are a pair of reconvergent lea.ds to the 2 LUT circuit shown in Figure lob. The
paths origina.ting at the node a and termina.ting at the sub-circuits implementing the nodes y and z in Figure
node z. If the reconvergent paths are realized by sepa- 10a have sufficient unused capacity to include a copy
rate LUTs, as in Figure 8a, then each path requires one of the 3-input AND node, and the completeness of a
LUT input connected to the fanout node. If the recon- K-input LUT ensures that the functions incorporating
vergent paths are contained within a sub-network that the copies can be realized. Replication of logic is not

45
 Y 2

a) Without replication, 3 LUTs

a) Reconvergent paths covered together, 4 LTJTs

Y z

b) With replication, 2 LUTs

Figure :lO: Replication of Logic at a Fanout Node

optimal assignment is found by exhaustively search-

ing all possible combinations of edge labels. If the
sub-network containing m edges, t,here are 2”’ different
combinations. For each combination a circuit is formed
by combining the source and destination nodes of invis-
ible edges into one LUT. If any of the resulting LUTs
have more than K inputs, then the combination of edge
b) Reconvergent paths covered separately, 3 LUTs labels is re.jected. Otherwise, the combination resulting
in the circuit containing the fewest LUTs is retained.
Figure 9: Covering Reconvergent Paths The computational cost of the search is controlled by
the limit on the number of edges in the sub-network.
In addition, the search can be pruned whenever a com-
always beneficial and LUT synthesis must determine bination leading to a LUT with more than IZ inputs is
at which fanout nodes replica.tion should occur. rejected.

3.3.3 Covering using Edge Visibility 4 Conclusion

In the fina. circuit produced by technology ma.pping
every edge of the original net,work is either driven as The key feature that differentiates the synthesis of
the output of a LUT or implemented within a LUT. LUT circuits from synthesis for conventional ASIC
The covering of reconvergent paths and the replication technologies is the completeness of the set of functions
of logic at fanout nodes can be described by the as- that can be realized by a K-input LUT. This complete-
signment of edge visibility labels [12]. A visible edge ness simplifies technology mapping by eliminating the
is driven by the output of a LUT, whereas an itlvisi- need for a library of separate functions. In addition,
ble edge is implemented within a LUT. For example, completeness presents opportunities to select decom-
the circuit shown in Figure llb covers by the network positions that improve the final circuit.
shown in Figure lla. In this circuit the invisible edges To date research in LUT synthesis has focused pri-
(2, y) and (to, y) are represent,ed by curved lines. This marily on technology mapping. The challenge for the
assignment of edge labels implies the replicat,ion of the future is to exploit the completeness of LUTs to im-
3-input OR node, a.nd leads t.o a circuit cont,aining 3 prove other phases of FPGA synthesis. In particu-
LUTs. In Figure llc the edges (2, z) a.nd (9, z) are in- lar, delay penalties incurred by programmable routing
visible, and the reconvergent pa.ths origina.ting at, t#he in FPGAs, provide motivation for the investigation of
node w are realized within a single LUT, leading to a the combined eff’ect of logic synthesis, placement, and
circuit containing 2 LUTs. routing on circuit performance. Another important is-
After the decomposition of infeasible nodes, the as- sue is t,he tradeoff between optimization to fit a design
signment of edge labels can be optimized using a di- into the fixed logic and routing resources available on
vide and conquer strategy. The network is partitioned a given FPGA, and optimization to improve the per-
into sub-networks, and within each sub-network, the formance of the final circuit.

46
 grammable Gate Arrays,” Proc. 27th DAC, June 1990, pp.
613-619.
w
[71 Ft. Murgai, Y, Nishizaki, N. Shenay, R.. K. Brayton,
A. Sangiovanni-Vincent&, “Logic Synthesis for Pro-
x Y grammable Gate Arrays,” Proc. 27th DAC, Jtme 1990, pp.
620-625.

+ PI P. Abouzeid, L. Bouchet, K. Sakouti, G. Saucier, P. Sicard,

z “Lexicographical Expression of Boolean Function for Mul-
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a) Original network 90, Oct. 1990, pp. 31-39.

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nology Mapping for a Two-Output RAM-based field Pro-
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illI I<. Karplus, “Xmap: a Technology Mapper for Table-

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1121 N. Woo, “A Heuristic Method for FPGA Technology Map-

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z [131 R. Murgai, N. Shenoy, R.K. Brayton, A. Sangiovanni-
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b) Edges (cz), (WY) invisible, 3 LUTs ble Look Up Architectures,” Proc. ICCAD, Nov. 1991, pp.
564-567.
!“’ ... ... ...
[I41 R. J. Francis, J, Rose, Z. Vranesic, “Technology Mapping
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i”‘ . . . ........... “.i
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I..4+
.................. .............I ....I
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Figure 11: Covering Using Edge Visibility
WI J. Cong, T. Ding, A. Kahng, P. Trajmar “Graph Based
FPGA Technology Mapping for Delay Optimization,”
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