Devices Implemented in LSI

 MOS Transistor Drain Drain

Broadly used owing to the Gate Gate

properties of high-speed, low-
Source Source
voltage, and high-integration.
nMOS pMOS

 Bipolar Transistor Collector Collector

Used in RF and analog Base Base

applications owing to its high- Emitter Emitter
drive-ability. npn pnp

 Other devices Anode

Diode, resistors, capacitors etc.

Cathode

MOS: Metal Oxide Semiconductor

Page 4
What is Semiconductor?

A semiconductor is a material that behaves between a conductor and

an insulator.

At room temperature, semiconductor has higher electric conductivity

than an insulator, but lower than a conductor.
At very low temperatures, pure or intrinsic semiconductors behave
like insulators.
At higher temperatures or under light, pure or intrinsic
semiconductors can become conductive.
The addition of impurities to a pure semiconductor can also increase
its conductivity.

Page 5
What is Semiconductor?
a) Conductor (Cu, Al) electron free from atomic bound

b) Semiconductor (Si, Ge, GaAs) electron loosely Materials are grouped

bounded to atom by 3 types in electrical
resistivity
c) Insulator (SiO2, SiN) electron tightly bounded to atom

a b c
Conductor Semiconductor Insulator

10-6 10-4 10-2 1 102 104 106 108 1010 1012 1014 1016 1018
ρ
【Ω・cm】

Intrinsic
Si
Cu, Al, W, CoSi2 Ge GaAs SiO2, Si3N4
10Ω Si Wafer

Page 6
 Intrinsic and Extrinsic Semiconductor
Group III IV V
Intrinsic semiconductor 5 6 7
B C N
A perfect semiconductor which has no impurities 13 14 15
Its characteristics comes from the semiconductor itself Al Si P
31 32
33
Ga Ge As
Extrinsic semiconductor -
A semiconductor to which impurity is doped
- -
Some part of its characteristics comes from the doped - -
- -
impurity
+ - -
- - -
-
Page 7
 P-type Silicon - Acceptor

It is very easy for an electron from a nearby

Silicon to Silicon bond to fall into this hole
and effectively move the hole away from the - - -
- - -
Boron atom - Si
14+
- Si
14+
- Si
14+

- - - - - -
- - -
Since the Boron atom will accept an electron, - Si
14+
-
B5+
- Si
14+

Boron and the other elements of Group III (B, - - - - - -

Ga) are referred to as acceptors - Si

14+
-
- Si
14+
-
- Si
14+
-

- - -

Silicon with acceptor is called as P-type

Silicon, since “positive” holes are generated
and contribute a current flow

Page 8
 N-type Silicon - Donor
If a Group V atom, such as Phosphorus, is introduced
into the Silicon lattice, it will have an extra electron
which may easily break away, becoming a conduction
electron

The Phosphorus is referred to a donor, since it donates - - -

an electron to the conduction band. 14+
-
14+
-
14+
-
Si Si Si
Other donor is As - - -
- - - - - - -
- - -
14+ 14+
Si P15+ Si
Silicon with donor is called as N-type - - -
- - - - - -
Silicon, since “negative” electrons are - - -
14+ 14+
generated and contribute the current flow
14+
- Si - Si - Si

- - -

Page 9
MOS Capacitor

Oxide (insulator) Metal* (gate electrode)

Semiconductor (substrate)

* actual metal or heavily doped polysilicon

Page 11
Behavior of MOS Capacitor
Accumulation Depletion Inversion
Vg<0V Vg>0V Vg>>0V Gate electrode

＋ ＋ ＋ ＋ ＋ ＋ ＋ ＋
Gate insulator
- - - - - - - - - - - -
ー＋ ー＋ ー＋ ー＋ ー ー ー ー ー ー ー ー
ー＋ ー＋ ー＋ ー＋ t ー＋ ー＋ ー＋ ー＋ t ー ー ー ー
ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋
ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ t ー＋ ー＋ ー＋ ー＋
ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋ ー＋
ー＋ ー＋ ー＋ B＋ ー＋ ー＋ ー＋ B＋ ー＋ ー＋ ー＋ B＋ Silicon substrate
(P-type)

Accumulation Depletion Inversion

Capacitance

S ex.
C=ax t t … 10nm
(a: constant) C… pF

Gate Voltage

Page 12
MOSFET
*** Focusing on n-channel transistor ***

Gate <Symbol>
Gate insulator
Gate
Source Drain Electrode
Drain
Electrode

W
Source
Electrode

Ｎ+
Ｎ+
L
Channel
ubstrate
P-S
L: channel length
W: channel width
N+: heavily doped silicon
FET: Field Effect Transistor
= low resistive electrode

Page 13
Operation of N-channel MOSFET (1)
- Gate characteristics Id
Ammeter Vd (ex. 1.2V)

Vd > 0 Vg (0V)
0
Drain current (Id)

Voltmeter
G
Threshold voltage (Vth) S D
extrapolation

Gate voltage Vg

Sub-threshold region (0£Vg£Vth)

Id = 0 (nearly)

Page 14
Operation of N-channel MOSFET (2)
- Gate characteristics
Id
Ammeter Vd (ex. 1.2V)

Vd > 0 Vg (<Vth)
0
Drain current (Id)

Voltmeter
G
Threshold voltage (Vth) S D

Gate voltage Vg

When Vg<Vth, the electric current is called sub-threshold

current. This is one of the leakage currents.

Page 15
Operation of N-channel MOSFET (3)
- Gate characteristics
Id
sub-threshold (weak inversion) Ammeter Vd (ex. 1.2V)

Vd > 0 Vg (=Vth)
0
Drain current (Id)

normal
Voltmeter
(strong inversion)
G
threshold voltage (Vth) S D

Gate voltage Vg

ex.
Vth: order of 1/10 V
Id : order of nA

Page 16
Operation of N-channel MOSFET (4)
- Gate characteristics
Id
Ammeter Vd (ex. 1.2V)

Vd > 0 Vg (>Vth)
0
Drain current (Id)

Voltmeter
G
Threshold voltage (Vth) S D

Gate voltage Vg

Page 17
Operation of N-channel MOSFET (5)
- Gate characteristics
Id
Ammeter Vd (ex. 1.2V)

Vd > 0 Vg (>>Vth)
0
Drain current (Id)

Voltmeter
G
Threshold voltage (Vth) S D

Gate voltage Vg

Page 18
Operation of N-channel MOSFET (6)
- Drain characteristics
Id
Ammeter Vd
Linear Saturation
Vg4 Vg 0

Voltmeter
Drain current Id

Vg3
G
Vg2 S D
Vg1
Vg<Vth
Drain voltage Vd

Even if Vd>0, there is no current

(except leakage) when Vg<Vth.

Page 19
Operation of N-channel MOSFET (7)
- Drain characteristics
Id
Ammeter Vd
Linear Saturation
Vg4 Vg 0

(=Vg3)
Voltmeter
Drain current Id

Vg3
G
Vg2 S D
Vg1
Vg<Vth
Drain voltage Vd

Apply Vg=Vg3, and watch what happens.

Page 20
Operation of N-channel MOSFET (8)
- Drain characteristics
Id
Ammeter Vd
Linear Saturation
Vg4 Vg 0

(=Vg3)
Voltmeter
Drain current Id

Vg3
G
Vg2 S D
Vg1
Vg<Vth
Drain voltage Vd

Page 21
Operation of N-channel MOSFET (9)
- Drain characteristics
Id
Ammeter Vd
Linear Saturation
Vg4 Vg 0

(=Vg3)
Voltmeter
Drain current Id

Vg3
G
Vg2 S D
Vg1
Vg<Vth
Drain voltage Vd

Page 22
Operation of N-channel MOSFET (10)
- Drain characteristics
Id
Ammeter Vd
Linear Saturation
Vg4 Vg 0

(=Vg3)
Voltmeter
Drain current Id

Vg3
G
Vg2 S D
Vg1
Vg<Vth
Drain voltage Vd

When Vd=Vg-Vth, it is called “pinch-off point”.

Page 23
Operation of N-channel MOSFET (11)
- Drain characteristics
Id
Ammeter Vd
Linear Saturation
Vg4 Vg 0

(=Vg3)
Voltmeter
Drain current Id

Vg3
G
Vg2 S D
Vg1 Leff
Vg<Vth
Drain voltage Vd

After pinch-off, the current becomes constant.

Electrons are attracted by drain field and flow through
the depletion region.

Page 24
Current characteristics of MOSFET (Summary)
<Fundamental Formula of drain current>
bn {Vd(Vg-Vthn) - Vd2/2 } bn = µCox W/L
(Linear region µ: Electron Mobility
0£ Vd £ Vg-Vthn) Cox: Gate capacitance per unit area
Id = W: Gate width
bn (Vg-Vthn)2 /2 L: Gate length
(Saturation region Vthn : Threshold voltage of NMOS
Vd > Vg-Vthn) (gate voltage required to switch ON transistor)

<Characteristics of drain current >

Id Linear region Vg = 1.2V
(Triode region) n
Drain current at Vg = Vd = Vdd
th
-V

Saturation is called as
Vg

region Saturation Conditions:

=

0.9V
Vd

Vgs - Vth > 0

Vg < 0.4V Vds > Vgs - Vth
0.6V

0 Vd 1.2V
Page 25
Operations of nMOS Transistor
0V <Characteristics of drain current >
Source Gate 0®1.5V
0V ƒ

gs)
Drain

ltage (V
 n+ n+ Saturation

Ids
p-well Current does not flow

Gate vo
‚
0.5V 
0®1.5V 0
0V 0 Vds 1.5

‚ n+ n+ <Formula of drain current>

p-well Channel is created and bn {Vd×(Vg-Vthn)-Vd2/2}
current starts flowing
(when 0£Vd£Vg-Vthn)
1.5V Ids=
0®1.5V bn (Vgs-Vthn)2/2
0V (when Vd>Vg-Vthn)
ƒ n+ n+ bn: proportionality coefficient
Vthn: threshold voltage (gate voltage
p-well Channel expands and required to switch ON transistor)
current increases

Page 26
Operations of pMOS Transistor
1.5V
Source
Gate 1.5"0V
1.5V <Current characteristics>
Drain 3

Gate
(|Vgs
1 p+ p+ saturation

volta
|)
n-well Current does not flow

-Ids
2

ge
1.0V
1.5"0V 1
1.5V 0
0 Vds+1.5 1.5
2 p+ p+
<Formula of current>
n-well Current starts flowing when
channel is created - bp{Vd×(Vg-Vthp)-Vd2/2}
0V (when Vg-Vthp £Vd £0)
1.5→0V Ids＝
1.5V - bp(Vgs-Vthp)2/2
(when Vds<Vgs-Vthp)
3 p+ p+ bp : proportionality coefficient
Vthp: threshold voltage (gate voltage
n-well Channel expands and
current increases required to switch ON transistor)

Page 27
Structure of CMOS Transistor

pMOS transistor nMOS transistor

Gate Gate
Source Drain Drain Source

p+ p+ n+ n+
gate oxide gate oxide
n-type substrate (n-) p-type substrate (p-)
(n-well) (p-well)

Si substrate material (large resistivity)

MOS: Metal-Oxide Semiconductor
CMOS: Complementally MOS

Page 28
Inverter

<CMOS inverter Structure >

Input Output
Power supply
Power supply
(1.5V) GND Circuit VDD (1.5V)
Schematic
Gate Gate

p+ p+ n+ n+
= Input Output

Source Drain Drain Source

n-well p-well
pMOS nMOS

GND
Simplest logic circuit with a pair of pMOS and
nMOS transistors

Page 30
Logic Circuit on Silicon Chip
Inverter

Drain current (- Ids)

<Cell Symbol>

Input
Power supply Vin Vout

voltag
<Circuit VDD (1.5V)
Schematics>

e (Vin
0

)
pMOS
0
Drain voltage +1.5 ( Vout) 1.5 <Layout pattern>
Input Output
voltage voltage VDD

Drain current (Ids)

(Vout)

(Vin)
(Vin)

oltage
nMOS

Input v
GND A Vout
0
0 Drain voltage (Vout) 1.5

Inverter characteristics are defined by current characteristics of both transistors. Vss

Page 31
Logic Gate

• 2 input NAND (O=A B) • 2 input NOR (O=A+B) • Combinational gate (O=A B+C)
A
A A
O O B O
B B C

A
O B A
A O
O
B
B
C

§ With complementary transistor configurations, all logic circuits can be implemented.

§ Basically their complementary operations are similar to those of an inverter.

Page 32
Flip Flops
Principle of operation

clock LP1 clock LP2

?
D D ? 1. Gate G1 is ON while clock
G1 G2
remains low, and data D is
clock
taken into loop LP1.

setup
time (D) D 2. When clock rises, G1 is OFF
D D
and G2 is ON to pass data D
into next loop LP2.
hold
time
D 3. When clock goes low, G2 is
D OFF and LP2 keeps its data D.

Note FF output is not determined until any value is set from outside from logic
simulation standpoint. Especially cares should be taken after power on.

Page 33
Flip Flops
Metastable State (Metastability)

- To set logical threshold voltage (VLT) of each GATE at the same level
is important to secure noise margin: VLT = 1/2 VDD.
- But big problem in FLIP FLOPs.

VLT VLT
VIN VOUT

- When input VIN is held at VLT and then gate becomes OFF, the flip
flop MIGHT may keep this level for unpredictable period.
- But actually when small plus noise is applied to left node of loop,
VOUT accordingly becomes 0. In minus case, Vout goes to 1.
- Behavior of VOUT is not predictable depending upon noise level:
metastable.
< hypothetical case >

Page 34
Flip Flops
Metastable State (Metastability)

< actual case > When falling edge of IN and rising

edge of CLK are very close, voltages
IN
at inverter loop within FF become
OUT
close to VLT depending on timing of IN.
CLK Succeeding behavior is unpredictable.
FF

IN
OUT may be dependent
on many causes
~VLT or ~VLT
CLK

This phenomenon surely happens when IN is asynchronous

with CLK. OUT must be sensed at least one clock cycle after
CLK rising edge under focusing.

Page 35
Circuit libraries on SoC
1. Logic cell library
- Primitive cells (Inverter, Buffer, NAND, NOR, FF, etc.)
- Data Path (Execution unit, selector, multiple-bit width)
- Clock Buffer
- Power Control Circuits (Power Switch, Substrate Bias Controller)

2. Memory library
- Register File
- RAM (Random Access Memory)
- ROM (Read Only Memory)

3. Analog Circuit library

- IO (Input and Output Buffer, Level Shifter)
- PLL (Phased Locked Loop)
- ADC (Analog to Digital Converter)
- RF (Radio Frequency Circuit)
- PA (Power Amplifier)
Page 37
 Ideal wiring Actual wiring on the silicon

Resistance(R) = 0 R ≠0
No signal attenuation. Voltage drops with current.
Power consumption.
Capacitance(C) = 0
C≠0
Voltage can change at once
Voltage cannot jump up or down
Reactance(L) = 0 L≠0
Electric current can change at once Current cannot jump up or down.

R=0

C = 0, L=0

The ideal wire Circuit model

Page 39
Effect of R, C and L
Voltage drop by R
The IR drop
The effect of R

Delay in rise and fall

The wiring delay
The effect of C

Oscillation,
Delay increased
The effect of L
Over
shoot The actual
Ringing waveform is more
complicated.
Delay

Page 40
Delay definitions
Vin
Logic delay through a gate is conveniently described by the
propagation delay time, tp. This is average time needed for VDD
the output to respond to a change in the input logic state:
VDD/
2
tp = ½ (tpHL+tpLH)
Time
VSS
Falling propagation delay (tpHL):
Time for output to fall by 50% of VDD references to input tpHL tpLH
Vout
changes by 50% of VDD.
VDD
90%VDD
Rising propagation delay (tpLH):
Time for output to rise by 50% of VDD references to input VDD/2
changes by 50% of VDD
10%VDD Time
Fall time (tf): VSS
Time for output to fall from logical level “1” to level “0”. tf tr

Logical level:
Rise time (tr):
Time for output to rise from logical level “0” to level “1”. - Level “0”: from VSS to 10% of VDD;
- Level “1”: from 90% of VDD to VDD.
Page 41
Charge up & Discharge

VDD (1.2V) VDD (1.2V)

Charge
up
1.2®0V 0®1.2V 0®1.2V Discharge
1.2®0V

CL CL

GND GND

Rise time and fall time: times required to charge or discharge the load capacitor.
Large load capacitance results in large delay.

Page 42
Rise time - Delay of charge up

Power
supply u Current flows when pMOS is ON,
(VDD)
Is= |Ids|
= ( bp/2)▪ (VDD - |Vthp|)2
u Electric charge to be charged
Charge up 0®VDD
VDD®0V
Q = CL▪VDD
CL
Rise time is:
GND tr = Q/|Ids|
Note: Assume at initial state, CL was CL VDD
fully dis-charged to 0V =
( bp/2) ▪(VDD-|Vthp|)2

Page 43
Fall time - Delay for discharge

t Current flows when nMOS is ON,

(VDD)
Ids= (bn/2)▪(VDD-Vthn)2
t Electric charge to be discharged
0VàVDD VDDà0V Q = CL ▪ VDD
discharge
CL
Fall time is:
GND tf = Q/Ids
CL・VDD
Note: Assume at initial state, CL was =
fully charged to VDD (bn/2)▪(VDD-Vthn)2

Page 44
Summary of delay time

CL ▪ VDD : rise time

(bp/2)▪(VDD-|Vthp|)2
Delay time =
CL ▪ VDD : fall time
(bn/2)▪(VDD-Vthn)2

u Faster, if gate length L is shorter

b = µ*Cox*W/L
u Faster, if gate width W is wider
Mobility Capacity of gate oxide per
unit area

Page 45
Gate Delay & Wiring Delay

Input Input

Output Output gate delay

ideal Input/output cannot change at once.

Input Output

Countermeasures for reducing delay

The capacity of the - Reduction of the resistance
wiring to the next - Reduction of the capacitance
gate - Larger driving force

Page 47
Skew

For more-than-1-bit
skew signal, skew is always
a big problem.

Clock signal will always

Input all the Arriving at each suffer from skew
signal at destination at problem.
the same different times.
time.
These lines have
different electrical The clock
(R, C, L) characteristics.

The clock skew

Skew causes difficulty in wiring clock lines, especially in

higher frequency range and limits the clock speed.

Page 48
Hazard & Glitch
Hazard is a problem caused by a small timing difference among several signals.

X High Low
X Z
Y Low High
Y Z Low Low

X X

Y Logically Z Z may Y
must be become 1 for
Z short time Z
always zero

static ONE hazard

(low going glitch)
static hazard
Hazard static ZERO hazard
(high going glitch)
dynamic hazard
(oscillation hazard)

Page 49
How to avoid hazard?
It is difficult to prevent hazard. However, we can avoid using hazard signal
by selecting a timing to use the signal.

0 1
X
X Z
Y
Y 0 0
1 0 Z

False output After enough time

caused by passed, the output
hazard. must be true.

To avoid hazard, outputs of combinational logic must be used after

proper time period passed since input signals become stable.

Page 50
When handling edge signal, you must be very careful about
hazard, because edge signal is very sensitive to hazard.
Especially, clock signal is very sensitive to hazard.

The clock has

CLK CLK advanced by 1 cycle
ahead by hazard.

This cause a big problem. Why??

Hazard cause big problems resulting in malfunction

of a system. Synchronous design may help us to get
out of these problems.

To avoid hazard on clock signal, do not insert any combinational logic in clock line.

Page 51
Power Consumption
Electric power ~ V.I ~ V.Q/T ~ V.CV/T
~ C.V2/T
C
~ f.C.V2

The power consumption of CMOS The keys to reduce power consumption.

<1> Making operation voltage low
P ~ f.C.V2 <2> Lowering an operating frequency.
<3> Reducing capacitance and so on.
Dynamic power

Power consumption limits the operating speed.

Large power consumption makes it difficult to
design packages.

However, the leakage current is becoming significant, we have to apply partial

power off strategy to reduce power significantly.

Page 52
Short Circuit Power

short circuit
current
Input
Input
Out
t

Short circuit
current

Power consumption by short circuit current is

about less than10 to 15% of the total power
consumption

Page 53
Leak Current
Isb leak current
Input
Out
Igs Devices with large leak current are not applicable
leak current to battery powered products.
(Gate leak)

Gate size shrink and low

voltage operation
conductor insulator
Thinner gate insulator

The increase of the gate leak

by the tunnel current

Counter measure High K material dielectric constant,

Partial power-off or electric permittivity

Page 54
Metastability of Flip-Flop
Inv1
in1 out1 If In is given a value, such as mean value of low and
In Out high voltage, Out becomes unstable for some period
D and we can not tell what the final value shall be.
out2 in2 This is called “metastability”.
Inv2

In Out may be less than 10 n sec

or

clock
We cannot predict the result.
FF
In Out This may happen when input signal
changes at the instant of the clock pulse.
clock

Page 55
In many cases, metastability can be avoided by ensuring that inputs are held
constant for specified periods before and after the clock pulse.

Hold time
Setup time
If input signal changes
clock during Setup and Hold
time, metastability will
In occur.

Input data must be

stable during this period.

In synchronous design, by applying STA,

we can avoid metastability of FFs.

Typical Setup time or Hold time is less than 100 p sec.

Page 56
Unknown initial value of Flip-Flop

We can not tell the value of FF right after power on. (How about SRAM?)

The output signal of FFs must be used after

proper initialization sequence.

Many problems caused by unknown initial value of FF

have been experienced. Pay special attention to this
issue whenever you use FFs (or SRAM).

If a logic you designed uses the unknown initial values of FFs in a way that they
cause unexpected operation, it means you have implemented a logic bug.

Page 57
Fan-out
Vcc
It is not zero.
Because of output voltage drop, there is a Vcc
limitation (fan-out) in the number of the High
Vin
circuits which can be connected to an output.
Low

Inserting buffers
with the help of
EDA tool.
Fan-out problem causes malfunction of
the circuits. EDA tools can help us to
avoid this problem. Must be
modified.

Page 58
Because larger load result in larger delay as shown below, fan out issue is also
related to speed.

small delay

large delay

Sometimes delay of N stage gate logic is larger than that of

having more stages gate logic if some gates have larger load.

Page 59
 Ground bounce
Cannot keep the
potential of the ground
at zero when there is a
large current in the
Sharing the ground with other signals neighborhood.

A false signal can be observed

when the potential of the ground
is shaken by the other signal.

Simultaneous signal change and ground bounce

Ground bounce

Ground bounce creates false signal on certain signal

line, thus sometimes causes a malfunction of a device.

Page 60
 Cross talk
Capacitive coupling: Electrostatic induction
Cross talk
Inductive coupling: Electromagnetic induction

Victim

Aggressor The signal, different from the

input, appears at the other end of
the line.
Signal Integrity .5 mm will cause
IR Drop: Voltage drop proportional to the a big problem
current.
Cross talk: Wrong signal detected by the
influence of the neighboring wire.

Cross talk creates false signal on certain signal line, thus sometimes causes a malfunction of a device.

IR drop creates insufficient power supply to certain circuit

on silicon and limit miniaturization and operating frequency.

Page 61
EMC/EMI
Electromagnetic pulse

False signal will be observed

caused by the electromagnetic
disturbance.

Electromagnetic pulse EMI: Electromagnetic Interference

Electromagnetic emission EMS: Electromagnetic Sustainability

EMC: Electromagnetic Compatibility

Electromagnetic interference may creates false signal on certain

signal line, thus sometimes causes a malfunction of a device.
It becomes difficult to comply with EMC guide lines as operating
frequency of devices goes high.

Page 62
Radiation from the package and cosmic ray
neutron
The influence of neutron radiation
and so on, are becoming +
significant. - +
+-
-
N-type
Alpha ray, gamma ray and
neutron radiation

Transistor malfunctions caused by the radiation

Large scale memory can not avoid this problem,

therefore some error correction system is necessary
for such large scale memory.

Page 63
The different characteristic of nMOS & pMOS
Tr Tf
When the driving
pMOS power of n/p MOS
Generally, nMOS
are the same
has a bigger
driving capability
nMOS In case of N > P

The rising becomes gentle because the

driving power of pMOS is weak.

It becomes difficult to keep the duty ratio of on/off such as the clock at 50%.

Clock skew problem may become critical

when inserting a buffer into the clock line.

Page 64
Electron migration
Atoms of wire material, aluminum or copper, are kicked out of the
wire line by electrons. This sometimes causes a breaking of wire.

aluminum wire several years later

aluminum
atoms kicked breaking
out of the wire

To avoid this problem we have to keep

electron flow current density less than some limitation.

Some DA tool can give us warning that there may

be electron migration problem.

Page 65
Other issues
Slow rising of the input Over current of
Vcc voltage around the Vth. MOS
Vth
0 Ringing of the input False signal
1 voltage around the Vth.
0

Vcc
Runt pulse: a narrow pulse which does
Vth
not reach a valid high or low level
0

Glitch: a pulse shorter than the

specified minimum

Spike: a short pulse similar to glitch but

often caused by ringing or cross talk.

Page 66