PS2 Model 25 Technical Reference Jun87

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First Edition (June 1987)
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© Copyright International Business Machines Corporation 1987. All rights reserved.

Preface
This publication describes the components of the IBM Personal

System/2™ Model 25 (Type 8525) and their interaction.
The information in this publication is for reference and is intended for

hardware and software designers, programmers, engineers, and
others who need to understand the design and operation of the Type
8525.
This manual is divided into the following sections:
Section 1. "System Board" discusses the functions of the system

board.
Section 2. "Coprocessor" describes the 8087-2 Math Co-
processor and provides programming and hardware interface
information.
Section 3. "Power Supply" provides electrical input/output spec-
ifications as well as a theory of operation for the power supply.
Section 4. "Keyboard" discusses the hardware, function,
encoding, and layouts of the keyboards.
Section 5. "System BIOS" describes the basic input/output
system and the interrupt interfaces. This section also contains a
BIOS memory map, descriptions of vectors with special
meanings, and a set of low memory maps.
Section 6. "Instruction Set" provides a quick reference for the
8086 and 8087 assembly instruction set.
Section 7. "Characters and Keystrokes" supplies the decimal
and hexadecimal values for characters.
A Glossary, Bibliography, and Index are also provided.
TM IBM Personal System/2 is a trademark of the International Business

Machines Corporation.
iii
Prerequisite Publications
• IBM Personal System/2 Model 25 (Type 8525) Guide to

Operations.
Suggested Related Publications
• BASIC for the IBM Personal Computer

• Disk Operating System (DOS)
• Hardware Maintenance Service
• Hardware Maintenance Reference
• Macro Assembler for the IBM Personal Computer.
Additional Information
• Additional technical information for the IBM Personal System/2

Model 25 (Type 8525) is available from the Technical Directory.
To receive a free copy of the Technical Directory, call toll free
1-800-iBM-PCTB, Monday through Friday, 8:00 a.m. to 8:00 p.m.,
Eastern Time.
Iv
Contents
SECTION 1. System Board .............................. 1-1

General Description .................................... 1-3
Microprocessor ....................................... 1-5
System Support Gate Array ........................... 1-6
1/0 Support Gate Array .............................. 1-8
DMA Controller ................................... 1-13
Interrupts ........................................ 1-13
Interrupt Sharing .................................. 1-14
Read/Write Memory ................................... 1-22
ROM ............................................... 1-22
I/O Channel .......................................... 1-23
Connectors ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-25
Signal Description ................................. 1-26
Signal Timings .................................... 1-28
Video Subsystem ..................................... 1-36
Block Diagram .................................... 1-37
Display Support ................................... 1-38
Text Modes ...................................... 1-38
Graphics Modes ................................... 1-38
Display Formats ................................... 1-40
Video Storage Organization ......................... 1-42
Video Registers ................................... 1-44
Video Initialization Tables ........................... 1-62
RAM-Loadable Fonts ............................... 1-64
Programming Considerations ........................ 1-71
Connector ....................................... 1-77
Diskette Drive Interface ................................ 1-78
Gate Array Registers ............................... 1-79
Controller Registers ............................... 1-81
Commands ....................................... 1-83
Signal Description ................................ 1-102
Connector ...................................... 1-104
Serial Port ......................................... 1-105
Application ...................................... 1-106
Controller Registers .............................. 1-107
Programmable Baud-Rate Generator ................. 1-116
Signal Descriptions ............................... 1-117
Connector ...................................... 1-119
v
Parallel Port ........................................ 1-120
Port Registers ................................... 1-120
Connector ...................................... 1-124
Beeper ............................................ 1-125
Earphone Connector ................................. 1-125
Connectors ......................................... 1-126
Specifications ....................................... 1-128
SECTION 2. Coprocessor ............................... 2-1

Description ........................................... 2-3
Programming Considerations ............................ 2-3
Hardware Interface .................................... 2-4
SECTION 3. Power Supply .............................. 3-1

Description ........................................... 3-3
Input and Output Power ................................. 3-4
Output Protection ...................................... 3-5
Power-Good Signal .................................... 3-5
Connectors ........................................... 3-6
SECTiON 4. Keyboard .................................. 4-1

Description ........................................... 4-3
Power-on Routine .................................. 4-4
Clock and Data Signals .............................. 4-5
Commands ........................................... 4-7
Scan Codes .......................................... 4-8
84/85-Key Keyboard ............................... 4-11
Encoding ........................................ 4-11
Layouts ......................................... 4-25
Cables and Connectors ................................ 4-46
Specifications ........................................ 4-47
SECTION 5. System BIOS ............................... 5-1

System BIOS Usage .................................... 5-3
Hardware Interrupts .................................... 5-4
Software Interrupts .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4
Interrupt Interface Listing ............................... 5-10
Interrupt 02H - Non-Maskable Interrupt Routine .......... 5-10
Interrupt 05H - Print Screen .......................... 5-10
Interrupt 08H - System Timer ........................ 5-11
Interrupt 09H - Keyboard ............................ 5-12
Interrupt 10H - Video ............................... 5-13
Interrupt 11 H - Equipment Determination ............... 5-28
vi
Interrupt 12H - Memory Size Determination ............. 5-29
Interrupt 13H - Diskette ............................. 5-30
Interrupt 14H - Asynchronous Communications .......... 5-37
Interrupt 15H - System Services ...................... 5-42
Interrupt 17H - Printer .............................. 5-53
Interrupt 19H - Bootstrap Loader ...................... 5-54
Interrupt 1AH - Time of Day .......................... 5-55
BIOS Data Area and Locations .......................... 5-56
Extended BIOS Data Area .............................. 5-61
ROM Tables ......................................... 5-62
Asynchronous Baud Rate Initialization Table ............ 5-62
Diskette Parameter Table ........................... 5-62
Model Byte .......................................... 5-63
SECTION 6. Instruction Set .............................. 6-1

8086 Register Model .................................... 6-3
Notes ............................................ 6-4
8086 Instruction Set .................................... 6-7
Data Transfer ...................................... 6-7
Arithmetic ........................................ 6-9
Logic ........................................... 6-13
String Manipulation ................................ 6-15
Control Transfer ................................... 6-15
Processor Control ................................. 6-20
Instruction Set Matrix .............................. 6-22
8087 Coprocessor Instruction Set ........................ 6-24
Notes ........................................... 6-24
Data Transfer ..................................... 6-24
Comparison ...................................... 6-26
Arithmetic ....................................... 6-26
Transcendental ................................... 6-28
Constants ........................................ 6-29
SECTION 7. Characters and Keystrokes .................... 7-1

Character Codes ................................... 7-2
Table Notes ....................................... 7-7
Quick Reference ................................... 7-8
Glossary ............................................ X-1
Bibliography ......................................... X-15
vii
Index ....... '........................................ X-17
vIII
Figures
1-1. System Functional Diagram ...................... 1-4

1-2. Memory Map .................................. 1-5
1-3. System Board Control Register, Hex 65 ............. 1-8
1-4. System Timer Block Diagram ..................... 1-9
1-5. Output Port, Hex 61 ............................ 1-11
1-6. Input Port, Hex 62 ............................. 1-12
1-7. DMA Channel Assignments ...................... 1-13
1-8. DMA Page Register Addresses ................... 1-13
1-9. Hardware Interrupt Listing ...................... 1-14
1-10. Shared Interrupt Hardware Logic ................. 1-15
1-11. System Board RAM Control/Status Register ........ 1-22
1-12. I/O Address Map .............................. 1-24
1-13. 110 Channel .................................. 1-25
1-14. 8-Bit 110 Timing ............................... 1-29
1-15. 8-Bit Memory Timing ........................... 1-30
1-16. 16-Bit 110 Timing .............................. 1-31
1-17. 16-Bit Memory Timing .......................... 1-32
1-18. Memory Refresh Timing ........................ 1-33
1-19. DMA Read Timing ............................. 1-34
1-20. DMA Write Timing ............................. 1-35
1-21. Video Subsystem Block Diagram ................. 1-37
1-22. Video Mode Summary .......................... 1-39
1-23. Alphanumeric Format .......................... 1-40
1-24. Attribute Byte ................................. 1-40
1-25. Modes 4 and 5 ................................ 1-41
1-26. Modes 6 and 11 ............................... 1-41
1-27. Text Modes 0 through 3 ......................... 1-42
1-28. Graphics Modes 4 through 6 ..................... 1-43
1-29. GraphicsModes11and13 ...................... 1-43
1-30. Video Memory Controller Index Register ........... 1-44
1-31. Sync Pulse Width Register ...................... 1-46
1-32. Vertical Total Adjust Register .................... 1-47
1-33. Scan Lines per Character Register ................ 1-47
1-34. Cursor Start Register ........................... 1-48
1-35. Cursor End Register ........................... 1-48
1-36. Cursor Position High Register .................... 1-49
1-37. Mode Control, Write ............................ 1-49
1-38. Mode Control, Read ............................ 1-50
ix
1-39. Interrupt Control Register ....................... 1-51
1-40. Character Generator Interface and Sync Polarity
Register ..................................... 1-51
1-41. Monitor Sense Bits ............................ 1-52
1-42. CGA Mode Register ............................ 1-54
1-43. CGA Border Control Register .................... 1-55
1-44. Modes 4 and 5 Color Selection ................... 1-55
1-45. Status Register ............................... 1-56
1-46. Extended Mode Control Register ................. 1-56
1-47. Last Palette Command ......................... 1-60
1-48. Color Palette Data Register ...................... 1-61
1-49. Memory Controller Initialization .................. 1-62
1-50. Video Formatter Initialization Table ............... 1-63
1-51. 16-Color Compatibility Initialization ............... 1-63
1-52. Font Memory Map ............................. 1-64
1-53. Sample Character ............................. 1-65
1-54. Block Specifier .... . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-68
1-55. Alternate Parameter Table ...................... 1-70
1-56. Write to Palette Address Register ................. 1-72
1-57. Read Palette Address Register ................... 1-72
1-58. Write Color followed by a Read ................... 1-73
1-59. Write Color followed by a Write ................... 1-74
1-60. Read Color followed by a Read ................... i -75
1-61. Read Color followed by a Write ................... 1-76
1-62. Display Connector ............................. 1-77
1-63. RAS Port A, Hex 3FO ........................... 1-79
1-64. RAS Port B, Hex 3F1 ........................... 1-79
1-65. Digital Output, Hex 3F2 ......................... 1-80
1-66. Digital Input, Hex 3F7 .......................... 1-80
1-67. Configuration Control, Hex 3F7 ................... 1-81
1-68. Main Status Register ........................... 1-82
1-69. Read Data Command .......................... 1-86
1-70. Read Data Result .............................. 1-86
1-71. Read Deleted Data Command .................... 1-87
1-72. Read Deleted Data Result ....................... 1-87
1-73. Read a Track Command ........................ 1-88
1-74. Read a Track Result ........................... 1-88
1-75. Read ID Command . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-89
1-76. Read ID Result ................................ 1-89
1-77. Write Data Command .......................... 1-90
1-78. Write Data Result .............................. 1-90
1-79. Write Deleted Data Command .................... 1-91
1-80. Write Deleted Data Result ....................... 1-91
x
1-81. Format a Track Command ....................... 1-92
1-82. Format a Track Result .......................... 1-92
1-83. Scan Equal Command .......................... 1-93
1-84. Scan Equal Result ............................. 1-93
1-85. Scan Low or Equal Command .................... 1-94
1-86. Scan Low or Equal Result ....................... 1-94
1-87. Scan High or Equal Command ................... 1-95
1-88. Scan High or Equal Result . . . . . . . . . . . . . . . . . . . . . .. 1-95
1-89. Recalibrate Command .......................... 1-96
1-90. Sense Interrupt Status Command ................. 1-96
1-91. Sense Interrupt Status Result .................... 1-96
1-92. Specify Command ............................. 1-97
1-93. Sense Drive Status Command .................... 1-97
1-94. Sense Drive Status Result ....................... 1-97
1-95. Seek Command ............................... 1-98
1-96. Invalid Command Result ........................ 1-98
1-97. Diskette Drive Connector . . . . . . . . . . . . . . . . . . . . . .. 1-104
1-98. Serial Port Block Diagram ...................... 1-105
1-99. Serial Port Addresses ......................... 1-107
1-100. Transmitter Holding Register ................... 1-107
1-101. Receiver Buffer Register ....................... 1-108
1-102. Divisor Latch ................................ 1-108
1-103. Interrupt Enable Register ...................... 1-109
1-104. Interrupt Identification Register. . . . . . . . . . . . . . . . .. 1-110
1-105. Line Control Register ......................... 1-111
1-106. Modem Control Register ....................... 1-112
1-107. Line Status Register .......................... 1-113
1-108. Modem Status Register ........................ 1-115
1-109. Serial Port Connector ......................... 1-119
1-110. Serial Interface Specifications .................. 1-119
1-111. Parallel Port Block Diagram .................... 1-120
1-112. Printer Control Register ....................... 1-121
1-113. Printer Status Register ........................ 1-122
1-114. Parallel Port Signal Timing ..................... 1-123
1-115. Parallel Port Connector ........................ 1-124
1-116. Beeper Tone Generation ....................... 1-125
1-117. System Board Connector Location ............... 1-126
1-118. Power Supply Connector ....................... 1-127
1-119. Keyboard Connector and POinting Device ......... 1-127
2-1. Coprocessor Data Types ......................... 2-4
2-2. Coprocessor Interconnection ..................... 2-5
3-1. V ac Input Requirements ......................... 3-4
3-2. V dc Output ................................... 3-4
xi
3-3. Output Protection ............................... 3-5
3-4. Power Supply Connector ......................... 3-6
4-1. Keyboard Data Stream .......................... 4-6
4-2. Commands from the Keyboard .................... 4-7
4-3. Scan Codes (Part 1 of 4) ......................... 4-9
4-4. Scan Codes (Part 2 of 4) ........................ 4-10
4-7. Scan Codes for 84/85 Numeric Keypad ............. 4-11
4-8. 101-Key Keyboard Layout ....................... 4-12
4-9. 102-Key Keyboard Layout ....................... 4-13
4-10. 84-Key Keyboard Layout ........................ 4-14
4-11. 85-Key Keyboard Layout ........................ 4-15
4-12. Character Codes .............................. 4-16
4-13. Special Character Codes ........................ 4-19
4-14. Keyboard Extended Functions .................... 4-20
4-15. Keyboard Cable Connectors ..................... 4-46
5-1. Software Interrupt Listing ........................ 5-5
5-2. BASIC and DOS Interrupts ....................... 5-7
5-3. Reserved Memory Locations ............... . . . . . .. 5-7
5-4. BASIC Workspace Variables ...................... 5-8
5-5. BIOS Memory Map ............................. 5-8
6-1. 8086 Register Model ............................ 6-3
6-2. Flag Register .................................. 6-4
6-3. Segment Override Prefix ......................... 6-5
6-4. reg Field Assignment ........................... 6-5
6-5. mod Field Assignment ........................... 6-6
6-6. rim Field Assignments .......................... 6-6
6-7. Conditional Transfer Operations .................. 6-19
xii
SECTION 1. System Board
General Description .................................... 1-3

Microprocessor ....................................... 1-5
System Support Gate Array ........................... 1-6
Bus Controller .................................. 1-6
Memory Controller and Parity Checker .............. 1-6
Bus Conversion Logic and Wait-State Generator ....... 1-7
System Clock Generator .......................... 1-7
1/0 Support Gate Array .............................. 1-8
Chip Select Logic ............................... 1-8
Keyboard and Pointing Device Controller ............ 1-9
System Timer .................................. 1-9
1/0 Ports ..................................... 1-11
DMA Controller ................................... 1-13
Interrupts ........................................ 1-13
Interrupt Sharing .................................. 1-14
Design Overview ............................... 1-14
Program Support ............................... 1-15
Precautions ................................... 1-17
ROM Considerations ............................ 1-18
Examples ..................................... 1-18
ReadlWrite Memory ................................... 1-22
ROM ............................................... 1-22
1/0 Channel .......................................... 1-23
Connectors .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-25
Signal Description ................................. 1-26
Signal Timings .................................... 1-28
Video Subsystem ..................................... 1~36
Block Diagram .................................... 1-37
Display Support ................................... 1-38
Text Modes ...................................... 1-38
Graphics Modes ................................... 1-38
Display Formats ................................... 1-40
Video Storage Organization ......................... 1-42
Video Registers ................................... 1-44
Video Memory Controller Registers ................ 1-44
Video Formatter Registers ....................... 1-53
Color Palette Registers .......................... 1-57
Video Initialization Tables ........................... 1-62
System Board 1-1

RAM-Loadable Fonts ............................... 1-64
Alternate Parameter Table ....................... 1-70
Programming Considerations ........................ 1-71
Connector ....................................... 1-77
Diskette Drive Interface ................................ 1-78
Gate Array Registers ............................... 1-79
Controller Registers ............................... 1-81
Commands ....................................... 1-83
Command Format .............................. 1-86
Command Status Registers ...................... 1-99
Signal Description ................................ 1-102
Connector ...................................... 1-104
Fixed Disk Connector. . . . . . . . . .. .. . . . . . . . . . . . . . . . . .. 1-104.1
Serial Port ......................................... 1-105
Application ...................................... 1-106
Controller Registers .............................. 1-107
Programmable Baud-Rate Generator ................. 1-116
Signal Descriptions ............................... 1-117
Input Signals ................................. 1-117
Output Signals ................................ 1-118
Connector ...................................... 1-119
Parallel Port .................................... 1-120
Port Registers ................................... 1-120
Connector ...................................... 1-124
Beeper ............................................ 1-125
Earphone Connector ................................. 1-125
Connectors ......................................... 1-126
Specifications ....................................... 1-129
Size ........................................ 1-129
Weight ...................................... 1-129
Power Cable ................................. 1-129
Environment ................................. 1-129
Heat Output .................................. 1-130
Noise Level .................................. 1-130
Electrical .................................... 1-130
1-2 System Board

General Description
The IBM Personal System/2™ Model 25 (Type 8525) is a highly inte-
grated system using five gate arrays: two for microprocessor
support, two for video support, and one for the diskette controller
support. The major functional areas are:
• 8086-2 microprocessor and its support logic

• 512K read/write memory standard, with an additional 128K
optional for a total of 640K
• 64K read-only memory (ROM)
• Input/Output (I/O) channel
• Integrated I/O functions
Color/graphics subsystem
Diskette drive interface
Fixed disk connector
Serial port
Parallel port
Keyboard and pointing device ports.
System dc power and a 'power good' signal from the power supply
enter the system board through a 12-pin connector. Other connectors
on the system board are for attaching the keyboard, pointing device,
coprocessor, display, earphone, serial and parallel devices, fan, and
storage media.
Two 62-pin card-edge sockets are attached to a vertical expansion

bus that is mounted to the system board. The I/O channel is extended
to these two I/O slots.
TM IBM Personal System/2 is a trademark of the International Business

Machines Corporation.
System Board 1-3

System Functional Diagram
1/0 Channel
8086
00-07
08-015
System Display
Support
Gate
Array
8087 1/0
00-07 Support
Gate
Array
08-015
Async
640K
RAM Printer
Fixed
Disk
Figure 1-1. System Functional Diagram
1-4 System Board

Microprocessor
The Intel 8086-2 is a 16-bit microprocessor with a 16-bit external data
bus, operating at 8 MHz. The microprocessor supports the same
20-bit addressing as IBM Personal Computers that use the 8088
microprocessor. The Type 8525 uses a 16-bit data bus with the sys-
tem's read-only and readlwrite memory, and an 8-bit data bus for all
110 and direct memory access (OMA) operations.
The memory read and write are 16-bit operations and take four clock
cycles of 125 ns, with no wait states, for a cycle time of 500 ns.
Normal 1/0 operations are 8-bit operations and take eight clock
cycles, including four wait states, for a cycle time of 1 j.ls. A signal on
the 1/0 channel, 1/0 channel ready (1/0 CH ROY), allows slower
devices to add more wait states to 1/0 and OMA operations (see "1/0
Channel" later in this section).
Logic has been added to the system board to support options for the
IBM Personal Computer family. This includes converting 16-bit oper-
ations to sequential 8-bit operations, inserting wait states into all 1/0
and OMA operations, and delaying microprocessor cycles to ensure
address setup times greater than or equal to the 8088-based systems.
The 8086-2 supports 16-bit operations, including multiply and divide,

and 20-bit addressing to access 1M (M = 1,048,576) of address
space. It also operates in maximum mode, so a math coprocessor
can be added as a feature. Memory is mapped as follows:
Hex Address Function
00000 - 9FFFF 640K Read/Write Memory
AOOOO - BFFFF Video Buffer
COOOO - EFFFF Reserved for BIOS on I/O Channel
FOOoo - FFFFF System ROM
Figure 1-2. Memory Map
System Board 1-5

The microprocessor is supported by two high-function support
devices: a system support gate array and an I/O support gate array.
System Support Gate Array
The system support gate array contains the bus controller, the
memory controller and parity checker, the wait-state generator and
bus conversion logic, the system clock generator, and the DMA page
register and support logic.
Bus Controller
The Type 8525 has three bus masters on the local bus: the micro-
processor, the coprocessor, and the system support gate array. The
gate array seizes the bus to generate memory refresh and DMA bus
cycles. It controls two request/grant lines (CPU RQ/GT and NPU
RQ/GT). One is connected to the microprocessor and the other to the
coprocessor.
When the coprocessor is not installed, the gat8 array generates a

request pulse to the microprocessor to get control of the bus. The
microprocessor then gives control of the bus and pulses the same
line to indicate a grant. When the coprocessor is installed, the gate
array generates this pulse to the coprocessor. If the coprocessor has
control of the bus, it grants control to the gate array. If the
coprocessor is not in control, it relays the request to the micro-
processor and relays the grant back to the gate array. This arrange-
ment gives the gate array the highest priority use of the bus.
Memory Controller and Parity Checker
The memory controller functions of the gate array control memory

and generate the memory refresh. Memory must be refreshed once
every 4 ms. Memory refresh takes nine clock cycles of 125 ns
through a dedicated refresh channel within the gate array.
The parity checker function generates the parity bits for system
memory and activates the '-parity check' signal when a parity error is
detected. Only the read/write memory on the system board is
checked.
1-6 System Board

Bus Conversion Logic and Walt-State Generator
The bus conversion logic converts word transfers to I/O devices into 2
single-byte transfers. Sixteen-bit transfers are only supported for the
system's read-only and readlwrite memory.
Additional logic generates the needed wait states for the micro-
processor bus cycles to 1/0 devices. This logic monitors the '1/0 CH
ROY' line to determine the wait states required.
System Clock Generator
The system clock generator uses a 48 MHz input that is internally

divided to give the output clock signal of 8 MHz with a 33% duty
cycle. It also generates a 1.84 MHz signal for the serial port.
The clock generator generates the 'reset' signal after sensing the
'power good' signal from the power supply.
System Board 1-7

1/0 Support Gate Array
The 110 support gate array contains the chip select (CS) logic, key-
board and pointing device controller, and 110 ports. It also contains
the interrupt controller.
Chip Select Logic
The gate array controls the following CS signals on the system board:
• Serial port
• Diskette controller
• Video controller
• Parallel port
• Fixed disk controller
Each select line can be disabled by programming the System Board

Control register, address hex 65. When the bit is set to 1, that func-
tion of the system board is enabled. Bit 7, parallel port output enable,
enables the parallel port's output drivers.
When the signal is enabled, the CS signal is generated to start a read

or write operation, and the read and write signals to the 110 channel
are blocked. When the signal is disabled, the CS signal is not gener-
ated, and all read and write operations are directed to the 110
channel. This register is read/write.
Bit Function
7 Parallel Port Output Enable

6 Reserved = 0
5 Reserved = 0
4 Serial CS
3 Diskette CS
2 Video CS
1 Parallel Port CS
o Fixed Disk CS
Figure 1-3. System Board Control Register, Hex 65
1-8 System Board

Keyboard and Pointing Device Controller
The interface logic for the keyboard and the pointing device is the
same, allowing the keyboard and pointing device to plug into either of
the two 6-pin connectors at the rear of the system.
The interface recetves the serial data and checks the parity. The data
is then presented to the system at the interface's output buffer, I/O
port hex 60.
System Timer
The system timer is an 8253 programmable interval timer/counter, or

equivalent, that functions as an arrangement of four external I/O ports
(hex 0040 through 0043). It receives its 1.19 MHz clock from the I/O
support gate array. Three ports are treated as counters; the fourth,
address hex 0043, is a control register for mode programming.
The content of a selected counter may be latched without disturbing

the counting operation by writing to the control register. If the content
of the counter is critical to a program's operation, a second read is
recommended for verification.
System Timer
System B us
Gate 0
.--- Clock in 0
+5Vdc Gate 1
- RAS-.SIP L Clock in 1
110 Port
Hex 0061 Gate 2
Port Bit 0
Clock in 2
IROO
Clock Out 0
1.19 MHz
Clock Out 1
I Driver I
Clock Out 2 J I
110 Port IANDI Low ~ToBeep er
Hex 0061 Pass
Port Bit 1 Filter
Figure 1-4. System Timer Block Diagram
System Board 1-9

The three timers are programmable and are used by the system as
follows:
Channel 0 is a general-purpose timer providing a constant time base.
Channel 0 System Timer
GATE 0 Tied High

ClK IN 0 1.19 MHz OSC
ClK OUT 0 IRQO
Channel 1 is for internal diagnostic tests.
Channel 1 Diagnostic
GATE 1 Tied High

ClK IN 1 -RAS_SIP from system support gate array
ClKOUT 1 Not connected
Channel 2 supports the tone generation for the audio.
Channel 2 Tone Generation
GATE 2 Controlled by bit 0 at port hex 61

ClK IN 2 1.19 MHz OSC
ClKOUT 2 To the beeper data of the 110 support gate array
1-10 System Board

1/0 Ports
The output port hex 60 is used by BIOS to store keystrokes. The

output port hex 61 is used as beeper control, enables I/O channel
check and parity checks, and is read/write. The input port hex 62
contains the status of certain signals on the system board and is
read-only. The bit descriptions of ports hex 61 and hex 62 follow.
Bit Function
7 Reserved
6 Reserved
5 -ENA I/O CH CK
4 -EN A RAM Parity CK
3 Reserved
2 Reserved
1 Beeper Data
o Timer 2 Gate (to beeper)
Figure 1-5. Output Port, Hex 61
Port 61
Bit Connected to Description
7-6 Not connected Reserved
5 -ENA I/O CH CK When set to 1, this bit stops -I/O CH CK from

generating a non-maskable interrupt (NMI).
When cleared to 0, an NMI is generated when
-I/O CH CK goes active.
4 -ENA RAM When set to 1, this bit stops a memory parity

PARITYCK error from generating an NMI. When cleared
to 0, an NMI is generated when a memory
parity error is sensed.
3-2 Not connected Reserved
1 Beeper Data This bit gates the output of timer 2. It is used

to disable the timer's sound source or modify
its output. When set to 1, this bit enables the
output; when cleared, it forces the output to
zero.
o Timer 2 Gate This line is routed to the timer input at GATE

2. When this bit is cleared to 0, the timer
operation is halted. This bit and bit 1 (beeper
data) control the operation of the timer's
sound source.
System Board 1·11

Bit Function
7 Parity
6 1/0 CH CK
5 Timer 2 Output
4 Reserved
3 Reserved
2 -Disk Installed
1 Coprocessor installed
o Reserved
Figure 1-6. Input Port, Hex 62
Port 62
Bit Connected to Description
7 Parity When set to 1, this bit indicates that a

memory parity error has occurred.
6 I/O CH CK When set to 1, this bit indicates that -I/O CH

CK is active.
5 Timer 2 Output This bit shows the status of the Timer 2

Output.
4-3 Not connected Reserved.
2 -Disk Installed When cleared to 0, this bit indicates that the

fixed disk and controller are installed.
Coprocessor When set to 1, this bit indicates that the Math

installed Coprocessor is installed.
o Not connected Reserved.
1-12 System Board

DMA Controller
The 8237 Direct Memory Access (DMA) controller and its support
logic in the gate array support four channels of 20 address bit DMA.
It operates at 4 MHz and handles only 8-bit data transfers. The DMA
channel assignments and page register addresses are:
Level Assignment
DRQO Not Available

DRQ1 Not Used
DRQ2 Diskette
DRQ3 Fixed Disk
Figure 1-7. DMA Channel Assignments
Hex
Address DMA Page Register
081 Channel 2
082 Channel 3
083 Channel 1
087 Channel 0
Figure 1-8. DMA Page Register Addresses
Three of the DMA channels (1, 2, and 3) are available on the I/O bus
and support high-speed data transfers between I/O devices and
memory without microprocessor intervention.
DMA data transfers take six clock cycles of 250 ns, or 1.5 micro-
seconds. 1/0 CH RDY can be pulled inactive to add wait states to
allow more time for slower devices.
Interrupts
The interrupt controller has eight levels of interrupts that are handled
according to priority in the I/O support gate array. Two levels are
used only on the system board. Level 0, the highest priority, is
attached to Channel 0 of the timer/counter and provides a periodic
interrupt for the timer tick. Level 1 is shared by the keyboard and the
pointing device. It is handled by a BIOS routine pointed to by inter-
rupt hex 71. Level 2 is available to the video subsystem, and level 7
is available to the parallel port; however, the BIOS routines do not
use interrupts 2 and 7. Level 4 is used by the serial port.
System Board 1-13

This controller also has inputs from the coprocessor's '-interrupt', the
memory controller's '-parity', and the '-I/O channel check' signals.
These three inputs are used to generate the NMI to the 8086-2.
The following table shows the hardware interrupts and their avail-
ability to the I/O channel.
Level System Board 1/0 Channel
NMI Parity Check and 1/0 Channel Check

Coprocessor
IROO Timer Channel 0 Not Available
IR01 Keyboard Not Available
POinting Device
IR02 Video Available
IR03 Not Used Available
IR04 Serial Port Available
IR05 Fixed Disk Available
IR06 Diskette Drive Available
IR07 Parallel Port Available
Note: Interrupts are available to the I/O channel if they are not enabled by the
system board function normally assigned to that interrupt.
Figure 1-9. Hardware Interrupt Listing
Interrupt Sharing
A standardized hardware design concept has been established to

enable multiple adapters to share an interrupt level. The integrated
adapters do not use interrupt sharing. The following describes this
design concept and discusses the programming support required.
Design Overview
Most interrupt-supporting adapters hold the IRQ line inactive and

then drive the line active to cause an interrupt. In contrast, the
shared interrupt hardware design allows the IRQ line to float high.
Each adapter on the line may cause an interrupt by pulsing the line
low. The leading edge of the pulse arms the interrupt controller; the
trailing edge of the pulse causes the interrupt.
Each adapter sharing an interrupt level must monitor the IRQ line.
When any adapter pulses the line, all other adapters on that interrupt
must not issue an interrupt request until they are rearmed.
1-14 System Board

If an adapter's interrupt is active when it is rearmed, the adapter
must reissue the interrupt. This prevents lost interrupts in case two
adapters issue an interrupt at exactly the same time and an interrupt
handler issues a Global Rearm after servicing one of them.
The following diagram shows the shared interrupt hardware logic.
+5
INT D Of----1D o
ENA
>ClK -0 >ClK -0
-ClR -ClR 2.2K Ohms
Syslem
Clock -----e>---+------'
+5 Tri 5Ial"::>'----*"- -IRO
,-----,
D 0
' - - - - - I > ClK -0

-ClR
-Global
Rearm - - - - < 1 > - - - - - - '
Figure 1-10. Shared Interrupt Hardware Logic
Program Support
The interrupt-sharing program support described in the following pro-

vides for an orderly means to:
• Link a task's interrupt handler to a chain of interrupt handlers

• Share the interrupt level while the task is active
• Unlink the interrupt handler from the chain when the task is deac-
tivated.
System Board 1-15

Linking onto the Chain: Each newly activated task replaces the inter-
rupt vector in low memory with a pointer to its own interrupt handler.
The old interrupt vector is used as a forward pointer and is stored
away at a fixed offset from the new task's interrupt handler. This
method of linking means the last handler to link is the first one in the
chain.
Sharing the Interrupt Level: When the new task's handler gains
control as a result of an interrupt, the handler reads the contents of
the adapter's Interrupt Status register to determine whether its
adapter caused the interrupt. If its adapter did cause the interrupt,
the handler services the interrupt, disables (clears) the interrupts
(eLi), and writes to address hex 02FX, where X corresponds to inter-
rupt levels 2 through 7. Each adapter in the chain decodes the
address, which results in a Global Rearm. The handler then issues a
nonSpecific End of Interrupt (EOI) and finally issues a Return from
Interrupt (lRET). If its adapter did not cause the interrupt, the handler
passes control to the next interrupt handler in the chain.
Unlinking from the Chain: To unlink from the chain, a task must first
locate its handier'S position within the chain. By starting at the inter-
rupt vector in low memory and using the offset of each handler's
forward pointer to find the entry point of each handier, the chain can
be methodically searched until the task finds its own handler. The
forward pointer of the previous handler in the chain is replaced by the
task's pointer, removing the handler from the chain.
Note: If the handler cannot locate its position in the chain or, if the
signature of any prior handler is not hex 4248, it must not unlink.
Error Recovery: If the unlinking routine discovers that the interrupt

chain has been corrupted, an unlinking error recovery procedure
must be in place. Each application can incorporate its own unlinking
error procedure into the unlinking routine. One application may
choose to display an error message requiring the operator to either
correct the situation or reset the system. The application, however,
must not unlink.
1-16 System Board

Precautions
The following precautions must be taken when designing hardware or

programs that use shared interrupts.
• Hardware designers should ensure that the adapters:

Do not power up with an interrupt pending or enabled.
Do not generate interrupts that are not serviced by a handler.
Generating interrupts when a handler is not active to service
them causes that interrupt level to lock up. The design
concept relies on the handler to clear its adapter's interrupt
and issue the Global Rearm.
Can be disarmed so that they do not remain active after their
application has terminated.
• Programmers should:
Ensure that their programs contain a short routine that can be
executed with the AUTOEXEC.BAT to disable their adapter's
interrupts. This precaution ensures that the adapters are
deactivated for a system reboot that does not clear memory.
Treat words as words, not as bytes.
Note: Remember that data is stored in memory using the

Intel format (word hex 424B is stored as hex 4B42).
Interrupt Chaining Structure

ENTRY: JMP SHORT PAST ; Jump around structure
FPTR OD 0 ; Forward Pointer
SIGNATURE DW 424BH ; Used when unlinking to identify
; compatible interrupt handlers
FLAGS DB 0 ; Flags
FIRST EQU a0H ; Flags for being first in chain
JMP SHORT RESET
RES_BYTES DB DUP 7(0) ; Future Expansion
PAST: ; Actual start of code
The interrupt chaining structure is a 16-byte format containing FPTR,

SIGNATURE, RES_BYTES, and a'Jump instruction to a reset routine.
It begins at the third byte from the interrupt handler's entry point.
The first instruction of every handler is a short jump around the struc-
ture to the start of the routine.
System Board 1-17

Except for those residing in adapter ROM, handlers designed for
interrupt sharing must use hex 424B as the signature to avoid cor-
rupting the chain due to misidentification of an interrupt handler.
Because each handler's chaining structure is known, the forward
pointers can be updated when unlinking.
The flag indicates that the handler is first in the chain and is used
only with interrupt 7. The Reset routine disables the adapter's inter-
rupt and then does a Far Return to the operating system.
ROM Considerations
Adapters with interrupt handlers residing in ROM must store the

forward pointer in latches or ports on the adapter. If the adapter is
sharing interrupt 7, it must also store a First. Storing this flag is nec-
essary because its position in the chain may not always be first.
Because the forward pointer is not stored in the third byte, these han-
dlers must contain a signature of hex 00.
Examples
In the following examples, note that interrupts are disabled before

passing control to the next handler on the chain. The next handler
receives control as if a hardware interrupt had caused it to receive
control. Note also that the interrupts are disabled before the nonspe-
cific EOI is issued, and are not reenabled in the interrupt handler.
This ensures that the IRET is executed (at which point the flags are
restored and the interrupts reenabled) before another interrupt is ser-
viced. This protects the stack from excessive buildup.
1-18 System Board

Interrupt Handler Example
OUR_CARD EQU xxxx Location of our card's interrupt
ISB EQU xx Interrupt bit in our cards interrupt
control/status register
REARM EQU 2F7H Global Rearm location for interrupt 7
SPC_EOI EQU 67H Specific EOI for interrupt 7
EOI EQU 20H Nonspecific EOI
OCR EQU 20H ; Location of interrupt controller
operational control register
IMR EQU 21H ; Location of interrupt mask register
MYSEG SEGMENT PARA

ASSUME CS:MYSEG.DS:DSEG
ENTRY PROC FAR
JMP SHORT PAST Entry point of handler
FPTR DD 0 Forward Pointer
SIGNATURE DW 424BH Used when unlinking to identify
compatible interrupt handlers
FLAGS DB 0 Flags
FIRST EQU 80H
JMP SHORT RESET
RES_BYTES DB DUP 7(0) Expansion
PAST: STI Actual start of handler code
PUSH Save needed registers
MOV DX.OUR_CARD Select our status register
IN AL.DX Read the status register
TEST AL.ISB Our card caused the interrupt?
JNE SERVICE Yes. branch to service logic
TEST CS: FLAGS. FIRST Are we the first ones in?
JNZ EXIT If yes. branch for EOI and Rearm
POP Restore registers
CLI Disable interrupts
JMP DWORD PTR CS:FPTR Pass control to next handler on chain
SERVICE: Service the interrupt

EXIT:
CLI Disable the interrupts
MOV AL.EOI
OUT OCR.AL Issue nonspecific EOI
MOV DX.REARM Rearm our card
OUT DX.AL
POP Restore registers
IRET
RESET: Disable our card
RET Return Far to operating system
ENTRY: ENDP
MYCSEG ENDS
END ENTRY
System Board 1-19

Linking Code Example
PUSH ES
ClI ; Disable interrupts
Set forward pointer to the value of the interrupt .vector in low memory
ASSUME CS:COOESEG.OS:COOESEG
PUSH ES
MOV AX.3S0FH DOS get interrupt vector
INT 21H
MOV SI.OFFSET CS:FPTR Set offset of our forward pointer
in an indexable register
MOV CS:[SI].BX Store the old interrupt vector
MOV CS:[SI+2].ES in our forward pointer
CMP ES:BYTE PTR[BX].CFH Test for IRET
JNZ SERVECTR
MOV CS: FLAGS. FIRST ; Set up first in chain flag
SERVECTR: POP ES
PUSH OS
Make interrupt vector in low memory point to our handler
MOV OX.OFFSET ENTRY Make interrupt vector point to our
interrupt handler
MOV AX,SEG ENTRY If OS not = CS. get it and
MOV OS.AX put it in OS
MOV AX.2S0FH DOS set interrupt vector
INT 21H
POP OS
; Unmask (enable) interrupts for our level
SET7: IN AL.IMR Read interrupt mask register
AND Al.07FH Unmask interrupt level 7
OUT IMR.Al Write new interrupt mask
MOV Al.SPC_EOI Issue specific EOI for level 7
OUT OCR.Al to allow pending level 7 interrupts
(if any) to be serviced
STI Enable interrupts
POP ES
1-20 System Board

Unlinking Code Example
PUSH OS
PUSH ES
ClI Disable interrupts
MOV AX,350FH DOS get interrupt vector
INT 21H ES:BX points to the first in the chain
MOV CX,ES Pickup segment part of interrupt vector
Are we the first handler in the chain?
MOV AX,CS Get code seg into comparable register
CMP BX,OFFSET ENTRY Interrupt vector in low memory
pointing to our handlers offset?
JNE UNCHAIN_A No, branch
CMP AX,CX Vector pointing to our handler's segment?
JNE UNCHAIN_A No, branch
Set interrupt vector in low memory to point to the handler
pOinted to by our pOinter
PUSH OS
MOV AX,CS:FPTR
MOV DX,WORD PTR CS:FPTR ; Set offset of interrupt vector
MOV DS,WORD PTR CS:FPTR[2] ; Set segment of interrupt vector
MOV AX, 250FH ; DOS set interrupt vector
INT 21H
POP OS
JMP UNCHAIN_X
UNCHAIN_A: ; CX = FPTR segment, BX = FPTR offset
CMP ES:[BX+6],4B42H Is handler using the appropriate
conventions (is SIGNATURE = 424BH?)
JNE exception No, invoke error exception handler
lOS SI ,ES: [BX+2] Get FPTR's segment and offset
CMP SI,OFFSET ENTRY Is this forward pointer pointing to
our handler's offset?
JNE UNCHAIN_B No, branch
MOV CX,DS Is this forward pOinter pointing to
CMP AX,CX our handler's segment?
JNE UNCHAIN_B No, branch
located our handler in the chain
MOV AX,WORD PTR CS:FPTR ; Get our FPTR's offset
MOV ES: [BX+2] ,AX ; Replace FPTR offset pointing to us
MOV AX,WORD PTR CS:FPTR[2] ; Get our FPTR's segment
MOV ES:[BX+4],AX ; Replace FPTR segment pointing to us
MOV Al,CS:FlAGS
AND Al,FIRST
OR ES: [BX+6] ,AX Replace offset of FPTR of handler
JMP UNCHAINj
MOV BX,SI Move new offset to BX
PUSH OS
PUSH ES
JMP UNCHAIN_A Examine the next handler in the chain
UNCHAINj: STI Enable interrupts
POP ES
POP OS
System Board 1-21

Read/Write Memory
The system board supports 640K bytes of read/write memory. The
first 128K is optional and consists of four 64K by 4-bit and two 64K by
1-bit chips. Sockets are provided on the system board for this
optional memory.
The next 512K (from 128K to 640K) is standard and is arranged as two
banks of 256K by 9-bit single-inline packages (SIPs). All read/write
memory is parity-checked.
The System Board RAM Control/Status register, hex 6B, is part of the
system gate array and may be used to remap memory. Remapping
occurs when the power-on self-test (POST) senses memory on the I/O
channel that is in contention with system memory. Also, if the first
128K is not installed or a failure in the first 128K is sensed, POST
remaps the remainder of memory to allow the system to operate.
Bit Function
7 Parity Check Pointer

1 = Lower 128K failed
o = Upper 512K failed
6 -Enable RAM, 90000-9FFFF
3 -Enable RAM, SOOOQ-SFFFF
2 -Enable RAM, 500<rQ-5FFFF
1 -Enable RAM, 4000Q-4FFFF
o Remap Low Memory
Figure 1-11. System Board RAM Control/Status Register
ROM
The system board has 64K by 8-bits of ROM or erasable program-
mable read-only memory (EPROM). Two module sockets are pro-
vided; both sockets have 32K by 8-bits of ROM. This ROM contains
POST, BIOS, dot patterns for 128 characters in graphics mode, and a
diskette bootstrap loader. The ROM is. packaged in 28-pin modules.
1-22 System Board

1/0 Channel
The I/O channel is an extension of the 8086-2 microprocessor bus that
is demultiplexed, repowered, and enhanced by the addition of inter-
rupts and OMA functions.
The 1/0 channel contains:
• An 8-bit, bidirectional data bus

• Twenty address lines
• Six levels of interrupts
• Control lines for memory and 1/0 read and write
• Clock and timing lines
• Three channels of OMA control lines
• Memory-refresh control lines
• A channel check line
• Power and ground for the adapters.
Four voltage levels are provided for 1/0 cards. The maximum avail-
able values (for each slot) in the following chart are for systems with
two diskette drives.
• +5 V dc (+5%, -3%) at 1.9A maximum

• -5 V dc (+ 10%, -8%) at 0.055A maximum
• +12Vdc(+5%, -3%) atO.72A maximum
• -12Vdc(+10%, -8%)atO.117Amaximum
The maximum available values (for each slot) in the following chart
are for systems with a fixed disk and a diskette drive.
• +5 V dc (+5%, -3%) at 1.6A maximum

• -5 V dc (+ 10%, -8%) at 0.055A maximum
• + 12 V dc (+ 5%, -3%) at 0.33A maximum
• -12Vdc(+10%, -8%) atO.117A maximum
The 'I/O CH ROY' line is available on the 1/0 channel to allow opera-
tion with slow 110 or memory devices. 1/0 CH RDY is made inactive by
an addressed device to lengthen the operation. For each clock cycle
that the line is held low, one wait state is added to the 1/0 and OMA
operations.
System Board 1-23

liD devices are addressed using mapped liD address space. The
channel is designed so that over 64,000 device addresses are avail-
able to the adapters on the liD channel.
The following is the liD address map for the IBM Personal System/2
Model 25. Hex 0100 to FFFF are available for use by adapters on the
liD channel, except for those addresses noted.
Hex Range Device
0000-001F DMA Controller, 8237A-5

0020-003F Interrupt Controller
0040-005F Timer
0060-0062 1/0 Ports
0063-006F System BoardlControl and Status
0080-008F DMA Page Registers

OOAO-OOAF* Interrupt Controller Extension
0320-032F Fixed Disk

0378-037F Parallel Port
03CO-03DF Video Subsystem
03FO-03F7 Diskette
03F8-03FF Serial Port
Note: 1/0 Addresses, hex 000 to OFF, are reserved for the system board 1/0 .
• The NMI mask can be set and reset through system software as follows:
Write hex 80 to 1/0 address hex AO (enable NMI)

Write hex 00 to 1/0 address hex AO (disable NMI)
Figure 1-12. 110 Address Map
The '-liD channel check' signal (-110 CH CK) causes an NMI to the
microprocessor.
1-24 System Board

Connectors
The I/O channel is repowered to provide sufficient power for both

62-pin connectors, assuming two low-power Schottky (LS) loads per
slot. IBM adapters typically use only one load per adapter.
The following figure shows the pin numbering and signal assignments
for the I/O channel connectors.
Rear Panel
Ground 81 A1 -I/O CH CK
RESET ORV 07
+5 V 06
IRQ 2 05
-5 V 04
ORQ2 03
-12 V 02
Reserved 01
+12 V DO
Ground 810 A10 I/O CH ROY
-MEMW AEN
-MEMR A19
-lOW A18
-lOR A17
-OACK3 A16
ORQ3 A15
-OACK1 A14
DRQ1 A13
-MREF A12
ClK 820 A20 A11
IRQ7 A10
IRQ6 A9
IRQ5 A8
IRQ4 A7
IRQ3 A6
-OACK2 A5
TC A4
ALE A3
+5 V A2
OSC A1
Ground 831 A31 AO
Figure 1-13. 1/0 Channel
System Board 1-25

Signal Description
The following is a description of the 1/0 channel signal lines. All lines
are TTL-compatible. The (0), (I), or (1/0) notation refers to output,
input, or input and output.
AO-A19 (0): Address bits 0 to 19: These lines are used to address
memory and 1/0 devices within the system. The 20 address lines
allow access to 1M of address space. Only the lower 16 lines are
used in 1/0 addressing, and all 16 should be decoded by 1/0 devices.
AO is the least significant and A19 is the most significant. These lines
are generated by either the microprocessor or the DMA controller.
AEN (0): Address Enable: This line is used to de-gate the micro-
processor and other devices from the 1/0 channel to allow DMA trans-
fers to take place. When this line is active, the DMA controller has
control of the address bus, data bus, and Read and Write command
lines. When this line is inactive, the microprocessor has control.
This line should be part of the adapter-select decode to prevent incor-
rect adapter selects during DMA operations.
ALE (0): Address Latch Enable: This line is provided by the bus
controller and is used on the system board to latch valid addresses
from the microprocessor. Addresses are valid at the falling edge of
ALE and are latched onto the bus while ALE is inactive. This signal is
forced active during DMA cycles.
ClK (0): System clock: This is the system clock signal with a fre-
quency of 8 MHz and a 33% duty cycle.
DO - D7 (1/0): Data bits 0 to 7: These lines provide data bus bits 0

to 7 for the microprocessor, memory, and 110 devices.
-DACK1 - -DACK3 (0): -DMA Acknowledge 1 to 3: These lines are

used by the controller to acknowledge DMA requests. DACKO is not
available on the Type 8525's 1/0 channel.
DRQ1 - DRQ3 (I): DMA Request 1 to 3: These lines are asynchro-

nous channel requests used by peripheral devices to gain DMA ser-
vices. They are prioritized with DRQ1 being the highest and DRQ3
being the lowest. A request is generated by bringing a request line to
an active level. A request line is held active until the corresponding
acknowledge line goes active.
1-26 System Board

-110 CH CK (I): -I/O Channel Check: This line generates an NMI. It is
driven active to indicate an uncorrectable error and held active for at
least two clock cycles.
1/0 CH RDY (I): I/O Channel Ready: This line, normally active
(ready), is pulled inactive (not ready) by a memory or I/O device to
lengthen I/O or memory cycles. It allows slower devices to attach to
the I/O channel with a minimum of difficulty. Any slow device using
this line should drive it inactive immediately after detecting a valid
address and a Read or Write command. For every clock cycle this
line is inactive, one wait state is added. This line should not be held
inactive longer than 17 clock cycles.
-lOR (0): -I/O Read: This command line instructs an I/O device to
drive its data onto the data bus. This signal is driven by the micro-
processor or the DMA controller.
-lOW (0): -I/O Write: This command line instructs an I/O device to
read the data on the data bus. This signal is driven by the micro-
IRQ2 - IRQ7 (I): Interrupt requests 2 through 7: These lines are

used to Signal the microprocessor that an I/O device requires atten-
tion. They are prioritized with IRQ2 as the highest priority and IRQ7 as
the lowest. When an interrupt is generated, the request line is held
active until it is acknowledged by the microprocessor.
-MEMR (0): -Memory Read: This command line instructs memory to

drive its data onto the data bus. This signal is driven by the micro-
-MEMW (0): -Memory Write: This command line instructs memory

to store the data present on the data bus. This signal is driven by the
microprocessor or the DMA controller.
-MREF (1/0): -Memory Refresh: This line indicates a refresh cycle.
OSC (0): Oscillator: This is a high-speed clock with a 70-ns period

(14.31818 MHz). It has a 50% duty cycle.
RESET DRV (0): Reset Drive: This line is used to reset or initialize
system logic upon power-up or during a low line-voltage. This signal
is synchronized to the falling edge of elK.
System Board 1-27

TC (0): Terminal Count: This line provides a pulse when the ter-
minal count for any DMA channel is reached.
Signal Timings
The following diagrams show the 1/0 signal timings for 1/0 and
memory operations.
1·28 System Board

8-Blt 1/0 Bus Cycles
ALE
~~--------------------
AO-A18==><___________________________________~
1-1- - - - - t 4 -----1-1 t5-1

~~----~/
I-'OR
1-----t6 ------II f--- t7-l

GO-D7
----------------------c==>---
I t4
-lOW ~~------------_/
f-t8-1 h9-1
00-07
<~----------~>---
f----- t1 0 -----j I- t11-j ~
f--t12---,
110 CH ROY V~-
Symbol Description Min (ns) Max (ns)
t1 Address valid to ALE inactive 20

t2 ALE inactive to Command active 60
t3 Command active from AEN inactive 95
t4 Command pulse width 605
t5 Address hold from Command inactive 45
t6 Data valid from Read active 540
17 Data hold from Read inactive 0
t8 Data valid from Write active 120
t9 Data hold from Write inactive 25
t10 110 CH ROY inactive from Command active 325
t11 Read Data valid from 110 CH ROY active 0
t12 Command inactive from 110 CH ROY active 160
Figure 1-14. 8-Bit I/O Timing
System Board 1-29

8-Bit Memory Bus Cycles
ALE ~~___________________________________
H1+t2-j
AEN ~~
f-t3-----j
AO-A19~___________________________________~
~I----------t4--------~I~t5~
~EMR
~'---------'/
~-D7 ------------~<
t6 ----------11
f--------- 1-t7-j
r__
[
MEMW _ _ _ ""~'--~--------t4~~~:/
f---- t8 -l 1-t9 ~
00-07 <~ ______~r__

L f------ t10 ------j f- t11 ~
f--- t12 ----l
----~
1/0 CH ROY

t7 Data hold from Read inactive 0
t10 I/O CH ROY inactive from Command active 115
t11 Read Data valid from I/O CH ROY active 0
t12 Command inactive from I/O CH ROY active 160
Figure 1-15. 8-Bit Memory Timing
1-30 System Board

16-Bit 110 Bus Cycles
ALE ~
f-- t1 + ~-----------------------------------
t21
AEN ~
f-- t3-1
A1-A19 5S><_______________~
AO
_s----'------_ _ _~/ ~
f----t4----1 f---- t4 --t t51
POR
f---- t6 ---1 ~ t71 f-- t6 ---1 f-- t7-1
~o-D7 ----------<0>----0-
f------ ----j r--- t4 t4---j
pow
f- t8-i ~ t91 f- t8-i f-- t9-i
~0-D7 <1 > < >--
~t101 ~ t11
t12 -i
~t10j 1 ~
t12 -1
t11
I/O CH ROY
"'J "'J

t10 I/O CH ROY inactive from Command active 325
t11 Read Data valid from I/O CH ROY active 0
t12 Command inactive from I/O CH ROY active 160
Figure 1-16. 16-Bit 1/0 Timing
System Board 1-31

16-Bit Memory Bus Cycles
ALE
~------
f-t1-tt21
~
AEN
~t3~
A1-A19 §><_______________~
AO
-~--------"'-----~/ '\SS
~t4---i ~t4~t51
fEMR t--t6---j fl7j c-t6---j ~171

~0-D7 ------------(O>------~C>_
f--- t4 --1 f--- t4---i
fEMW
f-t8-j ~t9i f-ts-j f-t9-j
IL00-07 ----------~< >~----~< ~

-
r i
t10 1- J.--
t12-1
t11 r i
t10 1- j.- t11
t12~
I/O CH ROY
"'J

tS Data valid from Write active 120
110 I/O CH ROY inactive from Command active 115
t11 Read Data valid from 1/0 CH ROY active 0
t12 Command inactive from 1/0 CH ROY active 160
Figure 1-17. 16-Bit Memory Timing
1-32 System Board

Memory Refresh
-MREF ~~---------'~
f---t1--j
AO- A7 -~~-~-~~~~--------------------~
rt2 t3 t4 -j
-MEMR ""''-_ _ _ _ _ _ _ _ ~/
f-- t5 -+- t6 -t-- t7---1
I/OCHROY ~
t1 -MREF active to -MEMR active 155

t2 Address valid to -MEMR active 75
t3 -MEMR pulse width 230
t4 -MEMR inactive to -MREF inactive 10
t5 -MEMR active to 1/0 CH ROY inactive 60
t6 1/0 CH ROY pulse width 600
t7 -MEMR inactive from 1/0 CH ROY active 0
Figure 1-18. Memory Refresh Timing
System Board 1-33

DMA Read
~~---------------
DRO(n) /
_ _ _~lt11
-DACK(n) ~ /
~--------------~
r- t2 -i--t4~t31
-lOW --------.,~ /~---
f---t5---1
AEN
------'/
AO - A19 "">,"""""" X r t7-j
X""""""""
f-ts-1
~ t9 I--- t10----1
-MEMR -----'--,~ /~---
f-- t11 -I ~t12---j

1/0 CH RDY--------'---~"'Jr---------
...=;j
I----- t13 ~.~ ~ t14
TC
Symbol
----~/
Description
"''----- Min (ns) Max (ns)
t1 -DACK active to DRO inactive 0

t2 -DACK active to -lOW active 200
t3 -lOW inactive to -DACK inactive 0
t4 -lOW pulse width 250
t5 AEN active to -lOW active 500
t6 -lOW inactive to AEN inactive 25
t7 -lOW active from -MEMR active 360
t8 -lOW inactive to -MEMR inactive 0
t9 Address valid to -MEMR active 0
t10 -MEMR pulse width 470
t11 -MEMR active to 1/0 CH RDY inactive 200
t12 -MEMR inactive from 1/0 CH RDY active 200
t13 TC active setup to -lOW inactive 290
t14 TC inactive from -lOW inactive 0
Figure 1-19. DMA Read Timing
1-34 System Board

DMA Write
DRa(n)
/ ~
It1 I
'" /
-OACK (n)
I t2 I t4 It3 I
-lOR
/
AEN
~ '"
f--- t5 ----1 It61
~
t1 -DACK active to ORa inactive 0

t2 -DACK active to -lOR active 0
t3 -lOR inactive to -OACK inactive 0
t4 -lOR pulse width 470
t5 AEN active to -lOR active 300
t6 -lOR inactive to AEN inactive 0
t7 -MEMW active from -lOR active 55
t8 -MEMW inactive to -lOR inactive 0
t9 Address valid to -MEMW active 140
t10 -MEMW pulse width 250
t11 -MEMW active to I/O CH ROY inactive 30
t12 -MEMW inactive from I/O CH ROY active 200
t13 TC active setup to -lOR inactive 290
t14 TC inactive from -lOR inactive 0
Figure 1-20. DMA Write Timing
System Board 1-35

Video Subsystem
The video subsystem is resident on the system board and consists of:
• Video memory controller gate array

• Video formatter gate array
• 64K bytes of multi port dynamic memory
• 8K bytes static RAM character generator
• 256-by-18-bit color palette with three 6-bit digital-to-analog con-
verters (OAC).
At the BIOS level (interrupt hex 10), the Type 8525 maintains compat-
ibility with the IBM Color Graphics Adapter (CGA).
The video modes are compatible with those modes supported by the
color graphics adapter with two modes added. The additional modes
are the 320-by-200 graphics with 256 colors available and the
640-by-480 graphics with two colors available.
1-36 Video Subsystem

Block Diagram
Video 8KRAM
Loadable
~
Memory
Control Character
Gate Generator
125MHZ~
Oscillator
Array MA 0-7
r---
Video
Buffer
(64K) -
I-- I-
DO-D7
1/0 R/W L
3DX Decod e
AO-A15
~
Video
Formatter
Gate r--
Address r- Array
- MUX 256x18
Color
Palette
with DACs
RGB
Syncs Analog
Monitor Sense 0 and 1 Monitor
Figure 1-21. Video Subsystem Block Diagram
Video Subsystem 1-37

Display Support
The video subsystem supports a 31.5 kHz analog color display or 31.5
kHz analog monochrome display. The system senses the type of
display and matches the initialization to it. The polarity of the vertical
synchronization signal to the display determines the number of hori-
zontal scans, either 400 or 480. The number of scan lines in relation
to the polarity is:
Scan Lines Vertical Sync Horizontal Sync
480 Negative Negative

400 Positive Negative
If the system senses the presence of a monochrome display, it sums

the colors and outputs the video signal to pin 4 (green) of the video
connector on the system board.
Text Modes
In the text modes, the character box size is 8-by-16. The character
font table is loaded into the character generator. All 16 scan lines are
programmed into the character generator.
Graphics Modes
In the graphics modes, the character font table is used to create the
character PELs. For most graphics modes, the character box is an
8-by-8 character box that is double-scanned to create an 8-by-16 char-
acter; however, all 16 scan lines of the 8-by-16 box are not program-
mable.
The 640-by-480 graphics mode is the exception. It uses an 8-by-16

character box and a separate font table. In this mode, 30 character
rows are displayed.

Video Modes Analog Display
Mode 0,1 40 column by 25 rows

40 Column 8-by-16 character box
Alphanumeric 320 by 400
16 of 256K colors or 16 of 64 shades of gray
(monochrome)
Display buffer B8000
2000 byte video buffer
Mode 2,3 80 column by 25 rows

80 Column 8-by-16 character box
Alphanumeric 640 by 400
(monochrome)
Mode 4,5 8-by-8 character box

320 by 200 Double-scanned
Graphics 320 by 200
(monochrome)
Alternate palette select
Two row scan address partitions
Mode 6 8-by-8 character box

Graphics 640 by 200
2 of 256K colors
Two row scan address partitions

640 by 480 640 by 480
Graphics 2 of 256K colors
Display buffer AOOOO
Linear addressing

Graphics 320 by 200
256 of 256K colors
Display buffer AOOOO
Linear addressing
Figure 1-22. Video Mode Summary

Display Formats
In alphanumeric (text) modes 0 through 3, two bytes define each char-

acter on the display screen. The even byte accesses the character
generator to create the PEL data. The odd byte defines the color of
the PELs. Sixteen colors are available for foreground, and eight
colors are available for background when blink is enabled (default).
Blink is contro!'ed in the eGA Mode ContrQI register, hex 308.
The format of the two bytes is shown in the following:
Odd Byte Even Byte
7 6 543 2 o 7 6 543 2 1 0
Attribute Character
Figure 1-23. Alphanumeric Format
The following are the bit definitions of the attribute byte. Bit 7 selects
a blinking character, or if blinking is disabled, selects palette
addresses above hex 07 for the background color.
JIlts Function
7 to 4 ElackgrQund Color Palette Address

3 to 0 Foreground Color Palette Address
Figure 1-24. Attribute Byte

In modes 4 and 5, the bit pair C1 and CO selects one of four colors for
each PEL.
Bil PEL Definition
7,6 C1,CO First PEL

5,4 C1,CO
3,2 C1,CO
1,0 C1,CO Last PEL
Figure 1-25. Modes 4 and 5
There are two color sets: color set 0 and color set 1. For information
about the colors selected, see "CGA Border Control Register, 309,"
later in this section under "Video Formatter Registers."
In modes 6 and 11, one bit defines each PEL, with the most significant
bit defining the first PEL. The foreground color maps to the color in
the CGA Border Control register if the B&W bit in the CGA Mode
Control Register is O. If the B&W bit is 1, the foreground color maps
to palette address hex 07. The background color always maps to
address hex 00.
Bil PEL Definilion
7 CO First PEL
6 CO
5 CO
4 CO
3 CO
2 CO
1 CO
0 CO Last PEL
Figure 1-26. Modes 6 and 11
In mode 13, a byte defines each PEL. This allows a choice of 256
colors for each PEL.

Video Storage Organization
The following is the memory mapping for text modes 0 through 3.
AOOOO
Character
I
Generator
Self-load
Storage
A7FFF
Not Used
88000 Character Code
88001 Attribute Code
Character Code
Attribute Code
0
I n
BFFFE
8FFFF
Figure 1-27. Text Modes 0 through 3
1·42 Video Subsystem

The following is the memory mapping for graphics modes 4 through
6. In modes 4 and 5, each byte defines four PELs. In mode 6, each
byte defines eight PELs.
BOOOO
Not Used
B8000 PEL Byte

Even Scan Lines
B8001 PEL Byte
0
0
BAOOO PEL Byte

Odd Scan Lines
BA001 PEL Byte
0
BFFFE
BFFFF
Figure 1-28. Graphics Modes 4 through 6
The following is the memory mapping for graphics modes 11 and 13.
In mode 11, each byte defines eight PELs; in mode 13, each byte
defines one PEL.
AOOOO PEL Byte
AOOOl PEL Byte
o
o
AFFFE
AFFFF
Figure 1-29. Graphics Modes 11 and 13

Video Registers
The video memory controller gate array responds to I/O addresses

304 and 305. The video formatter gate array responds to I/O
addresses 308 through 30F.
The color palette is programmed through the video formatter at

addresses 3C6 through 3C9. All registers are readable.
The following pages describe the memory controller registers, the

video formatter registers, the color palette registers, and the char-
acter generator. Sample programs of a font load and palette load are
also included.
Video Memory Controller Registers
The video memory controller contains an index register and 22 data

registers. Two I/O commands are required to write to one data reg-
ister: writing the desired index value to address hex 304, and then
writing the data to address hex 305.
Memory Controller Index Register, Hex 304: This register is

read/write, and pOints to the specific data register addressed through
hex 305.
Bit Function
7 Reserved
6 Reserved
5 Index5
4 Index4
3 Index3
2 Index2
1 Index1
0 IndexO
Figure 1-30. Video Memory Controller Index Register

The following is a list of the 22 data registers and their functions.
Index
(Hex) Register Description
00 Horizontal Total
01 Horizontal Characters Displayed
02 Start Horizontal Sync
03 Sync Pulse Width
04 Vertical Total
05 Vertical Total Adjust
06 Vertical Characters Displayed
07 Start Vertical Sync
08 Reserved
09 Scan Lines per Character
OA Cursor Start
OB Cursor End
OC Start of Screen High
OD Start of Screen Low
OE Cursor Position High
OF Cursor Position Low
10 Mode Control
11 Interrupt Control
12 Character Generator Interface and Sync Polarity, or
Display Sense
13 Character Font Pointer
14 Number of Characters to Load
20 Reserved

Horizontal Total Register, Index 00: This register contains the total
number of characters in the horizontal scan interval. The number
consists of both displayed and nondisplayed characters. This register
determines the frequency of the 'horizontal sync' signal.
Horizontal Characters Displayed Register, Index 01: This register

determines the total number of characters to be displayed during the
horizontal video scan interval. This register is loaded with a value of
hex 27. The hardware calculates the correct value based on the
mode selected.
Start Horizontal Sync Register, Index 02: This register specifies the
character position count at which the 'horizontal sync' signal
becomes active.
Sync Pulse Width Register, Index 03: This register specifies the
pulse widths of the horizontal and vertical synchronization signals.
The horizontal pulse width is programmed in units of character
clocks. The vertical pulse width is programmed in units of the hori-
zontal synchronization period. This register is programmed to match
the display specifications.
Bit Function
7 Width VSync3
6 VSync2
5 VSync1
4 VSyncO
3 Width HSync3
2 HSync2
1 HSync1
0 HSyncO
Figure 1-31. Sync Pulse Width Register
Vertical Total Register, Index 04: This register contains the 8 least
significant bits for the total number of scan lines in the vertical scan
interval. The most significant bit is the inversion of bit 6 of the Mode
Control register. The total number consists of both the displayed and
nondisplayed scan lines. This register and the Vertical Total Adjust
register determine the frequency of the 'vertical sync' signal.

Vertical Total Adjust Register, Index 05: This register is used to
adjust the total number of horizontal scan lines in the vertical scan-
ning interval. It allows for an odd number of horizontal lines (525 for
60 Hz). The minimum value for this register is hex 02.
Bit Function
7 Reserved
6 Reserved
5 VAdjust5
4 VAdjust4
3 VAdjust3
2 VAdjust2
1 VAdjust1
0 VAdjustO
Figure 1-32. Vertical Total Adjust Register
Vertical Characters Displayed Register, Index 06: This register con-

tains the 8 least significant bits for the number of scan lines displayed
in the vertical scan interval. The most significant bit is the inversion
of bit 6 of the Mode Control register.
Start Vertical Sync Register, Index 07: This register contains the 8
least significant bits for the vertical scan line count. It determines
when the 'vertical sync' signal becomes active. The most significant
bit is the inversion of bit 6 of the Mode Control register.
Scan Lines per Character Register, Index 09: This register deter-
mines the number of horizontal scan lines in a character row. In text
modes, the value is hex 07. In graphics modes 4 through 6, the value
is hex 01, and in modes 11 and 13, the value is hex 00. The hardware
calculates the proper value based on the mode selected.
Bit Function
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 RowSize3
2 RowSize2
1 Row Size1
0 RowSizeO
Figure 1-33. Scan Lines per Character Register

Cursor Start Register, Index OA: Bits 3 through 0 in this register
determine the horizontal scan line count at which the cursor output
becomes active. The value in this register should be lower than the
value in the Cursor End register. The minimum is O. The hardware
will double-scan the cursor to produce the proper cursor display for a
16-scan-line character box.
When bit 5 is 1, the cursor is not displayed.
Bit Function
7 Reserved
6 Reserved
5 Blank Cursor
4 Reserved
3 Cursor Start3
2 Cursor Start2
1 Cursor Start1
0 Cursor StartO
Figure 1-34. Cursor Start Register
Cursor End Register, Index 08: This register determines the hori-
zontal scan line count when the cursor output becomes inactive. The
value should be greater than the value in the Cursor Start register.
The maximum is 7.
Bit Function
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Cursor End3
2 Cursor End2
1 Cursor End1
o Cursor EndO
Figure 1-35. Cursor End Register
Start of Screen HI~h Register, Index OC: This register contains the 8
most significant bits for the starting memory address of the video
display buffer. Sixteen address bits determine the starting address.
lhis register is initialized to a value of hex 00.

Start of Screen Low Register, Index OD: This register, together with
the Start of Screen High register, gives the starting address of the
display buffer. For all modes, this register is initialized to a value of
hex 00.
Cursor Position High Register, Index OE: This register contains the
four most significant bits for the cursor location.
Bit Function
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Cursor PositionB
2 Cursor PositionA
1 Cursor Position9
o Cursor PositionS
Figure 1-36. Cursor Position High Register
Cursor Position Low Register, Index OF: This register contains the
eight least significant bits for the location of the cursor. A value of
hex 00 in both of these registers will locate the cursor in the upper
left corner. The cursor is not supported in any graphics mode.
Mode Control Register, Index 10: Writing to this register selects the
type of display and clock times, and selects some of the graphics
modes.
Bit Function
7 Inhibit Write
6 Reserved = 0
5 Reserved
4 Clock = 1
3 Compatibility
2 Reserved
1 Mode 11
o 256 Color
Figure 1-37. Mode Control, Write
Write
Bit 7 When set to 1, the Inhibit Write bit prevents any writes to the
horizontal and vertical registers. After a mode set, BIOS
sets this bit to 1 to prevent applications designed for other
color graphics adapters from altering those registers.

Bit 6 The inverse of this bit is used as the ninth bit of the vertical
compare circuits and must be set to O.
Bit 5 Reserved.
Bit 4 This bit selects the dot clock and must be set to 1.
Bit 3 When set to 1, this bit allows the circuitry to calculate the
correct horizontal register values for the 80-by-25 text
modes. This bit should be set to 1 for all modes.
Bit 2 Reserved.
Bit 1 When set to 1, this bit selects mode 11.
Bit 0 When set to 1, this bit selects mode 13. Bit 2 in the Extended
Mode Control register must also be set.
During certain operations, the circuitry calculates some of the

internal signals and returns the values to the Mode Control register.
Bit Function
7 80x25
6 Reserved
5 Clock Select
4 Clock
3 Alpha Mode
2 Double-Scan
1 Mode 11
0 Mode 13
Figure 1-38. Mode Control, Read
Read
Bit 7 This bit indicates the state of bit 0 in the CGA Mode Control
register. When set to 1, this bit indicates that 80-by-25 mode
is selected.
Bit 6 Reserved.
Bit 5 When this bit is 1, it indicates that the clock is not divided by
2, and the resolution is 640 PELs wide. When it is 0, the
resolution is 320.
Bit 4 When this bit is 1, it indicates that the dot clock is
25.175 MHz.
Bit 3 When set to 1, this bit indicates that the mode is a text mode.
Bit 2 When set to 1, this bit indicates that the scan lines are
double-scanned.
Bit 1 When set to 1, this bit indicates that mode 11 is selected.
Bit 0 When set to 1, this bit indicates that mode 13 is selected.

Interrupt Control Register, Index 11: This register controls IRQ2
output to the interrupt controller. It also shows the status of the inter-
rupt. The output drivers are tri-stated (bit 7) to allow a Read of the
Display Sense register.
Bit Function
7 Tri-State Output
6 IRQ2 Status
5 -Enable IRQ2
4 -Clear IRQ2 Latch
3 Reserved
2 Reserved
1 Reserved
o Reserved
Figure 1-39. Interrupt Control Register
Bit 7 When set to 1, this bit disables (tri-states) the output drivers
and selects the Display Sense register to be read at index 12
instead of the Character Generator Interface and Sync
Polarity register.
Bit 6 When set to 1, this bit indicates that the memory controller is
causing an interrupt. This bit is read-only.
Bit 5 When cleared to 0, this bit enables the interrupt.
Bit 4 When cleared to 0, this bit holds the interrupt latch clear.
Bits 3-0 These bits are reserved and should be 0.
Character Generator Interlace and Sync Polarity Register, Index 12:

This register controls the character font tables and the horizontal and
vertical synchronization signals, HSYNC and VSYNC. To read this reg-
ister, bit 7 of the Interrupt Control register must be 0.
Bit Function
7 Load Character Generator

6 Load Full Character Set
5 Swap Active Font
4 Enable 512 Characters
3 Reserved = 0
2 Enable Sync Outputs
1 VSYNC Polarity
o HSYNC Polarity
Figure 1-40. Character Generator Interface and Sync Polarity Register
Bit 7 When written as a 1, this bit loads the character generator.

When read as a 0, the bit indicates that the load has finished.
To start the load, this bit is first cleared and then set to 1.

Bit 6 When set to 1, this bit causes the character generator to load
the display memory during normal display time. When
clear, the display memory is loaded only during the vertical
blanking interval.
Bit 5 This bit selects the font page that is used as font table or that
the character generat9r loads. When set to 1, font page 1 is
selected; when cleared to 0, font page 0 is selected.
Bit 4 When this bit is set to 1, 512 character codes are displayable
in the text modes. Bit 3 of the attribute byte then determines
the font page when displaying the character. When this bit
is set to 1, only eight foreground colors are supported.
When this bit is cleared to 0, only 256 character codes are
displayed, and bit 5 of this register determines the active
font.
Bit 3 Reserved = O.
Bit 2 When set to 1, this bit enables HSYNC and VSYNC outputs to
the display.
Bit 1 When set to 1, this bit causes VSYNC to be positive polarity.
Bit 0 When set to 1, this bit causes HSYNC to be positive polarity.
Display Sense Register, Index 12: This register contains the sensed
levels of the monitor sense 1 and 0 signals at pins 13 and 14 of the
display connector. This information is used by BIOS to properly ini-
tialize all video registers to match the display. To read this register,
bit 7 of the Interrupt Control register is set to 1.
These levels are used to determine the type of display attached as

shown in the following. The bit is set when the polarity is positive.
Sense 1 Sense 0
Bit 1 Bit 0 Type of Display Attached
o 0 Reserved
o 1 Analog Monochrome Display
1 0 Analog Color Display
1 1 No Display Attached
Figure 1-41. Monitor Sense Bits

Character Font Pointer Register, Index 13: This register contains a
pOinter to the character font table. The only valid pointer values are
hex 00, 10, 20, or 30. The pointer value doubled and the hex value
AOOOO make up the segment for the font table. The character value
doubled is the offset into the table. See "RAM-Loadable Fonts," later
in this section.
Number of Characters to Load Register, Index 14: This register

determines the number of characters to load into the RAM-Ioadable
character generator during one vertical retrace interval. This register
is used only in the text modes.
Video FormaHer Registers
The video formatter registers at I/O addresses hex 308 and 309 dupli-
cate the functions of the 6845 registers in the color graphics adapter.
Registers are added at addresses hex 300 through 30F for Type 8525
initialization requirements. The video formatter registers at
addresses hex 3C6 through 3C9 control the color palette.
Register Description
308 CGA Mode Control

309 CGA Border Control
30A CGA Status
30B Reserved
30C Reserved
300 Extended Mode Control
30E Reserved
30F Reserved
3C6 PEL Mask
3C7 Palette Read Address
3C8 Color Palette Address
3C9 Color Palette Data

CGA Mode Control Register, 308: This register contains the mode
control information for color/graphics compatible functions.
Bit Function
7 Reserved
6 Reserved
5 Enable Blink
4 640-by-200 Mono
3 Enable Video
2 B&W
1 Graphics
o 80-by-25 Alpha
Figure 1-42. eGA Mode Register
Bits 7,6 Reserved.

Bit 5 When set to 1, this bit selects the blink option for text modes.
When cleared to 0, 16 background colors are available in the
text modes.
Bit 4 When set to 1, this bit selects mode 6, 640-by-200 double-
scanned graphics.
Bit 3 When set to 1, this bit enables display image.
Bit 2 When this bit is 1, palette addresses hex 00 and 07 are the
two colors used in modes 6 and 11. When the bit is 0,
address hex 00 and the address specified in the CGA Border
Control register are the two colors used.
Bit 1 When set to 1, this bit selects modes 4 and 5, 320-by-200
double-scanned graphics.
Bit 0 When set to 1, this bit selects the 80-by-25 text mode.

CGA Border Control Register, 309: This register contains the border
color information and selects the alternate color palette for modes 4
and 5. Although analog displays do not have borders, the border
color information selects the alternate foreground color for modes 6
and 11, and the background color for modes 4 and 5.
Bit Function
7 Reserved
6 Reserved
5 320-by-200 Palette Select
4 Alternate Intensity
3 to 0 Border Color
Figure 1-43. CGA Border Control Register
Bits 7,6 Reserved

Bit 5 When set to 1, this bit selects color set 1 for modes 4 and 5.
Bit 4 When set to 1 (default), this bit selects an intensified color
set for modes 4 and 5.
Bits 3-0 These bits select the palette address for the border color
information used by modes 4, 5, 6, and 11.
The following figure shows the effects of this register and the bit pair
C1,CO and how the two color sets map into the color palette.
BCR BCR
Bit 4 C1 CO Bit 5 Palette Address
X 0 0 X Background Color
0 0 1 0 02 Color Set 0
0 1 0 0 04 Color Set 0
0 1 1 0 06 Color Set 0
0 0 1 03 Color Set 1
Intensified Colors
0 1 0 OA Color Set 0
1 0 0 OC Color Set 0
1 1 0 OE Color Set 0
0 1 OB Color Set 1
1 0 OD Color Set 1
1 1 OF Color Set 1
Figure 1-44. Modes 4 and 5 Color Selection

CGA Status Register, 3DA: This register is read-only and contains
the status information for the color graphics adapter.
Bit Function
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Vertical Sync
2 Reserved
1 Reserved
o -Display Enable
Figure 1-45. Status Register
Extended Mode Control Register, 300: This register controls the

selection of the type of display and the advanced color support.
When cleared to 0, bit 7 indicates that a readable DAC is installed;
when set, it indicates that the DAC is not a readable type. Bit 2 must
be set to 1 to select mode 13.
Bit Function
7 -Readable DAC Installed

6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 256 Colors
1 Reserved
o Reserved = 0
Figure 1-46. Extended Mode Control Register

Color Palette Registers
Three registers are used to access the color palette: a mask register,
a read address register, and a write address register.
The color palette has 256 18-bit data registers and an 8-bit address
register. Each data register is divided into three 6-bit data areas, one
for each color. To load each data register takes three outputs in the
sequence of red, green, blue.
When accessing the palette, the interrupts should be disabled to

prevent the sequence from being interrupted. The palette supports
both a single-register write operation and a burst load operation.
To maintain software compatibility, programmers should use the

BIOS interface when loading the color palette. BIOS supports two
calls for setting and two calls for reading the color registers. The
calls are through interrupt 10H with (AH) = hex 10. The value in the
AL register determines the specific operation:
10 - Set individual color register

12 - Set block of color registers
15 - Read individual color register
17 - Read block of color registers

Single Register Load: The address for the specific color register (0 -
255) is loaded into the BX register. The DH, CH, and CL registers
contain the red, green, and blue values, respectively. In the following
example using the BIOS interface, the yellow color value is loaded
into the palette address normally assigned to white. If the Set Mode
call has been initialized to restore the color palette to its default
state, the mode must be set before changing the color palette.
;-----Set up the video mode
MOV AX,0004H ; Set mode to mode 4

INT 10H ; Video BIOS interrupt
;-----Read color 14 to get the red, green, and blue values for yellow
MOV AX,1015H Read individual color register

MOV BX,0EH Read color register 0EH
INT 10H Video BIOS interrupt
; Return with DH = red value
CH = green value
CL = blue value
;-----Set color 15 to the red, green, and blue values of yellow
MOV AX,1010H Set individual color register

MOV BX,0FH Set color register 0FH
INT 10H Video BIOS interrupt
Burst Load: This second call supports setting a block of color regis-
ters. Using this call, 1 to 256 color values can be set or read with a
single BIOS call. The BX register contains the address for the first
register to be set, and CX contains the number of registers. ES:DX
point to a table of color values, where each table entry contains the
red, green, and blue values for a color. The following example sets
the first 16 colors in the color palette.

;-----Set colors 0 thru 15 with a set block of color registers call
CODE SEGMENT 'CODE'

ASSUME CS:CODE. ES:NOTHING. OS:NOTHING
PROC FAR
PUSH OS
XOR AX.AX
PUSH AX Return address for ODS
PUSH CS
POP ES Establish ES addressing for table
MOV AX. 1012H Set block of color register call
MOV BX.0 Start with color 0
MOV CX,16 Set 16 color registers
MOV DX.OFFSET CLR_TABLE ES:DX point to color table
INT 10H Make the video BIOS interrupt
RET
LABEL BYTE
DB 00H.00H.00H Black 00
DB 00H,00H,2AH Blue 01
DB 00H.2AH.00H Green 02
DB 00H.2AH.2AH Cyan 03
DB 2AH.00H.00H Red 04
DB 2AH.00H.2AH Magenta 05
DB 2AH.15H.00H Brown 06
DB 2AH.2AH.2AH ; White 07
DB 15H.15H.15H Gray 08
DB 15H.15H.3FH Lt bl ue 09
DB 15H.3FH.15H Lt green 0A
DB 15H.3FH.3FH Lt cyan 08
DB 3FH.15H.15H Lt red 0C
DB 3FH.15H,3FH Lt magenta 0D
DB 3FH.3FH.15H Lt yellow 0E
DB 3FH.3FH,3FH Bright White 0F
CODE ENDS
END

PEL Mask Register, 3C6: This register is initialized to a value that
does not affect the color selection, hex FF. This value should not be
changed because mask operations are not supported on the Type
8525.
Palette Read Address Register, 3C7: This register contains the

pointer to one of 256 palette data registers and is used when reading
the color palette.
Reading this port returns the last command cycle to the palette. The
description of bits 1 and 0 is in the following table. All other bits
during a read of this port are reserved.
Bit 1 Bit 0 Last Palette Command
0 0 Write Palette Cycle

0 1 Reserved
1 0 Reserved
1 1 Read Palette Cycle
Figure 1-47. Last Palette Command
Color Palette Address Register, 3C8: This register contains the

pointer to one of 256 palette data registers and is used during a
palette load.

Color Palette Data Register, 3C9: This register contains a 6-bit value
that yields one of 64 color levels. To write a color, the address is
loaded into the Color Palette Address register. Three writes to this
register are needed for each palette address: the first is the red color
information, the second is the green, and the third is the blue.
To read a color, the address value is written to the Palette Read

Address register, followed by three reads of this register. The first
returns the red color information, the second returns the green, and
the third returns the blue.
Bit Function
7 Not Used
6 Not Used
5 PO 5
4 PO 4
3 P03
2 PO 2
1 PO 1
o PO 0
Figure 1-48. Color Palette Data Register

Video Initialization Tables
The following figures show the video register values used by BIOS for
the various display modes.
Index Data Register Modes

Pointer Description 0,1 2,3 4,5 6 11 13
00 Horz. Total 30 30 30 30 30 30
01 Horz. Displayed 27 27 27 27 27 27
02 Start Horz. Sync 2A 2A 2A 2A 2A 2A
03 Sync Pulse Width 26 26 26 26 26 26
04 Vert. Total 80 80 80 80 FF 80
05 Vert. Adjust 00 00 00 00 OA 00
06 Vert. Displayed 8F 8F 8F 8F OF 8F
07 Start Vert. Sync 98 98 98 98 E9 9B
08 Reserved XX XX XX XX XX XX
09 Char. Scan Lines 07 07 01 01 00 00
OA Cursor Scan Start 06 06 XX XX XX XX
OB Cursor Scan End 07 07 XX XX XX XX
OC Start of Screen (High) 00 00 00 00 00 00
00 Start of Screen (Low) 00 00 00 00 00 00
OE Cursor Position (High) 00 00 XX XX XX XX
OF Cursor Position (Low) 00 00 XX XX XX XX
."
IV
............... r' ................... 1
IVIVU'C'VVlll'VI 18 18 H,
IV 18 1A 19
11 Interrupt Control 30 30 30 30 30 30
12 Char. Gen/Sync Pol. 46 46 46 46 04 46
13 Char. Font Pointer 00 00 XX XX XX XX
14 Char. to Load FF FF XX XX XX XX
Figure 1-49. Memory Controller Initialization

Data Register Modes
Address Description 0,1 2,3 4,5 6 11 13
3C6 PEL Mask FF FF FF FF FF FF

308 CGA Mode Control 28 29 OA 18 18 08
309 CGA Border Control 30 30 30 3F 3F 30
3DA Status XX XX XX XX XX XX
3DB Reserved XX XX XX XX XX XX
3DC Reserved XX XX XX XX XX XX
3DD Extended Mode Control 00 00 00 00 00 04
3DE Reserved
3DF Reserved
Figure 1-50. Video Formatter Initialization Table
3C8 3C9
Index R G B Display Color
00 00 00 00 Black
01 00 00 2A Blue
02 00 2A 00 Green
03 00 2A 2A Cyan
04 2A 00 00 Red
05 2A 00 2A Magenta
06 2A 15 00 Brown
07 2A 2A 2A White
08 15 15 15 Gray
09 15 15 3F Light Blue
OA 15 3F 15 Light Green
OB 15 3F 3F Light Cyan
OC 3F 15 15 Light Red
00 3F 15 3F Light Magenta
OE 3F 3F 15 Yellow
OF 3F 3F 3F Bright White
Figure 1-51. 16-Color Compatibility Initialization

RAM-Loadable Fonts
In the text modes, the video buffer is divided into two data areas: the
text area at address B8000 and the character font tables at address
AOOOO. The text area consists of the character and attribute code for
each position on the display. The font table consists of the character
code and PEL data for each character in the set.
Restrictions are placed on where the character font can be loaded

into the video buffer. Four fonts are supported in text modes. The
memory map below shows the areas (blocks) in the video buffer
where the fonts are loaded. The font tables can be swapped in syn-
chronization with the 'vertical retrace' signal with several output com-
mands. A maximum of four fonts can be loaded into the font area, but
only two can be loaded into and displayed from the character gener-
ator at anyone time. Two fonts are provided in ROM, an 8-by-8 font
and an 8-by-16 font. The font loaded depends on the mode that is
active at the time.
AOOOO
Font a
A2000
Font 1
A4000
Font 2
A6000
Font 3
ABOOO
Reserved
BOOOO
Reserved
B8000
Char/Attribute
Video
Buffer
BFFFF
Figure 1-52. Font Memory Map

The following is an example of how the character "E" is defined in an
8-by-16 character box.
Scan Line. Data in Hex Data in Binary
o 00 00000000
1 00 00000000
2 7E 01111110
3 7E 01111110
4 60 01100000
5 60 01100000
6 7E 01111110
7 7E 01111110
8 60 01100000
9 60 01100000
10 7E 01111110
11 7E 01111110
12 00 00000000
13 00 0000000'0
14 00 00000000
15 00 00000000
Figure 1-53. Sample Character
The following programming example uses the BIOS routine to load a

font table into block O. Because of differences in the hardware, the
character generator is not loaded the same for all display adapters;
however, the BIOS routines are the same for all video subsystems
with RAM-Ioadable fonts. The Type 8525, for instance, supports only
8-by-8 and 8-by-16 character fonts, depending on the mode selected.

TITLE Load block e with character definitions from "SET_A"
CODE SEGMENT PARA 'CODE'

ASSUME CS:CODE.ES:CODE
EXl PROC NEAR

MOV AX.eeelH Mode set BIOS call for mode 1
INT leH
MOV CX.leeH Load 256 characters into the block
MOV DX.eeeeH Begin loading at offset zero
MOV BL.eeH Load the characters into block zero
MOV BH.leH 16 bytes per character definition
MOV AX.SEG SET_A Get the segment of the characters
MOV ES.AX ES = segment of character definitions
MOV AH.llH Character generator routines
MOV AL.eeH User alpha load BIOS call
MOV BP.OFFSET SET_A BP = offset of character definitions
INT leH
RET
EXl ENDP
;----8-by-16 definitions for "SET_A"
SET_A LABEL BYTE

INCLUDE SET_A_CHARS
SET_~END EQU $
CODE ENDS
END

Block 0 now contains the 256 character definitions from file SET_A.
To load block 1, change the block number, the character file pointer,
and the pointer for the block to be loaded, as indicated below.
EX2 PROC NEAR

MOV CX, Hl6H ; Load 256 characters into the block
MOV DX,6666H ; Begin loading at offset zero
MaV BL,61H ; Load the characters into block one
MaV BH,16H ; 16 bytes per character definition
MaV AX,SEG SET_B : Get the segment of the characters
MOV ES,AX ; ES = segment of character definitions
MOV AH,l1H ; Character generator routines
MaV AL,66H ; User alpha load BIOS call
MOV BP,OFFSET SET_B : BP = offset of character definitions
INT 16H
RET
EX2 ENDP
;----8-by-16 definitions for "SET_B"
SET_B LABEL BYTE

INCLUDE SET_B_CHARS
Blocks 2 and 3 can be loaded in the same manner, until all four
blocks contain character font information. The characters that were
loaded into the blocks are not available for display until they are
transferred to the character generator.
The character generator is broken into two parts, or font pages. Each
font page contains 256 character definitions. The character generator
is loaded from the four blocks of 256 character definitions.
A character set of 256 characters is loaded into the character gener-

ator by selecting one of the four blocks to be transferred. Two of the
four blocks are selected for a character set of 512 characters. The
Set Block Specifier call is used to transfer the blocks of character
definitions to the character generator.
The Set Block Specifier call uses the input parameter in BL to specify
which blocks are loaded into the character generator. Only the low
nibble (4 bits) of BL is used. Bits t and 0 specify which block to load
into the first 256 positions of the character generator, or font page o.
The first 256 positions are the character definitions for characters
o - 255. Bits 3 and 2 indicate which block to load into the second 256
positions of the character generator, or font page 1. The second 256
positions of the character generator define characters 256 - 511. If
the two bit pairs are equal (bit 0 is the same as bit 2 and bit 1 is the
same as bit 3), only font page 0 is loaded, which limits the character
set to 256 characters. The following figure summarizes the bit pat-
terns that indicate with which blocks the character generator is
loaded.
Bit Number
3 2 1 0 Font Page 1 Font Page 0
0 0 0 0 Not Used Block 0

0 0 0 1 Block 0 Block 1
0 0 0 Block 1 Block 0
0 0 1 Not Used Block 1
0 1 0 Not Used Block 2
0 a Block 3 Block 0
0 1 Block 3 Block 1
1 0 Block 3 Block 2
1 1 Not Used Block 3
Figure 1-54. Block Specifier
To load block 0 into font page 0 and block 3 into font page 1, the fol-
lowing BIOS call is used.
MOV AH,l1H ; Character generator routines

MOV AL,03H ; Set block specifier BIOS call
MOV BL,0CH ; Character generator block specifier
INT 10H
Font page 0 now contains the character definitions from block 0, and
font page 1 the character definitions from block 3. Because font page
o specifies characters 0 through 255, and font page 1 specifies the
characters 256 through 511, 512 characters are now available for
display. The BIOS write character routines, however, accept the AL
register as the character to be displayed. That allows a range of
characters starting at 0 and stopping at 255, and appears to limit the
number of characters to 256. The solution is to use a bit in the attri-
bute byte to specify the font page (see "Programming
Considerations" later in this section). Whenever a 512 character set

is available, bit 3 of the attribute byte selects font page 0 (characters
0- 255) or font page 1 (characters 256 - 511). If bit 3 is 1, font page 1
is used; if the bit is 0, font page 0 is used.
To display character hex 30, the following BIOS call can be used.
MOV AH.09H : Write attribute/character at cursor pos.

MOV AL.30H : AL = character to write
MOV BH.00H Display page 0
MOV eX.I : Display 1 character
MOV BL.07H : White character on black background

INT I0H : Attribute bit off selects font page 0
To display character hex 130 (304), the following BIOS call can be
used. Attribute bit 3 is still used as the intensity bit in alpha modes.
MOV AH.09H : Write attribute/character at cursor pos.
MOV AL.30H : AL = character to write
MOV BH.00H Display Page 0
MOV eX.I : Display 1 character
MOV BL.07H : Intense white character on black background
OR BL.08H : Turn on attribute bit 3 to select font page 1
INT I0H

Alternate Parameter Table
A table in BIOS, SAVE_TBl, is used to maintain various tables and

save areas. Each entry in this table is a doubleword. The format for
this table is:
Entry Description
Video Parameter Table Pointer

This must point to the video parameter table in BIOS.
2 Reserved = 0
3 Alpha Mode Auxiliary Font Pointer

This is a pOinter to a descriptor table used during a mode set to select
a user font in A/N mode. The table has the following format:
Size Description
Byte Bytes per character
Byte Block to load, should be 00 for normal operation
Word Count to store, should be hex 100 for normal operation
Word Character offset, should be 00 for normal operation
DWord Pointer to a font table
Byte Displayable rows, if the value is FF, the maximum calculated
value will be used; otherwise, this value is used.
Byte Consecutive bytes of mode values for which this font
description is to be used. The end of this stream is indicated
by a byte code of FF.
4 Graphics Mode Auxiliary Pointer

This is a pointer to a descriptor table used during a mode set to
select a user font in graphics mode. The table has the following
format:
Size Description
Byte Displayable rows
Word Bytes per character
5-7 Reserved as all 0'5.
Figure 1-55. Alternate Parameter Table
Normally, the auxiliary pointers, the third and fourth entries, are set
to all zeros. The Mode Set looks at these values and, if they are zero,
goes to the BIOS font table. If they are not zero, the Mode Set loads
the user font pointed to by the auxiliary pointer.
The pointer for SAVE_TBl exists at 40:A8. To use your own table,
create two tables, SAVE_TBl and, optionally, the font descriptor
table. Then set the pointer to point to the new SAVE_TBL.

Programming Considerations
Interrupt Usage: The Type 8525 video subsystem can be pro-

grammed to create an interrupt at the end of each vertical display
refresh time. An interrupt handler must be written by the application
to take advantage of this feature. The vertical retrace interrupt is on
IRQ2. (This interrupt does not support interrupt sharing).
The programmer can poll the Interrupt Control register, port 305
index 11, to determine whether the video caused the interrupt. The
IRQ2 status bit indicates that a vertical retrace interrupt did occur; it
does not indicate that the video is still in retrace. To find the status of
the 'vertical retrace' signal, check the CGA Status register, port 30A.
The Interrupt Control register also has 2 bits that control the interrupt
circuitry and 1 bit that controls the output of the video formatter. To
enable the interrupt
1. Clear bit 4 to clear the interrupt latch.

2. Clear bit 5 to enable the interrupt.
3. Set bit 4 to enable the latch.
512 Character Set: When using a 512 character set on the Type 8525,
the following procedures are recommended to maintain consistent
colors.
1. Set the block specifier, (AX) = 1103H.

2. Set the colors for 512, (AX) = 1000H (8X) =0712H.
3. Reload the first eight colors into the palette.
Note: The character hex 20 (normally a space) is used to fill the

blank area of the screen. Therefore, it is recommended that char-
acter hex 20 be a blank space.

Color Palette: When the character generator is loaded during the
vertical blanking interval, a maximum of 240 characters can be
loaded in SO-column modes and 120 characters in 40-column modes.
To prevent screen flicker, the color palette should be accessed only

during the vertical blanking interval. Also, when the palette is being
accessed, certain timing requirements must be observed. The fol-
lowing diagrams show these timing requirements.
~t1=:1
-WRITE
-READ
40 column 80 column
Symbol Write to Register and 320APA and 640APA
(ns) (ns)
t1 Followed by Write 240 120

t2 Followed by Read 240 120
Figure 1-56. Write to Palette Address Regi&ter
-READ
-WRITE
40 column 80 column
Symbol Read from Register and 320 APA and 640 APA
(ns) (ns)
t1 Followed by Read 240 120

t2 Followed by Write 240 120
Figure 1-57. Read Palette Address Register

-WRITE
f- t11 ~t11
-READ
RS1
RSO
Data
40 column 80 column
Symbol Write Color and 320 APA and 640 APA
(ns) (ns)
t1 Followed by Write Color 240 120

t2 Followed by any Read 240 120
Figure 1-58. Write Color followed by a Read

-WRITE f- t1 --i
-READ
RS1
RSO ~ ~
Data
40 column 80 column
Symbol Write Color and 320APA and 640APA
(ns) (ns)
t1 Followed by Write Color 240 120

t2 Followed by any Write 240 120
Figure 1-59. Write Color followed by a Write

-READ ~t2-1
-WRITE--------------------------------------------
RS1
RSO
Data
40 column 80 column
Symbol Read Color and 320 APA and 640 APA
(ns) (ns)
t1 Followed by Read Color 240 120

t2 Followed by any Read 480 240
Figure 1-60. Read Color followed by a Read

-READ
~t2---1
-WRITE----------------------------------------~~
RS1
RSO
Data
40 column 80 column
Symbol Read Color and 320 APA and 640 APA
(ns) (ns)
t1 Followed by Read Color 240 120

t2 Followed by any Write 480 240
Figure 1-61. Read Color followed by a Write

Connector
The display connects to a 14-pin connector on the system board. The

following are the pin numbering and signal assignments for the video
connector.
1 0 0 2
3 0 0 4
5 0 0 6
7 0 0 8
9 0 0 10
11 0 0 12
13 0 0 14
Pin No. Signal Name
1 Ground (Analog)
2 Red Video
3 Ground (Analog)
4 Green Video
5 Ground (Analog)
6 Blue Video
7 Ground (Analog)
8 Ground (Signal)
9 Hori.zontal Sync
10 Ground (Signal)
11 Vertical Sync
12 Ground (Signal)
13 Monitor Sense 0
14 Monitor Sense 1
Figure 1-62. Display Connector

Diskette Drive Interface
The diskette gate array contains the decode logic for the internal reg-
isters, the write logic, and the read logic. The gate array:
• Controls the clock signals needed for read and write

• Controls write precompensation
• Selects the data rate of transfer
• Provides a mask for the interrupt and DMA request lines
• Provides phase error detection for input to the phase-lock loop.
The phase detector/amplifier and the voltage controlled oscillator

(VCO) make up the phase-lock loop (PLL). They adjust the clock used
during data read to keep it in phase with the data signal.
The drives connect to the system board through a single 40-pin con-
nector, which supplies all signals necessary to operate two diskette
drives. The diskette drives are attached to the connector through an
internal, flat cable.
1·78 Diskette Drive

Gate Array Registers
The diskette gate array has five registers: three registers that show
the status of signals used in diskette operations, and two registers
that control certain interface signals.
RAS Port A Register: The RAS Port A register, hex 3FO, is a read-
only register that shows the status of the corresponding signals.
Bit Function
7 IRQ6
6 DRQ2
5 Step (latched)
4 Track 0
3 -Head 1 Select
2 Index
1 Write Protect
o -Direction
Figure 1-63. RAS Port A, Hex 3FO
RAS Port B Register: The RAS Port B register, hex 3F1, is a read-
only register that shows the status of signals between the diskette
drive and the controller.
Bit Function
7 Reserved
6 -Drive Select 1
5 -Drive Select 0
4 Write Data (latched)
3 Read Data (latched)
2 Write Enable (latched)
1 -Drive Select 3
o -Drive Select 2
Figure 1-64. RAS Port B, Hex 3F1
Diskette Drive 1-79

Digital Output Register: The Digital Output register (DaR), hex 3F2,
is a write-only register that controls drive motors, drive selection, and
feature enables. All bits are cleared by a reset.
Bit Function
7 Motor Enable 3
6 Motor Enable 2
5 Motor Enable 1
4 Motor Enable 0
3 DMA and Interrupt Enable
2 -Controller Reset
1,0 Drive Select 0 through 3
00 selects drive 0
01 selects drive 1
10 selects drive 2
11 selects drive 3
Figure 1-65. Digital Output, Hex 3F2
Digital Input Register: The Digital Input register, hex 3F7, is a read-
only register used to sense the state of the 'diskette change' signal. It
is also used for diagnostic purposes.
Bit Function
7 -Diskette Change
6 to 4 Reserved
3 DMA Enable
2 No Write Precomp
1 250K bps Rate Select
o Reserved
Figure 1-66. Digital Input, Hex 3F7

Configuration Control Register: The Configuration Control register,
hex 3F?, is a write-only register used to set the transfer rate and
select write precompensation.
Bit Function
7 Reserved = 0
6 Reserved = 0
5 Reserved = 0
4 Reserved = 0
3 Reserved = 0
2 No Write Precomp
1 250K bps Rate Select
o Reserved = 0
Figure 1-67. Configuration Control, Hex 3F7
Controller Registers
The diskette controller has two registers that are accessed by the
microprocessor: the Main Status register and the data register. The
Main Status register, hex 3F4, has the status information about the
controller and may be read at any time.
Data Registers, Hex 3F5: This address, hex 3F5, consists of several
registers in a stack, with only one register presented to the data bus
at a time. It stores data, commands, and parameters, and provides
diskette-drive status information. Data bytes are passed through the
data register to program or obtain results after a command.
Diskette Drive 1-81

Main Status Register, Hex 3F4: This register is read-only and is used
to facilitate the transfer of data between the microprocessor and the
controller.
Bit Function
7 Request for Master

6 Data Input/Output
5 Non-DMA Mode
4 Diskette Controller Busy
3.2 Reserved
1 Drive 1 Busy
o Drive 0 Busy
Figure 1-68. Main Status Register
The bits are defined as follows:
Bit 7 The data register is ready for transfer with the micro-
processor.
Bit 6 This bit indicates the direction of data transfer between the
diskette controller and the microprocessor. If this bit is set
to 1, the transfer is from the controller to the micro-
processor; if it is clear, the transfer is from the micro-
processor.
Bit 5 When this bit is set to 1, the controller is in the non-DMA

mode.
Bit 4 When this bit is set to 1, a Read or Write command is being
executed.
Bits 3, 2 Reserved
Bit 1 Drive 1 Busy-When set to 1, diskette drive 1 is in the seek

mode.
Bit 0 Drive 0 Busy-When set to 1, diskette drive 0 is in the seek
mode.
1-82 Diskette Drive

Commands
The diskette controller performs the commands listed below. Each

command is initiated by a multi byte transfer from the microprocessor,
and the result can also be a multi byte transfer back to the micro-
processor. Because of this multi byte interchange of information
between the controller and the microprocessor, each command is
considered to consist of three phases:
Command Phase: The microprocessor issues a series of Writes to

the controller that direct it to perform a specific operation.
Execution Phase: The controller performs the specified operation.
Result Phase: After completion of the operation, status and other

housekeeping information are made available to the microprocessor
through a sequence of Read commands from the microprocessor.
The following is a list of controller commands:
• Read Data
• Read Deleted Data
• Read a Track
• ReadlD
• Write Data
• Write Deleted Data
• Format a Track
• Scan Equal
• Scan Low or Equal
• Scan High or Equal
• Recalibrate
• Sense Interrupt Status
• Specify
• Sense Drive Status
• Seek.
Diskette Drive 1-83

Symbol Descriptions: Following are descriptions of symbols used in
the following section, "Command Format."
AO Address Line O-When clear, AO selects the Main Status

register; when set to 1, it selects the Data register.
DTL Data Length-When N is 00, DTL is the data length to be
read from or written to a sector.
EOT End of Track-The final sector number on a cylinder.
GPL Gap Length-The length of gap 3 (spacing between
sectors excluding the VCO synchronous field).
H Head Address-The head number, either 0 or 1, as speci-
fied in the 10 field.
HD Head-The selected head number, 0 or 1. (H = HD in all
command words.)
HLT Head Load Time-The head load time in the selected
drive (2 to 256 milliseconds in 2-millisecond increments).
HUT Head Unload Time-The head unload time after a read or
write operation (0 to 240 milliseconds in 16-millisecond
increments).
MF FM or MFM Mode-A 0 selects FM mode and a 1 selects
MFM (MFM is selected only if it is implemented).
MT Multitrack-A 1 selects multitrack operation. (Both HDO
and HD1 will be read or written.)
N Number-The number of data bytes written in a sector.
NCN New Cylinder-The new cylinder number for a seek oper-
ation.
ND Nondata Mode-This indicates an operation in the
nondata mode.
PCN Present Cylinder Number-The cylinder number at the
completion of a Sense Interrupt Status command
(present position of the head).
R Record-The sector number to be read or written.
SC Sector-The number of sectors per cylinder.
SK Skip-The skip deleted-data address mark.
1-84 Diskette Drive

SRT Stepping Rate-These four bits indicate the stepping rate
for the diskette drive as follows:
1111 1 ms
1110 2 ms
1101 3 ms
STO -3 Status 0 through Status 3-The four registers that store
status information after a command is executed.
STP Scan Test-If STP is 01, the data in adjacent sectors is
compared with the data sent by the microprocessor
during a scan operation. If STP is 02, alternate sectors
are read and compared.
USO -1 Unit Select-The selected driver number, encoded the
same as bits 0 and 1 of the Digital Output register.
Diskette Drive 1-85

Command Format
The following are commands that may be issued to the controller. An

X is used to indicate a don't-care condition.
Read Data
Command Phase
MT = Multitrack
MF = MFM Mode
SK = Skip Deleted-Data Address Mark
HD = Head Number
USx = Unit Select
765432 0
Byte 0 MT MF SK 0 0 1 1 0
Byte 1 X X X X X HD US1 usa
Byte 2 Cylinder Number
Byte 3 Head Address
Byte 4 Sector Number
Byte 5 Number of Data Bytes in Sector
Byte 6 End of Track
Byte 7 Gap Length
Byte 8 Data Length
Figure 1-69. Read Data Command
Result Phase
76543210
Byte 0 Status Register 0

Byte 4 Head Address
Figure 1-70. Read Data Result
1-86 Diskette Drive

Read Deleted Data
Command Phase
MT = Multitrack
MF = MFM Mode
HD = Head Number
USx = Unit Select
7 6 5 4 3 2 1 0
Byte 3 Head Address
ByteS Number of Data Bytes in Sector
Byte 6 End of Track
Byte 7 Gap Length
ByteS Data Length
Figure 1-71. Read Deleted Data Command
Result Phase
765432 0

Byte 4 Head Address
ByteS Sector Number
Figure 1-72. Read Deleted Data Result
Diskette Drive 1-87

Read a Track
Command Phase
MF = MFM Mode
HD = Head Number
USx = Unit Select
765432 0
Byte 0 o MF SK 0 0 0 1 0
Byte 3 Head Address
Byte 6 End of Track
Byte 7 Gap Length
Byte 8 Data Length
Figure 1-73. Read a Track Command
Result Phase
765432 0

Byte 4 Head Address
Figure 1-74. Read a Track Result
1-88 Diskette Drive

ReadlD
Command Phase
MF = MFM Mode
HD = Head Number
USx = Unit Select
76543210
Byte 0 o MF 0 0 1 0 1 0
Figure 1-75. Read 10 Command
Result Phase
765432 0

Byte 4 Head Address
Figure 1-76. Read 10 Result
Diskette Drive 1-89

Write Data
Command Phase
MT = Multitrack
MF = MFM Mode
HD = Head Number
USx = Unit Select
765432 0
Byte 0 MT MF 0 0 0 1 0 1
Byte 3 Head Address
Byte 6 End of Track
Byte? Gap Length
Byte 8 Data Length
Figure 1-77. Write Data Command
Result Phase
765432 0

Byte 4 Head Address
Figure 1-78. Write Data Result
1-90 Diskette Drive

Write Deleted Data
Command Phase
MT = Multitrack
MF = MFM Mode
HD = Head Number
USx = Unit Select
765432 0
Byte 0 MT MF 0 0 1 0 0 1
Byte 3 Head Address
Byte 6 End of Track
Byte 7 Gap Length
Byte 8 Data Length
Figure 1-79. Write Deleted-Data Command
Result Phase
765432 0

Byte 4 Head Address
ByteS Sector Number
Figure 1-80. Write Deleted-Data Result
Diskette Drive 1-91

Format a Track
Command Phase
MF = MFM Mode
HD = Head Number
USx = Unit Select
7654320
Byte 0 o MF 0 0 0
Byte 1 X X X X X HD US1 USO
Byte 3 Sectors per Cylinder
Byte 4 Gap Length
Byte 5 Data
Figure 1-81. Format a Track Command
Result Phase
76543210

Byte 4 Head Address
Figure 1-82. Format a Track Result
1-92 Diskette Drive

Scan Equal
Command Phase
MT = Multitrack
MF = MFM Mode
HD = Head Number
USx = Unit Select
76543210
Byte 0 MT MF SK 0 0 0 1
Byte 3 Head Address
Byte 6 End of Track
Byte 7 Gap Length
Byte 8 Scan Test
Figure 1-83. Scan Equal Command
Result Phase
765432 0

Byte 4 Head Address
Figure 1-84. Scan Equal Result
Diskette Drive 1-93

Scan Low or Equal
Command Phase
MT = Multitrack
MF = MFM Mode
HD = Head Number
USx = Unit Select
7 6 5 4 3 2 0
Byte 3 Head Address
Byte 6 End of Track
Byte 7 Gap Length
ByteS Scan Test
Figure 1-85. Scan Low or Equal Command
Result Phase
765432 0

Byte 4 Head Address
Figure 1-86. Scan Low or Equal Result
1-94 Diskette Drive

Scan High or Equal
Command Phase
MT = Multitrack
MF = MFM Mode
HD = Head Number
USx = Unit Select
7 6 5 4 3 2 1 0
Byte 3 Head Address
Byte 6 End of Track
Byte 7 Gap Length
ByteS Scan Test
Figure 1-87. Scan High or Equal Command
Result Phase
76543210

Byte 4 Head Address
ByteS Sector Number
Figure 1-88. Scan High or Equal Result
Diskette Drive 1-95

Recalibrate
Command Phase
USx "'" Unit Select
7 6 5 4 3 2 0
Byte a a a a a a 1 1 1
Byte 1 X X X X X a US1 usa
Figure 1-89. Recalibrate Command
Result Phase: This command has no result phase.
Sense Interrupt Status
Command Phase
7 6 5 4 3 2 0
I Byte a a a a a a a a
Figure 1-90. Sense Interrupt Status Command
Result Phase
765432 0
Byte a Status Register a

Byte 1 Present Cylinder Number
Figure 1-91. Sense Interrupt Status Result

Specify
Command Phase
SRT = Diskette Stepping Rate

HUT = Head Unload Time
HLT = Head Load Time
ND = NonData Mode
765432 0
Byte 0 0 0 0 0 0 0 1
Byte 1 SRT HUT
Byte 2 HLT ND
Figure 1-92. Specify Command
Sense Drive Status
Command Phase
USX = Unit Select

HD = Head Number
765432 0
Byte 0 0 0 0 0 0 1 0 0
Figure 1-93. Sense Drive Status Command
Result Phase
76543210
I Byte 0 Status 3 Register
Figure 1-94. Sense Drive Status Result
Diskette Drive 1-97

Seek
Command Phase
USx = Unit Select
765432 0
Byte 0 00001111
Byte 1 X X X X X 0 US1 USO
Byte 2 New Cylinder Number for Seek
Figure 1-95. Seek Command
Invalid Commands
Result Phase: The following status byte is returned to the micro-

processor when an invalid command has been received.
76543210
I Byte 0 Status 0 Register
Figure 1-96. Invalid Command Result
1-98 Diskette Drive

Command Status Registers
The following are definitions of the status registers STO through ST3.
Status 0 Register (STO)

The following are bit definitions for the Status 0 register:
Bit 7, 6 Interrupt Code (IC)

00 Normal Termination of Command-The command was
completed and properly executed.
01 Abrupt Termination of Command-The execution of the
command was started but not successfully completed.
10 Invalid Command Issue-The issued command was
never started.
11 Abnormal Termination-During the execution of a
command, the 'ready' signal from the diskette drive
changed state.
Bit 5 Seek End-8et to 1 when the controller completes the Seek
command.
Bit 4 Equipment Check-Set if a 'fault' signal is received from the
diskette drive, or if the 'track 0' signal fails to occur after 77
step pulses (Recalibrate command).
Bit 3 Not Ready-This flag is set when the diskette drive is in the
not-ready state and a Read or Write command is issued.
Bit 2 Head Address-Indicates the state of the head at interrupt.
Bit 1,0 Unit select 1 and 0 (US 1 and O)-Indicate a drive's unit
number at interrupt.
Status 1 Register (ST1)

Bit 7 End of Cylinder-Set when the controller tries to gain access

to a sector beyond the final sector of a cylinder.
Bit 6 Reserved.
Bit 5 Data Error-8et when the controller detects a CRC error in
either the ID field or the data field.
Diskette Drive 1-99

Bit 4 Overrun-8et if the controller is not serviced by the main
system within a certain time limit during data transfers.
Bit 3 Reserved.
Bit 2 No Data-Set if the controller cannot find the sector specified
in the 10 register during the execution of a Read Data, Write
Deleted Data, or Scan command. This flag is also set if the
controller cannot read the 10 field without an error during
the execution of a Read 10 command, or if the starting sector
cannot be found during the execution of a Read Cylinder
command.
Bit 1 Not Writable-Set if the controller detects a 'write-protect'
signal from the diskette drive during execution of a Write
Data, Write Deleted Data, or Format a Track command.
Bit 0 Missing Address Mark-Set if the controller cannot detect
the 10 address mark. At the same time, bit 0 of the Status 2
register is set.
Stalus 2 Register (ST2)

Bit 7 Reserved = o.
Bit 6 Control Mark-This flag is set if the controller encounters a
sector that has a deleted-data address mark during exe-
cution of a Read Data or Scan command.
Bil5 Data Error in Data Field-Set if the controller detects an
error in the data.
Bit 4 Wrong Cylinder-This flag is related to NO and is set when
the content of C is different from that stored in the 10 reg-
ister.
Bit 3 Scan Equal Hit (SH)-Set if the adjacent sector data equals
the microprocessor data during the execution of a Scan
command.
Bit 2 Scan Not Satisfied (SN)-Set if the controller cannoHind a
sector on the cylinder that meets the condition during a Scan
command.
Bit 1 Bad Cylinder-Related to NO and is set when the contents of
C on the medium are different from that stored in the 10 reg-
ister or when the content of C is hex FF.
1-100 Diskette Drive

Bit 0 Missing Address Mark in Data Field- Set if the controller
cannot find a data address mark or a deleted-data address
mark when data is read.
Status 3 Register (ST3)

Bit 7 Fault-Status of the 'fault' signal from the diskette drive.

Bit 6 Write Protect-Status of the '-write protect' signal from the
diskette drive.
Bit 5 Ready-5tatus of the 'ready' signal from the diskette drive.
Bit 4 Track O-Status of the '-track 0' signal from the diskette
drive.
Bit 3 Two Side-5tatus of the 'two side' signal from the diskette
drive.
Bit 2 Head Address-5tatus of the '-head 1 select' signal from the
diskette drive.
Bit 1 Unit Select 1-5tatus of the '-drive select l' signal from the
diskette drive.
Bit 0 Unit Select O-Status of the '-drive select 0' signal from the
diskette drive.
Diskette Drive 1-101

Signal Description
All signals are 74HCT series-compatible in both rise and fall times
and in interface levels. The following are the input signals to the
diskette drive. These signal thresholds are + 2.0 V dc high and + 0.8
V dc low.
-Drive Select 0-1: The select lines provide the means to enable or
disable the drive interface lines. When the signal is active, the drive
is enabled. When the signal is inactive, all control inputs are ignored,
and the drive outputs are disabled. The maximum drive-select delay
time is 500 ns.
-Motor Enable 0-1: When this signal is made active, the spindle
starts to turn. When it is made inactive, the spindle slows to a stop.
-Step: An active pulse on this line causes the head to move one
track. The minimum pulse width is 1 ~s. The direction of the head
motion is determined by the state of the '-direction' signal at the
trailing edge of the '-step' pulse.
-Direction: When this signal is active, the head moves to the next
higher track (toward the spindle) for each '-step' pulse. When the
signal is inactive, the head moves toward track O. This signal must
be stable for 1 ~s before and after the trailing edge of the '-step'
pulse.
-Head 1 Select: When this signal is active, the upper head (head 1) is
selected. When it is inactive, the lower head (head 0) is selected.
-Write Enable: When this signal is active, the write-current circuits

are enabled and data can be written under the control of the '-write
data' signal. This signal must be active 8 us before data can be
written.
-Write Data: An active pulse on this line writes a 1. These pulses

have a 4-,6-, or 8-~s spacing with a width of 250 ns for the
250,000-bps transfer rate. Write precompensation of 125 ns is done
by the diskette gate array.

The following are the output signals from the diskette drive. These
signal thresholds are +3.7 V dc high and +0.4 V dc low.
-Index: An active pulse of 1 ms indicates the diskette index.
-Track 0: When this signal is active, the head is on track O. This

signal is used to determine whether the drive is present. If, after
commanding the drive to seek track 0, the '-track 0' signal does not
go active, the drive is not present.
-Write Protect: This signal is active when the write-protect window is

uncovered. When this happens, the write current circuits are disa-
bled.
-Read Data: An active pulse on this line writes a logical 1. The pulse
width for the 250,000-bps rate is 250 ns.
-Diskette Change: This signal is active at power-on and whenever

the diskette is removed. It remains active until a diskette is present
and a '-step' pulse is received.
Diskette Drive 1-103

Connector
The following shows the signals and pin assignments for the con-
nector.
Pin 110 Signal Pin 110 Signal
1 N/A Signal Ground 2 N/A Reserved

3 N/A Signal Ground 4 N/A Reserved
5 N/A Signal Ground 6 N/A Not Connected
7 N/A Signal Ground 8 I -Index
9 N/A Signal Ground 10 Q -Motor Enable 1
11 N/A Signal Ground 12 d -Drive Select 0
13 N/A Signal Ground 14 d -Drive Select 1
15 N/A Signal Ground 16 0 -Motor Enable 0
17 N/A Signal Ground 18 0 -Direction
19 N/A Signal Ground 20 0 -Step
21 N/A Signal Ground 22 0 -Write Data
23 N/A Signal Ground 24 0 -Write Enable
25 N/A Signal Ground 26 I -Track 0
27 N/A Signal Ground 28 I -Write Protect
29 N/A Signal Ground 30 I -Read Data
31 N/A Signal Ground 32 0 -Head 1 Select
33 N/A Signal Ground 34 I -Diskette Change
35 N/A Ground 36 N/A Ground
37 N/A Ground 38 0 +5Vdc
39 N/A Ground 40 0 + 12 V dc
Figure 1-97. Diskette Drive Connector

Fixed Disk Connector
The IBM Personal System/2 Model 25 provides a dedicated I/O
channel for the connection of the IBM Personal System/220MB Fixed
Disk Drive and controller, or simi liar attachment. The signals across
this connector are the normal I/O channel signals needed for fixed
disk operation: I/O read and write, reset, data lines, 10 CH RDY,
IR05, and the DMA request and acknowledge lines. These signals
operate the same as the normal I/O channel signals described
earlier. The additional signals are as follows:
-Disk Card Select: (-DISK CS): The address decode logic for the
fixed disk is on the system board. It is enabled through the System
Board Control register (see "Chip Select Logic" earlier in this
section). When the logic is enabled, -DISK CS goes active on a valid
decode of A4 through A19 equal to hex 032x.
-Disk Installed: When active, this signal indicates that a fixed disk
and its controller are installed.
Address 0 through 2 (AO-A2): These three address lines are used to

select the specific register within the controller.
The following shows the signal timing for -DISK CS. The other signal
timings are the same as those on the I/O channel.
-DISK CS ' "' "' "' "

t1~
~'-- ~
' "' " ____ ~/'"
~ ~t2
' "' "' "' "' "
-lOR/-lOW
~ /
Symbol Parameter Description Min (ns)
t1 -DISK CS active to Command active 25

t2 Command inactive to -DISK CS inactive 45
Figure 1-97.1. Fixed Disk Signal Timing
Fixed Disk 1-104.1

The following shows the signal assignments for the fixed disk con-
nector.
Pin 110 Signal Name Pin 110 Signal Name
1 0 RESET DRV 2 I -DISK Installed

3 I/O DO 4 N/A Ground
5 I/O D1 6 N/A Ground
19 0 -lOR 20 N/A Ground
21 0 -lOW 22 N/A Ground
23 0 -DISK CS 24 N/A Ground
25 0 AO 26 N/A Ground
27 0 A1 28 N/A Ground
29 0 A2 30 0 +5Vdc
31 N/A Reserved 32 0 +5Vdc
33 0 -DACK3 34 N/A Ground
35 I DRQ3 36 N/A Ground
37 I IRQ5 38 N/A Ground
39 I I/O CH RDY 40 0 + 12Vdc
41 N/A Spare 42 0 + 12Vdc
43 N/A Spare 44 0 + 12Vdc
Figure 1-97.2. Fixed Disk Connector
1-104.2 Fixed Disk

Serial Port
The serial port is fully programmable and supports asynchronous
communications. It will add and remove start, stop, and parity bits. A
programmable baud-rate generator allows operation from 50 baud to
9600 baud. The port supports 5-, 6-, 7-, and a-bit characters with 1,
1.5, or 2 stop bits. A prioritized interrupt system controls transmit,
receive, error, and line status as well as data set interrupts.
The rear of the system unit has a 25-pin D-shell connector that con-
tains standard Electronic Industries Association (EIA) RS-232C inter-
face signals.
CS from I/O Gate Array

LAO-LA2
Data Bus
INTRPT 8250A
Asynchronous
Receive Clock Communications
Controller
1.84 MHz
from
CPU Gate Array
I EIA
Receivers
I
1
r--
Y25-P;n I
Connector .1
I
1
EIA
Drivers ~
Figure 1-98. Serial Port Block Diagram
Serial Port 1-105

The serial port has a controller that provides the following functions:
• Adds or deletes standard, asynchronous communications bits to

or from a serial data stream.
• Provides full double buffering, which eliminates the need for
precise synchronization.
• Provides a programmable baud-rate generator.
• Provides modem controls (CTS, RTS, OSR. OTR, RI, and CO).
Application
The serial port is addressed as communications port 1, addresses

hex 3F8 through 3FF; the port uses interrupt 4.
The data format is:

00 01 02 03 04 05 06 07
Stop
Bit
Data bit 0 is the first bit to be sent or received. The controller auto-
matically inserts the start bit, the correct parity bit (if programmed to
do so), and the stop bit (1,1.5, or 2, depending on the command in the
Line Control register).
1-106 Serial Port

Controller Registers
The register addresses are hex 3F8 through 3FF. These registers
control the controller's operations and are used to transmit and
receive data. The divisor latch access bit (OLAB), which is the most
significant bit of the Line Control register, affects the selection of the
divisor latches for the baud rate generator.
Specific registers are selected according to the following figure:
DLAB Port 1
State Addre •• Read/Write Register
0 03FS W Transmitter Holding

0 03FS R Receiver Buffer
1 03FS R/W Divisor Latch, Low Byte
1 03F9 R/W Divisor Latch, High Byte
0 03F9 R/W Interrupt Enable Register
X 03FA R Interrupt Identification Register

X 03FB R/W Line Control Register
X 03FC R/W Modem Control Register
X 03FD R Line Status Register
X 03FE R Modem Status Register
X 03FF R/W Scratch Register
Figure 1-99. Serial Port Addresses
Transmitter Holding Register, Hex 3F8: This register contains the

character to be sent. Bit 0 is the least significant bit and the first bit
sent serially.
Bit Function
7 Bit 7
6 BitS
5 Bit 5
4 Bit 4
3 Bit 3
2 Bit 2
1 Bit 1
OBit 0
Figure 1-100. Transmitter Holding Register
Serial Port 1·107

Receiver Buffer Register, Hex 3F8: This register contains the
received character. Bit 0 is the least significant bit and the first bit
received serially.
Bit Function
7 Bit 7
6 Bit 6
5 Bit 5
4 Bit 4
3 Bit 3
2 Bit 2
1 Bit 1
0 Bit 0
Figure 1-101. Receiver Buffer Register
Divisor Latch, 3F9 and 3F8: These two registers access the high byte
(3F9) and low byte (3F8) of the divisor latch. More information about
the divisor latch may be found under "Programmable Baud-Rate Gen-
erator" later in this section.
Bit High Byte Low Byte
7 Bit 15 Bit 7
6 Bit 14 Bit 6
5 Bit 13 Bit 5
4 Bit 12 Bit 4
3 Bit 11 Bit 3
2 Bit 10 Bit 2
1 Bit 9 Bit 1
0 Bit 8 Bit 0
Figure 1-102. Divisor Latch
Interrupt Enable Register, Hex 3F9: This register allows the four
types of controller interrupts to separately activate the 'chip-interrupt'
(INTRPT) output signal. The interrupt system can be totally disabled
by resetting bits 3 through 0 of the Interrupt Enable register to O. Sim-
ilarly, by setting the appropriate bits of this register to 1, selected
interrupts are enabled. Disabling the interrupt system inhibits the
Interrupt Enable register and the active INTRPT output from the chip.
All other system functions operate normally, including the setting of
the Line Status and Modem Status registers.
1-108 Serial Port

Bit Function
7 Reserved = 0
6 Reserved = 0
5 Reserved = 0
4 Reserved = 0
3 Enable Modem Status
2 Enable Rx Line Status
1 Enable Tx Buffer Empty
o Enable Data Available
Figure 1-103. Interrupt Enable Register
Bits 7-4 Reserved = O.

Bit 3 When set to 1, this bit enables the modem status interrupt.
Bit 2 When set to 1, this bit enables the receiver-line-status inter-
rupt.
Bit 1 When set to 1, this bit enables the transmitter-holding-
register-empty interrupt.
Bit 0 When set to 1, this bit enables the received-data-available
interrupt.
Interrupt Identification Register (UR), ftex 3FA: The controller has an

internal interrupt capability that makes communications possible with
reduced microprocessor intervention. To minimize programming
overhead during data character transfers, the controller prioritizes
interrupts into four levels: receiver line status (priority 1), received
data ready (priority 2), transmitter holding register empty (priority 3),
and modem status (priority 4).
Information about a pending interrupt is stored in the Interrupt Iden-

tification register. When addressed during chip-select time, this reg-
ister stops the pending interrupt with the highest priority, and no
other interrupts are acknowledged until the microprocessor services
that particular interrupt.
Serial Port 1-109

Bit Function
7 Reserved = 0
6 Reserved = 0
5 Reserved = 0
4 Reserved = 0
3 Reserved = 0
2 Interrupt ID Bit 1
1 Interrupt ID Bit 0
o Interrupt Not Pending
Figure 1-104. Interrupt Identification Register
Bits 7-3 Reserved = O.
Bits 2,1 These two bits, Interrupt 10 1 and 0, identify the pending
interrupts as shown.
IIR Bits Interrupt Control

2 1 Priority Type Cause To Reset
1 1 Highest Receiver Overrun, Parity, Read the Line Status Reg-

Line Status or Framing Error, ister
or Break Interrupt
0 Second Received Data in Receiver Read the Receiver Buffer

Data Avail- Buffer Register
able
0 Third Trans- THR is Empty Read IIR or Write to THR
mitter
Holding
Register
Empty
0 0 Fourth Modem Change in a Read the Modem Status
Status Signal's Status Register
from the Modem
Bit 0 This bit can be used in either hard-wired, prioritized, or

polled conditions to indicate whether an interrupt is pending.
When bit 0 is 0, an interrupt is pending, and the Interrupt
Identification register contents may be used as a pointer to
the appropriate interrupt service routine. When bit 0 is a 1,
no interrupt is pending, and polling (if used) continues.
1-110 Serial Port

Line Control Register, Hex 3FB: This register specifies the format of
the asynchronous data communications exchange. The register can
also be read at any time, eliminating the need to store line character-
istics separately in memory.
Bit Function
7 DLAB
6 Set Break
5 Stick Parity
4 Even Parity Select
3 Parity Enable
2 Number of Stop Bits
1 Word Length Select 1
o Word Length Select 0
Figure 1-105. Line Control Register
Bit 7 This is the divisor-latch access bit. It is set to 1 to gain

access to the divisor latches of the baud-rate generator
during a read or write operation. It is cleared to gain access
to the Receiver Buffer, the Transmitter Holding, or the Inter-
rupt Enable registers.
Bit 6 This bit is the set-break control bit. When bit 6 is set to 1,
the serial output is forced to an inactive level and remains
there regardless of other transmitter activity. The set-break
is disabled by clearing bit 6 to O.
Bit 5 This bit is the stick-parity bit. When this bit is set to 1 and
parity is enabled, the parity bit is sent as a 0 if parity is
even, or as a 1 if parity is odd.
Bit 4 This bit is the even-parity-select bit. When set to 1 and
parity is enabled, an even number of logical 1's are sent or
checked. When cleared to 0, an odd number of bits are sent
or checked.
Bit 3 This bit is the parity-enable bit. When this bit is set to 1, a
parity bit is sent or checked. The parity bit is used to
produce an even or odd number of 1's when the bits in the
data word and the parity bit are summed.
Bit 2 This bit specifies the number of stop bits in each serial char-
acter that is sent or received. When set to 1 and a word
length greater than 5 is specified, 2 stop bits are generated
or checked. If the word length is 5 and this bit is set to 1,
then 1.5 stop bits are generated or checked. When this bit is
cleared to 0, then 1 stop bit is specified.
Serial Port 1-111

Bits 1,0 These 2 bits specify the number of bits in each serial char-
acter that is sent or received. The encoding of these bits is
as follows:
Bit 1 Bit 0 Word Length in Bits
o o 5
o 1 6
1 o 7
1 1 6
Modem Control Register, Hex 3FC: The Modem Control register

(MCR) controls the output signals to the modem or data set (an
external device acting as a modem).
Bit Function
7 to 5 Reserved = 0
4 Loop
3 Out 2
2 Out 1
1 Request to Send
o Data Terminal Ready
Figure 1-106. Modem Control Register
Bits 7-5 Reserved = o.

Bit 4 This bit provides a loopback feature for diagnostic testing of
the controller. When this bit is set to 1, the following events
occur:
• SOUT is set to the active state.
• SIN is disconnected.
• The output of the Transmitter Shift register is "looped
back" to the Receiver Shift register input.
• The four modem-control inputs (-DSR, -CTS, -RLSD, and
-RI) are disconnected.
• The four modem-control outputs (-DTR, -RTS, -OUT 1, and
-OUT 2) are internally connected to the four modem
control inputs.
In the diagnostic mode, data sent is immediately received.

This feature allows the microprocessor to verify the
transmit- and receive-data paths of the controller.
In the diagnostic mode, the receiver and transmitter inter-

rupts are fully operational, as are the modem-control inter-
rupts; however, the interrupts' sources are now the lower 4
1-112 Serial Port

bits of the Modem Control register instead of the four
modem-control inputs. The interrupts are still controlled by
the Interrupt Enable register.
The controller's interrupt system can be tested by writing to

the lower 6 bits of the Line Status register and the lower 4
bits of the Modem Status register. Setting any of these bits
to 1 generates the appropriate interrupt (if enabled). Reset-
ting these interrupts is the same as for normal controller
operation. To return to normal operation, the registers must
be reprogrammed for normal operation, and then bit 4 of the
MCR is cleared to O.
Bit 3 This bit controls -OUT 2; when set to 1, it forces -OUT 2 active.
Bit 2 This bit controls -OUT 1; when set to 1, it forces -OUT 1 active.
Bit 1 This bit controls -RTS; when set to 1, it forces -RTS active.
Bit 0 This bit controls -DTR; when set to 1, it forces -DTR active.
Line Status Register, Hex 3FD: This register provides the micro-
processor with status information about the data transfer.
Note: Bits 1 through 4 are error conditions that produce a receiver

line-status interrupt whenever any of the corresponding conditions
are detected.
Bit Function
7 Reserved = 0
6 Tx Register Empty
5 Transmitter Holding Register Empty
4 Break Interrupt
3 Framing Error
2 Parity Error
1 Overrun Error
o Data Ready
Figure 1-107. Line Status Register
Bit 7 Reserved = o.
Bit 6 This bit is the transmitter empty indicator. It is set to 1
whenever the Transmitter Holding register and the Trans-
mitter Shift register are both empty.
Serial Port 1-113

Bit 5 This bit is the Transmitter Holding register empty (THRE)
indicator. It indicates the controller is ready to accept a new
character for transmission. In addition, this bit causes the
controller to issue an interrupt to the microprocessor when
the THRE interrupt is enabled. The THRE bit is set to 1 when
a character is transferred from the Transmitter Holding reg-
ister into the Transmitter Shift register. It is cleared when
the microprocessor loads the Transmitter Holding register.
Bit 4 This bit is the break interrupt indicator. It is set to 1 when-
ever the received data input is held in the spacing state (0)
for longer than a full-word transmission time (that is, the
total time of start bit + data bits + parity + stop bits).
Bit 3 This bit is the framing error indicator. It indicates the
received character did not have a valid stop bit. Bit 3 is set
to 1 whenever the stop bit is detected as a 0 (spacing level).
Bit 2 This bit is the parity error indicator and indicates the
received data character does not have the correct even or
odd parity. The parity error bit is set to 1 on a parity error
and is cleared when the Line Status register is read.
Bit 1 This bit is the overrun error indicator. It indicates that data
in the Receiver Buffer register was not read by the micro-
processor before the next character was transferred into the
register, thereby destroying the previous character. This
indicator is cleared when the microprocessor reads the con-
tents of the Line Status register.
Bit 0 This bit is the receiver data ready indicator. It is set to 1
whenever a complete incoming character has been received
and transferred into the Receiver Buffer register.
1-114 Serial Port

Modem Status Register, Hex 3FE: This register provides the current
state of the control lines from the modem (or external device) to the
microprocessor. In addition, 4 bits provide change information. They
are set whenever a control input from the modem changes state; they
are cleared when the microprocessor reads this register.
Note: Whenever bit 0, 1,2, or 3 is set, a modem status interrupt is

generated.
Bit Function
7 Data Carrier Detect

6 Ring Indicate
5 Data Set Ready
4 Clear to Send
3 Delta Data Carrier Detect
2 Trailing Edge Ring Indicate
1 Delta Data Set Ready
o Delta Clear to Send
Figure 1-108. Modem Status Register
Bit 7 When set to 1, this bit indicates -DCD is active. In the diag-
nostic mode, this bit is equivalent to OUT 2 of the Modem
Control register.
Bit 6 When set to 1, this bit indicates -RI is active. In the diag-
nostic mode, this bit is equivalent to OUT 1 of the Mode
Control register.
Bit 5 When set to 1, this bit indicates -DSR is active. In the diag-
nostic mode, this bit is equivalent to DTR of the Mode
Control register.
Bit 4 When set to 1, this bit indicates -CTS is active. In the diag-
nostic mode, this bit is equivalent to RTS of the Mode
Control register.
Bit 3 This bit is the delta data-carrier-detect indicator. It indicates
-DCD to the chip has changed state.
Bit 2 This bit is the trailing-edge ring-indicate indicator. It indi-
cates that -RI to the chip has changed from active to inactive.
Bit 1 This bit is the delta data-set-ready indicator. It indicates that
-DSR to the chip has changed state.
Bit 0 This bit is the delta clear-to-send indicator. It indicates that

-CTS to the chip has changed state.
Serial Port 1·115

Programmable Baud-Rate Generator
The controller has a programmable baud-rate generator that can

divide the clock input, which is 1.84 MHz, by any divisor from 1 to
65,535 (2 16 - 1). The output frequency of the baud-rate generator is
the bps rate multiplied by 16. Two a-bit latches store the divisor in a
16-bit binary format. These divisor latches are loaded during setup to
ensure desired operation of the baud-rate generator. When either of
the divisor latches is loaded, a 16-bit baud counter is immediately
loaded. This prevents long counts on the first load.
The following is a sample program that sets the baud rate at 1200
with an a-bit data word, 1 stop bit, and odd parity.
BEGIN PROC NEAR

MOV AL,8BH : Set port parameters
MOV AH,SSH : Initialize COM1 port
INT 14H : Serial port BIOS interrupt
ENDP
1-116 Serial Port

Signal Descriptions
The following describes the function of controller 1/0 signals.
Input Signals
-Clear to Send (-CTS): This signal is an input from the modem. The
status of this signal is reflected in bit 4 of the Modem Status register.
Bit 0 of the same register indicates whether -CTS has changed state
since the last reading.
-Data Set Ready (-DSR): When active, this signal indicates the
modem or data set is ready to establish the communications link and
transfer data with the controller. This signal is an input from the
modem. Its status is reflected in bit 5. of the Modem Status register.
Bit 1 of the same register indicates whether this signal has changed
state since the last reading.
Note: Whenever bit 5. of the Modem Status register changes state, an

interrupt is generated if the modem status interrupt is enabled.
-Data Carrier Detect (-DCD): When active, this signal indicates the
modem or data set detected a data carrier. This signal is an input
from the modem. Its status is reflected in bit 7 of the Modem Status
register. Bit 3 of the same register indicates whether the signal has
changed state since the last reading.
-Ring Indicate (-RI): When active, this signal indicates the modem or
data set detected a telephone ringing signal. This signal is an input
from the modem. Its status is reflected in bit 6 of the Modem Status
register. Bit 2 of the same register indicates whether the signal has
changed from active to inactive.
Note: Whenever bit 6 of the Modem Status register changes from 0

to 1, an interrupt is generated if the modem status interrupt is
enabled.
Serial Port 1-117

Output Signals
-Data Terminal Ready (-DTR): When active, this signal informs the
modem or data set that the controller is ready to communicate. This
signal can be made active by setting bit 0 of the Modem Control reg-
ister. It is inactive after a master reset operation.
-Request to Send (-RTS): When active, this signal informs the

modem or data set that the controller is ready to send data. It can be
made active by setting bit 1 of the Modem Control register. This
signal is inactive after a master reset operation.
-Output 1 (-OUT 1): User-designated output that can be made active

by setting bit 2 of the Modem Control register. -OUT 1 is inactive after
a master reset operation.
-Output 2 (-OUT 2): User-designated output that can be made active

by setting bit 3 of the Modem Control register. -OUT 2 is inactive after
a master reset operation. This signal controls interrupts to the
system.
1-118 Serial Port

Connector
The following figure shows the pin assignments for the serial port in a
communications environment when viewed from the rear of the
system unit.
1 13
roo0 0 0 0 0 0 0 0 0 0 0)
\000000000000.
14 25
Pin 110 Signal Name Pin 1/0 Signal Name
1 N/A Not Connected 14 N/A Not Connected

2 0 Transmit Data 15 N/A Not Connected
3 I Receive Data 16 N/A Not Connected
4 0 -Request to Send 17 N/A Not Connected
5 I -Clear to Send 18 N/A Not Connected
6 I -Data Set Ready 19 N/A Not Connected
7 N/A Signal Ground 20 0 -Data Terminal Ready
8 I -RLSD 21 N/A Not Connected
9 N/A Not Connected 22 I -Ring Indicate
11 N/A Tied to line 20 24 N/A Not Connected
13 N/A Not Connected
Figure 1-109. Serial Port Connector
The following are the specifications for the serial interface.
Function Condition
On Spacing condition (binary 0, positive voltage).
Off Marking condition (binary 1, negative voltage).
VoHage Function
Above + 15 V dc Invalid
+3to +15 V dc On
-3 to +3Vdc Invalid
-3 to -15V dc Off
Below -15 V dc Invalid
Figure 1-110. Serial Interface Specifications
Serial Port 1-119

Parallel Port
The parallel port allows the attachment of various devices that accept
8 bits of parallel data at standard TTL levels. The rear of the system
unit has a 25-pin, O-shell connector. This port is addressed as par-
allel port 1.
To allow the parallel port to receive data from external devices,

disable the output buffer by writing a 0 to bit 7 of the System Board
Control register.
Parallel Port
Enable .. Interrupt
Data
Bus
l..... Data
Output
Buffer 25-Pin bL Data
Wrap
Buffer
..
Connector
Control Control Wrap
---<
Output ~ and
Buffer Signal Input
Figure 1-111. Parallel Port Block Diagram
Port Registers
The following describe the registers used for this port in a parallel
printer application.
Data Latch, Hex 378: Writing to this address causes data to be stored
in the device data buffer. Reading this address returns the contents
of the buffer.
The output drivers for this data port will source 2.6 mA at a VOH of 2.4
V dc and sink 24 mA at a VOL of .5 V dc. Resistors (39 ohm) are in
series with the output drivers.
1-120 Parallel Port

Printer Controls, Hex 37A: Parallel port control signals are con-
trolled through this address and can be read by the microprocessor.
These signals are driven by open collector devices pulled up to + 5 V
dc through 4.7K Ohm resistors. The output drivers can sink 16 mA at
a VOL of .4 V dc.
Bit Function
7 Reserved
6 Reserved
5 Reserved
4 IRQ Enable
3 Select Input (Slct In)
2 -Initialize (-Init)
1 Auto FD XT
o Strobe
Figure 1-112. Printer Control Register
The following are bit definitions.
Bit 7-5 Reserved.

Bit 4 IRQ Enable-When set to 1, this bit allows an interrupt to
occur when -ACK changes from active to inactive.
Bit 3 Sict In-When set to 1, this bit selects the device.
Bit 2 -Init-When cleared to 0, this bit resets the device
(50-microsecond pulse, minimum).
Bit 1 Auto FD XT-When set to 1, this bit causes the device to line
feed after a line is printed.
Bit 0 Strobe-An active pulse, minimum of 0.5Ils, clocks data into
the device. Valid data must be present for a minimum of
0.51ls before and after the strobe pulse.
Parallel Port 1-121

Printer Status - Address 379: Parallel port status is stored at this
address to be read by the microprocessor. The following are bit defi-
nitions for this byte.
Bit Function
7 -Busy
6 -Acknowledge (-ACK)
5 Page End (PE)
4 Selected (Slct)
3 -Error
2 Reserved
1 Reserved
o Reserved
Figure 1-113. Printer Status Register
Bit 7 -Busy-This bit indicates the status of the device's 'busy'

signal. When the signal is active, this bit is a 0, and the
device cannot accept data. It is active during data entry,
while the device is offline, or while in an error state.
Bit 6 -ACK-This bit represents the current state of the device's
°
'-acknowledge'signal. A means the device has received
the character and is ready to accept another. Normally, this
signal is active for approximately 5 ~s before -BUSY goes
active.
Bit 5 PE-When set to 1, this bit indicates a printer has detected
the end of the paper.
Bit 4 Sict-When set to 1, this bit indicates the device is selected.
Bit 3 -Error-When cleared to 0, this bit indicates the device has
encountered an error condition.
Bits 2-0 Reserved.
1-122 Parallel Port

BUSY
~I
I
I
I
I I
I I
-ACK I ~----+I------------------------------
~_I_~
O.Sus Minimum
~~~oXimateIY i
If---"",~===---+-I -"£---+-....L.---i
Data ----~k I
I
i
I
I
>~-----
I I I
I I I
I I I
I I I
-STROBE ------------rl----~
!I~I
I II
I I
! I
Figure 1-114. Parallel Port Signal Timing
Parallel Port 1-123

Connector
The port has a 25-pin, D-shell connector at the rear of the system unit.
The following figure shows the signals and their pin assignments.
Typical printer input signals also are shown.
13 1
0 0 0 0 0 0 0 0 0 0 0 0
\ .000000000000.
OJ
25 14
Pin 1/0 Signal Name Pin 1/0 Signal Name
1 0 -Strobe 14 0 -Auto FD XT
2 1/0 DO 15 I -Error
3 1/0 D1 16 0 -Init
4 1/0 D2 17 0 -Slct In
5 1/0 D3 18 N/A Ground
10 I -ACK 23 N/A Ground
11 I Busy 24 N/A Ground
12 I PE 25 N/A Ground
13 I Sict
Figure 1-115. Parallel Port Connector
1-124 Parallel Port

Beeper
The beeper and its control ci rcuits and driver are on the system
board. The beeper drive circuit is capable of approximately 1/2 watt
of power. The control circuits allow the beeper to be driven three dif-
ferent ways:
1. A Direct Program Control register bit may be toggled to generate

a pulse train.
2. The clock input to the timer can be modulated with a program-
controlled 110 port bit.
3. The output from channel 2 of the timer may be programmed to
generate a waveform to the beeper.
Channel 2 (Tone generation for beeper)
Gate 2 Controlled by I/O Port Bit 1

Clock In 2 1.9318 MHz OSC
Clock Out 2 Used to drive beeper
Figure 1-116. Beeper Tone Generation
All three methods may be performed simultaneously. For more infor-

mation, see "System Timer" and "110 Ports" earlier in this section.
Earphone Connector
An earphone connector is provided at the rear of the system unit to
allow the user to disable the internal beeper (speaker) and listen to
the sound output through a set of earphones. The internal beeper is
disabled whenever a plug is inserted into this connector.
The connector will accept any 1/4-inch diameter audio plug. A

monophonic earphone with an impedance level of 15 to 35 ohms is
recommended. Some earphones with an impedance level as high as
100 ohms may also be acceptable. The drive level is fixed so that the
sound level will be directly related to the sensitivity of the earphones.
Earphones with 1/8-inch plugs may be used with adapter plugs.
System Board 1-125

Connectors
The following figures show the different types of system boards.
0 - - - - -.. . . fl
~----- m
m
iii]
DO
J7 m
12
84 g@]
MO
c:---+-------+
J4 (I]
m--+--~""-
13
1
m--t~r--- __
J9
00 o
mRRRRRRRRj
Ref. # Description ReI. # Description
1 Serial Connector 9 Earphone Connector

2 Parallel Connector 10 Keylock Connector
3 Diskette Drive Connector 11 80-pin 1/0 Connector
4 Math Coprocessor 12 Fixed Disk Connector
5 Microprocessor 13 Fan Connector
6 Optional 128K Memory 14 Power Supply Connector
7 POinting Device Connector 15 Display Connector
8 Keyboard Connector 16 Memory SIPs
Figure 1-117. System Board Connector Location
1-126 System Board

~--fl
~-m
t-+iit-- m
J6
J12
@]
A40
Ref. # Description Ref. # Description
1 Serial Connector 9 Earphone Connector

2 Parallel Connector 10 Keylock Connector
3 Diskette Drive Connector 11 aD-pin 1/0 Connector
4 Math Coprocessor 12 Fixed Disk Connector
5 Microprocessor 13 Fan Connector
6 Optional 128K Memory 14 Power Supply Connector
7 POinting Device Connector 15 Display Connector
8 Keyboard Connector 16 Memory SIPs
Figure 1-118. System Board Connector Location
System Board 1-127

The pin assignments for the power supply connector, J7, are as
follows. The pins are numbered 1 through 12 from the rear of the
system.
Connector Pin Assignments
J7 1 Power Good
2 Ground
3 +12V de
4 -12 V de
5 Ground
6 Ground
7 Ground
8 Ground
9 -5 V de
10 +5Vde
11 +5Vde
12 +5Vde
Figure 1-119. Power Supply Connector
The keyboard and pointing device connectors, J1 and J2, are six-pin,
90-degree printed circuit board (PCB) mounting, miniature DIN con-
nectors. For pin numbering, see the "Keyboard" section. The pin
assignments are as follows:
Pin Assignments
1 Keyboard Data
2 Not Connected
3 Ground
4 +5Vde
5 Keyboard Clock
6 Not Connected
Figure 1-120. Keyboard Connector and Pointing Device
1-128 System Board

Specifications
Size
• Length: 375 millimeters (14.7 inches)

• Depth: 319 millimeters (12.5 inches)
• Height: 384 millimeters (15.1 inches)
• Width: 241 millimeters (9.5 inches) base and 320 millimeters
(12.6 inches) total width.
Weight
• Monochrome Monitor Model 12.7 kilograms (28 pounds)

• Color Monitor Model 16.8 kilograms (37 pounds)
Power Cable
• Length: 1.8 meters (6 feet)
Environment
• Air Temperature
System On: 15°C to 32°C (60°F to 90°F)
System Off: 10°C to 43°C (50°F to 110°F)
• Wet Bulb Temperature
System On: 23°C (73°F)
System Off: 27°C (80°F)
System Board 1-129

• Humidity
System On: 8% to 80%
System Off: 20% to 80%
• Altitude
- Maximum altitude: 2133.6 meters (7000 feet)
Heat Output
• 683 British Thermal Units (BTUs) per hour
Noise Level
• 48 dBa average sound pressure at operator's position in the

operating mode.
• 47 dBa average sound pressure at the operator's position in the
idle mode.
Electrical
• Power: 240 VA
• Input
Nominal: 115 V ae 230 V ae
Minimum: 90 V ae 180 V ae
Maximum: 137 V ae 265 V ae
1-130 System Board

SECTION 2. Coprocessor
Description ........................................... 2-3

Programming Considerations ............................ 2-3
Hardware ~nterface .................................... 2-4
Coprocessor 2-1
Notes:
2-2 Coprocessor
Description
The Math Coprocessor (8087-2) enables the Type 8525 to perform
high-speed arithmetic functions, logarithmic functions, and trigono-
metric operations with extreme accuracy.
The 8087-2 coprocessor works in parallel with the microprocessor.

The paralleJ operation decreases operating time by allowing the
coprocessor to do mathematical calculations while the micro-
processor continues to do other functions.
The first five bits of every instruction's operation code for the
coprocessor are identical (binary 11011). When the microprocessor
and the coprocessor see this operation code, the microprocessor cal-
culates the address of any variables in memory, while the
coprocessor checks the instruction. The coprocessor takes the
memory address from the microprocessor if necessary. To gain
access to locations in memory, the coprocessor takes the local bus
from the microprocessor when the microprocessor finishes its current
instruction. When the coprocessor is finished with the memory
transfer, it returns the local bus to the microprocessor.
The coprocessor works with seven numeric data types divided into
the following three classes:
• Binary integers (3 types)

• Decimal integers (1 type)
• Real numbers (3 types).
Programming Considerations
The coprocessor extends the data types, registers, and instructions of
the microprocessor.
The coprocessor has eight 80-bit registers. This register space

allows constants and temporary results to be held in registers during
calculations, thus reducing memory access and improving speed as
well as bus availability. The register space can be used as a stack or
as a fixed register set. When used as a stack, only the top two stack
Coprocessor 2-3
elements are operated on. The figure below shows representations
of large and small numbers in each data type.
Significant
Digits
Data Type Bits (Decimal) Approximate Range (Decimal)
Word Integer 16 4 -32,768through +32,767
Short Integer 32 9 -2x109 through + 2x109
Long Integer 64 18 -9x1018 throllgh +9x10 18
Packed Decimal 80 18 -9 ..99 through +9.. 99 (18 digits)
Short Real' 32 6-7 8.43x10-37 through 3.37x1038
Long Real" 64 15-16 4. 19x10-3°7 through 1.67x10308
Temporary Real 80 19 3.4x1Q-4932 through 1.2x104932
, The Short Real and Long Real data types correspond to the single and
double-precision d~ta types.
Figure 2-1. Coprocessor Data Types
Hardware Interface
The coprocessor uses the same clock generator and system bus
interface components as the microprocessor. The microprocessor's
queue status lines (050 and 051) enable the coprocessor to obtain
and decode instructions simultaneously with the microprocessor.
The coprocessor's 'busy' signal (Busy) informs the microprocessor
that it is executing, and the coprocessor's Wait instruction (Wait for
Not Busy) forces the microprocessor to wait until the coprocessor has
finished executing.
When an incorrect instruction is sent to the coprocessor (for example,

divide by 0 or load a full register), the coprocessor can signal the
microprocessor with an interrupt on the NMI.
2-4 Coprocessor
There are two conditions that will disable the coprocessor interrupt to
the microprocessor:
1. The exception and the interrupt-enable bits of the control word

are set to 1's.
2. NMI is masked off.
Any program using the coprocessor's interrupt capability must

ensure that the second condition is never met during the operation of
the software, or an "endless wait" will occur. An endless wait has
the microprocessor waiting for BUSY to go inactive from the
coprocessor, while the coprocessor is waiting for the microprocessor
to interrupt.
Because a memory parity error may also cause an NMI, the program
should check the coprocessor status for an exception condition. If a
coprocessor exception condition is not found, control is passed to the
normal NMI handler. If an 8087 exception condition is found, the
program clears the exception by executing the FNSAVE or the
FNCLEX instruction, and the exception can be identified and acted
upon.
The NMI and the coprocessor's interrupt are tied to the NMI line
through the NMI interrupt logic.
110
Interrupt Gate INT INT 8086
Array NMI NMI CPU
r---
NMI .-=:... ClK
RQ/GTO
RQ/GT1
QSO QSl TEST A/DO - A/D15
A16 - A19
+ + t
Memory
CPU
Gate
Array
CPU
RQ/GT
ClK
NPU
... QSO QSl BUSY
RQ/GTO
RQ/GT
PARITY ---<
- RQ/GTl
ClK
INT
8087
CPU
r---
Figure 2-2. Coprocessor Interconnection
Coprocessor 2-5
Notes:
2-6 Coprocessor
SECTION 3. Power Supply
Description ........................................... 3-3

Input and Output Power ................................. 3-4
Output Protection ...................................... 3-5
Power-Good Signal .................................... 3-5
Connectors ........................................... 3-6
Power Supply 3-1

Notes:
3-2 Power Supply

Description
The system dc power supply for the color monitor is a single-phase,
113-watt, six-voltage level supply. It is internal to the display and
supplies power for the system unit, the display, its options, and the
keyboard. The supply provides 7.0 A of +5 V dc, 1.7 A of + 12 V dc,
100 rnA of -5 V dc, and 250 rnA of -12 V dc to the system board. In
addition, 450 rnA of 115 V dc and 220 rnA of + 12 V dc are provided to
the display assembly. All power levels to the system board are moni-
tored with undervoltage and overcurrent protection.
The dc power supply for the monochrome display is a single-phase,

90-watt, five voltage level power supply. The power to the system
board is identical to that of the color display assembly. In addition,
800 rnA of + 39 V dc is provided to the display assembly.
The power supply handles either 115 V ac or 220/240 V ac inputs by

means of a mechanical switch on the rear of the system unit. The
input is protected by an internal fuse. If dc overcurrent or under-
voltage conditions exist, the supply automatically shuts down until the
condition is corrected.
The system board and storage devices take approximately 4 A of +5

V dc, thus allowing approximately 3 A of + 5 V dc for the adapters in
the system expansion slots. The -5 V dc level is used for adapters.
The + 12 V dc power level powers the internal diskette drives and the
fixed disk drive. The + 12 V dc and -12 V dc are used for powering
the Electronic Industries Association (EIA) drivers for the serial port.
All four power levels are bused across the two system expansion
slots.
Power Supply 3-3

Input and Output Power
The nominal power requirements and voltages are listed in the fol-
lowing tables.
Nominal (V ae) Minimum (V ae) Maximum (V ae) Maximum Current
115 90 137 2.0 A

230 180 265 1.0 A
Figure 3-1. Vae Input Requirements
Nominal Load Current (A) Regulation Ripple

(V de) Min Max Tolerance (mV pop)
+5Vde 1.5 7.0 +5% to -3% 100

-5Vde 0.0 0.11 +10% to-8% 50
+ 12 V de 0.12 1.7 +5% to -3% 120
-12 V de 0.015 0.25 +10% to -8% 120
Figure 3-2. V de Output
3-4 Power Supply

Output Protection
The sense levels of the dc outputs are:
UndervoHage
Output (V de) Minimum (V de)
+5 +3.2
-5 -2.4
+12 +10.5
-12 -8.6
Figure 3-3. Output Protection
Power-Good Signal
The power supply provides a 'power good' signal to reset the system
logic, to indicate proper operation of the power supply, and to give
advance warning when the power is turned off.
The signal has a TTL-compatible active level of 2.4 to 5.25 V dc during

normal operation, or an inactive level of 0.0 to 0.4 V dc. The signal is
inactive if an undervoltage condition' occurs, or during the power-on
and power-off sequence. The 'power good' signal has a turn-on delay
that is at least 100 ms but no greater than 500 ms. This line can sink
2 rnA or source 100 IlA.
Power Supply 3-5

Connectors
The power supply attaches to the system board through a 12-pin con-
nector. The pin numbering and signal assignments are shown below.
Connector Pin Assignments
J7 1 Power Good
2 Ground
3 + 12 V de
4 -12Vde
S Ground
6 Ground
7 Ground
8 Ground
9 -S V de
10 +SVde
11 +SVde
12 +SVde
Figure 3-4. Power Supply Connector
3-6 Power Supply

SECTION 4. Keyboard
Description ........................................... 4-3

Sequence Key-Code Scanning ..................... 4-3
Keyboard Buffer ................................ 4-3
Keys ......................................... 4-4
Power-on Routine .................................. 4-4
Power-on Reset ................................. 4-4
Basic Assurance Test ............................ 4-4
Clock and Data Signals .............................. 4-5
Data Stream ................................... 4-6
Data Output .................................... 4-6
Commands ........................................... 4-7
Scan Codes .......................................... 4-8
84/85-Key Keyboard ............................... 4-11
Encoding ........................................ 4-11
Character Codes ............................... 4-11
Extended Functions ............................. 4-19
Shift States ................................... 4-21
Special Handling ............................... 4-23
Other Characteristics ........................... 4-24
Layouts ......................................... 4-25
Arabic ....................................... 4-26
Belgian ...................................... 4-27
Canadian French ............................... 4-28
Danish ....................................... 4-29
Dutch ........................................ 4-30
French ....................................... 4-31
German ...................................... 4-32
Israel i ....................................... 4-33
Italian ....................................... 4-34
Latin American ................................ 4-35
Norwegian .................................... 4-36
Portuguese ................................... 4-37
Spanish ...................................... 4-38
Swedish ...................................... 4-39
Swiss ........................................ 4-40
U.K. English ................................... 4-41
U.S. English ................................... 4-42
Canadian French ............................... 4-43
Keyboard 4-1
Latin American ................................ 4-44
U.S. English ................................... 4-45
Cables and Connectors ................................ 4-46
Specifications ........................................ 4-47
Power Requirements ............................ 4-47
Size ......................................... 4-47
Weight ....................................... 4-47
4-2 Keyboard
Description
The PC Enhanced keyboard has 101 keys and the Space Saving key-
board has 84 keys (102 or 85 in countries outside of the U.S.A.). The
84-key keyboard looks the same as the 101-key keyboard without the
numeric keypad. It has the same scan codes available as the 101-key
keyboard.
When the 84-key keyboard is in Num Lock state, the numeric keypad
is overlaid on the inboard keys. The NumLk key for this keyboard
(Shift + ScrLk) toggles the overlay on or off. The overlay character is
printed on the lower right keytop of the keys that are affected. At
system power-on, the keyboard monitors the signals on the 'clock'
and 'data' lines and establishes its line protocol.
Sequence Key-Code Scanning
The keyboard detects each key pressed, and sends each scan code in
the sequence pressed. When not serviced by the system, the key-
board stores the scan codes in its buffer.
Keyboard Buffer
A 17-byte first-in-first-out (FIFO) buffer in the keyboard stores the

scan codes until the system is ready to receive them.
A buffer-overrun condition occurs when more than 16 bytes are

placed in the keyboard buffer. An overrun code replaces the 17th
byte. If more keys are pressed while the buffer is full, the additional
keystrokes are lost.
When the keyboard is allowed to send data, the bytes in the buffer are
sent as in normal operation, and any additional keystrokes are sent.
Response codes do not occupy a buffer position.
When keystrokes generate a multiple-byte sequence, the entire

sequence must fit into the available buffer space; otherwise, a buffer-
overrun condition occurs.
Keyboard 4-3
Keys
With the exception of the Pause key, all keys are make/break. The
make scan code of a key is sent to the keyboard controller when the
key is pressed. When the key is released, its break scan code is sent.
Additionally, except for the Pause key, all keys are typematic. When
a key is pressed and held down, the keyboard sends the make code
for that key, delays 500 ms ±20%, and begins sending a make code
for that key at a rate of 10.9 characters per second ±20%.
If two or more keys are held down, only the last key pressed repeats
at the typematic rate. Typematic operation stops when the last key
pressed is released, even if other keys are still held down. If a key is
pressed and held down while keyboard transmission is inhibited, only
the first make code is stored in the buffer. This prevents buffer over-
flow as a result of typematic action.
Power-on Routine
Power-on Reset (POR) and the Basic Assurance Test (BAT) take
place when power is first applied to the keyboard.
Power-on Reset
The keyboard logic generates a 'power-on reset' signal when power

is first applied to the keyboard. POR occurs during 150 ms to 2.0
seconds from the time power is first applied to the keyboard.
Basic Assurance Test
The BAT consists of a keyboard processor test, a checksum of ROM,

and a RAM test. During the BAT, activity on the 'clock' and 'data'
lines is ignored. The BAT takes from 300 to 500 ms. This is in addi-
tion to the time required by the POR.
Upon satisfactory completion of the BAT, a completion code (hex AA)

is sent to the system, and keyboard scanning begins. If a BAT failure
occurs, the keyboard sends an error code to the system. The key-
board is then disabled pending command input. Completion codes
are sent 600 ms to 2.5 seconds after POR, and between 300 and 500
ms after a Reset command is acknowledged.
4-4 Keyboard
Following a successful POR, the system sets the line protocol to Scan
Set 1.
Clock and Data Signals
The keyboard and system communicate over the 'clock' and 'data'
lines. The source of each of these lines is an open-collector device
on the keyboard that allows either the keyboard or the system to
force a signal inactive. When no communication is occurring, the
'clock' line is active. The state of the 'data' line is held inactive by
the keyboard.
An inactive signal is between 0.0 and +0.7 volts. A signal at the

inactive level is a logical O. An active signal is between + 2.4 and
+ 5.5 volts. A signal at the active level is a logical 1. Voltages are
measured between a signal source and the dc ground.
The keyboard 'clock' line provides the clocking signals used to clock
serial data from the keyboard. If the system forces the 'clock' line
inactive, keyboard transmission is inhibited.
When the keyboard sends data to the system, it generates the 'clock'
signal to time the data. The system can prevent the keyboard from
sending data by forcing the 'clock' line inactive, or by holding the
'data' line inactive.
During the BAT, the keyboard allows the 'clock' and 'data' lines to go
active.
Keyboard 4-5
Data Stream
Data transmissions from the keyboard consist of an 11-bit data

stream sent serially over the 'data' line. The following table shows
the data stream.
Bit Function
1 Start Bit (Always 0)

2 Data Bit 0 (Least Significant)
3 Data Bit 1
4 Data Bit 2
5 Data Bit 3
6 Data Bit 4
7 Data Bit 5
8 Data Bit 6
9 Data Bit 7 (Most Significant)
10 Parity Bit (Odd Parity)
11 Stop Bit (Always 1)
Figure 4-1. Keyboard Data Stream
Data Output
When the keyboard is ready to send data, it first checks the status of
the 'clock' and 'data' lines. When the 'clock' line is inactive (key-
board inhibit). the keyboard stores the data in its buffer. When the
'data' line is inactive and the 'clock' line is active (system request to
send), the keyboard stores the data in its buffer and accepts the
system input.
If both lines are active, the keyboard sends the data stream. During
transmission, the keyboard monitors the 'clock' line. If the line goes
inactive before the parity bit is sent, the keyboard stores the data in
its buffer and returns the 'clock' and 'data' lines to active and then
waits on the system. If the parity bit has been sent, the keyboard
completes the transmission.
4-6 Keyboard
Commands
Reset (Hex FF): The system issues a Reset command to initiate a
keyboard reset and an internal self-test. The keyboard acknowledges
(ACK) receiving the command, but before executing the reset, the
keyboard waits for the system to accept the ACK. If the system
accepts the ACK, it pulses the clock and data lines with a 500-ms
active pulse. The keyboard remains in a reset mode until the clock
and data lines are pulsed or until another command is sent.
The following describes the commands that the keyboard sends to the
system, and shows their hexadecimal values.
Command Hex Value
BAT Completion Code AA

BAT Failure Code FC
Key Detection Error/Overrun FF
Figure 4-2. Commands from the Keyboard
BAT Completion Code (Hex AA): Following satisfactory completion

of the BAT, the keyboard sends hex AA. Any other code indicates a
failure of the keyboard.
BAT Failure Code (Hex FC): If a BAT failure occurs, the keyboard
sends this code, discontinues scanning, and waits for a system
response or reset.
Key Detection Error (Hex FF): The keyboard sends a key detection
error character (hex FF) if conditions in the keyboard make it impos-
sible to identify a switch closure.
Overrun (Hex FF): An overrun character (hex FF) is placed in the

keyboard buffer and replaces the last code when the buffer capacity
has been exceeded. The code is sent to the system when it reaches
the top of the buffer queue.
Keyboard 4-7
Scan Codes
Each key is assigned a make and break scan code and, in some
cases, an extra set of codes to generate artificial shift states in the
system. The typematic scan codes are identical to the make scan
code for each key.
The following keys send the codes shown, regardless of the shifted
states of the keyboard. Refer to the keyboard layout to determine the
character associated with each key.
4-8 Keyboard
Key No. Make Break Key No. Make Break
1 29 A9 47 20 AD
2 02 82 48 2E AE
3 03 83 49 2F AF
4 04 84 50 30 BO
5 05 85 51 31 B1
6 06 86 52 • 32 B2
7 07 87 53 33 B3
8" 08 88 54' 34 B4
9' 09 89 55 35 B5
10 " OA 8A 57 36 B6
11 OB 8B 58 10 90
12 " OC 8C 60 38 B8
13 • 00 80 61 39 B9
15 OE 8E 62 EO 38 EO B8
16 OF 8F 64 EO 10 E090
17 10 90 90 45 C5
18 11 91 91 47 C7
19 12 92 92 4B CB
20 13 93 93 4F CF
21 14 94 96 48 C8
22 15 95 97 4C CC
23 • 16 96 98 50 DO
24 • 17 97 99 52 02
25 " 18 98 100 37 B7
26 19 99 101 49 C9
27 1A 9A 102 40 CO
28 1B 9B 103 51 01
29 + 2B AB 104 53 03
30 3A BA 105 4A CA
31 1E 9E 106 4E CE
32 1F 9F 108 EO 1C E09C
33 20 AO 110 01 81
34 21 A1 112 3B BB
35 22 A2 113 3C BC
36 23 A3 114 3D BO
37 " 24 A4 115 3E BE
38 " 25 A5 116 3F BF
39 " 26 A6 117 40 CO
40 • 27 A7 118 41 C1
41 28 A8 119 42 C2
42 + 2B AB 120 43 C3
43' 1C 9C 121 44 C4
44 2A AA 122 57 07
45 + 56 06 123 58 08
46 2C AC 125 46 C6
+ Key 29 on U.S.A. keyboard only, keys 42 and 45 on all but U.S.A. keyboard.
* See "84/85-Key Keyboard" in this section.
Figure 4-3. Scan Codes (Part 1 of 4)
Keyboard 4-9
The remaining keys send a series of codes depending on the state of
various shift keys (Ctrl, Alt, and Shift), and the state of NumLk (On or
Off). Because the base scan code is identical to that of another key,
an extra code (hex EO) is added to the base code to make it unique.
The following charts show the make/break code using the left shift
key. If the right shift key is used, substitute its make/break for that of
the left shift key.
Base Case, or
Key Shift + NumLk Shift Case NumLk
75 EO 52/EO 02 EO AA EO 52/EO 02 EO 2A EO 2A EO 52/EO 02 EO AA

79 EO 46/EO C6 EO AA EO 46/EO C6 EO 2A EO 2A EO 46/EO C6 EO AA
81 EO 4F/EO CF EO AA EO 4F/EO CF EO 2A EO 2A EO 4F/EO CF EO AA
86 EO 51 lEO 01 EO AA EO 51/EO 01 EO 2A EO 2A EO 51/EO 01 EO AA
89 EO 40/EO CO EO AA EO 40/EO CO EO 2A EO 2A EO 40/EO CO EO AA
Key No. Base Case Shift Case
95 EO 35/EO 65 EO AA EO 35/EO 65 EO 2A
Key No. Base Case Shift or Ctrl Case All Case
124 EO 2A EO 37/EO 67 EO EO 37/EO 67 54/04

AA
126' E11D 45 E190 C5 EO 46 EO C6
• All associated scan codes are sent on the make of the key.
4-10 Keyboard
84/85-Key Keyboard
The ScrLk key on this keyboard sends the scan code of hex 45 C5
when in the shift case and is used to toggle the Num Lock state. The
following are the key numbers and scan codes for the affected keys
on the 84-key and 85-key keyboards while in the Num Lock state.
Key No. Make Break Key No. Make Break
8 47 C7 25 40 CO
9 48 C8 37 4F CF
10 49 C9 38 50 DO
12 4A CA 39 51 01
13 4E CE 40 37 B7
23 4B CB 52 52 02
24 4C CC 54 53 03
Figure 4-7. Scan Codes for 84/85 Numeric Keypad
Encoding
The keyboard routine, provided in ROM BIOS, converts the keyboard

scan codes into Extended ASCII. The extended ASCII codes returned
by the BIOS routine are mapped to the U.S. English keyboard layout.
Operating systems can make provisions for alternate keyboard
layouts by providing another keyboard routine. This section dis-
cusses only the ROM routine.
Extended ASCII encompasses 1-byte character codes, with possible

values of 0 to 255; an extended code for certain extended keyboard
functions; and functions handled within the keyboard routine or
through interrupts.
Character Codes
The character codes are passed through the BIOS keyboard routine
to the system or application program. In the following figures, "-1"
indicates the combination is suppressed in the keyboard routine. The
codes are returned in the AL register. See the "Characters and Key-
strokes" section in this manual for the exact codes.
Keyboard 4-11
•.:... :!!
co
N
; B 8888 8888 8888 888

~
!XI
"T1
10"
; B 8888
~
8888 8888 888
Key Base Case Uppercase Ctrl All
1
2
,
1
-
!
-1
-1
(*)
(*)
3 2 @ Nul(OOO) (*) (*)
4 3 # -1 (*)
5 4 $ -1 (*)
6 5 % -1 (*)
7 6 A R8(030) (*)
8 7 & -1 (*)
9 8 * -1 (*)
10 9 ( -1 (*)
11 0 ) -1 (*)
12 - U8(031) (*)
13 = "+ -1 (*)
15 Backspace Backspace Del(127) (*)
(008) (008)
16 -+1 (009) I~(*) (*) (*)
17 q Q DC1(017) (*)
18 w W ETB(023) (*)
19 e E ENQ(005) (*)
20 r R DC2(018) (*)
21 t T DC4(020) (*)
22 Y y EM(025) (*)
23 u U NAK(021) (*)
24 i I HT(009) (*)
25 0 0 81(015) (*)
26 P P DLE(016) (*)
27 [ { Esc(027) (*)
28 1 } G8(029) (*)
I
29 \ I F8(028) (*)
30 Caps -1 -1 -1 -1
Lock
31 a A 80H(001) (*)
32 s 8 DC3(019) (*)
33 d D EOT(004) (*)
34 f F ACK(006) (*)
35 9 G BEL(007) (*)
36 h H B8(008) (*)
37 j J LF(010) (*)
38 k K VT(011) (*)
39 I L FF(012) (*)
40 ; : -1 (*)
,
41 " -1 (*)
43 CR CR LF(010) (*)
Note:
(*) Refer to "Extended Functions" in this section.
Figure 4-12 (Part 1 of 3). Character Codes
4-16 Keyboard
Key Base Case Uppercase etr. Aft
44 Shift -1 -1 -1 -1
(Left)
46 z Z SUB(026) (*)
47 x X CAN(024) (*)
48 c C ETX(003) (*)
49 v V SYN(022) (*)
50 b B STX(002) (*)
51 n N 50(014) (*)
52 m M CR(013) (*)
53 < -1 (*)
54 > -1 (*)
55 I ? -1 (*)
57 Shift -1 -1 -1 -1
(Right)
58 Ctrl -1 -1 -1 -1
(Left)
60AIt -1 -1 -1 -1
(Left)
61 Space Space Space Space
62Alt -1 -1 -1 -1
(Right)
64 Ctrl -1 -1 -1 -1
(Right)
90Num -1 -1 -1 -1
Lock
95 (*) (*)
100 (*) (*)
105 (*) (*)
106 + + (*) (*)
108 Enter Enter LF(010) (*)
Notes:
(*) Refer to "Extended Functions" in this section.
Keyboard 4-17
Key Base Case Uppercase Ctrl All
110 Esc Esc Esc (*)

112 Null (') Null (') Null (') Null(')
115 Null (*) Null (') Null (*) Null(*)
116 Null (') Null (') Null (*) Null(')
118 Null (') Null (*) Null (') Null(')
119 Null (') Null (*) Null (') Null(')
121 Null (') Null (*) Null (') Null(*)
122 Null (*) Null (') Null (') Null(')
123 Null (*) Null (') Null (*) Null(*)
125 Scroll -1 84/85-key -1 -1
Lock NumLk
126 Pause(*') Pause(") Break(") Pause(")
Notes:
(') Refer to "Extended Functions" in this section.
(") Refer to "Special Handling" in this section.
4-18 Keyboard
The following figure lists keys that have meaning only in Num Lock,
Shift, or Ctrl states. These keys are only available on 101- and
102-key keyboards.
Num
Key Lock Base Case AR etrl
91 7 Home (0) -1 Clear Screen

92 4 +-(0) -1 Reverse Word(O)
93 1 End (0) -1 Erase to EOL(O)
96 8 W) -1 (*)
97 5 (0) -1 (0)
98 2 !(*) -1 (0)
99 0 Ins -1 (0)
101 9 PgUp (0) -1 Top of Text
and Home
102 6 -+(0) -1 Advance Word
(*)
103 3 PgDn -1 Erase to EOS
(0) (0)
104 Del (0,.0) (00) (00)
105 SysRq -1 -1
106 + + (0) -1 -1
Notes:
(0) Refer to "Extended Functions" in this section.
(00) Refer to "Special Handling" in this section.
Figure 4-13. Special Character Codes
Extended Functions
For certain functions that cannot be represented by a standard ASCII

code, an extended code is used. A character code of 00 (null) is
returned in AL. This indicates that the system or application program
should examine a second code, which will indicate the actual func-
tion. Usually, but not always, this second code is the scan code of the
primary key that was pressed. This code is returned in AH.
Keyboard 4-19
The following figure is a list of the extended codes and their func-
tions.
Second
Code Function
1 Alt Esc
3 Nul Character
14 Alt Backspace
15 I+- (Back-tab)
16-25 Alt Q, W, E, R, T, Y, U, I, 0, P
26-28 Alt [1 ......
30-38 Alt A, S, D, F, G, H, J, K, l
39-41 Alt ; , ,
43 Alt \
44-50 Alt Z, X, C, V, B, N, M
51-53 Alt , . I
55 Alt Keypad·
59-68 F1 to F10 Function Keys (Base Case)
71 Home
72 t (Cursor Up)
73 Page Up
74 Alt Keypad-
75 <- (Cursor left)
76 Center Cursor
77 .... (Cursor Right)
78 Alt Keypad +
79 End
80 J (Cursor Down)
81 Page Down
82 Ins (Insert)
83 Del (Delete)
84-93 Shift F1 to F10
94-103 Ctrl F1 to F10
104-113 Alt F1 to F10
114 Ctrl PrtSc (StartlStopEcho to Printer)
115 Ctrl <- (Reverse Word)
116 Ctrl .... (Advance Word)
117 Ctrl End (Erase to End of Line-EOl)
118 Ctrl PgDn (Erase to End of Screen-EOS)
119 Ctrl Home (Clear Screen and Home)
120-131 Alt 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, -, = Keys 2-13
132 Ctrl PgUp (Top 25 Lines of Text and Cursor Home)
133-134 F11, F12
135-136 Shift F11, F12
137-138 Ctrl F11, F12
139-140 Alt F11, F12
141 Ctrl Up/8
142 Ctrl Keypad -
143 Ctrl Keypad 5
144 Ctrl Keypad
145 Ctrl Down/2
146 Ctrllns/O
147 Ctrl Dell.
148 Ctrl Tab
Figure 4-14 (Part 1 of 2). Keyboard Extended Functions
4-20 Keyboard
Second
Code Function
147 Gtrl Dell.
148 Gtrl Tab
149 Gtrl Keypad /
150 Gtrl Keypad'
151 Alt Home
152 Alt Up
153 Alt Page Up
155 Alt Left
157 Alt Right
159 Alt End
160 Alt Down
161 Alt Page Down
162 Alt Insert
163 Alt Delete
164 Alt Keypad /
165 Alt Tab
166 Alt Enter
Figure 4-12 (Part 2 of 2). Keyboard Extended Functions
Shift Stales
Most shift states are handled within the keyboard routine, and are not
apparent to the system or application program. In any case, the
current status of active shift states is available by calling an entry
point in the BIOS keyboard routine. The following keys result in
altered shift states:
Shift: This key temporarily shifts keys 1 through 13, 16 through 29, 31
through 41, and 46 through 55, to uppercase (base case if in
GapsLock state). Also, the Shift key temporarily reverses the
NumLock or non-NumLock state of keys 91 through 93, 96, 98, 99, and
101 through 104 on a 101- or 102-key keyboard. If in NumLock state,
the Shift key temporarily invokes the cursor functions of keys 8-10, 12,
13,23-25,37-40,52 and 54 on an 84- or 85-key keyboard.
elrl: This key temporarily shifts keys 3,7, 12, 15 through 29,31
through 39, 43, 46 through 52, 75 through 89, 91 through 93, 95 through
108, 112 through 124 and 126 to the Gtrl state. The Gtrl key is also
used with the Alt and Del keys to cause the system-reset function,
with the Scroll Lock (ScrLk) key to cause the break function, and with
the Pause/Break key to cause the pause function. The system-reset,
break, and pause functions are described under "Special Handling"
later in this section.
Keyboard 4-21
Alt: This key temporarily shifts keys 1 through 29, 31 through 43, 46
through 55, 75 through 89, 95, 100, and 105 through 124 to the Alt
state. The Alt key is also used with the Gtrl and Del keys to cause a
system reset.
The Alt key also allows the user to enter any character code from 1 to
255. The user holds down the Alt key and types the decimal value of
the desired characters on the numeric keypad. The Alt key is then
released. If the number is greater than 255, a modu10-256 value is
used. This value is interpreted as a character code and is sent
through the keyboard routine to the system or application program.
Alt is handled in the keyboard routine.
CapsLock: This key shifts keys 17 through 26, 31 through 39, and 46
through 52 to uppercase. When the Gaps Lock key is pressed again, it
reverses the action. GapsLock is handled in the keyboard routine.
Scroll Lock (ScrLk): When interpreted by appropriate application pro-

grams, this key indicates that the cursor-control keys cause win-
dowing over the text rather than moving the cursor. When the ScrlLk
key is pressed again, it reverses the action. The keyboard routine
simply records the current shift state of the ScrLk key. It is the
responsibility of the application program to perform the function.
NumLock (NumLk): For the 101-key keyboard, this key shifts keys 91
through 93, 96 through 99, and 101 through 104 to uppercase. When
NumLk is pressed again, it reverses the action.
For the 84-key keyboard, it shifts keys 8 through 10, 12 and 13, 37
through 40, 23 through 25, and 52 through 54. The NumLock for this
keyboard is Shift plus the ScrLck key.
NumLock for both keyboards is handled by the keyboard routine.
Shift Key Priorities and Combinations: If combinations of the Alt,

Gtrl, and Shift keys are pressed and only one is valid, the priority is
as follows: Alt key first, Gtrl key second, and Shift key third. The only
valid combination is Alt and Gtrl, which is used in the system-reset
function.
4-22 Keyboard
Special Handling
System Reset: The combination of Alt, Ctrl, and Delete keys results
in the keyboard routine that starts a system reset or restart. System
reset is handled by BIOS.
Break: The combination of the Ctrl and Pause/Break keys results in

the keyboard routine signaling interrupt hex 1B. The extended char-
acters (AL) = hex 00, and (AH) = hex 00 are also returned.
Pause: The Pause key causes the keyboard interrupt routine to loop,
waiting for any character or function key to be pressed. This provides
a method of temporarily suspending an operation, such as listing or
printing, and then resuming the operation. The method is not
apparent to either the system or the application program. The key-
stroke used to resume operation is discarded. Pause is handled in
the keyboard routine.
Print Screen: The Print Screen key results in an interrupt invoking

the print-screen routine. This routine works in the alphanumeric or
graphics mode, with unrecognizable characters printing as blanks.
System Request: When the System Request (Alt + Print Screen) key
is pressed, a hex 8500 is placed in AX, and an interrupt hex 15 is exe-
cuted. When the key is released, a hex 8501 is placed in AX, and
another interrupt hex 15 is executed. If an application is to use
System Request, the following steps must be performed:
Save the previous address.

Overlay interrupt vector hex 15.
Check AH for a value of hex 85:
If yes, process may begin.
If no, go to previous address.
The application program preserves the value in all registers, except

AX, upon return. System Request is handled in the keyboard routine.
Keyboard 4-23
Other Characteristics
The keyboard routine does its own buffering (16 bytes). If a key is
pressed when the buffer is full, that key is ignored and the beeper
sounds.
The keyboard routine also suppresses the typematic action of the fol-
lowing keys: Ctrl, Shift, Alt, Num Lock (or NumLk), Scroll Lock (or
ScrLk), Caps Lock, and Ins (or Insert).
During each interrupt hex 09 from the keyboard, an interrupt hex 15,
function (AH) = hex 4F, is generated by the BIOS after the scan code
is read from the keyboard adapter. The scan code is passed in the
AL register with the carry flag set. This allows an operating system
to intercept each scan code before it is handled by the interrupt hex
09 routine, and to change or act on the scan code. If the carry flag is
changed to 0 on return from interrupt hex 15, the scan code is ignored
by interrupt hex 09.
4-24 Keyboard
Layouts
The 101/102 keyboard is available in the following 17 layouts:
• Arabic
• Belgian
• Canadian French
• Danish
• Dutch
• French
• German
• Israeli
• Italian
• Latin American
• Norwegian
• Portuguese
• Spanish
• Swedish
• Swiss
• U.K. English
• U.S. English
The 84/85-key keyboard is available in the following three layouts:
• Canadian French
• Latin American
• U.S. English
The layouts are shown in the above order on the following pages.
The characters normally found on the front face of the keybuttons are
shown on the lower right corner of the keys in the layouts.
Keyboard 4-25
"
~
0" > IWm
o
...
I» < l' H_ t Lock /
* -
Q.
Tab New
line a End i 7V .,.8A 99
Hollll! Pg l.\l
+
ClIps
Lork
4 ~ 56 61
-+
3,
4-
1 )
.0- End +2 " PgIJn
Enter
(trl o.
Insert Del
Page Nun -
Insert IiDIII!
Up lock I *
IJI!lete End
Page 7 .,.8 9
Down HIl1Ie PgIP
+
..
4 5 6
-+
1 2 3
End ... Pg Il1
Enter
0
Ins Del
..,.
N
I
011 [E<MP) [F1 IF2 IF3 IF4

1fs IF6 I~ 1
8
]
[F9 IF10 IF11 IF12
1
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CD
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0
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.-J
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,
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Ins.r lsuppr
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+
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+
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Ende ... 8; Id
Enter
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Elntg Entt
Page ttJm
/ -
Insert Home Up lock
*
Page 7 8 9
Delete End Down I'IIIne ... Po lb.
+
4
.- 5
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6
1 2 3
End ... l Po il1
Enter
0
Ins Del
.
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w
w
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Ins .~ ;/ -.
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z
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0 Insert Horne / -
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Up lock
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.-J Down Horne Pg Up
+
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2 3
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Enter
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7 .,.8
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Insert Home
L\l lock x -
~ 7 .,.8 9
Enter Page
Delete End
.-J Down Home PgL\l
+
Caps
lock .
4 5 6
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Cables and Connectors
The keyboard cable connects to the system with a 6-pin miniature DIN
connector and to the keyboard with a 6-position connector. The fol-
lowing table shows the pin configuration and signal assignments.
6
4
FEDCBA
DIN Connector Connector

Pins Signal Name Pins
1 +KBD DATA B
2 Not Connected F
3 Ground C
4 +5.0V dc E
5 +KBDCLK D
6 Not Connected A
Shield Frame Ground Shield
Figure 4-15. Keyboard Cable Connectors
4-46 Keyboard
Specifications
The specifications for the keyboards are:
Power Requirements
• +5 V-dc ± 10%
• Current cannot exceed 275 mAo
Size
• Length: 492 millimeters (19.4 inches), 101-key
• Length: 406 millimeters (16.0 inches), 84-key
• Depth: 210 millimeters (8.3 inches), 101-key
• Depth: 190 millimeters (7.5 inches), 84-key
• Height: 58 millimeters (2.3 inches), legs extended
Weight
• 2.25 kilograms (5.0 pounds), 101-key

• 1.90 kilograms (4.2 pounds), 84-key
Keyboard 4-47
Notes:
4-48 Keyboard
SECTION 5. System BIOS
System BIOS Usage .................................... 5-3

Parameter Passing .............................. 5-3
Hardware Interrupts .................................... 5-4
Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4
Vectors with Special Meanings ..................... 5-5
Interrupt Interface Listing ............................... 5-10
Interrupt 02H - Non-Maskable Interrupt Routine .......... 5-10
Interrupt 05H - Print Screen .......................... 5-10
Interrupt 08H - System Timer ........................ 5-11
Interrupt 10H - Video ............................... 5-13
Interrupt 11 H - Equipment Determination ............... 5-28
Interrupt 12H - Memory Size Determination ............. 5-29
Interrupt 13H - Diskette ............................. 5-30
Interrupt 13H - Fixed Disk ......................... 5-36.1
Interrupt 14H - Asynchronous Communications .......... 5-37
Interrupt 15H - System Services ...................... 5-42
Interrupt 17H - Printer .............................. 5-53
Interrupt 19H - Bootstrap Loader ...................... 5-54
Interrupt 1AH - System and Time-ot-Day Clock Services '" 5-55
BIOS Data Area and Locations .......................... 5-56
Extended BIOS Data Area .............................. 5-61
ROM Tables ......................................... 5-62
Fixed Disk Parameter Table ......................... 5-62
Asynchronous Baud Rate Initialization Table ............ 5-64
Diskette Parameter Table ........................... 5-64
Model Byte .......................................... 5-65
System BIOS 5-1

Notes:
5-2 System BIOS

System BIOS Usage
The basic inputloutput system (BIOS) resides in ROM on the system
board and provides device-level control for the major 1/0 devices in
the system. Additional ROM modules may be located on adapters to
provide device-level control for that adapter. BIOS routines enable
the assembler language programmer to perform block or character-
level 1/0 operations without concern for device address and operating
characteristics. System services, such as memory size determi-
nation, are provided by the BIOS.
The goal of BIOS is to provide an operational interface to the system

and relieve the programmer of the concern about the characteristics
of hardware devices. The BIOS interface insulates the user from the
hardware, allowing new devices to be added to the system, yet
retaining the BIOS level interface to the device. In this manner, hard-
ware modifications and enhancements are transparent to user pro-
grams.
The IBM Personal Computer Macro Assembler manual and the IBM
Personal Computer Disk Operating System (~OS) manual provide
useful programming information related to this section. A description
of the BIOS interface is given in this section.
Access to BIOS is through the 8086 software interrupts. The software

interrupts hex 10 through 1A each access a different BIOS routine.
For example, to determine the amount of memory available in the
system,
INT 12H
invokes the BIOS routine for determining memory size and returns
the value to the caller.
Parameter Passing
All parameters passed to and from the BIOS routines go through the
microprocessor registers. The description of each BIOS function
shows the registers used on the Call and the Return. For the memory
size example, no parameters are passed. The memory size, in 1K
increments, is returned in the AX register.
System BIOS 5-3

If a BIOS function has several possible operations, the AH register is
used as input to indicate the desired operation. For example, to set
the time of day, the following code is required:
MOV AH,l ;Function is to set time of day

MOV CX,HIGH_COUNT ;Establish the current time
MOV DX,LOW_COUNT
INT lAH ;Set the time
To read the time of day:
MOV AH,0 ;Function is to read time of day

INT lAH ;Read the timer
Genera"y, the BIOS routines save a" registers except for AX and the
flags. Other registers are modified on return only if they are
returning a value to the caller. The exact register use is in the
description of each BIOS function.
Hardware Interrupts
For the hardware interrupt assignments, see the Software Interrupt
Listing table later in this section. Interrupt level 0 corresponds to
interrupt vector 8, level 1 to interrupt vector 9, and so forth, including
interrupt level 7, which corresponds to interrupt vector OF.
For information about sharing interrupts, see "Interrupt Sharing" in

Section 1.
Software Interrupts
With software interrupt sharing, it is possible for software interrupt
routines to "daisy chain" BIOS interrupts hex 10 through 1F, similar
to hardware interrupt routines. The interrupt routine must check the
function value in AH, and if the value is not in the routine's range of
function calls, the interrupt routine transfers control to the next
routine in the chain.
5-4 System BIOS

Int Address Name
In Hex
o 0-3 Divide by Zero
1 4-7 Single Step
2 8-B Non-Maskable
3 C-F Breakpoint
4 10-13 Overflow
5 14-17 Print Screen
6 18-1B Reserved
7 1C-1F Reserved
8 20-23 Timer
9 24-27 Keyboard
A 28-2B Reserved
B 2C-2F Communications
C 30-33 Communications
D 34-37 Fixed Disk
E 38-3B Diskette
F 3C-3F Printer
10 40-43 Video BIOS
11 44-47 Equipment Check
12 48-4B Memory
13 4C-4F Diskette/Fixed Disk
14 50-53 Communications
15 54-57 System Services
16 58-5B Keyboard
17 5C-5F Printer
18 60-63 Resident BASIC
19 64-67 Bootstrap
1A 68-6B Time of Day
1B 6C-6F Keyboard Break
1C 70-73 Timer Tick
10 74-77 Video
1E 78-7B Pointer to Diskette Parameters
1F 7C-7F Video Graphics Characters
40 100-103 Diskette Pointer Save Area for Fixed Disk
41 104-107 Pointer to Fixed Disk Parameters
42 108-10B Video
43 10C-10F Character Graphics Table
46 118-11B Pointer to Extended Disk Parameters
4A 128-12B Reserved
60-67 180-19F Reserved for User Programs
Figure 5-1. Software Interrupt Listing
Vectors with Special Meanings
Interrupt Hex 1B - Keyboard Break Address: This vector points to the

code to be used when the Ctrl and Break keys are pressed on the
keyboard. The vector is invoked while responding to the keyboard
interrupt, and control is returned through an IRET instruction. The
power-on routines initialize this vector to an IRET instruction; nothing
occurs when the Ctrl and Break keys are pressed unless the applica-
tion program sets a different value.
System BIOS 5-5

Control may be retained by this routine, with the following consider-
ations. The Break may have occurred during interrupt processing, so
that one or more End of Interrupt commands must be sent to the inter-
rupt controller. Also, all I/O devices should be reset in case an oper-
ation was underway at that time.
Interrupt Hex 1C - Timer Tick: This vector points to the code to be

executed on every timer-tick interrupt. This vector is invoked while
responding to the timer interrupt, and control is returned through an
IRET instruction. The power-on routines initialize this vector to point
to an IRET instruction; nothing occurs unless the application modifies
the pointer. It is the responsibility of the application to save and
restore all registers that are modified.
Interrupt Hex 1D - Video Parameters: This vector is maintained for

compatibility with earlier IBM display adapters. For the current video
parameters, see "Alternate Parameter Table" in Section 1.
Interrupt Hex 1E - Diskette Parameters: This vector points to a data

region containing the parameters required for the diskette drive. The
power-on routines initialize the vector to point to the parameters con-
tained in the BIOS diskette routine. These default parameters repre-
sent the specified values for any IBM drives attached to the system.
Changing this parameter block may be necessary to reflect the spec-
ifications of other drives attached.
Interrupt Hex 1F - Graphics Character Extensions: When operating in

graphics modes 4,5, and 6, the read/write character interface forms
the character from the ASCII code point, using a set of dot patterns.
The dot patterns for the first 128 code points are contained in BIOS.
To gain access to the second 128 code points, this vector must be
established to point at a table of up to 1024 bytes, where each code
point is represented by 8 bytes of graphics information. At power-on,
this vector is initialized to 000:0, and it is the responsibility of the
application to change this vector if additional code points are needed.
Interrupt Hex 40 - Reserved: When a fixed disk is installed, the BIOS

routines use interrupt hex 40 to revector the diskette pointer.
5-6 System BIOS

Interrupt Hex 41 - Fixed Disk Parameters: This vector pOints to a
data region containing the parameters required for the fixed disk
drive. The power-on routines initialize the vector to point to the
parameters contained in the ROM disk routines. These default
parameters represent the specified values for the fixed disk drive.
Changing this parameter block may be necessary to reflect the spec-
ifications of other fixed disk drives attached.
Other Read/Write Memory Usage: The BIOS routines use 256 bytes
of memory from absolute hex 400 to 4FF. This memory is called the
BIOS data area. The routines also use an expandable memory
segment called the extended BIOS data area. Location hex 40E and
40F in the BIOS data area points to the extended data area. Both
memory segments are defined later in this section.
Memory locations hex 300 to 3FF are used as a stack area during the
power-on initialization and during bootstrap when it receives control
from power-on. The application can set its own stack area.
Interrupt Address Function
20 SO-S3 DOS Program Terminate

21 84-S7 DOS Function Call
22 88-SB DOS Terminate Address
23 8C-SF DOS Ctrl Break Exit Address
24 90-93 DOS Irrecoverable Error Vector
25 94-97 DOS Absolute Disk Read
26 98-9B DOS Absolute Disk Write
27 9C-9F DOS Terminate. Fix in Storage
28-3F AO-FF Reserved for DOS
40-5F 100-17F Reserved for BIOS
60-67 180-19F Reserved for User Program Interrupts
6S-6F 1A0-1BF Reserved
70 1CO-1C3 Reserved
71-7F 1EO-1FF Reserved
SO-S5 200-217 Reserved for BASIC
S6-FO 21S-3C3 Used by BASIC Interpreter while BASIC is Running
F1-FF 3C4-3FF Reserved
Figure 5-2. BASIC and DOS Interrupts
System BIOS 5-7

Address Mode Function
400-4AO BIOS See BIOS Data Area

4A1-4EF Reserved
4FO-4FF Reserved as Intra-application Communication Area
for any Application
500-5FF Reserved for DOS and BASIC
500 DOS Print Screen Status Flag Store
00= Print Screen Not Active, or Successful Print
Screen Operation
01 = Print Screen in Progress
FF = Error Encountered during Print Screen
Operation
504 DOS Single Drive Mode Status Byte
510-511 BASIC BASIC Segment Address Store
512-515 BASIC Clock Interrupt Vector Segment:Offset Store
516-519 BASIC Break Key Interrupt Vector Segment:Offset Store
51A-51D BASIC Disk Error Interrupt Vector Segment:Offset Store
Figure 5-3. Reserved Memory Locations
Offset Length Function
2E 2 Line Number of Current Line being Executed

30 2 Offset into Start of Program Text
4E 1 Character Color in Graphics Mode'
6A 1 Keyboard Buffer Contents
0= No Characters in Buffer
1 = Characters in Buffer
347 2 Line Number of Last Error
358 2 Offset into Start of Variables (End of Program Text 1-1)
• Set to 1, 2, or 3 to get text in colors 1-3. The default is 3.
Figure 5-4. BASIC Workspace Variables
Starting Address Function
00000 BIOS Interrupt Vectors

00080 Available Interrupt Vectors
00400 BIOS Data Area
00500 User Read/Write Memory
FOOOO Read-Only Memory
Figure 5-5. BIOS Memory Map
BIOS Programming Considerations
Warning: When using an in-circuit emulator in place of the system

microprocessor, take care to prevent the request/grant signals
between the emulator and the system support gate array from getting
out of synchronization, or damage to the gate array will result.
5-8 System BIOS

The BIOS code is invoked through software interrupts. The pro-
grammer should not code BIOS addresses into application programs.
The internal workings and absolute addresses within BIOS are
subject to change without notice.
If an error is reported by the disk or diskette code, reset the drive

adapter and retry the operation. A specified number of retries may
be needed on diskette reads to ensure that the problem is not
because of motor startup or head settling.
When altering I/O-port bit values, the programmer should change

only the bits necessary to the current task. When finished, the pro-
grammer should restore the original environment. Not following
these guidelines may cause incompatibility with present and future
applications.
Adapters with System-Accessible ROM Modules: The ROM BIOS

provides a means to integrate ROM code on adapters into the sys-
tem's code. During the POST, interrupt vectors are established for
the BIOS calls. After the default vectors are in place, a scan for addi-
tional ROM modules takes place. At this point, a ROM routine on the
adapter gains control and establishes or intercepts interrupt vectors
to hook itself into the system's code.
During POST, the absolute addresses hex COOOO through EFFFF are
scanned in 2K increments searching for valid adapter ROM.
Addresses hex COOOO through C7FFF are scanned before the video is
initialized and hex caooo through EFFFF are scanned at the end of
POST. A valid ROM is defined as follows:
Byte 0 Hex 55
Byte 1 HexAA
Byte 2 A length indicator representing the number of 512-byte
blocks in the ROM (length/512). A checksum is also done
to test the integrity of the ROM module. Each byte in the
defined ROM is summed modulo hex 100. This sum must
be 0 for the module to be deemed valid.
When the POST identifies a valid ROM, it does a Far Call to byte 3 of
the ROM (which should be executable code). The adapter may now
perform its power-on initialization tasks. The feature ROM should
return control to the BIOS routines by executing a Far Return.
System BIOS 5-9

Interrupt Interface Listing
The following contains the BIOS interrupts and the registers used on
the Call and Return.
Interrupt 02H - Non-Maskable Interrupt Routine
This routine attempts to find the storage location containing the bad
parity. If found, the segment address is displayed; if not found, four
question marks are displayed. An NMI is generated by a system
memory or I/O channel memory failure.
Interrupt OSH - Print Screen
This interrupt is invoked to print the screen contents. The cursor

position at the time this routine is invoked is saved and restored upon
completion. The routine is intended to run with interrupts enabled. If
a subsequent Print Screen key is pressed while this routine is
printing, it is ignored. The base printer status is checked for Not Busy
and Not Out of Paper. An initial status error aborts the print request.
Address 50:00 contains the status of the print screen:
50:0 = 00 Print screen has not been called, or upon return

from a call, indicates a successful operation.
= 01 Print screen is in progress - ignore this request.
= FF Error encountered during printing.
5-10 System BIOS, INT 02H

Interrupt 08H - System Timer
This routine handles the timer interrupt from channel 0 of the timer.
The input frequency is 1.19318 MHz and the divisor is 65,536,
resulting in approximately 18.2 interrupts every second.
The interrupt handler:
• Maintains a count of interrupts (doubleword at 40:6C) since

power-on time, which may be used to establish time of day. If the
system has been powered on for 24 hours, the overflow flag at
40:70 is incremented. The day counter word at 40:CE must be
updated when the time counter crosses a day boundary.
• Decrements the motor control count (40:40) of the diskette. Upon
reaching 0, it turns off the diskette drive motor, and resets the
motor running flags.
• Invokes a user routine through interrupt hex 1C at every timer
tick. The user must code a routine and place the correct address
in the vector table.
System BIOS, INT OSH 5-11

Interrupt 09H - Keyboard
This routine is invoked upon the make or break of every keystroke.
For ASCII keys, when a make code is read from port hex 60, the char-
acter and scan codes are placed in the keyboard buffer (40:1E for a
length of 32 bytes) at the address pointed to by the buffer tail pOinter
word at 40:1C. The buffer tail pointer is then increased by 2 unless it
wraps past the end of the buffer, in which case it is reinitialized to the
start of the buffer.
For shift keys, the keyboard flags are updated accordingly on makes
or breaks.
For the Ctrl-Alt-Delete sequence, the handler sets the memory-test-

complete word at 40:72 to hex 1234 and then jumps to POST. POST
checks the memory-test-complete word and does not retest memory if
hex 1234 is present.
For the Pause key, the handler loops until a valid ASCII keystroke is
pressed.
For the Print Screen key, interrupt 05 is invoked to print the screen.
For a Ctrl-Break sequence, the control break interrupt handler, inter-

rupt hex 1B, is invoked.
For the System Request key, interrupt hex 15 is invoked with

(AH) 85H; for Interrupt Complete, interrupt hex 15 is invoked with
(AH) = 91H.
The keyboard intercept is handled through interrupt hex 15, with

(AH) = 4FH.

Interrupt 10H - Video
Four text and five graphics modes of operation are available. The
text modes and three of the graphics modes are standard eGA
modes.
(AH) = OOH Set Mode
The AL register contains the mode value; if bit 7 in AL is set, the

video buffer is not cleared.
The cursor is not supported in graphics modes. Each color has

256K possibilities.
For the graphics modes 4, 5, 6, and 13, the font is an 8-by-8 char-
acter box that is double-scanned to generate the 8-by-16 char-
acter. The box size refers to the font supported by BIOS.
The power on default mode is 3.
Mode Alpha Buffer Box No. PEL

in Hex Type Colors Format Start Size Pages Dimensions
O. 1 A/N 16 40-by-25 88000 8-by-16 8 320-by-400
2, 3 A/N 16 80-by-25 88000 8-by-16 8 640-by-400
4, 5 APA 4 40-by-25 88000 8-by-8 320-by-200
6 APA 2 80-by-25 88000 8-by-8 640-by-200
11 APA 2 80-by-30 AOOOO 8-by-16 1 640-by-480
13 APA 256 40-by-25 AOOOO 8-by-8 320-by-200
System BIOS INT 10H 5-13

(AH) = 01 H Set Cursor Type
BIOS maintains only one cursor type for all video pages. If an
application requires that different cursor types be preserved for
different pages, it must maintain the different types itself.
When operating with 400 scan lines, the hardware modifies the
cursor type as follows:
Start line = (CH)*2
End line = [(CL)*2+ 1]
(CH) - Bits 4-0 = Start line for cursor
Hardware controls the cursor blink
(Cl) - Bits 4-0 = End line for cursor
(AH) = 02H Set Cursor Position

(DH,Dl) - Row.column (00.00) is upper left
(BH) - Page number (00 for graphics)
(AH) = 03H Read Cursor Position

(BH) - Page number (00 for graphics)
ON RETURN:
(DH.Dl) - Row.column of cursor for
requested page
(CH.Cl) - Cursor mode currently set
(AH) = 04H Reserved
(AH) = 05H Select Active Display Page
This function is valid only for alphanumeric modes (only those

modes support more than one page).
(Al) - New page value
0-7 for modes 0.1
0-3 for modes 2.3
5-14 System BIOS INT 10H

(AH) = 06H Scroll Active Page Up
(AL) - Number of lines; input lines blanked
at bottom of window.
AL = 0 means blank entire window
(BH) - Attribute to be used on blank line
(CH,CL) - Row,column of upper left corner of scroll
(DH,DL) - Row,column of lower right corner of scroll
(AH) = 07H Scroll Active Page Down

(AL) - Number of lines, input lines blanked at top
of window
AL = 0 means blank entire window
(BH) - Attribute to be used on blank line
(CH,CL) - Row,column of upper left corner of scroll
(DH,DL) - Row,column of lower right corner of scroll
(AH) = 08H Read Attribute/Character at Current Cursor Position

(BH) - Display page (alpha)
ON RETURN:
(AH) - Attribute of character read (alpha)
(AL) - Character read
(AH) = 09H Write Attribute/Character at Current Cursor Position
These two functions, (AH) = 09H and OAH, are similar. The func-
tion (AH) = 09 is used for the graphics modes. For the read/write
character interface in graphics modes (4, 5, and 6), the characters
are formed from a character image maintained in the system
ROM, which contains only the first 128 characters. To read or
write the second 128 characters, the user must initialize the
pointer at interrupt 1F (location 0007C) to point to the table con-
taining the code points for the second 128 characters (128-255).
For the graphics modes 11 and 13, 256 graphics characters are
supplied in the system ROM.
For the write character interface in graphics mode, the character

count in CX produces valid results only for characters on the
same row. Continuation to following lines will not produce
correct results.

For graphics modes other than mode 13, if bit 7 in BL is set to 1,
the color value is exclusive-OR'd with the current contents of the
video memory.
(Al) - Character to write
(Bl) - Attribute (alpha)/color (graphics)
(CX) - Count of characters to write
(AH) = OAH Write Character Only at Current Cursor Position

(CX) - Count of characters to write
(AH) = OBH Set Color Palette

This function is used to select the colors to be used in the
320-by-200 graphics modes. The following are the results for
modes 4 and 5:
Color ID = 0 selects the background color (0-15)
Color ID = 1 selects the color set to be used
In the alpha modes, the value set for palette color 0 indicates the
border color to be used.
(BH) - Palette color ID being set (0-127)
(Bl) - Color value to be used with that color ID
o = green (1) / red (2) / brown (3)
1 = cyan (1) / magenta (2) / white (3)
(AH) = OCH Write Dot
If 640-by-200 or 640-by-480 graphics mode is being used, then a

single black or white dot is written. For 320-by-200 modes
(modes 4, 5, and 6), a dot may be written using one of the four
possible color choices. For mode 13, a dot may be written using
one of the 256 possible color choices. In each case, the least sig-
nificant bits of AL hold the color value to be used. If bit 7 of AL is
set to 1, the color value is exclusive-OR'd with the current con-
tents of the dot (except mode 13).
(Al) - Color value
(CX) - Column number
(DX) - Row number

(AH) = ODH Read Dot
This function reads a dot in the same manner as Write Dot.

(CX) - Column number
(OX) - Row number
ON RETURN:
(Al) - Dot read
(AH) = OEH Write Teletype to Active Display
This function call is used to provide a teletype-like interface to the

video logic. The input character is written to the current cursor
position, and then the cursor position is updated. If the cursor
leaves the last column of the display field, the column is set to
zero and the row is incremented. If the row value exceeds the
display field, the cursor is placed on the last row, first column,
and the entire screen is scrolled up one line. The attribute for
filling the blank line is either the attribute of the previous cursor
position (alpha modes) or the color 0 (graphics modes). The
screen width is controlled by the previous Mode Set.
(Bl) - Foreground color in graphics mode
(AH) = OFH Current Video State

ON RETURN:
(AH) - Number of character columns on the screen
(Al) - Mode currently set (see AH=00)
(BH) - Current active display page
CAH) = 10H Color Palette Interface
CAL) = OOH Set Individual Register
On the IBM Personal System/2 Model 25, this routine is used

only to inhibit bit 3 of the attribute byte when 512 characters
are active to provide eight consistent colors. The only value
supported is (BX) = 0712H.
(BH) - Value to set
(Bl) - Register to set
System BIOS INT 10H 5·17

(AL) = 03H Toggle Intensify/Blinking Bit
(BL) = OOH Enable intensify
=OlH Enable blinking
(AL) = 10H Set Individual Color Register

(BX)= Color register to set
(DH)= Red value to set
(CH)= Green value to set
(CL)= Blue value to set
(AL) = 12H Set Block of Color Registers
The table format is red value, green value, blue value.

(ES:DX)= Pointer to a table of color values
(BX)= First color register to set
(CX)= Number of color registers to set
(AL) = 15H Read Individual Color Register

(BX)= Color register to read
ON RETURN:
(DH)= Red value returned
(CH)= Green value returned
(CL)= Blue value returned
(AL) = 17H Read Block of Color Registers
The table format is red value, green value, blue value.

(ES:DX)= Pointer to a destination table
for values
(BX)= First color register to be read
(CX)= Number of color registers to be read
(AL) = 1BH Sum Color Values to Gray Shades
This routine reads the red, green, and blue values found in
the color registers, performs a weighted sum (30% red, 59%
green, and 11 % blue), then writes the result into the red,
green, and blue components of the color register. The ori-
ginal data in each color register is not retained; if those
values will be needed later, they must be preserved by the
calling routine.

(BX)= First color register to sum
(CX)= Number of color registers to sum
(AH) = 11 H Character Generator Load
This function initiates a Mode Set, completely resetting the video

environment but maintaining the regen buffer. For a description
of the options available for character loads, refer to
"RAM-Loadable Fonts" in Section 1.
(AL) = OOH User Alpha Load
BH contains the value hex 10 for normal operation. If (BH) =

OEH, the characters are extended to 16-high by extending the
last line of the 14-high character.
(ES:BP)= Pointer to user table
(BH)= Number of bytes per character
(BL)= Block to load
(CX)= Count to store
(DX)= Character offset into table
(AL) = 01H Reserved If called, (AL) = 04H is executed.
(AL) = 02H ROM 8-by-8 Double-Dot Font

(BL)= Block to load
(AL) = 03H Set Block Specifier
This routine is executed after loading a font to make that

character font active. This routine is valid in alpha modes
only. For more information on block specifier, see
"RAM-Loadable Fonts" in Section 1.
When 512 characters are active, a function call with (AX) =

1000H and (BX) = 0712H should be executed to set eight con-
sistent colors.
(BL)= Character generator block selects
(AL) = 04H ROM 8-by-16 Font

(BL)= Block to load

(AL) = 10H Reserved If called, (AL) = OOH is executed.
The following routines are designed to be called immediately

after a Mode Set. Performing them at any other time will give
undetermined results.
(AL) = 20H User Graphics Chars (I NT 1FH - B-by-B)
This function allows the user to set up a pOinter to a font table

which defines the upper half (characters 128-255) of the
graphics characters (modes 4, 5, and 6).
(ES:BP) - Pointer to user table
(AL) = 21 H User Graphics Characters (I NT 43H)
This routine allows the user to set up a pointer to a font table

used for the modes 11 and 13 graphics characters.
(ES:BP) - Pointer to user table
(eX) - Points (bytes per character)
(BL) - Row specifier
= 00 - User specified in DL
= 01 (OEH) - 14
= 02 (19H) - 25
= 03 (2BH) - 43
(AL) = 23H ROM B-by-B Double-Dot Font
This function loads the ROM 8-by-8 double-dot font in the INT
43H pointer.
(BL)= Row specifier
(AL) = 24H ROM B-by-16 Font
This function loads the ROM 8-by-16 font in the INT 43H
pointer.
(BL)= Row specifier
(AL) = 30H Information

(CX)= Points
(DL)= Rows
ON RETURN:
(ES:BP)= Pointer to table
(BH) = OOH Return Current INT 1FH Pointer
(BH) = 01 H Return Current INT 43H Pointer
(BH) = 02H Reserved If called, (BH) = 06H is executed.
(BH) = 03H Return ROM 8-by-8 Font Pointer
(BH) = 04H Return ROM 8-by-8 Font Pointer (Top)
Returns pointer to top half (characters 128-255) of ROM

8-by-8 font.
(BH) = 06H Return ROM Alpha Alternate 8-by-16
Returns pointer to ROM 8-by-16 font. There is no alter-

nate 8-by-16 font.
(AH) = 12H Alternate Select
(Bl) = 20H Select Alternate Print Screen Routine
This loads the BIOS print screen pointer into INT 15H. No
alternate print screen routine is supported.
(Bl) = 31H Default Palette loading During Mode Set
The color registers are not altered during Mode Set if Disable
Default Palette loading is selected. The number of color reg-
isters loaded depends on the mode selected. Mode 13 loads
the first 248 color registers. All other modes load the first 16
registers. Shades of grey are supported for BW monitors, or
are enabled by using BIOS call (AH) = 12H, (Bl) = 33H.
(AL) = 00 Enable default palette loading
= 01 Disable default palette loading
ON RETURN:
(AL) = 12H Function supported

(BL) = 32H Video
This routine enables and disables the address decode for the
video 1/0 port and regen buffer.
(AL) = 00 Enable video
= 01 Disable video
ON RETURN:
(BL) = 33H Summing to Gray Shades
When enabled, summing occurs while loading the color

palette during Mode Set and Color Palette Interface routines.
(AL) = 00 Enable summing
= 01 Disable summing
ON RETURN:
(BL) = 35H Display Switch
When the system video adapter and expansion slot video

adapter have the same BIOS data areas and hardware capa-
bilities, they are in conflict. If POST detects the conflict, the
system video adapter is disabled and the expansion slot
video adapter becomes the primary adapter.
This routine allows switching the active display between

these two video adapters. The following shows the proce-
dure when initially switching to the system video adapter:
1. Initial Expansion Slot Video Off, (AL) = 00.
2. Initial System Video On, (AL) = 01.
Afterwards, switching displays is done through the sequence:

1. Switch Off Active Video, (AL) = 02
2. Switch On Inactive Video, (AL) = 03
Switching off the active video adapter disables the video

function that is active at that time. The Switch State buffer
saves the video state information used when that video
adapter is reactivated.

Switching on the inactive video adapter enables the video
function that was inactive and uses its buffer to retrieve the
video information.
All subroutines under display switching return a value of hex

12 to indicate that the function is supported.
(AL) = OOH Initial Feature Video Off

(ES:DX)- Pointer to Switch State buffer of 128 bytes
(AL) = 01 H Initial System Video On
(AL) = 02H Switch Active Video Off

(ES:DX)- Pointer to Switch State buffer
(AL) = 03H Switch Inactive Video On
(ES:DX)- Pointer to Switch State buffer saved earlier
(AH) = 13H Write String
CARRIER RETURN, LINE FEED, BACKSPACE, and BELL are

treated as commands rather than as printable characters.
(ES:BP)= Pointer to string to be written
(CX)= Character only count
(DX)= Position to begin string. in cursor terms
(BH)= Page number
(AL) = OOH Write Character String

(BL)= Attribute
Stri ng is (CHAR. CHAR. CHAR. . .. )
Cursor not moved
(AL) = 01 H Write Character String and Move Cursor

(BL)= Attribute
String is (CHAR. CHAR. CHAR •... )
(AL) = 02H Write Character and Attribute Strings
This function is for alpha modes only.

String - (CHAR. ATTR. CHAR. ATTR •... )
Cursor not moved

(AL) = 03H Write Character And Attribute Strings
This function is for alpha modes only.

STRING - (CHAR, ATTR, CHAR, ATTR, ... )
CURSOR IS MOVED
(AH) = 1AH Read/Write Display Combination Code
(AL) = OOH Read Display Combination Code
Display Code Description
OOH No Display
OSH Analog Monochrome
OCH Analog Color
ON RETURN:
(AL) = lAH - Function supported
(Bl) - Active display code
(BH) - Alternate display code
(AL) = 01 H Write Display Combination Code

(Bl) - Active display code
(BH) - Alternate display code
ON RETURN:
(AL) = lAH - Function supported
(AH) = 1BH Return Functionality and Video State Information
The user buffer contains functionality and video state information

as described by the requested implementation type. When the
implementation type in BX is set to 0, the buffer size is 64 bytes.
(BX)= Implementation type
(ES:OI)= User buffer pointer for return of
functionality/state information
ON RETURN:
(AL)= IBH - Function supported
(AH) = 1CH - FFH Reserved

The following is the format of the functionality and state information
table for the video. The size is 64 bytes, and the offset is shown as
the hex value from (DI).
Offset Size Description
00 Word Offset to Static Functionality Table

02 Word Segment to Static Functionality Table
04 Byte Video Mode (Refer to (AH) = 00 for Supported Modes)

05 Word Columns on Screen (No. of Char. Columns)
07 Word Length of Regen Buffer in Bytes
09 Word Start Address in Regen Buffer
OB Word Cursor Position for 8 Display Pages (Row,Col)
1B Word Cursor Mode Setting (Cusor Start/End Value)
10 Byte Active Display Page
1E Word Controller Address
20 Byte CRT Mode Set
21 Byte CRT Palette
22 Byte Rows on Screen (No. of Char. Lines)
23 Word Character Height (Scan Lines/Char.)
25 Byte Display Combination Code (Active)
26 Byte Display Combination Code (Alternate)
27 Word No. of Colors Supported for Current Mode
29 Byte No. of Display Pages Supported for Current Mode
2A Byte Scan Lines in Current Mode
= 0 - 200
= 1-350
= 2-400
= 3-480
2B - 2C Byte Reserved = 0
2D Byte Miscellaneous State Information
Bit 7,6 - Reserved
Bit 5 - Blink Enabled
Bit 4 - Reserved = 0
Bit 3 - Default Palette Loading
Bit 2 - Monochrome Display Attached
Bit 1 - Summing Active
Bit 0 - Reserved = 0
2E - 30 Byte Reserved
31 Byte Video Memory Available
= 0- 64K
= 1 - 128K
= 2 -192K
= 3 - 256K
32 Byte Save Pointer State Information
Bits 7-5 Reserved = 0
Bit 4 Palette Override Active
Bit 3 Graphics Font Override Active
Bit 2 Alpha Font Override Active
Bit 1 Dynamic Save Area Active
Bit 0 512 Character Set Active
33 - 3F Byte Reserved

The following is the format of the static functionality table pointed to
by the start of the functionality and state information table. The table
is 16 bytes long. A bit is set to 1 if the function is supported.
Bit Function
Byte 0 Video Modes (3 Bytes)

7 Mode 7
6 Mode 6
5 Mode 5
4 Mode 4
3 Mode 3
2 Mode 2
1 Mode 1
0 Mode 0
Byte 1 7 Mode F
6 Mode E
5 Mode D
4 ModeC
3 Mode B
2 Mode A
1 Mode 9
0 ModeS
Byte 2 7-4 Reserved

3 Mode 13
2 Mode 12
1 Mode 11
0 Mode 10
Bytes Reserved
3-6
Byte 7 Scan Lines Available in Text Modes

7-3 Reserved
2 400
1 350
0 200
ByteS Character Blocks Available in Text Modes

Byte 9 Max. Number of Active Character Blocks in Text Modes
Byte A Miscellaneous Functions
7 Reserved = 0
6 Color Register, See (AH) = 10H
5 Palette, See (AH) = 10H
4 Reserved = 0
3 Default Palette Loading, See (AH) = 12H
2 Character Font Loading, See (A H) = 11H
1 Summing
0 Reserved = 0
Byte B Miscellaneous Functions

7-4 Reserved = 0
3 DCC
2 Blink Enabled
1 Reserved = 0
0 Reserved = 0

Bit Function
Bytes Reserved
C,D
Byte E Save Pointer Functions

7-5 Reserved = 0
4 Palette Override
3 Graphics Font Override
2 Alpha Font Override
1 Dynamic Save Area
0 512 Character Set
ByteF Reserved
The following is the format for the SAVE _TBL. All entries are
doubleword. For more information, see "Alternate Parameter Table"
on page 1-70.
Entry Description
Video Parameter Table Pointer

This must point to the video parameter table in BIOS
2 Reserved as all O's
3 Alpha Mode Auxiliary Font Pointer

a user font in A/N mode. The table has the following format:
Size Description
Byte Bytes per character
Byte Block to load, should be 00 for normal operation
Word Count to store, should be hex 100 for normal operation
Word Character offset, should be 00 for normal operation
Byte Displayable rows, if the value is FF, the maximum calculated
value wi" be used; otherwise, this value is used.
4 Graphics Mode Auxiliary Pointer

a user font in graphics mode. The table has the following format:
Size Description
Byte Displayable rows
Word Bytes per character
5-7 Reserved as all O's.
System BIOS tNT 10H 5-27

Interrupt 11 H - Equipment Determination
This routine determines what optional devices are attached. The

EQUIPJLAG variable is set during the power-on diagnostics, using
the following hardware assumptions:
Port 3FA - Interrupt ID register (primary)

2FA - Interrupt ID register (secondary)
Bits 7-3 are always 0
Port 378 - Output port of printer 1
278 - Output port of printer 2
3BC - Output port of printer 3
ON RETURN:
(AX) - Equipment flag
Bit 15,14 = Number of printers attached
Bit 13.12 = Reserved
Bit 11.10.9 = Number of RS-232C ports attached
Bit B = Reserved
Bit 7.6 = Number of diskette drives
00=1, 01=2 only if bit 0 = 1
Bit 5.4 = Initial video mode
00 - reserved
01 - 40-by-25 using color
10 - 80-by-25 using color
11 - 80-by-25 using BW
Bit 3 = Reserved
Bit 2 = Pointing device attached
Bit 1 = Math coprocessor installed
Bit 0 = IPL diskette installed
5·28 System BIOS, INT 11 H

Interrupt 12H - Memory Size Determination
This routine returns the amount of RAM in the system as determined

by the POST routines.
The following are the memory determination assumptions:
• All installed memory is functional. If the memory test during

POST indicates less, that value becomes the default.
• All memory from 0 to 640K must be contiguous.
Note: The memory value returned will be the total system memory
minus the 1K block of extended BIOS memory. A 640K machine will
return 639K if all the memory is functioning properly.
ON RETURN:
(AX) - Number of contiguous lK blocks of memory
System BIOS, INT 12H 5-29

Interrupt 13H - Diskette
For operations requiring the diskette drive motor, the multitasking

hook function (INT 15H, (AX) = 90FDH) is called. This tells the oper-
ating system that the BIOS is waiting for the motor to accelerate,
allowing the operating system to perform a different task.
Before waiting for an interrupt, BIOS calls Device Busy (INT 15H, (AX)
= 9001H), informing the operating system of the Wait. The comple-
mentary Interrupt Complete (INT 15H, (AX) = 9101H) is called, indi-
cating that the operation is complete.
(AH) = OOH Reset DlskeHe System
This function issues a hard reset to the controller and then gener-
ates a Prepare command. The drive is recalibrated when the
next drive operation is initiated.
If an error is reported by the diskette code, the appropriate action

is to reset the diskette and then retry the operation.
(Dl) - Drive number
Bit 7 = 0 for diskette (value checked)
ON RETURN:
(ey) - Set indicates status ;s nonzero
(AH) - Status of operation (see Read Status)
Diskette status at 40:41 = status of operation

(AH) = 01 H Read Status of Last Operation
(Dl) - Drive number
ON RETURN:
(CY) - Set indicates status is nonzero
(AH) - Status of operation
(AH) Error (AH) Error
80 Time Out 08 Reserved

40 Seek Failure 06 Media Has Been Changed
20 General Controller Failure 04 Sector Not Found
10 CRC Error 03 Write Protect Error
OC Unsupported Track. 02 Bad Address Mark
SectorslTrack Combination 01 Invalid Function Request
09 DMA Boundary Error 00 No Error
(AH) = 02H Read Desired Sectors Into Memory
The two most significant bits in CL are the two most significant
bits of the 10-bit track number.
If an error is reported by the diskette code, the appropriate action

is to reset the diskette and then retry the operation.
(Dl) - Drive number.
(DH) - Head number. (origin of 0, not value checked)

(CH) - Track number, (origin of 0, not value checked)
(Cl) - Sector number, (origin of I, not value checked)
(Al) - Number of sectors (not value checked)
(ES:BX) - Address of buffer
ON RETURN:
(Al) - Number of sectors actually transferred
System BIOS, INt 13H 5-31

(AH) = 03H Write Desired Sectors from Memory
bits of the 10-bit track number. If an error is reported by the
diskette code, the appropriate action is to reset the diskette and
then retry the operation.
(Dl) - Drive number,
(DH) - Head number (origin of 0, not value checked)
(CH) - Track number (origin of 0, not value checked)
(Cl) - Sector number (origin of 1, not value checked)
ON RETURN:
(Al) - Number of sectors actually transferred
(AH) = 04H Verify Desired Sectors
(Dl) - Drive number,
(DH) - Head number (origin of 0, not value checked)
(CH) - Track number (origin of 0, not value checked)
(Cl) - Sector number (origin of 1, not value checked)
ON RETURN:
(Al) - Number of sectors verified

(AH) = 05H Format Desired Track
When using this function, (ES:BX) points to the buffer containing

the collection of desired address fields for the track. Each field
has 4 bytes with a format as follows:
Byte 0 Track number

Byte 1 Head number
Byte 2 Sector number
Byte 3 Number of bytes per sector
• 00 = 128
• 01 = 256
• 02 = 512
• 03 = 1024
There must be one entry for every sector on the track. This is
used to find the requested sector during read/write access.
Before formatting a diskette when there is more than one format,
Set Media Type (AH = 18H) must be called. If it is not called, the
default is the maximum capacity of the drive.
(DL) - Drive number.
(DH) - Head number (origin of 0. not value checked)
(CH) - Track number (origin of 0. not value checked)
(AL) - Number of sectors (origin of 1. not value checked)
ON RETURN:
(AH) = 06H - 07H Reserved for Fixed Disk Interface

ON RETURN:
(CY) - Set indicates error
(AH) - Status of operation = 01 for invalid command
System BIOS. INT 13H 5-33

(AH) - 08H Read Drive Parameters
There is a parameter table for each supported media type.

(Dl) - Drive number.
ON RETURN:
(ES:DI) - Pointer to 11 byte parameter table
associated with the maximum supported media types
on the drive in question.
(CH) - least significant 8 of 10 bits maximum number
of tracks (origin of 0)
(Cl) - Bits 7 and 6 - 2 most significant bits of maximum
tracks
- Bits 5 through e - maximum sectors per track
(origin of 1)
(DH) - Maximum head number

(origin of 0)
(Dl) - Number of diskette drives installed
(BH) = 0
(Bl) - Bits 7 through 4 = 0
Bits 3 through 0 - valid drive type
03 = 720 K. 3.5 inch. 80 track
(AX) = 0
If the drive number is invalid.

ES.AX.BX.CX.DH.DI = 0 ; Dl = number of drives.
If no drives are present. Dl = 0
Diskette status 40:41 = 0 and (CY) = 0
(AH) ... 09H - 14H Reserved for Fixed Disk Interface

ON RETURN:
(AH) - Status of operation = 01 for invalid command
5-34 Syst4m BIOS. INT 13H

(AH) = 15H Read DASD Type
(DL) - 7-bit drive number. bit 7 = 0 for diskette
(value checked)
ON RETURN:
(AH) = 00 - Drive not present
= 01- Diskette. no change line available
= 02 - Diskette. change line available
= 03 - Reserved for fixed disk interface
(AH) = 16H Disk Change Line Status

(value checked)
ON RETURN:
(CY) - Set if (AH) is not zero
(AH) = 00 - Disk change line not active
01 - Invalid drive number
06 - Disk change line active
Diskette status at 40:41 = (AH) on return
(AH) = 17H Set DASD Type for Format
The 'disk change' line status is checked for all drives supporting
the 'disk change' signal. This function is supported for compat-
ibility purposes; however, Set Media Type for Format, (AH) = 18H,
is the suggested function to use.

(value checked)
(AL) = 04 - 720K diskette in a 720K diskette drive
ON RETURN:
= 01 for invalid request

(AH) = 18H Set Media Type For Format
This function is called before issuing the first Format Desired

Track command. If the diskette is changed, this function is called
again. The diskette must be present.
This function monitors the 'disk change' signal. If the signal is

active:
1. The logic attempts to reset the signal to the inactive state.
2. If the attempt succeeds, BIOS sets the correct data rate for
formatting.
3. If the attempt fails, BIOS returns the time-out error (hex aD) in
AH.
There is one parameter table for each supported medium type.

(Dl) - 7-bit drive number. bit 7 = 0 for diskette
(value checked)
(CH) - least significant 8 of 10 bits. number
of tracks (origin of 0)
(Cl) - Bits 7 and 6 - 2 most significant bits of number of
tracks
- Bits 5 through 0 - sectors per track
(origin of 1)
ON RETURN:
(ES:DI) - Pointer to II-byte parameter table
for this medium type. unchanged if AH is nonzero
(CY) - Set if track and sectors/track is not supported

(AH) - Status of operation = 01 for invalid request
(AH) = 19H - FFH Reserved

ON RETURN:
= 01 for invalid command

Interrupt 13H - Fixed Disk
This interface provides access to fixed disks through the controller. It

is assumed that upon entry to the fixed disk portion of Interrupt 13H,
bit 7 of the drive number is set, indicating a fixed disk operation.
Before waiting for an interrupt, BIOS calls Device Busy with type =
disk (INT 15H, AX = 9001H), telling the operating system of the Wait.
The complementary Interrupt Complete (INT 15H, AX = 9101H) is
called, indicating that the operation is complete.
The function number (AH) is also checked for read/write. The sector
number (AL) is also checked for a valid range of Hex 01 to 80.
Registers will be preserved except when they are used to return

values.
(AH) = OOH Reset Disk System
Before waiting on a disk reset, the BIOS calls Device Busy (INT
15H, AX = 9000H). The reset is a time-out of approximately 3
seconds. This time-out value depends on the function number.
Diskette reset is invoked for all values of (DL). Disk Reset is

invoked only if the drive number is less than or equal to the
maximum number of fixed disks.
If an error is reported, reset the disk, then retry the operation.

(DL) - 7-bit drive number
Bit 7 = 1 for fixed disk
ON RETURN:
Disk status at 4e:74 = status of operation
System BIOS, INT 13H 5-36.1

(AH) = 01 H Read Status of Last Operation
(DL) - 7-bit drive number
ON RETURN:
(CY) - Always cleared (Operation successful)
(AL) - Status of last operation
(AH) - Status'of this operation (Will always be 88 - No error)
Disk status at 48:74 is reset to 8
Status Error Status Error

Code Code
FF Sense Operation Failed 00 Invalid Number of

EO Status Error/Error Sectors On Format
REG=O OS Sad Track Detected
CC Write Fault On Selected OA Sad Sector Flag Detected
Drive 09 DMA Eloundary Error
SS Undefined Error Occurred 08 DMA Failure
AA Drive Not Ready 07 Drive Parameter Activity
80 Time Out Failed
40 Seek Failure 05 Reset Failed
20 General Controller 04 Sector Not Found
Failure 03 Write Protect Error
11 ECC Corrected Data Error (Diskette Only)
10 Sad ECC On Disk Read 02 Sad Address Mark
OE Controlled Data Address 01 Invalid Function Request
Mark Detected 00 No Error
(AH) = 02H Read Desired Sectors Into Memory
The error code 11 indicates that the data read had a recoverable
error that was corrected by the ECC algorithm. The error may
not recur if the data is rewritten.
5-36.2 System BIOS, INT 13H

(OL) - 7-bit drive number.
(OH) - Head number. (origin of 0. not value checked)

(CH) - Track number. (origin of 0. not value checked)
(CL) - Sector number. (origin of 1. not value checked)
(AL) - Number of sectors
ON RETURN:
Disk status at 40:74 = status of operation
(AH) = 03H Write Desired Sectors from Memory
(OL) - 7-bit drive number.
(OH) - Head number (origin of 0. not value checked)
(CL) - Sector number (origin of 1. not value checked)
(AL) - Number of sectors
ON RETURN:
System BIOS. INT 13H 5-36.3

(AH) = 04H Verify Desired Sectors
(Dl) - 7-bit drive number.
(DH) - Head number (origin of 0. not value checked)
(Cl) - Sector number (origin of 1. not value checked)
(Al) - Number of sectors
ON RETURN:
(A H) = 05H Format Desired Track
(Dl) - 7-bit drive number.
(DH) - Head number
(CH) - Track number
(ES:BX) - Address of buffer points to a 512-byte
buffer. The first 2 bytes (sectors/track) contain
F. N for each sector.
F = 00 - for a good sector

80 - for a bad sector
N - sector number
For an interleave of 2 and 17 sectors per track, the table is:

DB 00H.01H.00H.0AH.00H.02H.00H.0BH.00H.03H.00H.0CH
DB 00H.04H.00H.0DH.00H.05H.00H.0EH.00H.06H.00H.0FH
DB 00H.07H.00H.10H.00H.08H.00H.11H.00H.09H
ON RETURN:
5-36.4 System BIOS. INT 13H

(AH) = OSH Read Drive Parameters
If drive number is invalid, then AH and DISK _STATUS contain the

value hex 07, and the carry flag is set.
If no fixed disks are attached, then AH and DISK _STATUS contain

the value hex 01, and the carry flag is set. The number of drives
attached, (DL), will never be returned as 0; therefore the value
(DL) is either 01 or 02.
(DL) - 7-bit drive number,
ON RETURN:
(DL) - Number of consecutive drives attached
(1-2) (controller card zero tally only)
(DH) - Maximum usable value for head number
(origin of a)
(CH) - Maximum usable value for cylinder number
(origin of a)
(CL) - Maximum usable value for sector number
and cylinder number high bits (origin of 1)
(AH) = 09H Initialize Drive Pair Characteristics

Interrupt 41H points to the single parameter table for drive O. If
(DL) is hex 80, drive 0 is initialized using interrupt 41H. For all
other values, an invalid command status is returned.
(DL) - 7-bit drive number.
ON RETURN:
(AH) = OAH and OBH These functions are reserved for diagnos-
tics.

(AH) = OCH Seek
If an error is reported by the disk code, the appropriate action is

to reset the disk, then retry the operation.
(DL) -,7-bit drive number.
(DH) - Head number
(CH) - Track number
ON RETURN:
(AH) = ODH Alternate Disk Reset
Disk Reset is invoked only if the drive number is less than or

equal to the maximum number of fixed disks.
ON RETURN:
(AH) = OEH and OFH These functions are reserved for diagnos-
tics.
(AH) = 10H Test Drive Ready

ON RETURN:

(AH) = 11 H Recallbrate
If an error is reported by the disk code, reset the disk, then retry
the operation.
ON RETURN:
(AH) = 14H Reserved for diagnostics.
(AH) = 15H Read DASD Type
If the drive number is out of range, AH contains 00 (Drive Not

Present) and (eX,OX) = 00,00.
bit 7 = 1 for fixed disk
ON RETURN:
(AH) = 00 - Drive not present
01
= - Reserved for diskette interface
02
= - Reserved for diskette interface
= 03 - Fixed disk
(CX,DX) - Number of 512-byte blocks

(AH) = 16H-18H Reserved for diskette drive.
(AH) = 19H Park Heads on Specified Drive

bit 7 = 1 for fixed disk
ON RETURN:
(CV) - Set indicates error
(AH) - Status of operation (01 for invalid command)
(AH) = 1AH-FFH Reserved
ON RETURN:
(CV) - Set indicates error
(AH) - 01 for invalid command

Interrupt 14H - Asynchronous Communications
These routines provide RS-232C support.
(AH) = OOH Initialize the Communications Port

(AL) - Parameters for initialization
(DX) - RS-232C card number (0 based)
7 6 5 4 3 2 1 0
Baud Rate Parity Stopbit Word Length
DOO- 110 XO- None 0-1 10 - 7 Bits

001 - 150 01 - Odd 1- 2 11 - 8 Bits
010 - 300 11 - Even
011 - 600
100 - 1200
101 - 2400
110-4800
111-9600
ON RETURN:
(AL) - Modem status
Bit 7 = Received line signal detect
Bit 6 = Ring indicate
Bit 5 = Data set ready
Bit 4 = Clear to send
Bit 3 = Delta received line signal detect
Bit 2 = Trailing edge ring indicate
Bit 1 = Delta data set ready
Bit 0 = Delta clear to send
(AH) - Line control status

Bit 7 = Ti meout
Bit 6 = Tx shift register empty'
Bit 5 = Tx holding register empty
Bit 4 = Break detect
Bit 3 = Framing error
Bit 2 = Parity error
Bit 1 = Overrun error
Bit 0 = Data ready

(AH) = 01 H Send Character
(AL) - Character to send
(OX) - RS-232C card number (0 based)
ON RETURN:
(AL) is preserved
(AH) - Status
Bit 7 = 1 unable to transmit
If bit 7 = 0 (able to transmit).
then bits 6 thru 0 are:
Bit 6 = Tx shift register empty
Bit 0 = Data ready
(AH) = 02H Receive Character
This routine waits for the character. Bits 1 through 4 have

meaning only if bit 7 (Timeout) is not set.
(OX) - RS-232C card number (0 based)
ON RETURN:
(AL) - Character received
(AH) - Line status
Bit 7 = Timeout
5-38 System BIOS. INT 14H

(AH) = 03H Read Status
ON RETURN:
(AL) - Modem status register
Bit 7 = Received line signal detect
Bit 6 = Ring indicate
Bit 5 = Data set ready
Bit 4 = Clear to send
Bit 3 = Delta received line signal detect
Bit 2 = Trailing edge ring indicate
Bit 1 = Delta data set ready
Bit 0 = Delta clear to send
(AH) - Line status register

Bit 7 = Timeout
Bit 6 = Tx shift register empty
Bit 0 = Data ready

(AH) = 04H Extended Initialize
(Al) - Break
00 - No break
01 - Break
(BH) - Parity
00 - None
01 - Odd
02 - Even
03 - Stick parity odd
04 - Stick parity even
(Bl) - Stop bit

00 - One
01 - Two if 6-, 7-, or 8-bit word length
One and a half if 5-bit word length
(CH) - Word length

00 - 5 bits
01 - 6 bi ts
02 - 7 bits
03 - 8 bits
(Cl) - Baud rate

00 - 110 Baud
01 - 150 Baud
02 - 300 Baud
03 - 600 Baud
04 - 1200 Baud
05 - 2400 Baud
06 - 4800 Baud
07 - 9600 Baud
08 - 19200 Baud
ON RETURN:
(AL) - Modem status register, see (AH)=03
(AH) - line status register, see (AH)=03

(AH) = 05H Extended Communications Port Control
(AL) = OOH Read Modem Control Register

ON RETURN:
(Al) - Modem status register. see (AH)=03
(AH) - line status register. see (AH)=03
(Bl) - Modem control register
Bit 4 = loop
Bit 3 = Out 2
Bit 2 = Out 1
Bit 1 = Request to Send
Bit 0 = Data Terminal Ready
(AL) = 01 H Write Modem Control Register

Bit 4 = loop
Bit 3 = Out 2
Bit 2 = Out 1
Bit 1 = Request to Send
Bit 0 = Data Terminal Ready
ON RETURN:
(Al) - Modem status register. see (AH)=03
(AH) - line status register. see (AH)=03
(AH) = 06F - FFH Reserved
System BIOS. INT 14H 5-41

Interrupt 15H - System Services
(AH) = 00 - 4EH Reserved

ON RETURN:
(CY) - Carry flag set
(AH) = 86 invalid function
(AH) = 4FH Keyboard Intercept
Keyboard intercept (keyboard escape) is called asynchronously

by the keyboard interrupt 09 routine. This allows for a keystroke
to be changed or absorbed. Normally the system returns with the
scan code unchanged, but the operating system can redirect an
interrupt 15H to its own routine and do one of the following:
• Replace (AL) with a different scan code and return with the
carry flag set, effectively changing the keystroke
• Process the keystroke and return with the carry flag cleared,
causing the interrupt 09 routine to ignore the keystroke.
(CY) - Set to change keystroke
(AL) = Scan code
ON RETURN:
(AL) = Scan code
(AH) = 50H - 7FH Reserved

ON RETURN:
(AH) = 86H
(AH) = BOH Device Open

(BX) = Device ID
(CX) = Process ID
(AH) = 81 H Device Close

(BX) = Device ID
(CX) = Process ID

(AH) = 82H Program Termination
(BX) = Oevice 10
(AH) = 83H Event Walt

(AL) = 00 Set interval
01 Cancel
=
(ES:BX) - Pointer to a byte in caller's memory
that will have the most significant
bit set as soon as possible after the
interval expires.
(CX,OX) - Number of microseconds to elapse before
posting.
ON RETURN:
(CY) - Cleared if (AL) is not zero
- Set if function is already busy
(AH) = 84H Joystick Support
(DX) = OOH Read Current Switch Settings

ON RETURN:
(CY) - Set if invalid call
(AL) = Switch settings (bits 7-4)
(DX) = 01 H Read Resistive Inputs
ON RETURN:
(CY) - Set if invalid call
(AX) = A{x) value
(BX) = A{y) value
(CX) = B{x) value
(OX) = B{y) value
(AH) = 85H System Request Key Pressed

(AL) = 00 - Make of key
= 01 - Break of key
(AH) = 86H Wait

(CX,OX) - Number of microseconds to elapse before
returning to caller
(AH) = 87H - 8FH Reserved

ON RETURN:
(AH) = 86H

(AH) = 90H Device Busy
This function allows the operating system to take control when

the system is about to wait for a device.
ON RETURN:
(AL) Type code (see (AH) = 91H)
(AH) = 91 H Interrupt Complete
This function is called to tell the operating system that an inter-

rupt has occurred. The type codes for functions 90H and 91 Hare
in the following categories:
00 to 7F Indicates serially reusable devices. The operating

system must serialize the access.
80 to BF Indicates reentrant devices; ES:BX is used to distin-
guish different calls (multiple liD calls are allowed
simultaneously).
CO to FF Indicates wait-only calls; there are no complementary
Posts for these Waits. They are timeout only. Times
depend on the type of device.
(AL) - Type Code
Type Description Timeout

00 Di sk Yes
01 Diskette Yes
02 Keyboard No
03 Pointing Device Yes
80 Network No
ES:BX --> Network Control Block
FD Diskette motor start Yes
FE Printer Yes
FC Fixed Disk Reset Yes
(AH) = 92H - BFH Reserved

(AH) = 86H

(AH) = COH Return System Configuration Parameters
ON RETURN:
(ES:BX)= Pointer to system descriptor vector in ROM
(CY) = Carry flag clear
(AH) = a
The following is the format of the system descriptor table.
Size Description
Word Length of Descriptor in Bytes,
Minimum is 8 Bytes
Byte Model Byte
Byte Sub model Byte
Byte BIOS Revision Level
Byte Feature Information Byte 1

Bit 7 = 1 BIOS uses DMA channel 3
Bit 6 = 0 One interrupt controller
Bit 5 = 0 No Real-time clock
Bit 4 = 1 Keyboard escape sequence (INT 15H) called in
keyboard interrupt (INT 09)
Bit 2 = 1 Extended BIOS data area is allocated
(AH) = C1 H Return Extended BIOS Data Area Segment Address

ON RETURN:
(CY) = Set on error
(ES) = Segment to extended BIOS data area

(AH) = C2H Pointing Device
After POST, the following default parameters are set:

Package size is set to 3 bytes.
Pointing device is disabled.
Sample rate is set to 100 reports per second.
Resolution is set to 4 counts per mm.
Scaling is set to 1:1.
When the device driver is called, the following information is on

the stack (each entry is word length):
Entry Description
1 Status (High Byte = 0)
Low Byte
Bit 7 1= Y data overflow
Bit 6 1 = X data overflow
Bit 5 Y data, 1 = negative
Bit 4 X data, 0 = positive
Bits 3,2 Reserved
Bit 1 1 = Right button pressed
Bit 0 1 = Left button pressed
2 X Data (High Byte = 0)

Low Byte - Bit 7 MSB, Bit 0 LSB
3 Y Data (High Byte = 0)

Low Byte - Bit 7 MSB, Bit 0 LSB
4 Z Data (High Byte = 0)

Low Byte = 0
The following are the return values for all functions of pointing
device:
ON RETURN:
(CV) = Set if unsuccessful operation
(AH) = Status
B0 - No error
01 - Invalid function call
02 - Invalid input
03 - Error
04 - Reserved
05 - No Far Call installed
06 - Reserved

(AL) = OOH Enable Pointing Device
(BH) = e Disable
= 1 Enable
(AL) = 01 H Reset Pointing Device
(AL) = 02H Set Sample Rate

(BH) - Rate value
e - Ie reports/sec
1 - 2e reports/sec
2 - 4e reports/sec
3 - 6e reports/sec
4 - Be reports/sec
5 - lee reports/sec
6 - 2ee reports/sec
(AL) = 03H Set Resolution

(BH) - Resolution value
e - 1 count /mm
1 - 2 counts/mm
2 - 4 counts/mm
3 - 8 counts/mm
(AL) = 04H Read Device Type

(BH) = Device ID
(AL) - 05H Initialization

(BH) - Data package size
1 - 1 Byte
2 - 2 Bytes
3 - 3 Bytes
4 - 4 Bytes
5 - 5 Bytes
6 - 6 Bytes
7 - 7 Bytes
8 - 8 Bytes

(AL) = 06H Extended Commands
(BH) = OOH Return Status

ON RETURN:
(Bl) - Status Byte 1
Bit 7 = 0 - Reserved
Bit 6 = 0 - Stream mode
=1 - Remote mode
Bit 5 = 1 - Pointer enabled
Bit 4 = 0 - 1:1 scaling
=1 - 2:1 scaling
Bit 2 = 1 - left button pressed
Bit 0 = 1 - Right button pressed
(Cl) - Status Byte 2

00 - 1 count/mm
01 - 2 counts/mm
02 - 4 counts/mm
03 - 8 counts/mm
(Ol) - Status Byte 3

0A - 10 reports/sec
14 - 20 reports/sec
2B - 40 reports/sec
3C - 60 reports/sec
50 - 80 reports/sec
64 - 100 reports/sec
C8 - 200 reports/sec
(BH) = 01 H Set Scaling to 1:1

(BH) = 02H Set Scaling to 2:1
(AL) = 07H Device Driver Far Call
Setting the segment and offset to all O's cancels the device
driver.
(ES) = Segment pointer
(SX) = Offset pointer
5-48 System BIOS. tNT 15H

Interrupt 16H - Keyboard
(AH) = OOH Keyboard Read

The ASCII characters and the scan code are extracted from the
buffer (40:1 E for a length of 32 bytes). The keyboard buffer
pointer (word at 40:1A) is increased by 2 or reinitialized to the
start of the buffer if the pointer is already at the end.
This function returns control only upon a keystroke being avail-

able; the keystroke is removed from the buffer. If no keystroke is
available, Device Busy (INT 15H, (AX) = 9002H) is called to tell
the operating system that a keyboard loop is about to take place,
allowing the operating system to perform another task. Eventu-
ally, the keyboard interrupt (INT 09) calls Interrupt Complete (INT
15H, (AX) = 9102H) to Post the operation complete.
ON RETURN:
(AH) - Scan code
(AL) - ASCII character
(AH) = 01 H Keystroke Status
The keystroke is not removed from the buffer.

ON RETURN:
(ZF) = Set if no code is available
= Clear if code is available
If code is available:
(AH) - Scan code
(AH) = 02H Shift Status
The bits in AL are set for the following conditions.

ON RETURN:
(AL) - Shift status
Bit 7 - Insert locked
Bit 6 - Caps locked
Bit 5 - Nums locked
Bit 4 - Scroll locked
Bit 3 - Alt key pressed
Bit 2 - Ctrl key pressed
Bit 1 - Left shift key pressed
Bit e - Right shift key pressed
System BIOS, INT i6H 5-49

(AH) = 03H Set Typematlc Rate
(AL) = 05H Set Typematlc Rate and Delay
If the typematic rate or delay is not within the supported

range, the function returns with no action taken.
(BH) - Delay value
(BL) - Typematic rate
Value Value Value

In BL Char/Sec in BL Char/Sec in BL Char/Sec
00 30.0 OB 10.9 16 4.3

01 26.7 OC 10.0 17 4.0
02 24.0 00 9.2 18 3.7
03 21.8 OE 8.6 19 3.3
04 20.0 OF 8.0 1A 3.0
05 18.5 10 7.5 1B 2.7
06 17.1 11 6.7 1C 2.5
07 16.0 12 6.0 10 2.3
08 15.0 13 5.5 1E 2.1
09 13.3 14 5.0 1F 2.0
OA 12.0 15 4.6
Value
inBH Delay Value
0 250 ms
1 500 ms
2 750 ms
3 1000 ms
(AH) = 05H Keyboard Write
This function places an ASCII character scan code combination in

the keyboard buffer as if that key had been pressed.
(CL) - ASCII character
(CH) - Scan code
ON RETURN:
(AL) = 00 Successful operation
= 01 Buffer full
5-51) System BIOS, INT 16H

(AH) = 10H Extended Keyboard Read
The ASCIl character and the scan code are extracted from the
buffer (40:1E for a length of 32 bytes). The keyboard buffer
pOinter (word at 40:1A) is increased by 2 or reinitialized to the
start of the buffer if the pointer is already at the end.
This function returns control only upon a keystroke being avail-

able; the keystroke is removed from the buffer.
ON RETURN:
(AL) - ASCII Character
(AH) - Scan code
(AH) = 11 H Extended Keystroke Status
This function does not remove the keystroke from the buffer.
ON RETURN:
(ZF) = Set if no code is available
= Clear if code is available
If code is available:
(AH) - Scan code

(AH) = 12H Extended Shift Status
The bits in AL and AH are set for the following conditions. Only
AX and the flags are changed. All other registers are preserved.
ON RETURN:
(AL) - Shift status
Bit 7 - Insert locked
Bit 6 - Caps locked
Bit 5 - Nums locked
Bit 4 - Scroll locked
Bit 3 - Alt key pressed
Bit 2 - Ctrl key pressed
Bit 1 - Left shift key pressed
Bit 0 - Right shift key pressed
(AH) - Extended shift status

Bit 7 - SysRq key pressed
Bit 6 - Caps Lock key pressed
Bit 5 - Num Lock key pressed
Bit 4 - Scroll Lock key pressed
Bit 3 - Right Alt key pressed
Bit 2 - Right Ctrl key pressed
Bit 1 - Left Alt key pressed
Bit 0 - Left Ctrl key pressed
5·52 System BIOS, INT 16H

Interrupt 17H - Printer
These routines provide printer support. When the printer is busy,

BIOS calls Device Busy (INT 15H, AX = 90FEH) to tell the oper-
ating system that a time out loop is about to begin.
(AH) = OOH Print Character

(AL) - Character to print
(OX) - Printer to be used (0,1.2) corresponding
to actual values in PRINTER_BASE area
ON RETURN:
(AH) - Status
Bit 7 - Not busy
Bit 6 - Acknowledge
Bit 5 - Out of paper
Bit 4 - Selected
Bit 3 - I/O error
Bit 2.1 - Unused
Bit 0 - Time out
(AH) = 01 H Initialize the Printer Port

(OX) - Printer to be used (0. 1, 2) corresponding to
actual values in PRINTER_BASE area
ON RETURN:
(AH) - Status - same as function 00
(AH) = 02H Read Status
(OX) = Printer to be used (0.1.2) corresponding to

actual values in PRINTER_BASE area
ON RETURN:
(AH) - Status - same as function 00
(AH) = 03H - FFH Reserved

Interrupt 19H - Bootstrap Loader
Track 0, sector 1 is read into the boot location (segment 0 offset 7COO)
and control is transferred there with the following values:
(CS) = 00H
(Ip) = 7C00H
(DL) = Drive that boot sector was read from
If there is a hardware error, control is transferred to the ROM BASIC

entry point.

Interrupt 1AH - Time of Day
(AH) = OOH Read System Time Counter
This function causes the timer overflow flag to be reset to O.

Timer counts occur at the rate of 1,193,180/65,536 counts per
second, or about 18.2 per second.
ON RETURN:
(CX) = High portion of count
(DX) = Low portion of count
(AL) = 0 if timer has not passed 24 hours worth
of counts since power-on, last system time
counter read or write
> 0 if timer has passed 24 hours worth of
counts since power-on, last system time
counter read or write
(AH) = 01 H Set System Time Counter

This function causes timer overflow flag to be reset to O. Timer
counts occur at the rate of 1,193,180/65,536 counts per second, or
about 18.2 per second.
ON RETURN:
(CX) - High portion of count
(DX) - Low portion of count
(AH) = OAH Read System Day Counter

ON RETURN:
(CX) = Count of days since 1-1-1980
(AH) = OSH Set System Day Counter

(CX) = Count of days since 1-1-1980
(AH) = OCH - FFH Reserved
ON RETURN:
(CY) - Set for invalid function request
System BIOS, INT 1AH 5-55

BIOS Data Area and Locations
The IBM BIOS routines use 256 bytes of memory from absolute
address hex 400 to 4FF.
Address Function
40:0 COM1 Port Address (Word)

40:8 LPT1 Port Address (Word)

40:A LPT2 Port Address (Word)
40:C LPT3 Port Address (Word)
40:E Extended BIOS Data Area Segment (Word)
40:10 Equipment Word (Word)

15,14 Number of Printers Attached
13,12 Reserved
11-9 Number of RS-232C Cards Attached
8 Reserved
7,6 Number of Diskette Drives
5,4 Initial Video Mode
00 = Unused
01 = 40-by-25 Color
10 = 80-by-25 Color
11 = 80-by-25 Monochrome
3 Reserved
2 Mouse Present
1 Coprocessor Installed
o IPL Diskette Installed
40:12 Reserved
40:13 Memory Size in K Bytes (Word)
40:15 Reserved
40:16 BIOS Control Flags
40:17 Keyboard Flags (Byte)

Alt and Ctrl bits are set if Alt or Ctrl keys are pressed.
7 Insert Locked
6 Caps Locked
5 Nums Locked
4 Scroll Locked
3 Alt Key Depressed
2 Ctrl Key Depressed
1 Left Shift Key Depressed
o Right Shift Key Depressed
5-56 System BIOS, Data Area

Address Function
40:18 Keyboard Flags 1 (Byte)

7 Insert Key Pressed
6 Caps Lock Key Pressed
5 Num Lock Key Pressed
4 Scroll Lock Key Pressed
3 Pause Locked
2 SysRq Key Pressed
1 Left Alt Key Pressed
o Left Ctrl Key Pressed
40:19 Storage For Alternate Keypad Entry (Byte)
40:1A Pointer To Buffer Head Within Data Segment 40 (Word)
40:1C Pointer To Buffer Tail Within Data Segment 40 (Word)
40:1E Keyboard Buffer (32 Bytes)
40:3E Drive Recalibration Status (Byte)

7 Working Interrupt Flag Always 0 on Return from Diskette
BIOS
3 Recalibrate Drive 3
o Recalibrate Drive 0
40:3F Motor Status (Byte)
7 Write Operation if Set
3 Drive 3 Motor On
2 Drive 2 Motor On
1 Drive 1 Motor On
o Drive 0 Motor On
40:40 Motor Off Counter (Byte), Decremented by Timer. When 0, All
Drive Motors Turned Off
40:41 Status of Last Diskette Operation (Byte)
80 - Time Out
40 - Seek Failure
20 - General Controller Failure
10 - CRC Error
OC - Unsupported Track, Sectors/Track Combination
09 - DMA Boundary Error
08 - DMA Failure
06 - Media Has Been Changed
04 - Sector Not Found
03 - Write Protect Error
02 - Bad Address Mark
01 - Invalid Function Request
00 - No Error
40:42 Status Returned from Controlier (7 Bytes)
40:49 Current CRT Mode (Byte)
See Interrupt 10H
40:4A Number of Columns on Screen (Word)
40:4C Regen Buffer Length in Bytes (Word)
40:4E Starting Address Offset of Regen Buffer (Word)
40:50 Cursor Position Page 1 (Word)

System BIOS, Data Area 5-57

Address Function

40:5A Cursor Position Page 6 (Word)
40:5C Cursor Position Page 7 (Word)
40:5E Cursor Position Page 8 (Word)
40:60 Cursor Mode (Word)

40:60 End Line for Cursor
40:61 Start Line for Cursor
40:62 Current Page being Displayed (Byte)

40:63 Base Port Address for Active Display (Word)
40:65 Current Setting of the 3-by-8 Register (Byte) Mirror Image
Written to Base Port Address + 4 for Set Mode
40:66 Current Palette Setting Color Card (Byte) Mirror Image Written to
Base Port Address + 5
40:67 - 6B Reserved
40:6C Timer Counter Low Word,High Word (DWord) Increased Approxi-
mately 18 Times per Second
40:70 Timer Overflow (Byte)

Not 0 = Timer Counted Past 24 Hours
0= NOT
40:71 BIOS Break Flag (Byte)

Bit 7 - Set if Break Key Pressed
40:72 Reset Flag (Word), If Hex 1234, Then No Need to Test Memory on
POST
40:74 Status of Last Disk Operation (Byte)
FF - Sense Operation Failed

EO - Status Error/Error Reg = 0
CC - Write Fault On Selected Drive
BB - Undefined Error Occurred
AA - Drive Not Ready
80 - Time Out
40 - Seek Failure
20 - General Controller Failure
11 - ECC Corrected Data Error
10 - Bad ECC on Disk Read
OE - Controlled Data Address Mark Detected
OD - Invalid Number of Sectors on Format
OB - Bad Track Detected
OA - Bad Sector Flag Detected
09 - DMA Boundary Error
08 - DMA Failure
07 - Drive Parameter Activity Failed
05 - Reset Failed
04 - Sector Not Found
03 - Write Protect Error
02 - Bad Address Mark
01 - Invalid Function Request
00 - No Error
5-58 System BIOS, Data Area

Address Function
40:75 Number of Fixed Disks Attached to System (Byte)
40:76 Reserved
40:77 Reserved
40:78 LPT1 Timeout Value (Byte)
40:79 LPT2 Timeout Value (Byte)
4O:7A LPT3 Timeout Value (Byte)
4O:7B Reserved
4O:7C COM1 Timeout Value (Byte)
40:70 COM2 Timeout Value (Byte)
4O:7E COM3 Timeout Value (Byte)
40:7F COM4 Timeout Value (Byte)
40:80 Start of Keyboard Buffer within Data Segment 40 (Word)

40:82 End of Keyboard Buffer within Data Segment 40 (Word)
40:84 Rows on the Screen (Byte)

40:85 Bytes per Character (Word)
40:87 Mode Options (Byte) = 00
40:88 Reserved
40:89 7-5 Reserved

4 1 - 8-by-16 Text Font
0- 8-by-8 Text Font
3 0 - Default Palette Loading Enabled
2 0 - Color Monitor Attached
1 - Monochrome Attached
Video Summing Enabled
o Reserved
4O:8A Display Combination Code
OB = BW Analog
OC = Color Analog
4O:8B Last Diskette (Byte)
Bits 7,6 Data Rate Selected
00 = 500K bps
01 = Reserved
10 = 250K bps
11 = Reserved
Bits 5,4 Step Rate Time Selected
00 = for SRT = OC
01 = for SRT = 00
10 = for SRT = OA
11 = Reserved
4O:8C Fixed Disk Status Returned by Controller (Byte)

40:80 Fixed Disk Error Returned by Controller (Byte)
40:8E Reserved =00
40:8F Reserved
System BIOS, Data Area 5-59

Address Function
40:90 Media State Drive 0 (Byte)

40:91 Media State Drive 1 (Byte)
Bit Description For 40:90 and 40:91
7,6 Data rate
00 - 500K bps
01 - Reserved
10 - 250K bps
11 - Reserved
5 Reserved
4 0 - Media/Drive Unestablished
3 Reserved
2-0 Reserved = 111 B
40:93 Reserved
40:94 Track Currently SEE Ked to, Drive 0 (Byte)
40:95 Track Currently SEEKed to, Drive 1 (Byte)
40:96 Keyboard Type (Byte)

7 Read ID in Process
6 Last Character was First ID Character
5 Force Num Lock if Rd ID and KBX
4 101/102-key Keyboard Installed
3 Right Alt Key Pressed
2 Right Ctrl Key Pressed
1 Last Code was EO Hidden Code
o Last Code was E1 Hidden Code
40:97 Keyboard LED Flags (Byte)
40:98 Pointer to Users Wait Flag (DWord)
40:9C User Timeout Value Low Word, High Word (DWord) in Microsec-
onds
40:AO Reserved
40:A1-A3 Reserved
40:A4-A7 Saved Fixed Disk Interrupt Vector
40:A8-AB Pointer to Alternate Parameter Table (Video)

40:AC-CD Reserved
40:CE Day Counter (Word)
40:DO-EF Reserved
40: FO-FF Reserved for User
50:00 Print Screen Status Byte
5·60 System BIOS, Data Area

Extended BIOS Data Area
Power-on Self Test (POST) allocates the highest possible 1K of

memory below 640K to be used as the extended data area. The word
pointer at 40:0E in the BIOS data area points to the segment. The first
byte in the extended BIOS data area is initialized to the length, in K
bytes, allocated. The data area within the allocated segment is:
Offset Function
(Hex)
00 Number of bytes allocated in multiples of K (Byte)
01-21 Reserved
22-2F POinting device interface BIOS data area (14 Bytes)
22 Device Driver Far Call Offset (Word)
24 Device Driver Far Call Segment (Word)
26 Pointing Device Flag (1st Byte)
7 Command in Progress
6 Resend
5 Acknowledge
4 Error
3 Reserved = 0
2-0 Index Count
27 Pointing Device Flag (2nd Byte)
7 Device Driver Far Call flag
6-3 Reserved
2-0 Package Size
28 - 2F Reserved
System BIOS, Extended Data Area 5-61

ROM Tables
The following tables are located in ROM.
Fixed Disk Parameter Table
The following shows the table format and the table entries for the
fixed disk.
Offset Size Function

(Hex)
o Word Maximum number of cylinders
2 Byte Maximum number of heads
3 Word Reserved
5 Word Starting write precompensation cylinder
7 Byte Not used
8 Byte Control byte
9 Byte Reserved
A Byte Reserved
B Byte Reserved
C Word Landing zone
E Byte Number of sectors/track
F Byte Reserved
5-62 System BIOS, ROM Tables

Type Cyls Heads Precomp Landing Zone
at Cyl
0 Indicates No Fixed Disk Installed

1 306 4 128 305
2 615 4 300 615
3 615 6 300 615
4 940 8 512 940
5 940 6 512 940

6 615 4 None 615
7 462 8 256 511
8 733 5 None 733
9 900 15 None 901
10 820 3 None 820
11 855 5 None 855
12 855 7 None 855
13 306 8 128 319
14 733 7 None 733
15 Indicates Parameters in Expanded Table
16 612 4 0 663
17 977 5 300 977
18 977 7 None 977
19 1024 7 512 1023
20 733 5 300 732
21 733 7 300 732
22 733 5 300 733
23 306 4 None 336
24 612 4 305 663
25 306 4 None 340
26· 612 4 None 670
27-255 Reserved
Type for IBM Personal System/2 20 MB Fixed Disk Drive and Controller.
System BIOS, ROM Tables 5-63

Asynchronous Baud Rate Initialization Table
Offset Size Funciion

(Hex)
0 Word Init value for 110 Baud
6 Word Init value for 600 Bal,ld
A Word Init value for 2400 Baud
C Word Init value for 4800 Baud
E Word Init value for 9600 Baud
Diskette Parameter Table
onset Size Function

(Hex)
0 Byte First specify byte
1 Byte Second specify byte
2 Byte Number of timer ticks to wait prior to turning
diskette motor off
3 Byte Number of bytes/sector
= 0 128 bytes/sector
4 Byte Sectors/track
5 Byte Gap length
6 Byte Data length
7 Byte Gap length for format
8 Byte Fill byte for format
9 Byte Head settle time in ms
A Byte Motor startup time in 1/8 seconds
5-64 System BIOS, ROM Tables

Model Byte
The model byte is located at FOOO:FFFE in ROM. Use the read system
configuration parameters (INT 15H, (AH) = COH) to find the model
and submodel byte. For the IBM Personal System/2 Model 25, the
model byte is hex FA and the submodel byte is 01.
System BIOS, Model Bytes 5·65

Notes:
5-66 System BIOS, Model Bytes

SECTION 6. Instruction Set
8086 Register Model .................................... 6-3

Notes ............................................ 6-4
8086 Instruction Set .................................... 6-7
Data Transfer ...................................... 6-7
Arithmetic ........................................ 6-9
Logic ........................................... 6-13
String Manipulation ................................ 6-15
Control Transfer .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-15
Instruction Set Matrix .............................. 6-22
8087 Coprocessor Instruction Set ........................ 6-24
Notes ........................................... 6-24
Data Transfer ..................................... 6-24
Comparison ...................................... 6-26
Arithmetic ....................................... 6-26
Transcendental ................................... 6-28
Constants ........................................ 6-29
Instruction Set 6-1

Notes:
6-2 Instruction Set

8086 Register Model
AX: AH AL Accumulator
BX: BH BL Base
CX: CH CL Count
DX: DH DL Data
General Register File
SP Stack Pointer
BP Base Pointer
SI Source Index
DI Destination Index
IP Instruction Pointer
FLAGSH FLAGSL Status Flags
CS Code Segment
DS Data Segment
Segment Register File
SS Stack Segment
ES Extra Segment
Figure 6-1. 8086 Register Model
Instruction Set 6-3

Flag Register
Bit Function
15 to 12 Don't Care
11 Overflow Flag
10 Direction Flag
9 Interrupt Enable Flag
8 Trap-Single Step Flag
7 Sign Flag
6 Zero Flag
5 Don't Care
4 Auxiliary Carry - BCD
3 Don't Care
2 Parity Flag
1 Don't Care
o Carry Flag
Figure 6-2. Flag Register
Notes
1. If d = 1, then "to"; if d = 0, then "from."

2. If w = 1, then word size; if w = 0, then byte size.
3. If sw = 01, then 16 bits of immediate data from the operand.
4. If sw = 11, then an immediate data byte is sign extended to form
the 16-bit operand.
5. If v = 0, the "count" = 1; if v = 1, the "count" is in (Cl) or (CX).
6. x = don't care.
7. z is used for string primitives for comparison with zero flag.
6-4 Instruction Set

Segment Override Prefix
001reg110
Operand Register Defaun With Prefix
IP (Code Address) CS Never

SP (Stack Address) CS Never
BP (Stack Address or Stack Marker) 55 BP + OS or ES, or CS
51 or 01 (not including strings) OS ES, 55, or CS
51 (Implicit Source Address for strings) OS ES, 55, orCS
01 (Implicit Destination Address for E·S Never
strings)
Figure 6-3. Segment Override Prefix
reg Field Assignments
16-Blt 8-Blt Segment
000 AX 000 AL 00 ES
001 CX 001 CL 01 CS
010 OX 010 OL 10 55
011 BX 011 BL 11 OS
100SP 100 AH
101 BP 101 CH
110 51 110 OH
111 01 111 BH
Figure 6-4. reg Field Assignment
Instruction Set 6-5

Second Instruction Byte
I mod xxx rIm
mod Displacement
00 OISP = 0*, disp-Iow and disp-high are absent

01 OISP = disp-Iow sign-extended to 16-bits, disp-high is absent
10 OISP = disp-high: disp-Iow
11 DISP = rIm is treated as a "reg" field
OISP follows 2nd byte of instruction (if required)

* If mod = 00 and rIm = 110, then Effective Address = disp-high:disp-Iow.
Figure 6-5. mod Field Assignment
rim Operand Address
000 (BX) + (SI) + OISP

001 (BX) + (01) + OISP
010 (BP) + (SI) + DISP
011 (BP) + (01) + OISP
100 (SI) + DISP
101 (01) + OISP
110 (BP) + DISP
100 (BX) + OISP
Figure 6-6. rIm Field Assignments
6-6 Instruction Set

8086 Instruction Set
Data Transfer
MOV = Move
Register/Memory to/from Register

1100010dw Lmod reg rim
Immediate to Register/Memory
1 1100011w 1 mod 000 rim 1 data 1 data if w = 1
Immediate to Register
11011wreg 1 data 1 data if w = 1
Memory to Accumulator
11010000W 1 addr-Iow 1 addr-high
Accumulator to Memory
11010001W 1 addr-Iow 1 addr-high
Register/Memory to Segment Register

110001110 1 mod 0 reg rim 1
Segment Register to Register/Memory

110001100 1 mod 0 reg rim 1
PUSH = Push
Register/Memory
111111111 mod 110 rIm
Register
1 01010reg
Instruction Set 6-7

Segment Register
1 000reg110 1
POP = Pop
Register/Memory
110001111 1 mod 000 rIm
Register
1 01011reg
Segment Register
1 000reg111 1
XCHG = Exchange
Register/Memory with Register

11000011W 1 mod reg rIm
Register with Accumulator

110010reg 1
IN = Input to AL/AX from
Fixed Port
1 1110010w 1 port
Variable Port
1 1110110w
OUT = Output from ALI AX to

Fixed Port
1 1110011w 1 port
Variable Port (OX)

1 1110110w 1
6-8 Instruction Set

XLAT = Translate Byte to AL
111010111
LEA = Load EA to Register
110001101 1 mod reg rIm
LDS = Load Pointer to DS
111000101 1 mod reg rIm
LES = Load Pointer to ES
111000100 I mod reg rIm

LAHF = Load AH with Flags
110011111
SAHF = Store AH with Flags
110011110
PUSHF = Push Flags
110011100
POPF = Pop Flags
110011101
Arithmetic
ADD = Add
RegisterlMemory with Register to Either

1 OOOOOOdw 1 mod reg rIm 1
Immediate to RegisterlMemory
1100000sw I mod 000 rIm I data I data if sw = 01
Instruction Set 6-9

Immediate to Accumulator
I 0000010w I data I data if w = 1
ADC = Add with Carry

Register/Memory with Register to Either
I 000100dw I mod reg rIm I
I 100000sw I mod 010 rIm I data I data if sw = 01
INC = Increment
Register/Memory
I 1111111w I mod 000 rIm
Register
I 01000reg
AAA = ASCII Adjust for Add
I 00110111
DAA = Decimal Adjust for Add
I 00100111
SUB = Subtract
Register/Memory and Register to Either
Immediate from Register/Memory
1100000SW I mod 010r/m I data I data if sw = 01
6-10 Instruction Set

Immediate from Accumulator
I 0010110w I data I dataifw= 1
SBB = Subtract with Borrow

Immediate from Register/Memory
1100000sw I mod 011 rIm I data I data if sw = 01
DEC = Decrement
Register/Memory
I ll11111w mod 001 rIm
Register
I 01001reg
NEG = Change Sign
I 1111011w I mod 011 rIm

CMP = Compare
Register/Memory and Register

I 001110dw I mod reg rIm
Immediate with Register/Memory
1100000SW I mod 111 rIm I data I data if sw = 01
Immediate with Accumulator
Instruction Set 6-11

AAS = ASCII Adjust for Subtract
! 00111111
DAS = Decimal Adjust for Subtract
! 00101111
MUL = Multiply (Unsigned)
!1111011w 1 mod 100 rIm
IMUL = Integer Multiply (Signed)
!1111011W 1 mod 101 rIm
AAM = ASCII Adjust for Multiply
111010100 1 00001010
DIV = Divide (Unsigned)
1 1111011w 1 mod 110 rIm
IDIV = Integer Divide (Signed)
1 1111011w 1 mod 111 rIm
AAD = ASCII Adjust for Divide
1 11010101 1 00001010
CBW = Convert Byte to Word
110011000
CWD = Convert Word to Double Word
1 10011001

Logic
NOT = Invert Reglster/Memory
I 1111011w I mod 010 rIm

SHL/SAL = Shift Loglcal/Arlthmetlc Left
I 110100Vw I mod 100 rIm

SHR = Shift Logical Right
I 110100vw I mod 101 rIm

SAR = Shift Arithmetic Right

ROL = Rotate Left

ROR = Rotate Right

RCL = Rotate through Carry Left

RCR = Rotate through Carry Right

AND = And

I ool000dw I mod reg rIm I
11000oo0W I mod 100 rIm I data I data if w = 1

I 0010010w I data data if w = 1
TEST = AND Function to Flags; No Result
RegisterlMemory and Register

I 100001 Ow I mod reg rIm
Immediate Data and Register/Memory
I 1111011w I mod 000 rim I data I data if w = 1
Immediate Data and Accumulator

11010100W data data if w = 1
OR = Or
RegisterlMemory and Register to Either
I 000010dw I mod reg rim I
11000000W I mod 001 rIm data I data if w = 1
XOR = Exclusive Or
11000000W I mod 110 rim data data if w = 1
I 0011010w data I data if w = 1

String Manipulation
REP = Repeat
1 1111001z
MOVS = Move String
11010010W
CMPS = Compare String
11010011W
SCAS = Scan String
11010111W
LODS = Load String
11010110w
STOS = Store String
11010101W
Control Transfer
CALL = Call
Direct within Segment

111101000 1 disp-Iow 1 disp-high
Indirect within Segment

111111111 1 mod 010 rIm
Direct Intersegment
10011010 offset-low offset-high
seg-Iow seg-high

Indirect Intersegment
111111111 1 mod 011 rIm
JMP == UncondHlonal Jump
Direct within Segment-Short

111101011 1 disp
Indirect within Segment

111111111 1 mod 100 rIm
Direct Intersegment
11101010 offset-low offset-high
seg-Iow seg-high
Indirect Intersegment
111111111 1 m9d 101 rIm
RET == Return from Can
Within Segment
111000011
Within Segment Adding Immediate to SP

111000010 1 data-low 1 data-high
Intersegment
111000011
Intersegment Adding Immediate to SP

111000010 1 data-low 1 data-high
JE/JZ == Jump on EquallZero
1 01110100 1 disp

JLlJNGE = Jump on Less/Not Greater, or Equal
I 01111100 I disp
JLE/JNG = Jump on Less, or Equal/Not Greater
101111110 I disp
JB/JNAE = Jump on Below/Not Above, or Equal
I 01110010 I disp
JBE/JNA = Jump on Below, or Equal/Not Above
I 01110110 I disp
JP/JPE = Jump on Parity/Parity Even
I 01111010 I disp
JO = Jump on Overflow
I 01110000 I disp
JS = Jump on Sign
I 01111000 I disp
JNE/JNZ = Jump on Not Equal/Not Zero
I 01110101 I disp
JNLlJGE = Jump on Not Less/Greater, or Equal
I 01111101 I disp
JNLE/JG = Jump on Not Less, or Equal/Greater
I 01111111 I disp

JNB/JAE = Jump on Not Below/Above, or Equal
101110011 1 disp
JNBE/JA = Jump on Not Below, or Equal/Above
101110111 1 disp
JNP/JPO = Jump on Not Parity/Parity Odd
101111011 1 disp
JNO = Jump on Not Overflow
1 01110001 1 disp
JNS = Jump on Not Sign
101111001 1 disp
LOOP = Loop CX Times
1 11100010 1 disp
LOOPZ/LOOPE = Loop while Zero/Equal
111100001 1 disp
LOOPNZ/LOOPNE = Loop while Not Zero/Not Equal
111100000 1 disp
JCXZ = Jump on CX Zero
111100011 1 disp

Instruction Condition Interpretation
JE orJZ ZF = 1 "equal" or "zero"
JL or JNGE (SF xor OF) = 1 "less" or "not greater or equal"
JLE or JNG ((SF xor OF) or ZF) "less or equal" or "not greater"
= 1
JB or JNAE or JC CF = 1 "below" or "not above or
equal"
JBE or JNA (CF or ZF) = 1 "below or equal" or "not
above"
JP or JPE PF = 1 "parity" or "parity even"
JO OF = 1 "overflow"
JS SF = 1 "sign"
JNE or JNZ ZF = 0 "not equal" or "not zero"
JNL or JGE (SF xor OF) = 0 "not less" or "greater or equal"
JNLE or JG ((SF xor OF) or ZF) "not less or equal" or "greater"
= 0
JNB or JAE or JNC CF = 0 "not below" or "above or
equal"
JNBE or JA (CF or ZF) = 0 "not below or equal" or
"above"
JNP or JPO PF = 0 "not parity" or "parity odd"
JNO OF = 0 "not overflow"
JNS SF = 0 "not sign"
"Above" and "below" refer to the relation between two unsigned values, while
"greater" and "less" refer to the relation between two signed values.
Figure 6-7. Conditional Transfer Operations
INT = Interrupt
Type Specified
111001101 1 Type
Type 3
111001100
INTO = Interrupt on Overflow
111001110
IRET = Interrupt Return
11001111

Processor Control
CLC = Clear Carry
111111000
STC = Set Carry
111111001
CMC = Complement Carry
111110101
NOP = No Operation
110010000
CLD = Clear Direction
111111100
STD = Set Direction
111111101
CLI = Clear Interrupt
111111010
STI = Set Interrupt
1111 11011
HLT = Halt
111110100

WAIT = Walt
110011011
LOCK = Bus lock prefix
111110000
ESC = Escape (to 8087)
1 11011xxx 1 mod xxx rim

Instruction Set Matrix
LO o 2 3 4 5 6 7
HIO ADD ADD ADD ADD ADD ADD PUSH POP

b,l,r/m W I,r/m b,t,r/m w,t,r/m b,ia w,ia ES ES
ADC ADC ADC ADC ADC ADC PUSH POP

b,l,r/m w,l,r/m b,t,r/m w,t,r/m b,i w,i SS SS
2 AND AND AND AND AND AND OEG OAA

b,l,r/m w,l,r/m b,t,r/m w,t,r/m b,i w,i =ES
3 XOR XOR XOR XOR XOR XOR SEG AAA

b,l,r/m w,l,r/m b,t,r/m w,t,r/m b,i w,i =S+
4 INC INC INC INC INC INC INC INC

AX CX OX BX SP BP SI 01
5 PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH

7 JO JNO JBI JNBI JEI JNEI JBEI JNBEI

JNAE JAE JZ JNZ JNA JA
8 Immed Immed Immed Immed TEST TEST XCHG XCHG

b,r/m w,r/m b,r/m is,rlm b,r/m w,r/m b,r/m w,r/m
9 NOP XCHG XCHG XCHG XCHG XCHG XCHG XCHG

CX OX BX SP BP SI 01
A MOV MOV MOV MOV MOVS MOVS CMPS CMPS

mAL mAL ALm ALm b W b W
B MOV MOV MOV MOV MOV MOV MOV MOV

i AL i CL i OL i BL iAH iCH i OH i BH
C RET RET LES LOS MOV MOV

(I+SP) b,i,r/m w,i,r/m
o Shift Shift Shift Shift AAM AAO XLAT

b W b,v w,v
E LOOPNZI LOOPZI LOOP JCXZ IN IN OUT OUT

LOOPNE POOPE b W b W
F LOCK REP REP HLT CMC Grp 1 Grp 1

z b,r/m w,r/m
Code Definition Code Definition
b Byte m Memory
d Direct rIm EA is Second Byte
i Immediate si Short, Intrasegment
ia Immed. to Accum. t To CPU Register
id Indirect v Variable
is Immed. Byte, Sign w Word
Ext.
Long. Intersegment z Zero

LO 8 9 A B C o E F
HID OR OR OR OR OR PUSH
b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,i w,i CS
SBB SBB SBB SBB SBB SBB PUSH POP

b,f,r/m w,f,r/m b,t,r/m w,t, rIm b,i w,i OS OS
2 SUB SUB SUB SUB SUB SUB SEG= OAS

3 CMP CMP CMP CMP CMP CMP SEG= AAS

4 DEC DEC DEC DEC DEC DEC DEC DEC

5 POP POP POP POP POP POP POP POP

7 JS JNS JPI JNPI JLI JNLI JLEI JNLEI

JPE JPO JNGE JGE JNG JG
8 MOV MOV MOV MOV MOV LEA MOV POP

b,f,r/m w,f,r/m b,t,r/m w,t,r/m sr,t,r/m sr,f.r/m rIm
9 CBW CWO CALL WAIT PUSHF POPF SAHF LAHF
CX I,d BX SP BP SI 01
A TEST TEST STOS STOS LOOS LOOS SCAS SCAS

b,i w,i b W b W b W
B MOV MOV MOV MOV MOV MOV MOV MOV

iAX iCX iOX iBX i SP iBP iSI iOI
C RET RET INT INT INTO IRET

I,(I+SP) I Type 3 (Any)
o ESC ESC ESC ESC ESC ESC ESC ESC

0 1 2 3 4 5 6 7
E CALL JMP JMP JMP IN IN OUT OUT
d d I,d si,d v,b V,W v,b V,W
F CLC STC CLI STI CLO STO GRP2 GRP3

b,r/m w,r/m
Where: mod xxx rIm

XXX 000 001 010 011 100 101 110 111
Immed ADD OR ADC SBB AND SUB XOR CMP
Shift ROL ROR RCL RCR SHLISAL SHR -- SAR
Grp 1 TEST - NOT NEG MUL IMUL DIV DIV
Grp 2 INC DEC CALL CALL JMP
id I,id id
JMP
I,id
PUSH --

8087 Coprocessor Instruction Set
Notes
MF = Memory format
00 - 32-bit Real
01 - 32-bit Integer
10 - 64-bit Real
11 - 64-bit Integer
ST(O) = Current Stack top

STeil = ilh register below Stack top
d = Destination
o-Destination is ST(O)
l-Destination is ST(i)
P = POP
o-No Pop
l-Pop ST(O)
R = Reverse
o-Destination (op) Source

l-Source (op) Destination
For FSQRT: -O::;;ST(O)::;; + 00

For FSCALE: -215::;;ST(1) < +215 and ST(l) interger
For F2XM1: 0 ::;;ST(O) ::;;2-1
For FYL2X: O<St(O) < 00 - 00 <ST(l) < + 00
For FYL2XP1: 0< IST(O)I < (2-..}2)/2 - 00 <ST(l) < 00
For FPTAN: O::;;ST(O) <1t/4
For FPATAN: O::;;ST(O)<ST(l)< +00
The following is an instruction set summary for the 8087 coprocessor.

In the following, the bit pattern for escape is 11011.
Data Transfer
FLD = Load
Integer/Real Memory to ST(O)
I escape MF 1 I mod 000 rIm I disp-Iow I disp-high
Long Integer Memory to ST(O)
I escape 111 I mod 101 rIm I disp-Iow I disp-high

Temporary Real Memory to 8T(0)
BCD Memory to 8T(0)
8T(I) to 8T(0)
I escape 001 11 ooo8T(i)
FST = Store
8T(0) to Integer/Real Memory
8T(0) to 8T(i)
I escape 101 11 0108T(i)
FSTP = Store and Pop

8T(0) to Integer/Real Memory
8T(0) to Long Integer Memory
8T(0) to Temporary Real Memory
8T(0) to BCD Memory
8T(0) to 8T(i)
I escape 101 11 011 8T(i)
FXCH = Exchange ST(I) and ST(O)
I escape 001 11 oo18T(i)

Comparison
FCOM = Compare

ST(i) to ST(O)
I escape 000 11 010 ST(i)
FCOMP = Compare and Pop

ST(i) to ST(O)
I escape 000 11 011 ST(i)
FCOMPP .., Compare ST(I) to ST(O) and Pop Twice
I escape 110 I 11 011001
FTST = Test ST(O)
I escape 001 I 11 100 100
FXAM = Examine ST(O)
I escape ~1 11 100 101
Arithmetic
FADD = Addition
Integer/Real Memory with ST(O)

I escape MF 0 I mod 000 rim I disp-Iow I disp-hlgh
ST(i) to ST(O)
I escape dP 0 11 OOOST(i)

FSUB = Subtraction
1 escape MF 0 1 mod lOR rIm 1 disp-Iow 1 disp-high
ST(i) to ST(O)
1 escape dP 0 11 10Rr/m
FMUL = Multiplication

1 escape MF 0 1 mod 001 rIm 1 disp-Iow 1 disp-high
ST(i) to ST(O)
1 escape dP 0 11 001 rIm
FDIV = Division

1 escape MF 0 1 mod l1R rIm 1 disp-Iow 1 disp-high
ST(i) to ST(O)
1 escape dP 0 1 l111R rIm
ST(i) to ST(O)
1 escape dP 0 1 l111R rIm
FSQRT = Square Root of ST(O)
1 escape 001 111111010
FSCALE = Scale ST(O) of ST(1)
1 escape 001 111111101
FPREM = Partial Remainder of ST(O) -T- ST(1)
1 escape 001 111111000

FRNDINT = Round ST(O) to Integer
1 escape 001 111111100
FXTRACT = Extract Components of ST(O)
1 escape 001 111110100
FABS = Absolute Value of ST(O)
1 escape 001 111100001
FCHS = Change Sign of ST(O)
1 escape 001 111100000
Transcendental
FPTAN = Partial Tangent of ST(O)
1 escape 001 111110010
FPATAN = Partial Arctangent of ST(O) + ST(1)
1 escape 001 111110011
F2XM1 = 2 ST(O) -1
1 escape 001 111110000
FYL2X = ST(1) x Log 2 ffIST(O)"
1 escape 001 111111001
FYL2XP1 = ST(1) X Log 2 ffIST(O) + 1"
1 escape 001 111111001

Constants
FLDZ == Load + 0.0 Into ST(O)
1 escape 001 111101110
FLD1 = Load + 1.0 Into ST(O)
1 escape 001 111101000
FLDP1 = Load 1t Into ST(O)
1 escape 001 111101011
FLDL2T = Load Log 2 10 Into ST(O)
1 escape 001 111101001
FLDLG2 = Load Log 10 2 Into ST(O)
1 escape 001 111101100
FLDLN2 = Load Log e 2 into ST(O)
1 escape 001 111101101
Processor Control
FINIT = Initialize NDP
1 escape 011 111100011
FENI = Enable Interrupts
1 escape 011 111100000
FDISI = Disable Interrupts
1 escape 011 111100001

FLDCW = Load Control Word
1 escape 001 1 mod 101 rim 1 disp-Iow 1 disp-high
FSTCW = Store Control Word
FSTSW = Store Status Word
FCLEX = Clear Exceptions
1 escape 011 111100010
FSTENV = Store Environment
FLDENV = Load Environment
FSAVE = Save State
FRSTOR = Restore State
FINCSTP = Increment Stack Pointer
1 escape 001 111110111
FDECSTP = Decrement Stack Pointer
1 escape 001 111110110

FFREE = Free ST(I)
1 escape 001 1 11000ST(i)
FNOP = No Operation
1 escape 001 111010000
FWAIT = CPU Walt for NDP
110011011

Notes:
6·32 Instruction Set

SECTION 7. Characters and Keystrokes
Character Codes ................................... 7-2

Table Notes ....................................... 7-7
Quick Reference ................................... 7-8
Characters and Keystrokes 7-1

Character Codes
Value As Characlers Value As Characlers
Hex Dec Symbol Keyslroke. Noles
18 24 I Ctrl X
19 25 I Ctrl Y
1A 26 - Ctrl Z
1B 27 - Ctrl [
Esc, Shift
Esc, Ctrl
Esc
1C 28 L- Ctrl
1D
1E
29
30
-&
CtrlJ
Ctrl6
Backspace,
1F 31 ... Ctrl-
20 32 Blank Space Bar,

Shift
Space Shift,
Backspace
Space,
Ctrl Space,
09 Ctrll
Alt Space
21 33 ! ! Shift
OA
22 34 " " Shift
23 35 # # Shift
24 36 $ $ Shift
25 37 % % Shift
26 38 & & Shift
27 39 Shift
28 40 ( ( Shift
29 41 ) )
2A 42 . . Note 1
2B 43 + + Shift
2C 44
2D 45 - -
2E 46 Note 2
7-2 Characters and Keystrokes

Value AIICha..cte,. Value All· Character.
He. Dec S,mbol Ke,.trOll.. Note. Hell Dac S,mbol Ke,.trok.. . Notes
2F 47 I I
48 75 K K Note 4
30 48 0 0 Note 3
4C 76 L L Note 4
31 49 1 1 Note 3
4D 77 M M Note 4
32 50 2 2 Note 3 4E 78 N N
33 51 3 3 Note 3 4F 79 0 0 Note 4
34 52 4 4 Note 3 50 60 P P Note 4
35 53 5 5 Note 3
51 81 Q Q Note 4
36 54 6 6 Note 3
52 62 R R Note 4
37 55 7 7 Note 3
53 63 S S Note 4
36 56 8 8 Note 3
54 64 T T Note 4
39 57 9 9 Note 3
55 85 U U Note 4
SA 58 : : Shift
56 86 V V Note 4
38 59 ; ;
57 87 W W Note 4
3C 60 < < Shift
58 88 X X Note 4
3D 61 = =
59 69 Y Y Note 4
3E 62 > > Shift
5A 90 Z Z Note 4
3F 63 ? ? Shift
58 91 [ [
40 64 @ @ Shift
5C 92 \ \ Note 4
41 65 A A Note 4
50 93 I I
42 68 8 8 Note 4
5E 94 1\ 1\ Shift
43 67 C C Note 4
44 68 0 0 Note·4
5F 85 - - Shift
45 69 E E Note 4
60 96 • •
61 97 a a Note 5
48 70 F F Note 4
47 71 62 98 b b Note 5
G G Note 4
48 72 63 99 c c Note 5
H H Note 4
64 100 d d Note 5
49 73 I I Note 4
4A 74 J J Note 4 85 101 e e Note 5
68 102 f f Note 5

Value Aa Character. Value Aa Character.
Hex Dec Symbol Keystroke. Nolas Hex Dec Symbol Kaystroka. Notea
67 103 9 80 128 C All 128 Nole6

9 Note 5
68 104 h h 81 129 ii All 129 Nole6

NOle5
69 105 i i 82 130 II All 130 Nole6

Note 5
6A 106 j j Nole5
83 131 A All 131 Nole6
68 k k 84 132 ii All 132 Nole6

107 Note 5
6C 106 I I Note 5
85 133 a All 133 Nole6
60 109 m m NOle5
86 134 a All 134 Nole6
6E n n 87 135 9 All 135 Nole6

110 Nole5
6F 111 0 0
68 138 A All 138 Note 6
NoteS
70 89 137 II Alt137 Note 6

112 P P Nole5
71 113 q q 8A 138 0) Alt138 Note 6

Nole5
72 114 r r 88 139 i Altl39 Note 6

Nole5
73 115 s s 8C 140 I Alt140 Nole6

Nole5
74 116 I I 80 141 1 Alt 141 Note 6

NoleS
75 117 u u Nole5 8E 142 A Altl42 Note 6
76 118 y y NOle5 8F 143 A Altl43 Nole6
77 119 w w Note 5 90 144 E All 144 Nole6
78 120 x x Nole5 91 145 sa Altl45 Note 6
79 121 Y Y Nole5 92 146 If:. All 146 Note 6
7A 122 z z Nole5 93 147 6 Alt147 Note 6
78 123 { { Shift 94 146 6 Altl46 Note 6
7C 124
I
I
I
I Shift 95 149 () Altl49 Note 6
70 125 } } 96 150 0 Alt150 Nole6

Shift
7E 126
- - Shift 97 151 0 Alt151 Note 6
Note 6
7F 127 D. Clrl- 98 152 Y Altl52
99 153 0 Altl53 NOle6
9A 154 0 Altl54 Note 6

Value Aa Characters Value As Characters
Hex Dec Symbol Keystrokes Notes Hex Dec Symbol Keystrokes Notes
B7 163
9B 155 ¢ Alt 155 Note 6 ---n All 183 Note 6
9C 156 £ Altl56 Note 6 B8 184

R Alt 184 Note 6
~
9D 157 ¥ Alt 157 Note 6 B9 185 Alt 185 Note 6
9E 158 Pt Alt 158 Note 6
9F 159 f Alt 159 Note 6 BA 186 Alt 186 Note 6
AO 160 a Alt 160 Note 6 BB 187 ==;-, Alt 187 Note 6
Al 161 I Alt 161 Note 6 BC 188 :::::J Alt 188 Note 6
A2 162 6 Alt 162 Note 6 BD 189

---.U Alt 189 Note 6
163 oj Alt 163

A3 Note 6
A4 164 II Alt 164 Note 6

BE 190
~ All 190 Note 6
A5 165 N Alt 165 Note 6

BF 191 ---, Alt191 Note 6
A6 166 .!!.. Alt 166 NoteS

CO 192 --c::== Alt 192 Note 6
Cl 193 I Alt 193 Note 6

A7 167 E.. Alt 167 Note 6
C2 194 Alt 194 Note 6
A8 168 i, Alt 168 Note 6
A9 169 r- Alt 169 Note 6

C3 195
~ Alt 195 Note 6
AA 170 --, Alt 170 NoteS

C4 196 Alt 196 Note 6
C5 197 Alt 197 Nole6

AB 171 Yo Alt 171 Note 6
C6 196 Alt 198 Note 6
AC 172 V- Alt 172 Note 6 I
AD 173 i Alt 173 Note 6

C7 199
F All 199 Nole6
AE 174 « Alt 174 Note 6

C8 200 L All 200 Nole6
» C9 201 All 201 Note 6

AF 175 Alt 175 Note 6
BO 176
...
...
... Alt 176 Note 6
~-=
II
Bl 177 I Alt 177 Note 6
CA 202 Alt202 Note 6
B2 178 I Alt 178 Note 6

CB 203 --, -,=- All 203 Note 6
B3 179 Alt 179 Note 6

CC 204
I~ Alt204 Note 6
CD All 205 Note 6

B4 180 - Alt 180 Note 6
205
B5 181
= Alt 181 Note 6
B6 182
-11 AIt.182 Note 6
CE
CF
206
207
=::=: AIt206
Alt207
Nole6
Note 6
DO 208 Alt208 Note 6

Value As Characters Value As Characters
Hex Dec Symbol Keystrokes Notas
EC 236 00 All 236 NOle6
ED 237 1/1 Alt237 Note 6
EE 238 E Alt238 Note 6
EF 239 n Alt239 Note 6
FO 240 = Alt240 Note 6
F1 241 ± Alt241 Note 6
F2 242 ~ Alt242 Note 6
F3 243 S A1t243 Note 6
F4 244 r Alt244 Note 6
F5 245 J Alt245 Note 6
F6 246 + Alt245 Note 6
F7 247 ... Alt247 Note 6
F8 246 0 Alt248 Note 6
F9 249
• Alt249 Note 6
FA 250 • Alt250 Note 6
FB 251 .r Alt251 NOle6
FC 252 n Alt252 Note 6
FD 253 2 Alt253 Note 6
FE
FF
254
255
•
BLANK
Alt254
Alt255
Note 6
Nole6

Table Notes
1. Asterisk (*) can be typed by pressing the • key or, in the Shift
state, pressing the 8 key.
2. Period (.) can be typed by pressing the. key or, in the Shift or
Num Lock state, pressing the Del key.
3. Numeric characters 0-9 can be typed by pressing the numeric
keys on the top row of the keyboard or, in the Shift or Num Lock
state, pressing the numeric keys in the keypad portion of the key-
board.
4. Uppercase alphabetic characters (A-Z) can be typed by pressing
the character key in the Shift or Caps Lock state.
5. Lowercase alphabetic characters (a-z) can be typed by pressing
the character key in the normal state or in Caps Lock and Shift
state combined.
6. The three digits after the Alt key are typed from the numeric
keypad. Character codes 001-255 may be entered in this fashion
(with Caps Lock activated, character codes 97-122 display upper-
case).

Quick Reference
• •
DECIMAL
VALUE
.~~~~AL
•VALUE
0
0
16
1
32
2
48
3
64
4
80
5
96
6
,
112
@ p
,.
BLANK BLANK
0 0 (NULL) ~ (SPACE) 0 P
1 1 g ..... 1 A Q a q
2
3
2
3
-• " t II
.. #
2
3
B R
C S
b r
c s
4 4
•
4- § 0/0
'If $ 4
5
D T
E U
d t
e u
-
5 5
6 6 ~ & 6 F V f v
• -t
7 7
I
7 G W g W
8 8 i ( 8 H X h x
.
9 9 0 ~ ) 9 I y 1 Y
--.
10 A
* ·· J Z J z
11 B cJ +- + · K [ k {
'I
12 C S? L , < L 1 II
13 D ~ +--+ - -- M ] m } ""
14 E ~ •, . > N /\ n '"
15 F ~ / ? 0 - 0 6

I~~AL . 128 144 160 176 192 208 224 240
•
0
I~~~AL
IItAUiE
0
8 9
,
C; E a
A
,
B C D E
ex: -
F
1 1
..
u re
,
1
000
.:::::....
.....
..... p +
, ,
2 2 e lE 0 l!!
,
I r >
3 3 a" 0" U r-- lL n <
.. .. ,.., b
4 4 a 0 n
, , ,...
f--
L r
5 5 a 0 N f::::: F a J
.
Jl -.
a u" a ---i
0
6 6 == -
,
7 7 ~
..U 0
--n T "'"
"'"
8 8 " .
e y (, 9 <I> 0
.. •• I J
9 9 e
,
0 I e •
e U -,
•• ~L
10 A Q •
..1 ¢ Y2 - 6
11 B I - -v-
12 c "1 £ Y4 ::::L 00 n
13 D
,
1 ¥ ,. ~ ¢ 2
14 E A R« d
~ E I
15 F A f » I n BLANK
'FF'

Glossary
This glossary includes terms and alphanumeric (A/N). Pertaining to a

definitions from the IBM Vocabulary character set that contains letters,
for Data Processing, Telecommuni- digits, and usually other characters,
cations, and Office Systems, such as punctuation marks.
GC20-1699.
alternating current (ac). A current
that periodically reverses its direc-
tion of flow.
~. Prefix micro; 0.000 001.
American National Standard Code
~s. Microsecond; 0.000 001 second. for Information Interchange (ASCII).
The standard code, using a coded
A. Ampere. character set consisting of 7-bit
coded characters (8 bits including
ac. Alternating current. parity check), used for information
exchange between data processing
accumulator. A register in which systems, data communication
the result of an operation is formed. systems, and associated equipment.
The ASCII set consists of control
active high. Designates a signal characters and graphic characters.
that has to go high to produce an
effect. Synonymous with positive ampere (A). The basic unit of elec-
true. tric cu rrent.
active low. Designates a signal that A/N. Alphanumeric.

has to go low to produce an effect.
Synonymous with negative true. analog. (1) Pertaining to data in
the form of continuously variable
adapter. An auxiliary device or unit physical quantities. (2) Contrast
used to extend the operation of with digital.
another system.
AND. A logic operator having the
address bus. One or more conduc- property that if P is a statement, Q is
tors used to carry the binary-coded a statement, R is a statement, ... ,
address from the microprocessor then the AND of P, Q, R, ... is true if
throughout the rest of the system. all statements are true, false if any
statement is false.
all points addressable (APA). A
mode in which all pOints of a dis- AND gate. A logic gate in which the
playable image can be controlled by output is 1 only if all inputs are 1.
the user.
APA. All pOints addressable.
Glossary X-1
ASCII. American National Standard lation mechanism between hard-
Code for Information Interchange. ware and application software.
assemble. To translate a program baud. (1) A unit of signaling speed

expressed in an assembler lan- equal to the number of discrete con-
guage into a machine language. ditions or signal events per second.
For example, one baud equals one
assembler. A computer program bit per second in a train of binary
used to assemble. signals, one-half dot cycle per
second in Morse code, and one 3-bit
assembler language. A computer- value per second in a train of
oriented language whose signals each of which can assume
instructions are usually in one of eight states. (2) In asynchro-
one-to-one correspondence with nous transmission, the unit of modu-
computer instructions. lation rate corresponding to one unit
of interval per second; that is, if the
asynchronous transmission. duration of the unit interval is 20
(1) Transmission in which the time milliseconds, the modulation rate is
of occurrence of the start of each 50 baud.
character, or block of characters, is
arbitrary; once started, the time of BCC. Block-check character.
occurrence of each signal repres-
enting a bit within a character, or BCD. Binary-coded decimal.
block, has the same relationship to
significant instants of a fixed time beginner's all-purpose symbolic
frame. (2) Transmission in which instruction code (BASIC). A pro-
each information character is indi- gramming language with a small
vidually transmitted (usually timed repertoire of commands and a
by the use of start elements and simple syntax, primarily designed
stop elements). for numeric applications.
audio frequencies. Frequencies binary. (1) Pertaining to a

that can be heard by the human ear selection, choice, or condition that
(approximately 15 Hertz to 20,000 has two possible values or states.
Hertz). (2) Pertaining to a fixed radix
numeration system having a radix of
auxiliary storage. (1) A storage 2.
device that is not main storage.
(2) Data storage other than main binary digit. (1) In binary notation,
storage; for example, storage on either of the characters 0 or 1.
magnetic disk. (3) Contrast with (2) Synonymous with bit.
main storage.
binary notation. Any notation that
BASIC. Beginner's all-purpose uses two different characters,
symbolic instruction code. usually the binary digits 0 and 1.
basic input/output system (BIOS). A binary synchronous communi-

software layer serving as an iso- cations (BSC). A uniform proce-
X-2 Glossary
dure, using a standardized set of bps. Bits per second.
control characters and control char-
acter sequences for synchronous BSC. Binary synchronous commu-
transmission of binary-coded data nications.
between stations.
buffer. (1) An area of storage that
BIOS. See "basic input/output" is temporarily reserved for use in
system. performing an input/output opera-
tion, into which data is read or from
bit. Synonym for binary digit. which data is written. Synonymous
with I/O area. (2) A portion of
bits per second (bps). A unit of storage for temporarily holding
measure representing the number of input or output data.
discrete binary digits transmitted by
a device in one second. bus. One or more conductors used
for transmitting signals or power.
block. (1) A string of records, a
string of words, or a character string byte. (1) A sequence of eight adja-
formed for technical or logic cent binary digits that are operated
reasons, to be treated as an entity. upon as a unit. (2) A binary char-
(2) A set of things, such as words, acter operated upon as a unit.
characters, or digits, treated as a (3) The representation of a char-
unit. acter.
block-check character (BCC). In C, Ceisius.

cyclic redundancy checking, a char-
acter that is transmitted by the Cartesian coordinates. A system of
sender after each message block coordinates for locating a point on a
and is compared with a block-check plane by its distance from each of
character computed by the receiver two intersecting lines, or in space
to determine if the transmission was by its distance from each of three
successful. mutually perpendicular planes.
boolean operation. (1) Any opera- CAS. Column address strobe.

tion in which each of the operands
and the result take one of two CCITT. International Telegraph and
values. (2) An operation that Telephone Consultative Committee.
follows the rules of boolean algebra.
Celsius (C). A temperature scale.
bootstrap. A technique or device Contrast with Fahrenheit (F).
designed to bring itself into a
desired state by means of its own CGA. Color graphics adapter.
action; for example, a machine
routine whose first few instructions channel. A path along which
are sufficient to bring the rest of signals can be sent; for example,
itself into the computer from an data channel, output channel.
input device.
Glossary X-3
character generator. (1) In com- CS. Chip select.
puter graphics, a functional unit that
converts the coded representation CTS. Clear to send. Associated
of a graphic character into the with modem control.
shape of the character for display.
(2) In word processing, the means cyclic redundancy check (CRC).
within equipment for generating (1) A redundancy check in which
visual characters or symbols from the check key is generated by a
coded data. cyclic algorithm. (2) A system of
error checking performed at both
character set. (1) A finite set of the sending and receiving station
characters upon which agreement after a block-check character has
has been reached and that is con- been accumulated.
sidered complete for some purpose.
(2) A set of unique representations daisy-chained. Two or more
called characters. (3) A defined devices or programs attached or
collection of characters. linked in series.
characters per second (cps). A DAC. Digital-to-analog converter.

standard unit of measurement for
the speed at which a printer prints. dB. Decibel.
chip select (CS). A signal, line, or dc. Direct current.

bit that activates a specified device
or circuit logic. decibel. (1) A unit that expresses
the ratio of two power levels on a
collector. An element in a tran- logarithmic scale. (2) A unit for
sistor toward which current flows. measuring relative power.
column address strobe (CAS). A Deutsche Industrie Norm (DIN).

signal that latches the column (1) German Industrial Norm.
addresses in a memory chip. (2) The committee that sets German
dimension standards.
complement. A number that can be
derived from a specified number by DIN connector. One of the connec-
subtracting it from a second speci- tors specified by the DIN committee.
fied number.
DIP. Dual in-line package.
conjunction. Synonym for AND
operation. direct current (dc). A current that
always flows in one direction.
contiguous. Touching or joining at
the edge or boundary; adjacent. direct memory access (DMA). A
method of transferring data between
cps. Characters per second. main storage and 110 devices that
does not require processor inter-
CRC. Cyclic redundancy check. vention.
X-4 Glossary
disable. To stop the operation of a EBCDIC. Extended binary-coded
circuit or device. decimal interchange code.
disabled. Pertaining to a state of a ECC. Error checking and cor-

processing unit that prevents the rection.
occurrence of certain types of inter-
ruptions. Synonymous with masked. EIA. Electronic Industries Associ-
ation.
disk. Loosely, a magnetic disk.
enable. To initiate the operation of
dlskeHe. A thin, flexible magnetic a circuit or device.
disk and a protective jacket, in
which the disk is permanently end 01 block (EO B). A code that
enclosed. Synonymous with flexible marks the end of a block of data.
or floppy disk.
end 01 Iile (EOF). An internal label,
dlskeHe drive. A device for storing immediately following the last
data on and retrieving data from a record of a file, Signaling the end of
diskette. that file. It may include control
totals for comparison with counts
display. (1) A visual presentation accumulated during processing.
of data. (2) A device for visual
presentation of information on any end-ol-text (ETX). A transmission
temporary character imaging control character used to terminate
device. (3) To present data visu- text.
ally.
end-ol-transmission (EOT). A trans-
DMA. Direct memory access. mission control character used to
indicate the conclusion of a trans-
DSR. Data set ready. Associated mission, which may have included
with modem control. one or more texts and any associ-
ated message headings.
DTL. Data length - a field value for
diskette and fixed disk operation. end-ol-transmission-block (ETB). A
transmission control character used
DTR. Data terminal ready. Associ- to indicate the end of a transmission
ated with modem control. block of data when data is divided
into such blocks for transmission
dual in-line package (DIP). A purposes.
widely used container for an inte-
grated circuit. DIPs have pins in two EOB. End of block.
parallel rows. The pins are spaced
1/10 inch apart. EOF. End of file.
duplex. In data communication, EOI. End of interrupt.

pertaining to a Simultaneous
two-way independent transmission EOT. End-of-transmission.
in both directions.
Glossary X-5
error checking and correction be retrieved is the item that has
(ECC). The.detection and cor- been in the queue for the longest
rection of all single-bit errors, plus time.
the detection of double-bit and some
multiple-bit errors. flag. (1) Any of various types of
indicators used for identification.
ESC. The escape character. (2) A character that signals the
occurrence of some condition, such
escape character (ESC). A code as the end of a word. (3) Depre-
extension character used, in some cated term for mark.
cases, with one or more succeeding
characters to indicate by some con- flexible disk. Synonym for diskette.
vention or agreement that the coded
representations following the char- flip-flop. A circuit or device con-
acter or the group of characters are taining active elements, capable of
to be interpreted according to a dif- assuming either one of two stable
ferent code or according to a dif- states at a given time.
ferent coded character set.
font. A family or assortment of
extended blnary-coded decimal characters of a given size and style;
interchange code (EBCDIC). A set for example, 10 point Press Roman
of 256 characters, each represented medium.
by 8 bits.
format. The arrangement or layout
F. Fahrenheit. of data on a data medium.
Fahrenheit (F). A temperature frame. (1) In SDLC, the vehicle for

scale. Contrast with Celsius (C). every command, every response,
and all information that is trans-
failing edge. Synonym for negative- mitted using SDLC procedures.
going edge. Each frame begins and ends with a
flag. (2) In data transmission, the
FCC. Federal Communications sequence of contiguous bits brack-
Commission. eted by and including beginning and
ending flag sequences.
fetch. To locate and load a quantity
of data from storage. g. Gram.
FF. The form feed character. G. (1) Prefix giga; 1 000000000.

(2) When referring to computer
field. (1) In a record, a specified storage capacity, 1 073741 824
area used for a particular category bytes (2 to the 30th power).
of data. (2) In a data base, the
smallest unit of data that can be gate. (1) A combinational logic
referred to. circuit having one output channel
and one or more input channels,
FIFO (flrst-In,.flrst out). A queuing such that the output channel state is
technique in which the next item to completely determined by the input
X-6 Glossary
channel states. (2) A signal that Initialize. To set counters,
enables the passage of other switches, addresses, or contents of
signals through a circuit. storage to 0 or other starting values
at the beginning of, or at prescribed
gram (g). A unit of weight (equiv- points in, the operation of a com-
alent to 0.035 ounces). puter routine.
graphic. A symbol produced by a Input/output (1/0). (1) Pertaining to

process such as handwriting, a device or to a channel that may be
drawing, or printing. involved in an input process, and, at
a different time, in an output
Hertz (Hz). A unit of frequency process. (2) Pertaining to a device
equal to one cycle per second. whose parts can be performing an
input process and an output process
hex. Common abbreviation for at the same time. (3) Pertaining to
hexadecimal. Also, hexadecimal either input or output, or both.
can be noted with an H following the
value. Instruction. In a programming lan-
guage, a meaningful expression that
hexadecimal. Pertaining to a specifies one operation and identi-
selection, choice, or condition that fies its operands, if any.
has 16 possible different values or
states. These values or states are instruction set. The set of
usually symbolized by the ten digits instructions of a computer, of a pro-
o through 9 and the six letters A gramming language, or of the pro-
through F. gramming languages in a
progralT1ming system.
high-order position. The leftmost
position in a string of characters. intensity. In computer graphics, the
See also most-significant digit. amount of light emitted at a display
point.
Hz. Hertz.
interface. A device that alters or
immediate instruction. An instruc- converts electrical signals between
tion that contains within itself an distinct devices, programs, or
operand for the operation specified, systems.
rather than an address of the
operand. interleave. To arrange parts of a
sequence so that they alternate with
Index register. A register whose parts of one or more other
contents may be used to modify an sequences of the same nature and
operand address during the exe- so that each sequence retains its
cution of computer instructions. identity.
inhibited. Pertaining to a state of a interrupt. (1) A suspension of a

device that does not allow inter- process, such as the execution of a
ruptions or instructions. computer program, caused by an
event external to that process, and
Glossary X-7
performed in such a way that the mAo Milliampere; 0.001 ampere.
process can be resumed. (2) In a
data transmission, to take an action machine code. The machine lan-
at a receiving station that causes guage used for entering text and
the transmitting station to terminate program instructions onto the
a transmission. (3) Synonymous recording medium or into storage
with interruption. and which is subsequently used for
processing and printout.
1/0. Input/output.
machine language. (1) A language
irrecoverable error. An error that that is used directly by a machine.
makes recovery impossible without (2) Deprecated term for computer
the use of recovery techniques instruction code.
external to the computer program or
run. magnetic disk. (1) A flat circular
plate with a magnetizable surface
k. Prefix kilo; 1000. layer on which data can be stored
by magnetic recording. (2) See also
K. 1024 (1024 = 2 to the 10th diskette.
power). When referring to storage
capacity, 1024 bytes. mark. A symbol or symbols that
indicate the beginning or the end of
kg. Kilogram; 1000 grams. a field, of a word, of an item of data,
or of a set of data such as a file, a
kHz. Kilohertz; 1000 hertz. record, or a block.
latch. (1) A simple logic-circuit mask. (1) A pattern of characters

storage element. (2) A feedback that is used to control the retention
loop in sequential digital circuits or elimination of portions of another
used to maintain a state. pattern of characters. (2) To use a
pattern of characters to control the
least-significant digit. The right- retention or elimination of portions
most digit. See also low-order posi- of another pattern of characters.
tion.
masked. Synonym for disabled.
load. In programming, to enter data
into storage or working registers. mega (M). Prefix 1 000 000.
low-order position. The rightmost megahertz (MHz). 1 000 000 hertz.

position in a string of characters.
See also least-significant digit. MFM. Modified frequency modu-
lation.
m. (1) Prefix milli; 0.001. (2) Meter.
micro M. Prefix 0.000001.
M. (1) Prefix mega; 1 000000.
(2) When referring to computer microcode. A code, representing
storage capacity, 1 048576 bytes (1 the instructions of an instruction set,
048576 = 2 to the 20th power).
x-a Glossary
implemented in a part of storage area of recording media at single
that is not program-addressable. density.
microprocessor. An integrated modulation. The process by which

circuit that accepts coded some characteristic of one wave
instructions for execution; the (usually high frequency) is varied in
instructions may be entered, inte- accordance with another wave or
grated, or stored internally. signal (usually low frequency). This
technique is used in modems to
microsecond (l1s). 0.000001 second. make business-machine signals
compatible with communication
milll (m). Prefix 0.001. facilities.
milliampere (mA). 0.001 ampere. modulo check. A calculation per-

formed on values entered into a
millisecond (ms). 0.001 second. system. This calculation is
designed to detect errors.
mnemonic. A symbol chosen to
assist the human memory; for modulo-check. A check in which an
example, an abbreviation such as operand is divided by a number N
"mpy" for "multiply." (the modulus) to generate a
remainder (check digit) that is
mode. (1) A method of operation; retained with the operand. For
for example, the binary mode, the example, in a modul0-7 check, the
interpretive mode, the alphanumeric remainder will be 0, 1, 2, 3, 4, 5, or
mode. (2) The most frequent value 6. The operand is later checked by
in the statistical sense. again dividing it by the modulus; if
the remainder is not equal to the
modem (modulator-clemodulator). check digit, an error is indicated.
A device that conver,ts serial (bit by
bit) digital signals from a business most-significant digit. The leftmost
machine (or data communication (nonzero) digit. See also high-order
equipment) to analog signals that position.
are suitable for transmission in a
telephone network. The inverse ms. Millisecond; 0.001 second.
function is also performed by the
modem on reception of analog multiplexer. A device capable of
signals. interleaving the events of two or
more activities, or capable of dis-
modified frequency modulation tributing the events of an inter-
(MFM). The process of varying the leaved sequence to the respective
amplitude and frequency of the activities.
'write' signal. MFM pertains to the
number of bytes of storage that can n. Prefix nano; 0.000000001.
be stored on the recording media.
The number of bytes is twice the NAND. A logic operator having the
number contained in the same unit property that if P is a statement, Q is
a statement, R is a statement" .. ,
Glossary X-9
then the NAND of p. Q .R •... is true if NRZI. Nonreturn-to-zero (inverted)
at least one statement is false. false recording.
if all statements are true.
ns. Nanosecond; 0.000000001
NAND gate. A gate in which the second.
output is 0 only if all inputs are 1.
NUL. The null character.
nano (n). Prefix 0.000000001.
null character (NUL). A control
nanosecond (ns). 0.000000001 character that is used to accomplish
second. media-fill or time-fill. and that may
be inserted into or removed from a
negative-going edge. The edge of a sequence of characters without
pulse or signal changing in a nega- affecting the meaning of the
tive direction. Synonymous with sequence; however. the control of
falling edge. the equipment or the format may be
affected by this character.
NMI. Non-maskable interrupt.
open collector. A switching tran-
nonreturn-to-zero change-on-ones sistor without an internal connection
recording (NRZI). A transmission between its collector and the
encoding method in which the data voltage supply. A connection from
terminal changes the signal to the the collector to the voltage supply is
opposite state to send a binary 1 made through an external (pull-up)
and leaves it in the same state to resistor.
send a binary O.
operand. (1) An entity to which an
nonreturn-to-zero (inverted) operation is applied. (2) That which
recording (NRZI). Deprecated term is operated upon. An operand is
for non-return-to-zero change-on- usually identified by an address part
ones recording. of an instruction.
NOR. A logic operator having the operating system. Software that

property that if P is a statement. Q is controls the execution of programs;
a statement. R is a statement •...• an operating system may provide
then the NOR of p. Q. R •... is true if services such as resource allo-
all statements are false. false if at cation. scheduling. I/O control. and
least one statement is true. data management.
NOR gate. A gate in which the OR. A logic operator having the
output is 0 only if at least one input property that if P is a statement. Q is
is 1. a statement. R is a statement •...•
then the OR of p. Q. R •... is true if at
NOT. A logical operator having the least one statement is true. false if
property that if P is a statement. all statements are false.
then the NOT of P is true if P is false.
false if P is true. OR gate. A gate in which the output
is 1 only if at least one input is 1.
X-10 Glossary
output. Pertaining to a device, using separate facilities for the
process, or channel involved in an various parts. (5) Contrast with
output process, or to the data or serial.
states involved in an output process.
parameter. (1) A variable that is
output process. (1) The process given a constant value for a speci-
that consists of the delivery of data fied application and that may denote
from a data processing system, or the application. (2) A name in a
from any part of it. (2) The return of procedure that is used to refer to an
information from a data processing argument passed to that procedure.
system to an end user, including the
translation of data from a machine parity bit. A birary digit appended
language to a language that the end to a group of binary digits to make
user can understand. the sum of all the digits either
always odd (odd parity) or always
overcurrent. A current of higher even (even parity).
than specified strength.
parity check. A redundancy check
overflow indicator. (1) An indicator that uses a parity bit.
that signifies when the last line on a
page has been printed or passed. picture element (PEL). In computer
(2) An indicator that is set on if the graphics, a basic graphic element
result of an arithmetic operation that can be used to construct a
exceeds the capacity of the accu- display image; for example, a dot, a
mulator. line segment, a character.
overrun. Loss of data because a polling. (1) Interrogation of devices

receiving device is unable to accept for purposes such as to avoid con-
data at the rate it is transmitted. tention, to determine operational
status, or to determine readiness to
overvoltage. A voltage of higher send or receive data. (2) The
than specified value. process whereby stations are
invited, one at a time, to transmit.
parallel. (1) Pertaining to the con-
current or simultaneous operation of POR. Power-on reset.
two or more devices, or to the con-
current performance of two or more port. An access point for data entry
activities. (2) Pertaining to the con- or exit.
current or simultaneous occurrence
of two or more related activities in positive-going edge. The edge of a
multiple devices or channels. pulse or signal changing in a posi-
(3) Pertaining to the simultaneity of tive direction. Synonymous with
two or more processes. (4) Per- rising edge.
taining to the simultaneous proc-
essing of the individual parts of a priority. A rank assigned to a task
whole, such as the bits of a char- that determines its precedence in
acter and the characters of a word, receiving system resources.
Glossary X-11
propagation delay. (1) The time read/write memory. A storage
necessary for a signal to travel from device whose contents can be modi-
one point on a circuit to another. fied. Also called RAM.
(2) The time delay between a signal
change at an input and the corre- recoverable error. An error condi-
sponding change at an output. tion that allows continued execution
of a program.
protocol. (1) A specification for the
format and relative timing of infor- red-green-blue-intensity (RGBI).
mation exchanged between commu- The description of a direct-drive
nicating parties. (2) The set of rules color monitor that accepts input
governing the operation of func- signals of red, green, blue, and
tional units of a communication intensity.
system that must be followed if com-
munication is to be achieved. redundancy check. A check that
depends on extra characters
pulse. A variation in the value of a attached to data for the detection of
quantity, short in relation to the time errors. See cyclic redundancy
schedule of interest, the final value check.
being the same as the initial value.
register. (1) A storage device,
radix. Another term for base. having a specified storage capacity
such as a bit, a byte, or word, and
radix numeration system. A posi- usually intended for a special
tional representation system in purpose. (2) A storage device in
which the ratio of the weight of any which specific data is stored.
one digit place to the weight of the
digit place with the next lower retry. To resend the current block
weight is a positive integer (the of data (from the last EOB or ETB) a
radix). The permissible values of the prescribed number of times, or until
character in any digit place range it is entered correctly or accepted.
from 0 to one less than the radix.
reverse video. A form of high-
RAM. Random access memory. lighting a character, field, or cursor
Read/write memory. by reversing the color of the char-
acter, field, or cursor with its back-
RAS. Row address strobe. ground; for example, changing a red
character on a black background to
read. To acquire or interpret data a black character on a red back-
from a storage device, from a data ground.
medium, or from another source.
RF modulator. The device used to
read-only memory (ROM). A convert a composite video signal to
storage device whose contents a radio-frequency signal that can be
cannot be modified. The memory is used at the antenna level input of a
retained when power is removed. home TV.
RGBI. Red-green-blue-intensity.
X-12 Glossary
RI. Ring indicate; a signal associ- serializer/deserializer (SEROES). A
ated with modem· control. device that serializes output from,
and deserializes input to, a business
rising edge. Synonym for positive- machine.
going edge.
short circuit. A low-resistance path
ROM. Read-only memory. through which current flows, rather
than through a component or circuit.
ROM/BIOS. The ROM resident
basic input/output system, which sink. A device or circuit into which
provides the level control of the current drains.
major I/O devices in the computer
system. SIP. Single-inline package.
row address strobe (RAS). A signal source. The origin of a signal or

that latches the row address in a electrical energy.
memory chip.
square wave generator. A signal
RS-232C. A standard by the EIA for generator delivering an output
communication between computers signal having a square waveform.
and external equipment.
start bit. A signal to a receiving
RTS. Request to send. Associated mechanism to get ready to receive
with modem control. data or perform a function.
SOLC. Synchronous Data Link stop bit. A signal to a receiving

Control. mechanism to wait for the next
signal.
sector. That part of a track or band
on a magnetic drum, a magnetic strobe. An instrument that emits
disk, or a disk pack that can be adjustable-rate flashes of light.
accessed by the magnetic heads in Used to measure the speed of
the course of a predetermined rota- rotating or vibrating objects.
tional displacement of the particular
device. synchronization. The process of
adjusting the corresponding signif-
serial. (1) Pertaining to the icant instants of two signals to
sequential performance of two or obtain the desired phase relation-
more activities in a single device. In ship between these instants.
English, the mOdifiers serial and
parallel usually refer to devices, as Synchronous Oata Link Control
opposed to sequential and consec- (SOLC). A protocol for manage-
utive, which refer to processes. ment of data transfer over a data
(2) Pertaining to the sequential or link.
consecutive occurrence of two or
more related activities in a single synchronous transmission.
device or channel. (3) Contrast with (1) Data transmission in which the
parallel.
Glossary X-13
time of occurrence of each signal nated by an EOT character.
representing a bit is related to a (4) Synonymous with data trans-
fixed time frame. (2) Data transmission.
mission in which the sending and
receiving devices are operating con- TTL. Transistor-transistor logic.
tinuously at substantially the same
frequency and are maintained, by typematic key. A keyboard key that
means of correction, in a desired repeats its function when held
phase relationship. pressed.
time-out. (1) A parameter related vector. In computer graphics, a

to an enforced event designed to directed line segment.
occur at the conclusion of a prede-
termined elapsed time. A time-out video. Computer data or graphics
condition can be cancelled by the displayed on a cathode ray tube,
receipt of an appropriate time-out monitor, or display.
cancellation signal. (2) A time
interval allotted for certain oper- volt. The basic practical unit of
ations to occur; for example, electric pressure. The potential that
response to polling or addressing causes electrons to flow through a
before system operation is inter- circuit.
rupted and must be restarted.
w. Watt.
track. (1) The path or one of the set
of paths, parallel to the reference waH. The practical unit of electric
edge on a data medium, associated power.
with a single reading or writing
component as the data medium word. (1) A sequence of 16 adja-
moves past the component. (2) The cent binary digits that are operated
portion of a moving data medium upon as a unit. (2) A character
such as a drum, or disk, that is string or a bit string considered as
accessible to a given reading head an entity.
position.
write. To make a permanent or
transmission. (1) The sending of transient recording of data in a
data from one place for reception storage device or on a data medium.
elsewhere. (2) In ASCII and data
communication, a series of charac- write precompensatlon. The
ters including headings and text. varying of the timing of the head
(3) One or more blocks or mes- current from the outer tracks to the
sages. For asc and start-stop inner tracks of the diskette to keep a
devices, a transmission is termi- constant 'write' signal.
X·14 Glossary
Bibliography
Intel Corporation. The 8086 Family Intel Corporation. Component Data

User's Manual. This manual intro- Catalog. This book describes Intel
duces the 8086 family of microcom- components and their technical
puting components and serves as a specifications.
reference in system design and
implementation. Motorola, Inc. The Complete Micro-
computer Data Library. This book
Intel Corporation. 80861808718088 describes Motorola components and
Macro Assembly Reference Manual their technical specifications.
for 808818085 Based Development
System. This manual describes the National Semiconductor Corpo-
8086/8087/8088 Macro Assembly ration. 8250 Asynchronous Commu-
Language and is intended for nications Element. This book
persons who are familiar with documents physical and operating
assembly language. characteristics of the INS 8250.
Bibliography X-15
Notes:
X-16 Bibliography
Index
baud rate initialization

A table 5-64
AAA 6-10 character generator
AAD 6-12 routine 5-19
AAM 6-12 communications 5-37
AAS 6-12 current video state 5-17
adapters with ROM 5-9 data area 5-56
ADC 6-10 device busy 5-44
ADD 6-9 device close 5-42
address device open 5-42
map, 110 1-24 disk change status 5-35
serial port 1-106 diskette 5-30
video subsystem 1-44 diskette parameter table 5-64
AEN (address enable) 1-26 display code, r/w 5-24
ALE (address latch enable), 110 eqUipment determination 5-28
channel 1-26 event wait 5-43
alphanumeric (A/N) modes 1-40 extended data area 5-61
alternate key 4-22 extended initialize 5-40
alternate parameter table, extended keyboard read 5-51
video 1-70 extended keystroke status 5-51
alternate select 5-21 extended shift status 5-52
AND 6-13 fixed disk 5-36.1
Arabic keyboard 4-26 fixed disk parameter table 5-62
arithmetic instructions 6-9, 6-26 fixed disk parameters 5-7
ASCII characters 7-2 format track 5-33, 5-36.4
ASCII, extended 4-11 hardware interrupts 5-4
async baud rate table 5-64 initialize the communications
asynchronous communications, port 5-37
interrupt 14 5-37 initialize the printer port 5-53
int 1A, clock services 5-55
int 17, printer 5-53
B int 19, bootstrap 5-54
basic assurance test, keyboard 4-4 interrupt complete 5-44
BASIC reserved interrupts 5-7 interrupt 02, NMI routine 5-10
BAT commands, keyboard 4-7 interrupt 05, print screen 5-10
baud-rate generator 1-116 interrupt 08, system timer 5-11
baud rate table 5-64 interrupt 09, keyboard 5-12
beeper 1-125 interrupt 10, video 5-13
beeper control 1-11 interrupt 16 5-49
Belgian keyboard 4-27 joystick 5-43
BIOS keyboard intercept 5-42
alternate select 5-21 keyboard write 5-50
X-17
keystroke status 5-49 verify sectors 5-32, 5-36.4
memory size video state information 5-24
determination 5-29 video tables 5-25
model byte 5-65 wait 5-43
palette registers 5-17 write character at cursor 5-16
parameter passing 5-3 write dot 5-16
park heads 5-36.8 write sectors from
pOinting device 5-46 memory 5-32, 5-36.3
print character 5-53 write string 5-23
program termination 5-43 write teletype to display 5-17
programming write value at cursor 5-15
considerations 5-8 block diagram
read cursor position 5-14 parallel port 1-120
read OASO type 5-35, 5-36.7 serial port 1-105
read day counter 5-55 shared interrupt 1-15
read dot 5-17 system board 1-4
read drive parameters 5-34, system timer 1-9
5-36.5 video 1-37
read sectors into memory 5-31, bootstrap 5-54
5-36.2 border control register 1-55
read status 5-31, 5-36.2, 5-39, break code 4-4
5-53 break key 4-23
read system time counter 5-55 buffer, keyboard 4-3
read value at cursor bus card 1-23
position 5-15
receive character 5-38
reset disk 5-36.1 c
reset diskette 5-30 cable 4-46
return config parameters 5-45 CALL 6-15
return ext segment Canadian French keyboard 4-43
address 5-45 Canadian keyboard 4-28
ROM table 5-62 caps lock key 4-22
scroll active page down 5-15 CBW 6-12
scroll active page up 5-15 CGA border control register 1-55
select active display page 5-14 CGA mode control register 1-54
send character 5-38 channel check (-110 CH CK) 1-27
set color palette 5-16 channel ready (110 CH ROY) 1-27
set cursor position 5-14 channel, I/O
set cursor type 5-14 character box 1-38
set OASO type 5-35 character codes 4-11
set day counter 5-55 character generator routine 5-19
set media type 5-36 character matrix 1-65
set system time counter 5-55 character set, 512 1-67
set typematic rate 5-50 characters 7-2
shift status 5-49 chip select 1-8
software interrupts 5-4 CLC 6-20
system request 5-43 CLO 6-20
system services 5-42
X.18
CLI 6-20
ClK 1-26
D
clock (ClK) 1-26 Danish keyboard 4-29
clock and data signals 4-5 data
clock services 5-55 data area, BIOS 5-56
CMC 6-20 data bits (DO-D7) 1-26
CMP 6-11 data output, keyboard 4-6
CMPS 6-15 data stream, keyboard 4-6
codes data stream, serial port 1-106
character 4-11 data transfer instructions 6-7,6-24
extended 4-19 DEC 6-11
make/break 4-8 default colors 1-63
color palette load 1-58 delay, typematic 4-4
color/graphics description
See video I/O channel 1-26
colors, default 1-63 keyboard 4-3
colors, mode 4,5 1-55 parallel port 1-120
commands video 1-36
diskette drive 1-83 device busy 5-44
keyboard 4-7 device close 5-42
comparison instructions 6-26 device open 5-42
configuration register 1-81 digital I/O registers 1-80
connectors disk change line status 5-35
fixed disk 1-104.1 diskette controller select 1-8
I/O channel 1-25 diskette drive interface 1-78
keyboard and pointing change signal 1-80
device 4-46 commands 1-83
parallel port 1-124 data transfer 1-81
power supply 1-128,3-6 parameter table 5-64
serial port 1-119 phase-lock loop 1-78
system board 1-126,1-127 registers 1-79
video 1-77 status registers 1-99
constants instructions 6-29 diskette interrupt, BIOS 5-30
control key 4-21 diskette parameter table 5-64
control transfer instructions 6-15 display combination code, r/w 5-24
controller, diskette 1-81 display support, video 1-38
Ctrl state 4-19 DlV 6-12
current video state 5-17 DMA request 1 to 3
cursor position 5-14 (DRQ1 - DRQ3) 1-26
CWD 6-12 DOS reserved interrupts 5-7
Dutch keyboard 4-30
X-19
E FNOP 6-31
font save table 1-70
encoding, keyboard 4-11
fonts, RAM-Ioadable 1-64
equipment determination 5-28
format track 5-33, 5-36.4
ESC 6-21
FPATAN 6-28
event wait 5-43
FPREM 6-27
extended ASCII 4-11
FPTAN 6-28
extended codes 4-19 French keyboard 4-31
extended codes, keyboard 4-21
FRNDINT 6-28
extended data area, BIOS 5-61
FRSTOR 6-30
extended initialize 5-40
FSAVE 6-30
extended keyboard read 5-51
FSCALE 6-27
extended keystroke status 5-51
FSQRT 6-27
extended shift status 5-52
FST 6-25
FSTCW 6-30
FSTENV 6-30
F FSTP 6-25
FABS 6-28 FSTSW 6-30
FADD 6-26 FSUB 6-27
FCHS 6-28 FTST 6-26
FCLEX 6-30 function enable 1-8
FCOM 6-26 functionality and state
FCOMP 6-26 information 5-25
FCOMPP 6-26 FWAIT 6-31
FDECSTP 6-30 FXAM 6-26
FDISI 6-29 FXCH 6-25
FDIV 6-27 FXTRACT 6-28
FENI 6-29 FYL2X 6-28
FFREE 6-31 FYL2XP1 6-28
FIFO 4-3 F2XM1 6-28
FINCSTP 6-30
FINIT 6-29
fixed disk connector 1-104.1 G
fixed disk controller select 1-8
gate array
fixed disk interrupt, BIOS 5-36.1 diskette drive 1-78
fixed disk parameter table 5-62
110 support 1-8
FLD 6-24
system support 1-6
FLDCW 6-30
German keyboard 4-32
FLDENV 6-30
graphics modes 1-41
FLDLG2 6-29
FLDLN2 6-29
FLDL2T 6-29 H
FLDP1 6-29
hardware interrupts 1-13,5-4
FLDZ 6-29
HLT 6-20
FLD1 6-29
FMUL 6-27
X-20
bootstrap 5-54
I clock services 5-55
I/O CH CK 1-27 hardware 1-13,5-4
I/O channel 1-23 keyboard 5-12
address map 1-24 NMI routine 5-10
ALE (address latch print screen 5-10
enable) 1-26 printer 5-53
channel check (-1/0 CH shared logic 1-15
CK) 1-27 sharing 1-14
channel ready (1/0 CH software 5-4
ROY) 1-27 system timer 5-11
ClK 1-26 10, video 5-13
connector 1-25 11, equipment
description 1-26 determination 5-28
-memory refresh 1-27 12, memory size 5-29
-MEMR, -MEMW 1-27 13, diskette 5-30
oscillator (OSC) 1-27 13, fixed disk 5-36.1
read (-lOR) 1-27 14, communications 5-37
Reset Drive (RESET DRV) 1-27 15, system services 5-42
terminal count (TC) 1-28 16, keyboard 5-49
timing 1-28 interrupt complete 5-44
write (-lOW) 1-27 interrupt identificatio!,)
1/0 port 1-11,1-125 register 1-109
1/0 support gate array 1-8 interrupt requests 1-27
IDIV 6-12 INTO 6-19
IMUl 6-12 IRET 6-19
IN 6-8 Israeli keyboard 4-33
INC 6-10 Italian keyboard 4-34
information, return video 5-24
initializatiol"! tables 1-62
initialize J
initialize the communications
JB/JNAE 6-17
port 5-37
JBE/JNA 6-17
initialize the printer port 5-53
JCXZ 6-18
instructions JE/JZ 6-16
arithmetic 6-9, 6-26
Jl/JNGE 6-17
comparison 6-26
JlE/JNG 6-17
constants 6-29
JMP 6-16
control transfer 6-15
JNB/JAE 6-18
data transfer 6-7,6-24
JNBE/JA 6-18
diskette drive 1-83
JNE/JNZ 6-17
logic 6-13 JNLlJGE 6-17
rotate 6-13
JNlE/JG 6-17
shift 6-13
JNO 6-18
string manipulation 6-15
JNP/JPO 6-18
INT 6-19 JNS 6-18
interrupt 1-13
JO 6-17
BIOS interface listing 5-5
joystick 5-43
X-21
JP/JPE 6-17 US English 4-42
JS 6-17 keyboard write 5-50
keys, typematic 4-4
keystroke status 5-49
K
key-code scanning 4-3
keyboard 4-3 L
basic assurance test 4-4 LAHF 6-9
buffer 4-3 Latin American keyboard 4-35
cable 4-46 layout, keyboard 4-12
commands 4-7 layouts, keyboard
connector 1-128 Arabic 4-26
data output 4-6 Belgian 4-27
data stream 4-6 Canadian 4-28
encoding 4-11 Canadian French 4-43
interrupt 09 5-12 Danish 4-29
interrupt 16 5-49 Dutch 4-30
key-code scanning 4-3 French 4-31
layout 4-12 German 4-32
line protocol 4-5 Israeli 4-33
make/break 4-4 Italian 4-34
paR (power.-on reset) 4-4 Latin American 4-35
routine 4-24 Norwegian 4-36
scan codes 4-8 Portuguese 4-37
shift states 4-21 Spanish 4-38
keyboard controller 1-9 Spanish/Latin 4-44
keyboard intercept 5-42 Swedish 4-39
keyboard layouts Swiss 4-40
Arabic 4-26 U.S.A. English 4-45
Belgian 4-27 UK English 4-41
Canadian 4-28 US English 4-42
Canadian French 4-43 LOS 6-9
Danish 4-29 LEA 6-9
Dutch 4-30 LES 6-9
French 4-31 line protocol 4-5
German 4-32 listing, software interrupt 5-5
Israeli 4-33 ioadable fonts 1-64
Italian 4-34 loading color palette 1-58
Latin American 4-35 locations, system board 1-126,
Norwegian 4-36 1-127
Portuguese 4-37 LOCK 6-21
Spanish 4-38 LaDS 6-15
Spanish/Latin 4-44 logic instructions 6-13
Swedish 4-39 LOOP 6-18
Swiss 4-40 LOOPNZ/LOOPNE 6-18
U.S.A. English 4-45 LOOPZ/LOOPE 6-18
UK English 4-41
X-22
M o
main status register 1-81 OR 6-14
make code 4-4 oscillator (OSC), I/O channel 1-27
memory OUT 6-8
control/status register 1-22 output, keyboard 4-6
read-only 1-22 Overrun command 4-7
read/write 1-22
reserved locations 5-8
ROM table 5-62
p
memory map page down 5-15
BIOS 5-8 palette registers 5-17
video font 1-64 parallel port 1-120
video storage 1-42 parallel port select 1-8
memory map, system 1-5 parameter passing (BIOS) 5-3
memory read (-MEMR) 1-27 park heads 5-36.8
memory refresh (-MREF) 1-27 pause key 4-23
memory size determination 5-29 pointing device 5-46
-MEMW (memory write) 1-27 pointing device controller 1-9
microprocessor 1-5 POP 6-8
mode control register 1-54 POPF 6-9
mode 4,5 colors 1-55 Portuguese keyboard 4-37
mqdel byte 5-65 power good 3-5
modem control/status power-on routine, keyboard 4-4
registers 1-112 power requirements 4-47
modes, video 1-39 power supply 3-3
modules, RAM 1-22 circuit protection 3-5
modules, ROM/EPROM 1-22 connector 1-128
MOV 6-7 connectors 3-6
MOVS 6-15 inputs 3-4
MUl 6-12 outputs 3-4
power good signal 3-5
print character 5-53
N print screen key 4-23
NEG 6-11 print screen, interrupt 05 5-10
non-maskable interrupt printer interrupt 5-53
routine 5-10 priorities, shift key 4-22
NOP 6-20 processor control, 8087 6-29
Norwegian keyboard 4-36 program termination 5-43
NOT 6-13 programming considerations
number lock key 4-22 BIOS 5-8
Numlock state 4-19 chip selects 1-8
interrupt sharing 1-15
video 1-71
protocol 4-5
PUSH 6-7
PUSHF 6-9
X-23
reserved interrupts, BASIC and
Q DOS 5-7
quick reference charts 7-8 reset disk system 5-36.1
quick reference, character set 7-8 reset diskette system 5-30
reset drive signal (RESET
DRV) 1-27
R reset, power-on 4-4
RAM modules 1-22 reset, system 4-23
RAM subsystem 1-22 RET 6-16
RAS port registers 1-79 return config parameters 5-45
rate, typematic 4-4 return ext segment address 5-45
RCL 6-13 return video information 5-24
RCR 6-13 ROL 6-13
read cursor position 5-14 ROM subsystem 1-22
read DASD type 5-35,5-36.7 ROM table 5-62
read day counter 5-55 ROM, adapters with 5-9
read dot 5-17 ROR 6-13
read drive parameters 5-34, 5-36.5 rotate instructions 6-13
read sectors into memory 5-31, routine, keyboard 4-24
5-36.2
read status 5-39, 5-53
read status disk 5-36.2 S
read status diskette 5-31 SAHF 6-9
read system time counter 5-55 SAR 6-13
read value at cursor position 5-15 save table 1-70
readlwrite display code 5-24 SBB 6-11
read, 1/0 channel 1-27 scan codes 4-8
read, memory (-MEMR) 1-27 scanning, key-code 4-3
ready (IIO CH RDY) 1-27 SCAS 6-15
receive character 5-38 scroll active page down 5-15
register, border control 1-55 scroll active page up 5-15
registers scroll lock key 4-22
color palette 1-57 select active display page 5-14
diskette drive 1-79 send character 5-38
memory controller 1-44 serial port 1-105
parallel port 1-120 connector 1-119
serial port 1-107 signals 1-117
system board control 1-8 serial port interrupt call 5-37
system board RAM serial port select 1-8
control 1-22 set color palette 5-16
video 1-44 set cursor position 5-14
video formatter 1-53 set cursor type 5-14
REP 6-15 set DASD type 5-35
request/grant 1-6 set day counter 5-55
requests set media type 5-36
DMA 1-26 set system time counter 5-55
interrupts 1-27 set typematic rate 5-50
X-24
shared interrupt logic 1-15 system board RAM control
sharing, interrupt 1-14 register 1-22
shift instructions 6-13 system clock (ClK) 1-26
shift key 4-21 system memory map 1-5
shift key priorities 4-22 system request 5-43
shift states 4-21 system request key 4-23
shift status 5-49 system reset 4-23
SHLlSAl 6-13 system services interrupt 5-42
SHR 6-13 system support gate array 1-6
signals (I/O) system timer 1-9
diskette 1-102 system timer, interrupt 08 5-11
I/O channel 1-26 system, return parameters 5-45
keyboard 4-5
parallel port 1-120
RQ/GT 1-6 T
serial port 1-117 tables, video 5-25
software interrupts 5-4 terminal count (TC) 1-28
Spanish keyboard 4-38 TEST 6-14
Spanish/latin keyboard 4-44 text modes 1-40
speaker (beeper) 1-125 time of day, interrupt 1A 5-55
speaker tone generation 1-10 timer/counter 1-9
specifications timer, system 1-9
keyboard 4-47 timing
parallel port 1-120 color palette 1-72
serial port 1-119 DMA operation 1-34
system board 1-129 I/O channel 1-28
states, shift parallel port 1-122
static functionality table 5-26 tone generation, beeper 1-10
status registers, diskette 1-99 typematic keys 4-4
STC 6-20
STD 6-20
STI 6-20
STOS 6-15
u
U.K. English keyboard 4-41
string manipulation U.S.A. English keyboard 4-45
instructions 6-15 US English keyboard 4-42
SUB 6-10
subsystem
RAM 1-22 v
ROM 1-22 vectors with special meanings 5-5
video 1-36 verify sectors 5-32, 5-36.4
support, joystick 5-43 video 1-36
supported drives 5-30 alternate parameters
Swedish keyboard 4-39 table 1-70
Swiss keyboard 4-40 BIOS tables 5-25
system board border control 1-55
functional diagram 1-4 character size 1-38
system board control register 1-8 color palette registers 1-57
X-2S
connector 1-77
considerations 1-71
w
default tables 1-62 wait 5-43, 6-21
display format 1-40 write character at cursor 5-16
display support 1-38 write dot 5-16
formatter registers 1-53 write memory command
interrupt 10 5-13 (-MEMW) 1-27
loadable fonts 1-64 write sectors from memory 5-32,
memory controller 5-36.3
registers 1-44 write string 5-23
memory maps 1-42 write teletype to display 5-17
mode 4,5 colors 1-55 write value at cursor 5-15
modes 1-39 write, 1/0 channel (-lOW) 1-27
timing 1-72
512 characters 1-67
video controller select 1-8
X
video state information 5-24 XCHG 6-8
XLAT 6-9
XOR 6-14
Numerics
512 character set 1-67
8086 microprocessor 1-5
8253 timerlcounter 1-9
X-26
--
-
--
-
-
---
- -- -
--
-
-
-
-- - ---
- - ----
---_.-
- --
®
©Copyright
International Business
Machines Corporation, 1987
All Rights Reserved
Printea in the
United States of America
References in this
publication to IBM
products or services do not
imply that IBM intends
to make them available
outside the United States.
84X0672

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First Edition (June 1987)

This publication could include technical inaccuracies or typographical errors. Changes

THE PUBLICATION OF THE INFORMATION CONTAINED HEREIN IS NOT INTENDED TO

© Copyright International Business Machines Corporation 1987. All rights reserved.

This publication describes the components of the IBM Personal

The information in this publication is for reference and is intended for

This manual is divided into the following sections:

Section 1. "System Board" discusses the functions of the system

A Glossary, Bibliography, and Index are also provided.

TM IBM Personal System/2 is a trademark of the International Business

• IBM Personal System/2 Model 25 (Type 8525) Guide to

Suggested Related Publications

• BASIC for the IBM Personal Computer

• Additional technical information for the IBM Personal System/2

SECTION 1. System Board .............................. 1-1

SECTION 2. Coprocessor ............................... 2-1

SECTION 3. Power Supply .............................. 3-1

SECTiON 4. Keyboard .................................. 4-1

SECTION 5. System BIOS ............................... 5-1

SECTION 6. Instruction Set .............................. 6-1

SECTION 7. Characters and Keystrokes .................... 7-1

Glossary ............................................ X-1

Bibliography ......................................... X-15

1-1. System Functional Diagram ...................... 1-4

General Description .................................... 1-3

System Board 1-1

1-2 System Board

• 8086-2 microprocessor and its support logic

Two 62-pin card-edge sockets are attached to a vertical expansion

TM IBM Personal System/2 is a trademark of the International Business

System Board 1-3

Figure 1-1. System Functional Diagram

1-4 System Board

The 8086-2 supports 16-bit operations, including multiply and divide,

Hex Address Function

00000 - 9FFFF 640K Read/Write Memory

AOOOO - BFFFF Video Buffer

COOOO - EFFFF Reserved for BIOS on I/O Channel

FOOoo - FFFFF System ROM

Figure 1-2. Memory Map

System Board 1-5

System Support Gate Array

When the coprocessor is not installed, the gat8 array generates a

Memory Controller and Parity Checker

The memory controller functions of the gate array control memory

1-6 System Board

System Clock Generator

The system clock generator uses a 48 MHz input that is internally

System Board 1-7

Chip Select Logic

Each select line can be disabled by programming the System Board

When the signal is enabled, the CS signal is generated to start a read

7 Parallel Port Output Enable

Figure 1-3. System Board Control Register, Hex 65

1-8 System Board

The system timer is an 8253 programmable interval timer/counter, or

The content of a selected counter may be latched without disturbing