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Serial Peripheral Interface (SPI) : Synchronous Serial Data Transfers

The document discusses the Serial Peripheral Interface (SPI) protocol. It describes the basic SPI configuration with a master and slave device and how data is transferred. It provides timing diagrams and examples of SPI devices like sensors, memory, and microcontrollers.

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peterrohan357
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25 views21 pages

Serial Peripheral Interface (SPI) : Synchronous Serial Data Transfers

The document discusses the Serial Peripheral Interface (SPI) protocol. It describes the basic SPI configuration with a master and slave device and how data is transferred. It provides timing diagrams and examples of SPI devices like sensors, memory, and microcontrollers.

Uploaded by

peterrohan357
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Serial Peripheral Interface (SPI)

 Synchronous serial data transfers


 Multipoint serial communication between a
“master” and a “slave” device
 Clock permits faster data rates than async
communications (framing unnecessary)
 Signals = clock, data in/out, “slave select”
 Master controls data transfers:
 transmit a synchronization clock
 activate slave select signal
 All device data registers effectively linked into
a single “shift register”
Single master, single-slave
SPI connections

Slave SS
Master CS Slave
Select
Clock SCK
Shift register Gen Shift register
MOSI

MISO

SCLK – serial clock, generated by the master


MOSI – master output/slave input
MISO – master input/slave output
SS – slave select/enable signal
Single master, multiple slave
SPI implementation

Slave-selects
Single master, multiple slave SPI
implementation – daisy chained

• Dout of one device connected to Din of next


(creates a single shift register)
• All devices selected concurrently by the Master
SPI serial data timing
 Programmable clock rate and timing for flexibility
 CPOL = clock polarity (0=active-high, 1= active-low)
 CPHA = clock phase (sample on leading/trailing pulse edge)
CPHA=0 : data output immediately when PCSn active
data sampled on leading edge

CPOL
is the
“idle”
state
SPI serial data timing
 CPHA=1
 data output on 1st clock edge after PCSn active
 data sampled on trailing edge
Data output Sample data

PCSn active
Maxim MAX5154
12-Bit Serial DAC
Data Output

Chip-Select
Serial Clock
Data Input
MAX5154 serial data format

Command and address bits select channel and


conversion properties.
VTI Technologies
SCP1000 Pressure Sensor
Supports SPI or I2C (factory programmed)
19 bit pressure, 14 bit temperature
SPI Signals

I2C signals

Trigger
Data Ready
Analog Devices
ADIS16003 Dual-axis accelerometer

SPI
Interface

12-bit acceleration/10-bit temperature


ADIS16003 Dual-axis accelerometer
SPI interface timing
SST: SST25VF016B
16 Mbit SPI serial flash memory
Use in DVDs, hard drives,
PCs, WLANs, LCD monitors,
MP3 players, FPGAs, etc.
•50 MHz clock
•8-lead SOIC package
•7 us byte program
•18 ms block erase

suspend (hold) serial transfer


4-wire SPI interface
write protection
SST25VF016B serial flash :
device operation instructions
Motorola MC14499 7-segment LED
display decoder/driver with SPI
 7-segment alphanumeric LED decoder/driver
 drives 4 characters with decimal points
 NPN output drivers for common-cathode LEDs
STM32 Serial Peripheral Interface (SPI)

 Dual function: SPI (default) or I2S


 Synchronous, serial, full-duplex communication
 Configurable as SPI master or slave
 Programmable clock polarity/phase
 Programmable baud rate
 Supports busy-wait, interrupt, and DMA I/O
STM32 SPI block diagram

Slave
select
SPI data register (SPI_DR)

Transmit buffer for writing / Receive buffer for reading

SPI 8-bit data frame format (DFF = 0):


DR[7:0] = data; DR[15:8] = 00000000
SPI 16-bit data frame format (DFF = 1):
DR[15:0] = data
SPI control register 1 (SPI_CR1)

BIDIMODE: 0 = 2-line/unidirectional, 1 = 1-line/bidirectional


BIDIOE: bidirectional mode output enable (0 = receive, 1 = xmit)
CRCEN: hardware CRC calculation enable
CRCNEXT: 1 = next xfer is data (no CRC), 0 = next xfer is CRC
DFF: data frame format (0 = 8-bit, 1 = 16-bit)
RXONLY: receive only (0 = full duplex, 1 = output disabled/receive-only)
SSM: software slave management – NSS pin ignored (1 = enable)
SSI: internal slave select (this bit forced onto NSS pin if output enabled: SSOE)
LSBFIRST: frame format (0 = shift out MSB first, 1 = shift out LSB first)
SPE: SPI enable
BR[2:0] – baud rate control (master) Fbaud = Fpclk / (2^(BR+1))
MSTR: master selection (0 = slave, 1 = master)
CPOL: clock polarity (idle value)
CPHA: clock phase (0 = 1st clk transition to capture data, 1 = 2nd)
SPI control register 2 (SPI_CR2)

TXEIE: Tx buffer empty interrupt enable (on TXE flag set)


RXNEIE: Rx buffer not empty interrupt enable (on RXNE flag set)
ERRIE: error interrupt enable (CRCERR, OVR, MODF in SPI mode)

FRF: frame format (0 = Motorola mode, 1 = TI mode)

SSOE: SS output enable (if in Master mode)

TXDMAEN: Tx buffer DMA enable (DMA request when TXE flag set)
RXDMAEN: Rx buffer DMA enable (DMA request when RXNE flag set)
DMA automatically xfers data between memory and SPI_DR
SPI status register (SPI_SR)

FRE: frame format error (for SPI TI slave mode or I2S slave mode)
BSY: SPI/I2S busy communicating (set/cleared by hardware)
OVR: overrun error – master sends before RXNE cleared by slave
MODF: master mode fault – master NSS pin lulled low(SPI only)
CRCERR: CRC error in received value (SPI only)
UDR: underrun error (I2S only) 1st clock before data in DR
CHSIDE: channel side to xmit/has been received (0 = left/1 = right) (I2S only)
TXE: 1 = Tx buffer empty: can load next data to buffer;
clears on DR write
RXNE: 1 = Rx buffer not empty: valid received data in buffer;
clears on DR read

• Use TXE/RXNE rather than BSY for each transmission.


• Trigger SPI interrupts with TXE, RXNE, MODF, OVR, CRCERR, FRE
Master Operation Setup
MOSI pin = data output; MISO pin = data input.
SPI_CR1:
1. Select BR[2:0] bits to define the serial clock baud rate

2. Select CPOL and CPHA bits to define one of the four relationships between
the data transfer and the serial clock.
3. Select DFF bit to define 8- or 16-bit data frame format

4. Select LSBFIRST bit to define the frame format (MSB or LSB first).

5. Set MSTR and SPE bits.

6. If the NSS pin is required in input mode, in hardware mode, connect the
NSS pin to a high-level signal during the complete byte transmit sequence.
In NSS software mode, set the SSM and SSI bits in the SPI_CR1 register. If
the NSS pin is required in output mode, the SSOE bit only should be set.
7. Select FRF bit in SPI_CR2 to select the Motorola or TI SPI protocol.

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