UNIT-5 ADVANCED MICROPROCESSOR

 OVERVIEW OF 8086 MICROPROCESSOR

8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in 1976. It is
a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to 1MB storage. It
consists of powerful instruction set, which provides operations like multiplication and division easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable
for system having multiple processors and Minimum mode is suitable for system having a single processor

 FEATURES OF 8086 MICROPROCESSOR

1. Single +5V power supply
2. Clock speed range of 5-10MHz
3. Capable of executing about 0.33 MIPS (Millions instructions per second)
4. It is 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data
bus resulting in faster processing.
5. It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance.
6. Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
7. It has 256 interrupts.

 8086 ARCHITECTURE
Microprocessor & Interfacing techniques Notes

 The above diagram depicts the architecture of an 8086 Microprocessor.

 8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus
Interface Unit).

EU (Execution Unit)

 Execution unit gives instructions to BIU stating from where to fetch the data and then decode and
execute those instructions. Its function is to control operations on data using the instruction decoder &
ALU. EU has no direct connection with system buses as shown in the above figure, it performs
operations over data through BIU.
Let us now discuss the functional parts of 8086 microprocessors.
 ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
 Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored
in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control
Flags.

 Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the list of
conditional flags −
 Carry flag − This flag indicates an overflow condition for arithmetic operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from
lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given
by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to BCD conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits
of the result contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the
Parity Flag is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is
set to 0.
Microprocessor & Interfacing techniques Notes

 Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative,
then the sign flag is set to 1 else set to 0.
 Overflow flag − This flag represents the result when the system capacity is exceeded.
 Control Flags
Control flags controls the operations of the execution unit. Following is the list of control flags −
 Trap flag − It is used for single step control and allows the user to execute one instruction at a
time for debugging. If it is set, then the program can be run in a single step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption
of a program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled
condition.
 Direction flag − It is used in string operation. As the name suggests when it is set then string
bytes are accessed from the higher memory address to the lower memory address and vice-a-
versa.
 General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers
can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid
register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX,
CX, and DX respectively.
Microprocessor & Interfacing techniques Notes

 AX register − It is also known as accumulator register. It is used to store operands for arithmetic
operations.
 BX register − It is used as a base register. It is used to store the starting base address of the
memory area within the data segment.
 CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.
 DX register − This register is used to hold I/O port address for I/O instruction.
 Stack pointer register
It is a 16-bit register, which holds the address from the start of the segment to the memory location,
where a word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as writing
data to the ports and the memory. EU has no direction connection with System Buses so this is possible
with the BIU. EU and BIU are connected with the Internal Bus.
It has the following functional parts −
 Instruction queue − BIU contains the instruction queue. BIU gets up to 6 bytes of next instructions and
stores them in the instruction queue. When EU executes instructions and is ready for its next
instruction, then it simply reads the instruction from this instruction queue resulting in increased
execution speed.
 Fetching the next instruction while the current instruction executes is called pipelining.

 Segment register − The total memory size is divided into segments of various sizes. The process of
dividing memory this way is called Segmentation. In memory, data is stored as bytes. Each byte has a
specific address. Intel 8086 has 20 lines address bus. With 20 address lines, the memory that can be
addressed is 220 = 1,048,576 bytes (1 MB).
 8086 can access memory with address ranging from 00000 H to FFFFFH. In 8086, memory has four
different types of segments. These are:
 CS − It stands for Code Segment. It is used for addressing a memory location in the code
segment of the memory, where the executable program is stored.
Microprocessor & Interfacing techniques Notes

 DS − It stands for Data Segment. It consists of data used by the program and is accessed in the
data segment by an offset address or the content of other register that holds the offset address.

 SS − It stands for Stack Segment. It handles memory to store data and addresses during
execution.
 ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to
hold the extra destination data.
 Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to be
executed.
 Pointers and Index Registers
 The pointers contain offset within the particular segments.
 The pointer register IP (instruction Pointer) contains offset within the code segment. The pointer
register BP (base pointer) contains offset within the data segment.
 The pointer register SP (stack pointer) contains offset within the stack segment.
 The register SI (source index) is used to store the offset of source data in data segment.
Microprocessor & Interfacing techniques Notes

 The register DI (destination index) is used to store the offset of destination in data or extra
segment.
 The index registers are particularly useful for string manipulation.

 Physical Address

 The physical address is expressed in terms of the logical address.

 In the form of Base Address: OFFSET address
Ex : 3000H:2000H
 Base address is the address of segment (data, extra, stack, or code).
 Physical address=Segment address*10H + offset address
 The equivalent physical address will be 3000*10+2000= 32000H. The address summer of 8086
does all the work to generate this 20-bit physical address.
 As we have only 16 bit registers two registers will be used to express the logical address. The
segment registers are used for the base address.

 INSTRUCTION PIPELINING
 An instruction pipeline is a technique used in the design of computers to increase their instruction
throughput (the number of instructions that can be executed in a unit of time). The basic instruction
cycle is broken up into a series called a pipeline. Rather than processing each instruction sequentially
(one at a time, finishing one instruction before starting the next), each instruction is split up into a
sequence of steps so different steps can be executed concurrently (at the same time) and in parallel
(by different circuitry). Each instruction is split into a sequence of dependent steps. The first step is
always to fetch the instruction from memory; the final step is usually writing the results of the
instruction to processor registers or to memory.
 There are five stages of pipelining:
1. Instruction fetch
Microprocessor & Interfacing techniques Notes

2. Instruction decode and register fetch

3. Execute
4. Memory access
5. Register write-back

 Above diagram contains following points:

• All stages will be of equal duration.
• Each instruction goes through all five stages of pipeline.
• All the stages will be performed parallel.
• No memory conflicts.
• All the accesses occur simultaneously.

 FACTORS AFFECTING PIPELINE PERFORMANCE

• If five stages are not of equal duration, then there will be some waiting time at various stages.
• Conditional branch instruction which can invalidate several instruction fetches.
• Interrupt which is unpredictable event.
• Register and memory conflicts.

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