WHAT ARE THE KEY FEATURES OF AXI PROTOCOL?

The key features of the AXI protocol are:

• separate address/control and data phases
• support for unaligned data transfers, using byte strobes
• uses burst-based transactions with only the start address issued
• separate read and write data channels, that can provide low-cost Direct Memory Access (DMA)
• support for issuing multiple outstanding addresses
• support for out-of-order transaction completion
• permits easy addition of register stages to provide timing closure
EXPLAIN AXI ARCHITECTURE. WHAT ARE THE DIFFERENT CHANNELS AS PER AXI PROTOCOL?
The AXI protocol is burst-based and defines the following independent transaction channels:
• read address
• read data
• write address
• write data
• write response.

An address channel carries control information that describes the nature of the data to be transferred.

The data is transferred between master and slave using either:

• A write data channel to transfer data from the master to the slave. In a write transaction, the slave uses
the write response channel to signal the completion of the transfer to the master.
• A read data channel to transfer data from the slave to the master.
The AXI protocol:
• permits address information to be issued ahead of the actual data transfer
• supports multiple outstanding transactions
• supports out-of-order completion of transactions

ADVANTAGES OF AXI OVER AHB PROTOCOL?

1. AXI has 1 read address channel, 1 write address channel, 1 read data channel, 1 write data channel. 1
write response channel That is all together it has 5 parallel channels.
Whereas AHB has 1 address channel, 1 read data channel, 1 write data channel.
2. AXI as native support for multiple outstanding transactions.
3. AXI supports transaction IDs. The user may issue multiple outstanding transactions per transaction ID.
4. User can insert a pipeline register anywhere in the path of any of the 5 channels, which helps in timing
closure and help achieve higher operating frequency.
5. The length of the burst is always known right at the start. This feature is supported by using AxLEN
bits. Wherein AHB is unknown at the start.
6. Write Strobes Are supported.
7. AXI3 supports Locked Transfers, AXI4 does not support Locked Transfers.
WHAT DO YOU MEAN BY MULTIPLE OUTSTANDING TRANSACTIONS? WHY IS IT USEFUL?
Master initiates a transaction and doesn't wait for it to complete(response to arrive) and initiates
another transaction. So the first transaction is an outstanding transaction. AXI supports multiple
outstanding transactions so an AXI master doesn't have to wait for a transaction to complete to initiate a
new one. So the performance
is boosted.

WHY READ HAS ONLY 2 CHANNELS?

READ operation doesn't have a response channel because direction both the read data and read
response is from slave to master. With every beat, the slave will send a read response along with the
data in read data channel.

WHAT IS THE MINIMUM AND MAXIMUM DATA BUS WIDTH SUPPORTED IN AXI?
The data bus width as per spec can be 8,16,32...,1024 bits. So the minimum is 8 and maximum is 1024
bits

WHY IS WRITE DATA CHANNEL TREATED AS BUFFERED?

Write data channel information is always treated as buffered so that the master can perform write
transactions without slave acknowledgment of previous write transactions.
WHICH CHANNELS ARE EXCLUSIVE TO THE SLAVE?
Write Response and Read data channels.

AS PER AXI TERMINOLOGY DIFFERENTIATE BETWEEN BEAT, BURST AND TRANSACTION?

Transaction - The complete set of required operations on the AXI bus.
Burst - Required payload data to is transferred.
Beats - Burst can comprise multiple data transfers.

CAN A MASTER CAN GIVE WLAST IN MIDDLE OF A BURST TRANSFER?

No, Because early burst termination is not supported.

WHAT IS EASY ADDITION OF REGISTER STAGES TO PROVIDE TIMING CLOSURE?

Each AXI channel transfers information in only one direction, and the architecture does not require any
fixed relationship between the channels.

This means a register stage can be inserted at almost any point in any channel, at the cost of an
additional cycle of latency.

WHAT IS AN INTERCONNECT?
An Interconnect is a component with more than one interface that connects one or more master
components to one or more slave components.
WHAT IS CONTROL INFORMATION?
The characteristics of a transaction(read/write) like burst_length, burst_size, burst type, atomic
characteristics, etc are called the control information.

WHAT ARE THE MAJOR ACTIONS DONE BY INTERCONNECT?

Manages the transactions between the MASTER and SLAVE like Routing, providing responses, buffer.
TOPOLOGIES USING INTERCONNECT?
Shared address and data buses, shared address buses and multiple data buses, multilayer with multiple
addresses and data buses.
WHAT IS MEANT BY HIGH LATENCY?
If the AXI slave component is taking more time in responding back to the master for the completion of
the transfer then such components
are said to be having high initial access latency.
WHICH COMPONENT IS RESPONSIBLE FOR CALCULATING SUBSEQUENT TRANSFERS IN A BURST?
Slave(calculates address of subsequent transfers)
DIFFERENCE BETWEEN CHANNEL AND BUS ? IF THEY ARE SAME THEN WHY TWO DIFFERENT NAMES?
The input and output on hardware are set to individual channels. But the bus is just a pathway from
and-to somewhere.

WHAT IS NEED OF INTERLEAVING?

Data interleaving increases the throughput.

WHAT DOES AXLEN AND AXSIZE REPRESENTS?

The AXSIZE signal denotes how much amount of data in bytes can be accommodated in a single beat of
the burst.

AXLEN denotes how many transfers are there in a burst.

WHAT IS THE PURPOSE OF BYTE LANE STROBE ? IS STROBE USED FOR BOTH READ AND WRITE
OPERATION?
The strobe signal is used to indicate which bytes of the write data bus are valid for each transfer of data.
No, it's only used in a write operation.

WHAT'S THE PURPOSE OF LAST SIGNAL DURING A TRANSACTION? DOES BOTH READ AND WRITE
OPERATION USE IT? IF YES, WHICH CHANNEL IS USED TO SEND THIS SIGNAL?
This signal indicates the last transfer in a write/read burst. Yes, Write data and read data channels are
used to send this signal.

EXPLAIN THE BASIC HANDSHAKING MECHANISM IN AXI.

1.The source uses the VALID signal to indicate when valid information is available.
2.The VALID signal must remain asserted, meaning set to high, until the destination accepts the
information.
3.The destination indicates when it can accept information using the READY signal. The READY signal
goes from the channel destination to the channel source.
4.This mechanism is not an asynchronous handshake and requires the rising edge of the clock for the
handshake to complete.
DOES VALID AND READY SIGNAL HAVE DEPENDENCIES ON EACH OTHER?
No, the initiator and receiver should not wait for the assertion of handshaking signal but after a
successful handshake, valid must be deasserted as per spec.
WHEN SHOULD THE VALID SIGNAL GO HIGH AND LOW?
VALID should go high when the initiator has valid information to send. It should go low if there is no valid
information and it should go low after a successful handshake.
WHEN MUST THE SLAVE GIVE WRITE RESPONSE?
Write response is generated after the completion of a write transaction.

WHAT IS DEADLOCK CONDITION?

There are certain dependencies on how handshaking signals should be asserted. If it's violated
handshaking will not occur and the process will be stalled. It's called a deadlock scenario.

For eg., A deadlock condition can occur if the slave is waiting for WVALID before asserting AWREADY.
WHY THERE WAS NO WRITE RESPONSE FOR EACH BEAT IN BURST WRITE. BUT THERE IS A SEPARATE
READ RESPONSE FOR EACH BEAT IN A READ BURST?
For read transfers, the information and the response flow are from slave to master. But for a write
transaction, the information and the response are in different directions.
So individual responses for each transfer will involve more clock cycles and unnecessary traffic because
of the two-way flow between master and slave.
So it is better to have a single response for a write transaction compared to a response for each transfer
in a read transaction.

HOW TO ENSURE DATA INTEGRITY ON AXI?

By ensuring proper channel handshaking dependencies as per the protocol, We can ensure data
integrity.
IS THERE A POSSIBILITY THAT A READ TRANSACTION CAN COMPLETE IN ONE CYCLE?
NO, because data handshaking happens at least one CLK cycle after the address handshaking.
WHAT WILL HAPPEN IF LAST IS NOT ASSERTED AFTER COMPLETION OF THE TRANSFER?
With respect to write operation, WLAST indicates it's the last transfer in write burst. So if WLAST is not
provided by MASTER, the slave will not know whether the transfer is completed or not. So it will not be
able to assert any response signal.
IN AXI WE HAVE ANY TIME OUT CONDITION W.R.T CHANNEL HANDSHAKE.
NO, But it's based on the user's requirement.
WHAT IS 4KB ADDRESS BOUNDARY IN AXI?
The granularity of mapping in AXI is 4KB. That means the smallest "block" of addresses that can be
assigned to a given slave/peripheral is 4KB. And all allocations are multiples of 4KB. So when you cross a
4K boundary you are potentially going from slave A's address space to slave B' Discarding read data that
is not required can result in lost data when accessing a read-sensitive device such as a FIFO.

When accessing such a device, a master must use a burst length that exactly matches the size of the
required data transfer
IMPORTANCE OF RRESP AND BRESP?

After the initiation of a transaction, the Master must have status information of that particular
transaction. Sometimes an address to which a transaction
is initiated will not be available because the address will not be there or maybe not accessible because of
the secured type. Sometimes the slave may not accept the data.

So in these conditions the master but be aware of the status so it can act accordingly. So response signals
are important.

TYPES OF RESPONSES?
Okay, exclusive okay, decode error, slave error.

IF MASTER IS SENDING A ADDRESS BUT NONE OF THE SLAVE IS HAVING THAT ADDRESS. SO WHICH
RESPONSE WILL YOU GET?
Decode error

WITH RESPECT TO THE ASSERTION OF VALID AND READY SIGNALS, WHICH ORDER OF ASSERTION
PROVIDES MOST EFFICIENT HANDSHAKING?
When both the source and destination happen to indicate in the single rising edge, that they can transfer
the address, data, or control information.
In this case, the transfer occurs at the rising clock edge when the assertion of both VALID and READY can
be recognized. This means the transfer occurs at the next rising edge.

WHY THE SPECIFICATION RECOMMENDS DEFAULT STATE OF AWREADY AS HIGH?

When AWREADY is HIGH the slave must be able to accept any valid address that is presented to it. As the
default, AWREADY state of LOW forces the transfer to take at least two cycles, one to assert AWVALID
and another to assert AWREADY.