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Verilog Seq

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Aditya Agarwal
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11 views13 pages

Verilog Seq

Uploaded by

Aditya Agarwal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Using Verilog Constructs for Storage Elements

module flipflop (D, Clock, Q);


input D, Clock;
output reg Q;
always @(posedge Clock)
Q = D;
endmodule
Blocking and Non-Blocking Assignments

f = x1 & x2;

This notation is called a blocking assignment.

A Verilog compiler evaluates the statements in an always block in the


order in which they are written.

If a variable is given a value by a blocking assignment statement, then


this new value is used in evaluating all subsequent statements in the
block.
module example5_3 (D, Clock, Q1, Q2);
input D, Clock;
output reg Q1, Q2;
always @(posedge Clock)
begin
Q1 = D;
Q2 = Q1;
end
endmodule
Incorrect code for two cascaded flip-flops.
Since the always block is sensitive to the positive clock edge, both
Q1 and Q2 will be implemented as the outputs of D flip-flops.

However, because blocking assignments are involved, these two


flip-flops will not be connected in cascade.
The first statement Q1 = D; sets Q1 to the value of D. This new
value is used in evaluating the subsequent statement
Q2 = Q1; which results in Q2 = Q1 = D.
Verilog also provides a non-blocking assignment, denoted with <=.

All non-blocking assignment statements in an always block are


evaluated using the values that the variables have when the always block
is entered.

Thus, a given variable has the same value for all statements in the block.

The meaning of non-blocking is that the result of each assignment is not


seen until the end of the always block.
module example5_4 (D, Clock, Q1, Q2);
input D, Clock;
output reg Q1, Q2;
always @(posedge Clock)
begin
Q1 < = D;
Q2 < = Q1;
end
endmodule
module example5_5 (x1, x2, x3, Clock, f, g);
input x1, x2, x3, Clock;
output reg f, g;
always @(posedge Clock)
begin
f = x1 & x2;
g = f | x3;
end
endmodule
module example5_6 (x1, x2, x3, Clock, f, g);
input x1, x2, x3, Clock;
output reg f, g;
always @(posedge Clock)
begin
f < = x1 & x2;
g < = f | x3;
end
endmodule
ASYNCHRONOUS CLEAR
Following module defines a D flip-flop with an asynchronous active-low
reset (clear) input.

When Resetn, the reset input, is equal to 0, the flip-flop’s Q output is set to
0.
The sensitivity list specifies the negative edge of Resetn as an event trigger
along with the positive edge of the clock.
We cannot omit the keyword negedge because the sensitivity list cannot
have both edge-triggered and level sensitive signals.
module flipflop (D, Clock, Resetn, Q);
input D, Clock, Resetn;
output reg Q;
always @(negedge Resetn or posedge Clock)
if (!Resetn)
Q <= 0;
else
Q <= D;
endmodule
SYNCHRONOUS CLEAR

Module below shows how a D flip-flop with a synchronous reset


input can be described.
In this case the reset signal is acted upon only when a positive clock
edge arrives.
module flipflop (D, Clock, Resetn, Q);
input D, Clock, Resetn;
output reg Q;
always @(posedge Clock)
if (!Resetn)
Q <= 0;
else
Q <= D;
endmodule

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