Unit I

Introduction to Processing Units

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 Unit 1: Syllabus
Introduction to Processing units
Computer System, Processor, Block diagram, Processor logic unit, Control unit,
Instruction format, Assembly language, High level language, Embedded computing
applications, Microcontroller, Instruction set architectures (CISC, RISC), Harvard
and Von Neumann, Floating and fixed point
Introduction of controller families: 8-bit, 16-bit,32-bit,64-bit, ARM Processor
families, Cortex A, Cortex R and Cortex M, Thumb 2 instruction set

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Block diagram of a
computer system

MP
IC

 Bus: Collection of wires

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Source: T.L Floyd, “Digital Fundamentals”, 9e Bus
 Block diagram of a computer
 All computer systems consists of basic functional blocks that include a
CPU, memory and input/output ports.
 These blocks are connected together with three internal buses: Address
bus, Control bus, Data bus collectively called as system bus.
 A port is a physical interface on a computer through which data is passed
to and from peripherals.
 The memory includes program memory(ROM) to store instructions to
be executed to solve a specific problem and data memory to store data
during executing instructions.

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 Processor
 A processor unit is that part of a computer system or digital system
that implements the operations in the system.
 A Processor IC interfaced with many other components to realize
computer system.
 The user is expected to give instructions to the processor by writing
a program in assembly or high level language.

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 Processor: Block Diagram

Central
Processing
Other Units
Unit
(CPU)

IC package

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 CPU: Block diagram

Processor
Control Unit
Logic Unit

 Processor logic unit is a digital circuit capable of performing

different operations, which are controlled by control unit by
generating control signals.

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Processor Logic Unit(PLU)
 In most of the processors, the different operations are implemented by means of
arithmetic & logical operations.
 The processor logic unit consists of circuits to implement simple basic operations
like add, shift, etc…
 The other operations are generated by using basic operations available with the
support of control unit.
E.g. Multiplication operation is generated by repeated add instruction/ Shift
instruction
 Processor logic unit consists of circuits to implement Arithmetic & Logic
operations. These circuits are called as Arithmetic & Logic Unit(ALU).
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 PLU….

 The ALU receives the information(operands) from the registers and performs a
given operation as specified by control unit.
 The operation to be performed (instruction) by CPU is specified by the user by
writing programs.
E.g. C program.
 So, the PLU consists of ALU( additional digital circuits also) & registers
connected by buses.

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Simple PLU:
Bus
Organization

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 Bus Organization
 Different units are connected by buses: Bus organization
 Bus organization is also called as data path architecture because
different functional units & their connectivity through buses is
specified.
 Each register is connected to two multiplexers( MUX) to form input
buses A & B.
 The input buses A & B are applied to a ALU.
 The function selected in the ALU determines the particular operation
that is to be performed.
 The result of the operation goes through the output bus S into the
inputs of all registers.
 The shift operation is implemented in the shifter.
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 Bus Organization: An Example
 Operands:
- MUX A selector: One among 4 registers is to be connected to input
bus A & B , hence at least two select line(bits) are required.
MUX –A MUX-B
Select lines Register Select lines Register
A1 A0 Selected B1 B0 Selected
0 0 R0 00 R0
0 1 R1 01 R1
1 0 R2 10 R2
1 1 R3 11 R3

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Number of multiplexers
 One MUX is required to connect a bit of register to ALU, the number MUX required
is equal number of bits(size of ALU).
E.g: Size of ALU=4 bits => Register Size=4 bits

0 0 0 0

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Bus Organization: An Example
ALU
 Assume ALU performs 8 different operations.
 Hence, requires at least 3 bits of input to differentiate the operation.
 The ALU performs different operations according to table shown below.

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Bus Organization: An Example
Shifter
 Assume if Shift select=1, shift the data,
shift select=0, no shift
Decoder
 Decoder select a register to store data after operation.
 Assume decoder generate load signal to different register according to table shown below.
Destination Register
select Selected
D1 D0
00 R0
01 R1
10 R2
11 R3
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 So the control unit is ………

Operation and
Operands

Control Signals

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 Example:
 Assume: Operation to be performed is addition (by user)
R1 R1+R2
 Operation is called as an instruction.
 R2 is source operand & R1 is source as well as destination

Different Control signals

 MUX A select: 01 to select R1
 MUX B select:10 to select R2
 Function select: 000 for addition
 Shift select:0 no shift
 Destination select: 01 to load data to R1

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 Example contd…

 The macro operation(operation/Instruction) addition involves many

micro operations.
 Micro operations
- Place contents of R1 onto bus A
- Place contents of R2 onto bus B
- Perform Addition in ALU
- No shifting of data(transfer data)
-Select Destination register

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 Example…
 So, for the operation assumed, the control signals to be
generated are,

 The processor(Control unit & PLU) understands instructions in

binary format called as Machine(Processor) level language.
 It is not possible for the user to give instructions in binary
format.
 Hence, we have assembly language & high level language.

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 So,
how to write
instructions?

Mnemonics

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 Machine Independent High level languages

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Source: T.L Floyd, “Digital Fundamentals”, 9e
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 Example….
 Compiler & assembler generates machine codes, based on instruction format
of the processor.
 Instruction format or control word of the PLU considered:

 Function select is also called as Opcode(Operation Code)

 Machine code of the operation considered:
32H (H-Hexadecimal)

 So, this is one byte(8 bits) instruction.

 Assembly instructions are called instruction set of processor.

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Timing Sequence
 Each micro operation assumed takes some time for completion.
 The control signals are expected to generate in a sequence starting from source
operand selection.
 Assume, different successive times instants during which control signals generated
to complete the operation.
 T0 is time instant during which control signals for register selection are generated.
T0: Register selection (MUX A Sel=01, MUX B Sel= 10)
T1: Addition (Opcode=000)
T2: Shift( Shift Select=0)
T3: Destination Selection(Decoder input=01)
 To complete all micro operations, at least 4 time instants are required.
 The sequence of time instants form timing sequence.
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 Control unit modified

Operation and
Operands

Clock

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Questions?
 What is instruction code?
 What determines frequency of the clock?
 What is micro and macro instruction?
 What is control signal?
 What is mnemonics?
 What is an ALU size?
 What is a bus?

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 Control Unit(CU) Basics
 CU generates different control signals needed to perform different operations in data
path.
 2 ways to implement: Hardwired & Micro programmed
E.g: Consider a assembly program as follows for the PLU Considered.
(Note: Instructions & Mnemonics assumed are arbitrary.)
Begin
SUB R2,R1 Assembler Directives
CPL R3
AND R2,R3
OR R2,R3
end Instructions

 Assembler directives are used to give information to assembler only, no machine codes are generated,
hence called as pseudo instructions in the program.
(Assembler directives are similar to pre processor directives of high level languages).

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 Assembly Program with machine codes

 If the sequence of machine codes to be generated are known, then a digital circuit can be
designed to generate the machine codes => “Hardwired” Control Unit
 So, hardwired control unit is predesigned hardware capable of generating one sequence
of machine codes.

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 Control unit: Micro programmed
 The sequence of control signals(micro program) necessary to execute the
different instructions are stored in ROM called control ROM( Micro program
memory/Program memory).
 To execute instructions, the control signals stored in the ROM can be
accessed.
 The control signals read from the ROM are used to control the micro
operations associated with different instructions to be executed at any time.
 The address of the next instruction is generated by a special hardware called
micro program sequencer.

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Micro programmed Control unit

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Questions
1. Mention different functional units of a computer.
2. What is a processor?
3. What is Processor unit & Control unit ?
4. What is address bus, data bus, control bus?
5. What is address space of the processor?
6. What is the size of the memory supported by processor?

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 Questions
1. What is required in a processor to support memory?
2. What is data memory?
3. What is program memory?
4. What is chip select signal?
5. How many memory chips of size 4k x 4 are required to
realize 8k x 8 memory?

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 Microprocessor (MP) & Microcontroller (MC)
MP MC
 A silicon chip representing a Central • A microcontroller is a highly
Processing Unit (CPU), which is capable integrated chip that contains a CPU,
of performing arithmetic as well as RAM, On Chip ROM/FLASH
logical operations according to a pre- memory for program storage, Timer
defined set of Instructions. and Interrupt control units and
dedicated I/O ports.
 It is a dependent unit. It requires  It is a self contained unit and it
the combination of other chips like doesn’t require external Interrupt
Timers, Program and data memory Controller, Timer, UART etc. for
chips, Interrupt controllers etc. its functioning.
for functioning.
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 Microprocessor (MP) & Microcontroller (MC)
MP MC
 Doesn’t contain a built in I/O  Most of the controllers contain multiple
port. The I/O Port functionality built-in I/O ports which can be
operated as a single 8 or 16 or 32 bit
needs to be implemented with the Port or as individual port pins.
help of external Programmable
 Targeted for embedded market
Peripheral Interface Chips.
where performance is not so
 Targeted for high end market
critical (At present this
where performance is important. demarcation is invalid).
 Most of the time general purpose
 Mostly application oriented or
in design and operation. domain specific.
 Limited power saving options
 Includes lot of power saving
compared to microcontrollers. features.
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 Microprocessor (MP) & Microcontroller (MC)

Data Pgm Data Pgm

Memory Memory Memory Memory

 E.g:8051,STM32F407VG
 E.g:8086,Intel I5,I7
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 Instruction Set Architectures(ISAs)
 An instruction set, or instruction set architecture (ISA), is the part of the
processor architecture related to programming.
 All processors are supported by instruction set /instructions (Assembly
instructions) which are dependent on organization of different components in
PLU.
 Depending upon the way of supporting different instructions, the ISA is divided
into
-Reduced Instruction Set Computer(RISC)
-Complex Instruction Set Computer(CISC)
 Other types of ISA
- Very Long Instruction Word(VLIW), etc….
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 CISC & RISC Design Philosophy: CISC Vs RISC
CISC RISC
 More number of instructions  Lesser no. of instructions.
 Instructions are complex to  Instructions are Easier to
understand. understand.
• Hardware support for many • Software support for many
instructions (More silicon Usage) instructions/operations.
A programmer can achieve the desired (Less silicon usage)
functionality with a single instruction which Programmer needs to write more code to
in turn provides the effect of using more execute a task since the instructions are
simpler single instructions in RISC simpler ones
• Clock cycles per instruction(CPI) is  Clock cycles per instruction(CPI) is
more. less.
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 CISC & RISC Design Philosophy: CISC Vs RISC
CISC RISC
 Code density is more.  Code density is less.
 Less number of registers.  More number of registers.
 Memory to memory operations  No memory to memory operations
are supported. are supported.
Load & store operations in a Load & store operations not in
instruction a instruction ( So called as
load-store architecture)

• More number of addressing • Less number of addressing modes.

modes. • Fixed length instructions.
• Variable length instructions. • Design of Pipelining is easier.
• Design of Pipelining is Complex.
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 CISC & RISC Design Philosophy: CISC Vs RISC
CISC RISC
 Non Orthogonal Instruction  Orthogonal Instruction
Set Set
All instructions are not allowed to Allows each instruction to operate on
operate on any register and use any any register and use any addressing mode.
addressing mode. It is instruction • Examples: ARM, MSP 430, PIC
specific.
POWERPC, ATmega328P
• Examples: 8086

NOTE: The fact is, the designers are not worried about the architecture(CISC/RISC). So,
the features from both the architectures are mixed up to increase the performance(Increase
speed & reduce memory consumption).

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 Questions
 What is code density?
 What is an orthogonal instruction set?
 Why CPI is less in RISC architecture?
 Which is the preferable control unit to support complex operations ?
 What is the advantage/disadvantage of fixed length instructions?
 What is hardware support for an instructions?

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Von Neumann & Harvard Architecture
 This classification is based on processor architecture design to support memory.
 Address Space:
- No. of locations a processor/controller can address.
E.g: 8086: Address bus=20 bits, so address space is 1 Mb
(00000H-FFFFFH)
8051: Address bus=16 bits, so address space is 64 Kb
(0000h-FFFFh)
ARM Cortex M4: Address bus= 32 bits, So address space is
4GB(00000000h-FFFFFFFFh).

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Von Neumann/Princeton Architecture
 In this architecture, address space is
shared between program memory &
data memory.
E.g: STM32F407VG(based on Cortex M4)
-Total Address space is 4GB(32 bit address)
- The address space is shared between code
(Program flash), data(SRAM)
IO( peripheral),etc.

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 Von Neumann/Princeton Architecture….

 Single shared bus(Address, data & control: System bus) for

Instruction and Data fetching.

 The speed of execution is less because sharing of bus.

 The complexity of design of processor is less because single bus.

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Harvard Architecture
 In this architecture, address space
is not shared between program
memory & data memory.
E.g:8051 0xFFFF 0xFFFF
- Total address space for program
memory is 64KB & for data
64 KB 64 KB
memory is 64KB. Data
Program
- Program memory & data memory Memory Memory

locations are separate.

0x0000 0x0000
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 Harvard Architecture...

 Separate buses for Instruction and Data fetching.

 The speed of execution is more because separate buses.

 The processor design is complex.

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 Von Neumann & Harvard Architecture…

Final Note:
 Though STM32F407VG is Von Neumann address space, the architecture
is supported with separate buses for program and data space to increase
the speed.
 In fact, many controllers are based on separate bus architecture for
program and data memory.
 Von Neumann address space and Harvard bus architecture

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 Endianness
• Endianness refers to the sequential order in which bytes are arranged
into larger numerical values when stored in memory.
-Wiki
• Little-endian Operation

• E.g:STM32F407VG

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 Endianness…

 Big-endian Operation

E.g. Motorola 68000

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Fixed point and Floating point Processors

 Processing can be separated into two categories: fixed point and

floating point.
 These designations refer to the format used to store and manipulate
numeric representations of data.
 Fixed-point CPUs are designed to represent and manipulate integers –
positive and negative whole numbers.
 Floating-point CPUs represent and manipulate rational numbers in a
manner similar to scientific notation IEEE 754 ( Sign, mantissa and an
exponent).
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 Fixed point and Floating point ...

 The term ‘fixed point’ refers to a fixed number of digits after the decimal point.
E.g. 123.45, 1234.56, 12345.67
 With ‘floating-point’ representation, the placement of the decimal point can
‘float’ relative to the significant digits of the number.
E.g.1.234567,123456.7,0.00001234567, 1234567000000000
 The floating-point computation assures a much larger dynamic range - the largest
and smallest numbers that can be represented.
 Floating-point processing yields much greater precision(accuracy) than fixed-
point processing.

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 Fixed point and Floating point ...

 Certain processors are made fixed point where computations on floating

point numbers are carried out by converting them to fixed representations.
 These fixed point processors are relatively economical and faster for some
operations(integer operations).
 STM32F205 is a fixed point ARM cortex M3 based microcontroller.
 The floating point processors are supported with dedicated floating point
unit(FPU) to perform operations on floating point numbers by converting
them to single precision(32 bit) and double precision(64 bit) IEEE
754 representation.
 STM32F407VG is a single precision floating point ARM cortex M4 based
microcontroller.
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 Fixed point and Floating point ….
 Single precision(SP) floating point number representation

 E.g: 85.125= 1010101.001 =1.010101001 x 26

Sign=0
Biased exponent=127+6=133=10000101
Normalized Mantissa=010101001 (zeros are appended to make it 23 bits)
IEEE 754 format: SP
0 100 0010 1 010 1010 0100 0000 0000 0000 =42AA4000H

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 Fixed point and Floating point ….
 Double precision(DP) floating point number representation

 85.125= 1010101.001 =1.010101001 x 26

Sign=0
Biased exponent=1023+6=1029=100 0000 0101
Normalized Mantissa=010101001 (zeros are appended to make it 52 bits)
IEEE 754 format: DP
0 100 0000 0101 0101 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
=0x4055480000000000H
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 Introduction to controller families
 8-bit MCUs are low pin count devices offer great advantage in power consumption
compared to 16 bit and 32-bit counterparts.
 Typical Applications: Personal blood pressure monitors, pulse oximeters, heart rate
monitors, RF/Zigbee or Wi-Fi interfaces, transceivers, smartcards, power windows of
automobiles, smoke detectors, glass breakage detectors, thermostats, smart meters,
etc.
 In addition, these devices found abundant usage in consumer products like TV remotes,
geysers, smart rice cookers, washing machines, smart fans, etc.

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 8 bit MCUs

8 bit MCUs families:

 Intel 8051 family: 8051,8031,8052,8032, AT89C51, AT89LV51 (Intel is not silicon
provider).
 Microchip PIC® and AVR® Micro controllers:PIC16F, PIC18F series, AVR DD,
AVR DA, AVR DB and ATtiny1627 families. (AVR is Atmel earlier)
 STMicroelectronics STM8 series: STM8S, STM8L, STM8AF and STM8AL
 Infineon 8FX Microcontroller: CY95F632H/K, CY95F633H/K, CY95F634H/K,
CY95F636H/K (CY: Cypress is now Infineon)

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 What is Arm(earlier ARM)?
 The Arm holdings design 32/64 bit reduced instruction set computer
(RISC) instruction set architecture (ISA) (?)
 ARM does not manufacture silicon.
 ARM's business is to sell IP cores, which licensees use to create
microcontrollers and CPUs based on this core.
 IP cores:
-Gate Netlist (Hard)
-Synthesizable RTL code (Soft)

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 IPs Vs Silicon

 E.g: STM32F407VG(MCU used in lab by STMicroelectronics)

ARM Cortex M4 Core given ARM company

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ARM Design Features
Conditional execution of most
instructions, reducing branch overhead
and compensating for the lack of a branch
predictor(?).
 In ARM assembly, the loop is:
It avoids branch instructions when
loop :CMP Ri, Rj ; set condition "NE" if (i != j):
generating code for small if statements.
“ GT" if (i > j) or "LT" if (i < j)
In the C programming language, the loop is:
SUBGT Ri, Ri, Rj ; if "GT" (greater than), i = i-j;
while (i != j) SUBLT Rj, Rj, Ri ; if "LT" (less than), j = j-i;
{
BNE loop ; if "NE" (not equal), then loop
if (i > j)
 The Conditional execution avoids the branches
i -= j;
around the then and else clauses.
else
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}
Design Features contd..
• Another feature of the instruction set is the ability to fold shifts and rotates
into the data processing instructions. For example, the C statement:
a += (j << 2);
could be rendered as a single-word, single-cycle instruction on the ARM.
ADD Ra, Ra, Rj, LSL #2
This results in the typical ARM program being denser than expected with
fewer memory accesses; thus the pipeline is used more efficiently.
• Enhanced DSP/SIMD/VFP instructions are added to standard ARM
instruction set to support faster operation.
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 Design Features contd..
Advanced Microcontroller Bus Architecture (AMBA) has been widely used for ARM

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 ARM Processor Families

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 ARM Cortex Processor Families
 A Profile : Application processors which are designed to handle complex applications such as
high-end embedded operating systems (OSs)
-These processors requiring the highest processing power, virtual memory system support with
memory management units (MMUs).
E.g: High-end mobile phones(Samsung S6: Samsung Eqynos).
 R Profile: Real-time, high-performance processors targeted primarily at the higher end of the
real-time market.
-Those applications, such as high-end breaking systems and hard drive controllers, in which
high processing power and high reliability are essential and for which low latency is important.
 M Profile : Processors targeting low-cost applications in which processing efficiency is
important and cost, power consumption, low interrupt latency, and ease of use are critical.
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 Typical Application Domains

Source: google

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ARM Cortex-M Series

63 For more info on CoreMark: www.eembc.org MGR,ECE,RVCE

CoreMark
 CoreMark is small, portable, easy to understand, free, and displays a single
number benchmark score to represent the speed of processors.
 A processor with higher CoreMark number is faster. This rating is given by
CoreMark consortium.
 Earlier DMIPS(Dhrystone Million Instructions Per second) is the metrics used
specify the speed of processors.
 To avoid the problems associated with the DMIPS, CoreMark rating is
introduced.
 More info on CoreMark: https://www.eembc.org/coremark/

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 ARM Instruction Versions
Security

ML

DSP

ARMv9

ARMv7-M ARMv8-R/M www.arm.com

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 Traditional Arm ISAs
 ARM instruction set: 32 bit in size
 Thumb instruction set: 16 bit
Code Density Comparison

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 Traditional Arm ISAs
 Problem with ARM and Thumb: Interworking
 BX instruction is to be executed transfer control from ARM mode the Thumb
mode and to return to ARM mode.

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 Traditional Arm ISAs
 Solution is Thumb-2: Mixture of 16 bit and 32 bit instructions.
 Microcontroller used in lab is based on Thumb-2.

Exp1 code segment Disassembly view

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