Date: May 20, 2024 Project: etapa1

ADC_CLK_10 display:display_inst ARDUINO_IO[15..0]

GSENSOR_INT[2..1] ARDUINO_RESET_N
MAX10_CLK2_50
data_o[7..0]
LEDR[9..0]

7:0
13'h0
DRAM_ADDR[12..0]
SW[9..0] 2'h0
DRAM_BA[1..0]
KEY[1..0]
pll_spi:pll_spi_inst
GSENSOR_CS_N
areset
inclk0 GSENSOR_SCLK
MAX10_CLK1_50
1'h0
DRAM_CAS_N
spi_bitreceived GSENSOR_SDI
DATAIN OUT0
GSENSOR_SDI
1'h0
DRAM_CKE
1'h0
DRAM_CLK
1'h0
DRAM_CS_N
DRAM_DQ[15..0]
1'h0
DRAM_LDQM
1'h0
DRAM_RAS_N
1'h0
DRAM_UDQM
1'h0
DRAM_WE_N
GPIO[35..0]
GSENSOR_SDO
8'h0
HEX0[7..0]
8'h0
HEX1[7..0]
8'h0
HEX2[7..0]
8'h0
HEX3[7..0]
8'h0
HEX4[7..0]
8'h0
HEX5[7..0]
4'h0
VGA_B[3..0]
4'h0
VGA_G[3..0]
1'h0
VGA_HS
4'h0
VGA_R[3..0]
1'h0
VGA_VS

Page 1 of 1 Revision: etapa1

Date: May 20, 2024 Project: etapa1

display:display_inst
ADC_CLK_10 ARDUINO_IO[15..0]
GSENSOR_INT[2..1] data_o[0]~reg[7..0] ARDUINO_RESET_N
data_i[7..0]
MAX10_CLK2_50 D 13'h0
clk_i DRAM_ADDR[12..0]
data_o[7..0]
ack_i ENA LEDR[9..0]

7:0
spi_controller:spi_controller_inst 8'h0SCLR
2'h0 DRAM_BA[1..0]
SW[9..0] data_r~2 data_r~3 rst_ni
KEY[1..0] 6 0 1'h0 DRAM_CAS_N
6 1
pll_spi:pll_spi_inst data_r~0 GSENSOR_CS_N
areset c0 7
inclk0 c1 data_r~1 GSENSOR_SCLK
MAX10_CLK1_50 7 0
1 1'h0 DRAM_CKE
spi_bitreceived data_r~10 OE GSENSOR_SDI
DATAIN OUT0 DATAIN OUT0 GSENSOR_SDI
2
1'h0 DRAM_CLK
0 data_r~11
2 1'h0
1 DRAM_CS_N
data_r~12 DRAM_DQ[15..0]
1 1'h0 DRAM_LDQM
0 data_r~13
1 1'h0 DRAM_RAS_N
1
1'h0 DRAM_UDQM
data_r~14
0 1'h0 DRAM_WE_N
0 0 data_r~15 GPIO[35..0]
1 GSENSOR_SDO
data_r~4 8'h0 HEX0[7..0]
5 8'h0
spi_data_i data_r~5 HEX1[7..0]
5 0
1 8'h0 HEX2[7..0]
data_r~6 8'h0
1'h0 CIN LessThan3 HEX3[7..0]
29'h0 A[28..0] < OUT 4 8'h0 HEX4[7..0]
26{6},6:4 B[28..0] 4 0 data_r~7
Decoder0 8'h0 HEX5[7..0]
data_r~8 1
4'h0 VGA_B[3..0]
spi_clk 3:1 IN[2..0] OUT[7..0] 3
4'h0 VGA_G[3..0]
0 data_r~9
1'h0 CIN Add2 3 1'h0
1 VGA_HS
A[6..0] + OUT[6..0] Mux1
7'h6d B[6..0] sclk_o 4'h0
4:0

3:1 SEL[2..0] 1'h1 0 sclk_o VGA_R[3..0]

8'h0 data_w[7..0] OUT
DATA[7..0] 1 1'h0 VGA_VS
A[31..0] Equal0 data_r[7..0]
4:0

OUT
32'h0 B[31..0] = data_r[0]~reg[7..0]
spi_data_o~2
0 D
1'h0 CIN LessThan1 1'h1 CIN LessThan2 A[31..0] Equal1 1'h1 1
4:0
SEL[0]438<-0

A[4..0] < OUT always0 5'h2 A[4..0] < OUT 32'h1 B[31..0] = OUT ENA
A[31..0] Equal2
5'h10 B[4..0] B[4..0] spi_data_o~1 OUT 8'h0SCLR
0 32'h10 B[31..0] =
4:0

Mux0
1'h0 CIN Add1 1'h0 1 1'h1 CIN LessThan0
SEL[2..0]
4:1

counter~[4..0] A[4..0] + OUT[4..0] A[4..0] < OUT acq~reg0

1'h0 CIN Add0 5'h0 0 DATA[7..0] OUT 0 spi_data_o~0 0 spi_data_o~3
2:1

A[4..0] + OUT[4..0] 1 5'h1d B[4..0] 5'h8 B[4..0] D

1 1 acq
5:0

5'h1 B[4..0] CLK Q

switch
6'h0 addr[5..0] 0 1'h0SCLR
1'h1 rw 1'h11 CLRN

chip_select_o
clk_i
counter[4..0]
D chip_select_o~reg0
PRE
D
5'h0SCLR CLK
ENA Q
rst_ni_i 1'h0SCLR
req
switch

0 spi_data_o~4 spi_data_o~reg0
1 D
CLK spi_data_o
ENA Q
1'h0SCLR

Page 1 of 1 Revision: etapa1

Date: May 20, 2024 Project: etapa1

display:display_inst
data_o[0]~reg[7..0]
data_i[7..0]
clk_i
data_o[7..0]
ack_i

rst_ni

Page 1 of 1 Revision: etapa1

Date: May 20, 2024 DE10_LITE_Golden_Top.v Project: etapa1

1 // ============================================================================
2 // Ver :| Author :| Mod. Date :| Changes Made:
3 // V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file
4 // ============================================================================
5
6
7 //=======================================================
8 // This code is generated by Terasic System Builder
9 //=======================================================
10
11 `define ENABLE_ADC_CLOCK
12 `define ENABLE_CLOCK1
13 `define ENABLE_CLOCK2
14 `define ENABLE_SDRAM
15 `define ENABLE_HEX0
16 `define ENABLE_HEX1
17 `define ENABLE_HEX2
18 `define ENABLE_HEX3
19 `define ENABLE_HEX4
20 `define ENABLE_HEX5
21 `define ENABLE_KEY
22 `define ENABLE_LED
23 `define ENABLE_SW
24 `define ENABLE_VGA
25 `define ENABLE_ACCELEROMETER
26 `define ENABLE_ARDUINO
27 `define ENABLE_GPIO
28
29 module DE10_LITE_Golden_Top (
30
31 //////////// ADC CLOCK: 3.3-V LVTTL //////////
32 `ifdef ENABLE_ADC_CLOCK
33 input ADC_CLK_10 ,
34 `endif
35 //////////// CLOCK 1: 3.3-V LVTTL //////////
36 `ifdef ENABLE_CLOCK1
37 input MAX10_CLK1_50 ,
38 `endif
39 //////////// CLOCK 2: 3.3-V LVTTL //////////
40 `ifdef ENABLE_CLOCK2
41 input MAX10_CLK2_50 ,
42 `endif
43
44 //////////// SDRAM: 3.3-V LVTTL //////////
45 `ifdef ENABLE_SDRAM
46 output [12:0] DRAM_ADDR ,
47 output [1:0] DRAM_BA,
48 output DRAM_CAS_N ,
49 output DRAM_CKE,
50 output DRAM_CLK,
51 output DRAM_CS_N ,
52 inout [15:0] DRAM_DQ,
53 output DRAM_LDQM ,
54 output DRAM_RAS_N ,
55 output DRAM_UDQM ,
56 output DRAM_WE_N ,
57 `endif
58
59 //////////// SEG7: 3.3-V LVTTL //////////
60 `ifdef ENABLE_HEX0
61 output [7:0] HEX0,
62 `endif
63 `ifdef ENABLE_HEX1
64 output [7:0] HEX1,
65 `endif
66 `ifdef ENABLE_HEX2
67 output [7:0] HEX2,
68 `endif

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Date: May 20, 2024 DE10_LITE_Golden_Top.v Project: etapa1

69 `ifdef ENABLE_HEX3
70 output [7:0] HEX3,
71 `endif
72 `ifdef ENABLE_HEX4
73 output [7:0] HEX4,
74 `endif
75 `ifdef ENABLE_HEX5
76 output [7:0] HEX5,
77 `endif
78
79 //////////// KEY: 3.3 V SCHMITT TRIGGER //////////
80 `ifdef ENABLE_KEY
81 input [1:0] KEY,
82 `endif
83
84 //////////// LED: 3.3-V LVTTL //////////
85 `ifdef ENABLE_LED
86 output [9:0] LEDR,
87 `endif
88
89 //////////// SW: 3.3-V LVTTL //////////
90 `ifdef ENABLE_SW
91 input [9:0] SW,
92 `endif
93
94 //////////// VGA: 3.3-V LVTTL //////////
95 `ifdef ENABLE_VGA
96 output [3:0] VGA_B,
97 output [3:0] VGA_G,
98 output VGA_HS,
99 output [3:0] VGA_R,
100 output VGA_VS,
101 `endif
102
103 //////////// Accelerometer: 3.3-V LVTTL //////////
104 `ifdef ENABLE_ACCELEROMETER
105 output GSENSOR_CS_N ,
106 input [2:1] GSENSOR_INT ,
107 output GSENSOR_SCLK ,
108 inout GSENSOR_SDI ,
109 inout GSENSOR_SDO ,
110 `endif
111
112 //////////// Arduino: 3.3-V LVTTL //////////
113 `ifdef ENABLE_ARDUINO
114 inout [15:0] ARDUINO_IO ,
115 inout ARDUINO_RESET_N ,
116 `endif
117
118 //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL //////////
119 `ifdef ENABLE_GPIO
120 inout [35:0] GPIO
121 `endif
122 );
123
124
125
126 //=======================================================
127 // REG/WIRE declarations
128 //=======================================================
129
130
131 logic [7:0] data_r;
132 logic acq;
133 logic clk,sclk;
134 logic spi_operation ,spi_bittowrite ,spi_bitreceived ;
135 assign GSENSOR_SDI = spi_operation ? spi_bittowrite : 1'bz;
136 assign spi_bitreceived = GSENSOR_SDI ;

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Date: May 20, 2024 DE10_LITE_Golden_Top.v Project: etapa1

137
138 //=======================================================
139 // Structural coding
140 //=======================================================
141
142 spi_controller spi_controller_inst (
143 .data_w(8'b00000000 ),
144 .addr(6'b000000 ),
145 .rw(1'b1),
146 .data_r(data_r),
147 .req(SW[0]),
148 .acq(acq),
149 .rst_ni_i(KEY[0]),
150 .clk_i(clk),
151 .spi_clk(sclk),
152 .sclk_o(GSENSOR_SCLK ),
153 .chip_select_o (GSENSOR_CS_N ),
154 .spi_data_o (spi_bittowrite ),
155 .spi_data_i (spi_bitreceived ),
156 .switch(spi_operation )
157 );
158
159 pll_spi pll_spi_inst (
160 .areset(!KEY[0]),
161 .inclk0(MAX10_CLK1_50 ),
162 .c0(clk),
163 .c1(sclk),
164 .locked()
165 );
166
167 display display_inst (
168 .clk_i(clk),
169 .ack_i(acq),
170 .data_i(data_r),
171 .data_o(LEDR[7:0]),
172 .rst_ni(KEY[0])
173 );
174
175
176 endmodule
177

Page 3 of 3 Revision: etapa1

Date: May 20, 2024 spi_controller.sv Project: etapa1

1 module spi_controller (
2 input logic [7:0] data_w,
3 input logic [5:0] addr,
4 input logic rw,
5 output logic [7:0] data_r,
6 input logic req,
7 output logic acq,
8 input logic rst_ni_i,
9 input logic clk_i,
10 input logic spi_clk,
11 output logic sclk_o,
12 output logic chip_select_o ,
13 output logic spi_data_o ,
14 input logic spi_data_i ,
15 output logic switch
16 );
17
18 parameter time_to_counter = 16;
19 logic [4:0] counter;
20
21 assign sclk_o = (counter != 0) ? spi_clk : 1'b1;
22 assign switch = (chip_select_o == 0) ? ((counter <= 8) ? 1'b1 : (rw ? 1'b0 : 1'b1)) : 1'bx;
23
24 always @(posedge clk_i or negedge rst_ni_i) begin
25 if (!rst_ni_i) begin
26 counter <= 0;
27 end else begin
28 if (!chip_select_o && counter < time_to_counter ) begin
29 counter <= counter + 1;
30 end else begin
31 counter <= 0;
32 end
33 end
34 end
35
36 always @(posedge clk_i or negedge rst_ni_i) begin
37 if (!rst_ni_i) begin
38 chip_select_o <= 1;
39 end else begin
40 if (req) begin
41 chip_select_o <= 0;
42 if (counter == time_to_counter ) begin
43 chip_select_o <= 1;
44 end
45 end
46
47 end
48 end
49
50 always @(posedge clk_i or negedge rst_ni_i) begin
51 if (!rst_ni_i) begin
52 data_r <= 8'bxxxxxxxx ;
53 end else begin
54 if(switch)begin
55 if(counter<=8)begin
56 if(counter == 0) begin
57 spi_data_o <= 1'b1;
58 end else if(counter == 1) begin
59 spi_data_o <= 1'b0;
60 end else if(counter>=2)begin
61 spi_data_o <= addr[counter - 2];
62 end end else
63 begin
64 spi_data_o <= data_w[counter - 9];
65 end
66 end else begin
67 data_r[counter -9] <= spi_data_i ;
68 end
69 end
70 end

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Date: May 20, 2024 spi_controller.sv Project: etapa1

71
72 always @(posedge clk_i or negedge rst_ni_i) begin
73 if (!rst_ni_i) begin
74 acq <= 0;
75 end else if (counter == time_to_counter ) begin
76 acq <= 1;
77 end else begin
78 acq <= 0;
79 end
80 end
81
82
83
84
85 endmodule
86

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Date: May 20, 2024 display.sv Project: etapa1

1 module display (
2 input logic clk_i,
3 input logic ack_i,
4 input logic [7:0] data_i,
5 input logic rst_ni,
6
7 output logic [7:0] data_o
8 );
9
10 logic[7:0] inverted;
11
12 assign inverted ={data_i[0], data_i[1], data_i[2], data_i[3], data_i[4], data_i[5],
data_i[6], data_i[7]};
13 always @(posedge clk_i or negedge rst_ni) begin
14 if(!rst_ni) begin
15 data_o <= 8'b00000000 ;
16 end
17 else if(ack_i) begin
18 data_o <= inverted;
19 end
20 end
21
22 endmodule

Page 1 of 1 Revision: etapa1