Using case statements ·with the Multiplexer based architecture .

'1
• . . ff' . h . -- prov1ct
speed efficient solutions and 1s more e 1cient t an mference of . es area
. . PUOrity
usmg if-then-else statements. A- enc,
Fig. 4.6.5 shows the synthesized circuit of 4: 1 mux using B
case statement. For synthesize again the Xilinx XC4000 family Mux
C
is used as technology library. In tht:se examples, the case
implementation requires only one XC4000 CLB while the if D
implementation requires two CLBs (using the Synopsys FPGA
compiler). In this case, design the mux using the case statement SEL (1:0)
because fewer resources are used and delay path is shorter. Fig. 4.6.4 : Multiplex~r .
IISing
. · . · . case statement
The following examples mfer a 4 : 1 Multiplexer using a case statement.
library ieee;
use ieee.std_logic_1164.all;
.let o/r
o,10
entity MUX4_1 is
port( Sel : in std_logic;_vector(l downto 0); 0 O A
A, B, C, D : in std_logic; · 1?,·
Y : out std_logic );
end MUX4_1; C

'
f)
architecture behavior2 of MUX4 1 is
begin - l .
'
-- Most common and easies·t to read method
. ;.:. Multiplexer selection very clear using case statement
process (Sel, A, B, c, D)
begin ·
case Selis
when "00" => Y<=A·,
when "01" ;:::> Y<=B·
wh~n "10" => Y<=C;
when "11" => Y<=D·
when others => y<~A.
end case; '
end process;
end behavior2;
 • /4rtttt' rims 11±1
II VLSI Design & Technology (PTU)
~20 Comb·

. - , a conditional assignment may be more natural t 0

inationa\
.
c·ircuit D
es191 ,,,_,1E!--
sign
&Techn
ology (PTU) d
4 21
.·
!Iowe_ve,,_ whateve, ala type" Used, lo, « ample, ""''' "°"•
Combinational Circuit Design

always beit""'
In sununarv. " 111 1"' . • d · d •• \Vrite 5ta d from an mteger data type before the case statement and back again after.,
s1·gnal assirr1m1cni ma v be preferable to avoid mtro ucmg a ditional, unwanted 1 , _a Seleo,. ~teJllent.
verte . n be cumbersome .
-. ' . ' "' " ogic · '"'d con h thlS ca
circuit. · · in Y%r al thoug
. Binary Encoder :
_ VHDL Modeling of Encoders : An s.3 .
49
_g.1 oder is modeled ac~ordmg to the truth table of Table 4.9.1 using the if, case
Discn:tc quantities
. of digital information., data, are often r e p r e tnsaeCodn ~ All g,3 ene
Stateme nt' and addumnally fo, VIIDL, eond,uo.,, '"" « leet<d , igo,J
A r for
binary bcmg the most popular. ed forni; 0
1
Encoders a.re used to enc~de discrete data into a coded form and decoders , 1 use
as11signments . a default assigned output value to avoid having to explicitly
. define
.. all
convert it back into its ong111al undecoded form . are Used to , mode s . ut conditions that should not occur under normal operating conditions.
2
An encoder
. that has 2n (or less) input lines encodes input data to . tv
s - 8 == 248 mp. nment is a " don ' t care" val ue to nurum1ze
· · . syn th es1ze
. d Iog1.c.
output Imes . n encoded
Th
8 · assig
e default put co nditions that are not explicitly defined default to binary 000, more
The rruth table for an 8-3 binary encoder (8 inputs and 3 outp ts . •• If all. 24ouldmbe syn thesized than is necessary.
Table .4.9.1. It is assumed that only one input has a value of 1 atu ~y 1
) ts •shown in
otherwise the output has some undefined value and the circuit is meam· ng1ess. given time ,
•
~ ~
i statement :
f. 8 -., Pnrrvvu

/able 4.9.1: Truth table for an 8-3 binary encoder

~
1ibf3 rIEEE;
yD L0Gl(_ll 64 · all ' IEEE.NUMERIC_STD.all;
Outputs use IEEE.ST -
Inputs
A7 A6 A5 A4 A3 A2 Al AO Y2 YI YO C0DER8 is )·
0 0 0 0 0 0 I 0 0 0 entity EN . in std_ log1. c- vector (7 downto O ' .
0
port (A.
Y: out std_ log1c_. vector (2 downto 0)),
0 0 0 0 0 0 I 0 0 0 I
end ENCODER8;
0 0 0 0 0 I 0 0 0 I 0
0 0 0 0 I 0 0 0 0 I I architecture ARCH of ENCODER8 is
0 0 0 I 0 0 0 0 I 0 0 begin
0 0 I 0 0 0 0 0 I 0 I process (A)
0 I 0 0 0 0 0 0 I I 0
begin
If (A= "00000001") then Y <= "000";
J 0 0 0 0 0 0 0 I I I
elsif (A = "00000010") then Y <= "001" ;
• The encoder described by the truth table may be modeled by using the if, case
. statements, or selected signal assignments . . elsif (A= "00000100") then Y <= "010";
• Once again, case statements are more concise and clear than if statements and this elsif (A= "00001000") then Y <= "011";
becomes increasingly ob,~ous when the number of inputs to the encoder increase. elsif (A= "00010000") then Y <= "100";
• 11
Selected signal assignment is also very clear. It is the concurrent equivalent of case elsif (A= "00100000") then Y <= "101";
statement.
elsif (A= "01000000") then Y <= "110";
• The far loop is better for modeling a larger or more generic m-n bit encoder. All models elsif (A= "10000000") then Y <= "111";
of such a circuit must use a default "don 't care" value to minimize the synthesizei
else Y <= "XXX";
circuit as only 8 of the 256 (i) input conditions need to be specified. The synthesis 100 '
end if;
if capable, replaces "don ' t care" values with logic O or I values as necessary in order to
minimize the circuit's logic. end process;
• TI . V .
us means HDL mteger data type cannot be used for the case selector 111
. a case
,
-
end ARCH;

Fig. 4.9 .1 show s a Simulation waveform display of the above VHDL model. From
 & Technology (PTU)
4-36 Combinational . n & Technology (PTU)
\/LS\ D .:..::::· Circuit
v~ - -
., fa-4.10.l : Truth table of 3;8 decoder when 5 => Y <= "00100000"·
. ·-· ,

' Input . Outputs when 6 => Y <= "01000000";

when 7 => Y <= "10000000";
A2 A1 Ao Y, y6 Ys Y4 Y3 Y2 yl '? end case;
0 0 0 0 0 0 0 0 . 0 -K
0 I end process;
0 0 0 0 0 0 -r---
J
0 0 1 . 1 0 dbehaviora:;:.l;-:--:--:--:-----:-------
-r--- en
0 1 0 0 0 0 0 0 1 ~g select signal_assignment :
0 0
0 0 0 0 1 0
-r--
0 1 1 0 0 librat'Y IEEE;
0 0 0 1 0 0 .
- r-- use JEEE.STD_LOGI(_l 164.all, IEEE.NUMERIC_STD.all;
1 0 0 0

-
0
. - r--- use JEEE.STD_LOGIC_ARITH .all;
1 0 1 0 0 1 0 0 0 0 0 a I use !EEE.~TD_LOGICUNSIGNED.all;
1 1 0 0 1 0 0 . 0 0 0 0
I 1 1 1 0 0 0 0 0 0 0
- entity Decoder3_8 is
1) Using Case statement : Port ( A: in integer range Oto 7;
Y: out std_logic_vector(7 downto O));
library IEEE;
use IEEE.STD_LOGIC_l 164.all, IEEE.NUMERIC_STD.all; end Decoder3_8;

use IEEE.STD_LOGIC_ARITH .all;

use IEEE.STD~LOGI(_UNSIGNED.all; architecture behavioral of Decoder3_8 is
begin

entity Decoder3_8 is with Aselect

Port ( A: in integer range Oto 7; Y<= "00000001" when 0,

Y: out std_logic_vector(7· downto 0)); "00000010" when 1,

end Decoder3_8; "00000100" when 2,
architecture behavioral of Decoder3..,8 ts "00001000" when 3,
begin "00010000" when 4,
process (A) "00100000" when 5,
begin "01000000" when 6,
case A is "10000000" when 7,
when 0 => Y <= "00000001"; ed "O000OOOO" when others;
when 1 => Y<= "00000010"; n behaVioral;

when 2 => Y <= "00000100";

when 3 => Y <= "00001000";
when 4 => Y <= "00010000";
 --
L ...-11 u ... .. . r -- .

4.12 VHDL Modeling of Code Converter':

Code systems and coding devices . are 1used
. in data processing
aki .d . s1.on 1l
and tran Sll1Js
equipment, and development of automatic contro s 1s m ng rap1 progress. A code is i tibran
use ie
, cess-
based on the features of each coding system. The common codes used are binary exe ected. 1
grey, BCD etc. ' entit
Table 4.12.1 : Code Conversion

· Decimal Binary Excess-3 Grey

0 0000 0011 0000 end
1 0001 0100 0001
0010 01-01 0011 arc
2
be
3 0011 0110 0010
4 0100 0111 0110
5 0101 1000 0111
6 Q_UQ 1001 0101
7 0111 1010 0100
8 1000 1011 1100
9 1001 1100 1101
10 1010 1101 1111
11 1011 1110 1110
12 . 1100 1111 1010
13 1101 0000 1011
14 1110 0001 1001 ·
15 1111 0010 1000
Ill "111111

VLSI Design & Technology (PTU2 4-52 Combinati chnology_ (PTU}

"1101" when "1010", when "1110" => ex3 "00l0";

"1110" when "101.-1", when "1111" => ex3:<= "00ll";
\ '"1111" wben ''.1100", end case~ :---.
"0000" •w,hen "1101",
end process;
"0001" when "1110", ·
"0010" when others; dexam;
e n ~ arithmetic operator :
xam;
3)
using:-------------
, Using case statement : ~ieee;
Ii . td Logic_l 164.all;
library ieee; se ,eee.s - .
u . td Logic_arith.all;
use ieee.std_loglc_l164.all; use ieee,s - • .
entitY bin2eX3 1s_ .
port (bin : in _std_log1c_vector(3 dQwnto 0);
entity bin2ex3 is
ex3 : out std_logic_vector(3 dow~to O));
port (bin : in std_logic_vector{3 downto ,0);
ex3: out std_logic_vector{3 downto O)); end bin2ex3;
end biri2exJ;
. . ,, .11,,
architecture exam of bin2ex3 is
-architecture exam of bin2ex3 is be-gin
begin ex3 <=bin+ "0011";

process (bin) . •. II end exam;

begin For · the simulation_ of this VHDL -~odel, the input signals bin are monitored.
case bin is Fig. 4.12.l(a) shows a Simulation wavefol'Il). display ,_pJ the -above VHDL model. In the
when "0000" => ex~ <= "0011"; waveform _at fl-3.6ns the value of ex3 is '~lOP"·.!._":hich .the equivalent to binary code. From

--
when "0001" => ex3 <= "0100"; these we can conclude . that the functional simulation of binary to excess-3 converter is
when "0010" => ex3 <= "0101"; successful by satisfying the truth table.
when "0011" => ex3 <= "0110";
when "0100" => ex3 <= "1000";
'•~
Snalon W.Yffllnll look tleP • .. •
e,'',' ..-- ~~-.i i'o~t!-"~ «• C• "" '. ,iii.,, l
..
when "0101" => ex3 <= "1001"; ~ , :-~~~i~-~-:-i~~:~:.~1-~?1~_::.~ 1~·• ·... . ,..•·,. ,.........·
when "0110" => ex3 <= "1010";

when "0111" => ex3 <= "1011";

"""
"""
when "1000" => ex3 <= "1100"; """
·•"""
wheri "1001" => ex3 <,;, "1101";
when "1010" => ex3 <= "1110"·
\ ' ·,
when "1011" => ex3 .<= "1111";
when "1100" => ·ex3 <= "0000";
when "1-101'" => ex3-<=-"0001"; F'•g. 4 .t2.l(a) : Simulation result of binary to excess-3 converter
 VLSI Design & Technology (PTU) 4-58 Combinational ' hnOlogy (I-' I U) 4-59
& rec~--=-- -----..;:.
- _circuit
Der
"0110000" when "1110", -- e
"0111000" when "1111", -- f
1ji
_,,_,, o
eslgn
,.,«
.
V}IDL code ro, the cueuit can be Biv.n
the rnal signals s,, Sas,, s. s, can be .,
'"" "°'"
Cornblnati

.:,•,1~..,,1i,,,,.""" c..,.,

"1111111" when others; -- turn off all leds ed-·

. f!te inte .
0 as StdJogic or hit· ow ltlctlkid
iS os code: ,
end bcdto?seg; vt-lDL .
4.13 Implementation of Boolean Equations : i Ubra rJ jeee, . 1164.all;
td_log1c_ .
·eee.s
ose 1 .

The follmving steps can be adopted to implement the Boolean e q uns a into
tio ~
\1t,-. oleanis ..
code. . . 'lllll tft)I bO C. in std_log1c/ .
en rt (A,B, • •)
I. First simplify the given Boolean equation using the Karnaugh' s map. po y: out std_log1c ;
2. Then realize the equation into circuit. boolean;,
3. By using the circuit diagram write the VHDL code using the dataflow end
- or struch,-'
method. . .... ill ~rchitecture equation of boolean is
4. You can also write the truth table for the simplified Boolean equation and then . signal s1, s2, s3, s4,s5:_std_logic;
table you can write the VHDL code in Behavioural modeling. using !hi&
begin
5. The data. flow method is one of the most common and simple method to imple sl<"' n?,t A;
/' Boolean equations because it generates the smaller and faster synthesized circuit. ment s2<= B xnor C;
Example 4.1 : Write down the VHDL code for following logical expression. - s3<= B xor C;
F (A,B,C) = k m (0, 3, 5, 6) s4<= s1 and s2;
Solution: ctB AB AB AB AB C B AB AB AB AB s5<= s3 and A;
- -- - . 00 01 11 10 Y<= s4 or s5;
1 0 01 1 .3 0. 2 coCDoCDo end equation;
0
4
,5
0_7 1• 6 C1 0 CD O CD Simulation :

Simplified Boolean equation Fig. P. 4.1.l(b) shows a simulation result for the above Boolean equation. At
y = Al!G:+ AeC + ABC + ABt = ABC + ABC + ABC + ABC instance 184.2 ns the inputs A, B, and C are 0, I and l respectively. Their corresponding
-- .
output can be verified from Table P. 4.1.1. It shows ~t ;uncti~nal simulation is successful.
y = A(BC + BC) + A (B CT BC) ii
Table P. 4.1.1 : Truth table for example 4.1
y = ~ C ) + A (BEBC)
A B C -
A B@C A_(BEBC) A(BEBC) y
The circuit realization · of above A B C (fiEBC)
simplified. Boolean equation is shown in
S1
'1 S1 S2 SJ s, Ss
Fig. P. 4.1.l(a). 0 I
0 0 0 1 1 0 1
Where, S1 = A 0 0 1 0 0 0
1 1 0
0 0 0 0-
S 2 = B@C 1 0 1 0 1
0 I
0 I I 1 I 0 1 -

S3 =B$C
0 ()
I 0 0 0 ' 1 0 0
S4 =
--
A(B.EBC) 1 I l \
I 0 I 0 0 l 0
\ \
S5 = A(BEBC) Fig. P. 4.1.l(a) I I 0 0 0 I 0
- I

_ __..-:-