Chapter 4

Reversible Logic Gates

Abstract A reversible logic gate is a memory-less logic element that realizes an in-
jective logical function. Fredkin gate, Toffoli gate, interaction gate, and switch gate
are typical ones. Here, we investigate basic properties of reversible logic gates and
circuits, which are needed in the following chapters. First, logical universality of
them is discussed. Then, a construction method of an almost garbage-less reversible
combinatorial logic circuit is explained. Reducing the total amount of garbage sig-
nals is an important problem in designing reversible logic circuits. Finally, relations
among Fredkin gate, reversible logic elements with 1-bit memory (RLEMs), and
reversible sequential machines (RSM) are studied. In particular, it is shown that we
can construct a completely garbage-less circuit out of Fredkin gates and delay ele-
ments that simulates a given RSM. This result will be used to show universality of
reversible cellular automata in the later chapters.

Keywords reversible logic gate, Fredkin gate, garbage-less circuit, rotary element,
reversible sequential machine

4.1 Reversible Logic Gates and Circuits

In Chaps. 2 and 3, we presented reversible logic elements with memory (RLEMs),

and studied their universality and how to use them. There, we gave a systematic
method of composing reversible sequential machines (RSMs) out of them. In this
chapter, we study reversible logic elements without memory, which are usually
called reversible logic gates, and circuits made of them. We first introduce typi-
cal reversible logic gates, in particular, Fredkin gate, Toffoli gate and others, and
investigate their logical universality. Next, we explain how a “garbage-less” circuit
can be constructed from them that realizes a given (not necessarily injective) logical
function. In the design theory of circuits composed of reversible logic gates, it is an
important problem to reduce the amount of garbage signals produced in the circuit.
This is because production of garbage information leads inevitable power dissipa-
© Springer Japan KK 2017 77
K. Morita, Theory of Reversible Computing, Monographs in Theoretical Computer Science.
An EATCS Series, DOI 10.1007/978-4-431-56606-9_4
78 4 Reversible Logic Gates

tion in the computing system [2, 5]. In Sect. 4.2, we consider the relationship among
reversible logic gates, rotary element (RE), and RSMs. In particular, we shall show
that RE and RSMs can be realized by completely garbage-less circuits composed of
Fredkin gates and delay elements. In Chap. 6, a garbage-less construction method
of reversible Turing machines (RTMs) out of REs is shown. Hence, it is also pos-
sible to realize RTMs as garbage-less circuit composed of Fredkin gates and delay
elements. In Sects. 12.3, 13.2 and 13.3, these results will be used to design compu-
tationally universal reversible cellular automata having very simple local transition
rules, in which any circuit composed of Fredkin gates can be embedded.

4.1.1 Reversible logic gates

We define a logical function, a logic gate, and a reversible logic gate as follows.
Definition 4.1. A function f : Bm → Bn is called a logical function or a Boolean
function (m, n ∈ {1, 2, . . .}), if B = {0, 1}, where 0 and 1 stand for the truth values
“false” and “true”, respectively. An element that realizes the function f is called an
m-input n-output logic gate. If the function f is injective, then the gate that realizes
f is called a reversible logic gate. Note that, in this case, m ≤ n must hold.
Early study on reversible logic gates was made by Petri [11]. Then, Toffoli
[16, 17], and Fredkin and Toffoli [5] investigated them in connection with physi-
cal reversibility. We first introduce typical examples of reversible logic gates.
Fredkin gate proposed by Fredkin and Toffoli [5] is one that realizes the logical
function fF : {0, 1}3 → {0, 1}3 such that fF : (c, p, q) 7→ (c, c· p + c·q, c·q + c· p),
where ·, +, and ¯ stand for logical product, logical sum, and negation, respectively.
Here, we depict it as in Fig. 4.1 (a), which is the original representation given in
[5]. There are also other representations shown in Fig. 4.1 (b) and (c). In the design
theory of quantum logic circuits, Fig. 4.1 (b) or (c) is often used.
As in Fig. 4.2, the input c controls how to connect the other two input lines to the
output lines. The truth table of the Fredkin gate is given in Table 4.1, from which
injectivity of fF is easily verified.

c ✲ x=c
c ✲ c c ✲ c
p ✲ y = c· p + c·q
p ✲ c·q + c· p p ✲ c·q + c· p
q ✲ z = c·q + c· p
q ✲ c· p + c·q q ✲ c· p + c·q
(a) (b) (c)

Fig. 4.1 Pictorial representations of Fredkin gate. The representation (a) is the original one given
in [5], while (b) or (c) is often used in the design theory of quantum logic circuits. Note that the
positions of the second and the third outputs of (b) and (c) differ from those of (a)
4.1 Reversible Logic Gates and Circuits 79

c=0 ✲0 c=1 ✲1
p ✲q p ✲p
q ✲p q ✲q

Fig. 4.2 Operations of Fredkin gate

Table 4.1 The truth table of the logical function fF : (c, p, q) 7→ (x, y, z) of Fredkin gate
c pq xy z
0 00 00 0
0 01 01 0
0 10 00 1
0 11 01 1
1 00 10 0
1 01 10 1
1 10 11 0
1 11 11 1

Fredkin gate has another property that is related to the conservation law in
physics. A logical function f : {0, 1}m → {0, 1}n is called bit-conserving, if the
following condition holds.

∀x = (x1 , . . . , xm ) ∈ {0, 1}m , ∀y = (y1 , . . . , yn ) ∈ {0, 1}n

( f (x) = y ⇒ (|{i | xi = 1 ∧ i ∈ {1, . . . , m}}| = |{i | yi = 1 ∧ i ∈ {1, . . . , n}}|)

Namely, the number of 1’s in the input is always the same as the number of 1’s
in the output. If the signals 0 and 1 are represented by absence and presence of a
particle, some amount of energy, or something like them in a physical system, then
this property corresponds to the conservation law of mass, energy, or other physical
quantity. From Table 4.1 we can see Fredkin gate is a bit-conserving gate.
The generalized AND/NAND gate proposed by Toffoli [16] is the gate that real-
izes the function θ (n) : (x1 , x2 , . . . , xn−1 , xn ) 7→ (x1 , x2 . . . , xn−1 , (x1 ·x2 · · · xn−1 ) ⊕ xn ),
where ⊕ is the operation of exclusive OR. It controls the input xn by the logical
product of x1 , x2 , . . . , xn−1 , i.e., if x1 ·x2 · · · xn−1 = 0 then the n-th output is xn , and if
x1 ·x2 · · · xn−1 = 1 then it is xn . The functions θ (2) and θ (3) are called the controlled
NOT (CNOT) and the Toffoli gate, respectively. The logical function realized by
the Toffoli gate is thus fT : (x1 , x2 , x3 ) 7→ (x1 , x2 , (x1 ·x2 ) ⊕ x3 ). The Toffoli gate is
depicted as in Fig. 4.3, and the truth table of fT is given in Table 4.2.

x1 ✲ y1 = x1
x2 ✲ y2 = x2
x3 ✲ y3 = (x1 ·x2 ) ⊕ x3

Fig. 4.3 Toffoli gate

80 4 Reversible Logic Gates

Table 4.2 The truth table of the logical function fT : (x1 , x2 , x3 ) 7→ (y1 , y2 , y3 ) of Toffoli gate
x1 x2 x3 y1 y2 y3
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 1
1 1 1 1 1 0

4.1.2 Reversible combinatorial logic circuits

Connecting reversible logic gates, we can compose a logic circuit. We introduce a

reversible combinatorial logic circuit that realizes an injective logical function.

Definition 4.2. Let S be a finite set of reversible logic gates. A reversible combi-
natorial logic circuit Φ over S is a system composed of a finite number of copies
of reversible logic gates taken from S, which are connected each other under the
following constraint.
1. Each output of a gate can be connected to at most one input of some other gate,
i.e., fan-out of an output is inhibited.
2. Two or more outputs should not be connected to one input port of some other
gate, i.e., merging of outputs is inhibited.
3. The circuit should not contain a closed path, i.e., no feedback loop is allowed.

Note that, in the above definition, fan-out (copying) of an output is not allowed
in 1. There are several reasons to put this restriction. The first reason is as follows.
In the traditional technique for (irreversible) logic circuits, fan-out is implemented
at the cost of supplying some amount of energy. Since energy consumption is an
important problem in reversible computing, fan-out should be inhibited, and such an
operation must be treated explicitly in a logic circuit. Secondly, a quantum circuit,
which is a circuit model in quantum computing, can be viewed as an extension of
a reversible logic circuit. In a quantum circuit, signals have values of quantum bits
rather than classical bits (i.e., 0 or 1). In quantum physics, “no-cloning theorem” for
quantum bits has been proved [4, 19]. Hence, a signal in a quantum circuit cannot
be copied. Since reversible logic circuits are often used as parts of quantum circuits,
fan-out is inhibited also in these circuits. The third reason is that we sometimes
use an “inverse” circuit of a given reversible circuit (see Sect. 4.1.4). If the original
circuit contains fan-out, then the inverse circuit will have a merge of two or more
outputs, and thus there arises a problem to define its behavior.
4.1 Reversible Logic Gates and Circuits 81

Let Φ be a reversible combinatorial logic circuit. The input ports of gates that
are not connected to other gates are the input ports of the entire circuit Φ. Likewise,
the output ports of gates that are not connected to other gates are the output ports of
Φ. Obviously, if we supply truth values to the input ports of Φ, then it gives output
values from those output ports. Thus, the whole circuit Φ implements some injective
logical function. However, here, we use the following technique to “embed” a non-
injective logical function in Φ. The set of input ports of Φ are partitioned into a
set X = {x1 , . . . , xm } of actual inputs, and a set C = {c1 , . . . , ck } of constant inputs.
The set of output ports of Φ are partitioned into a set Y = {y1 , . . . , yn } of actual
outputs, and a set G = {g1 , . . . , gl } of garbage outputs (Fig. 4.4). Note that we also
use the symbols x1 , . . . , xm , c1 , . . . , ck , y1 , . . . , yn , and g1 , . . . , gl to represent the truth
value at the corresponding ports. Furthermore, the logical function realized by the
whole circuit is written by the same symbol Φ. Hence, Φ(c1 , . . . , ck , x1 , . . . , xm ) =
(g1 , . . . , gl , y1 , . . . , yn ).

c1 ✲ ✲ g1
.. ..
. .
ck ✲ ✲ gl

x1 ✲
Φ ✲ y1
.. ..
. .
xm ✲ ✲ yn

Fig. 4.4 Embedding a logical function f : (x1 , . . . , xm ) 7→ (y1 , . . . , yn ) in a reversible combinatorial

logic circuit Φ. It has constant inputs c1 , . . . , ck , and garbage outputs g1 , . . . , gl , besides actual
inputs x1 , . . . , xm , and actual outputs y1 , . . . , yn

Definition 4.3. Let f : {0, 1}m → {0, 1}n be a logical function, and Φ be an injective
logical function with the sets of actual inputs X = {x1 , . . . , xm }, constant inputs C =
{c1 , . . . , ck }, actual outputs Y = {y1 , . . . , yn }, and garbage outputs G = {g1 , . . . , gl }.
We say f is embedded in Φ, if the following condition holds.

∃(c1 , . . . , ck ) ∈ {0, 1}k ,

∀(x1 , . . . , xm ) ∈ {0, 1}m , ∀(y1 , . . . , yn ) ∈ {0, 1}n ,
∃(g1 , . . . , gl ) ∈ {0, 1}l
( f (x1 , . . . , xm ) = (y1 , . . . , yn ) ⇒ Φ(c1 , . . . , ck , x1 , . . . , xm ) = (g1 , . . . , gl , y1 , . . . , yn ))

This condition says that by allowing to supply appropriate constant values to

c1 , . . . , ck , and to generate garbage outputs from g1 , . . . , gl , the circuit Φ computes
the logical function f (even if it is non-injective).
82 4 Reversible Logic Gates

4.1.3 Logical universality of reversible logic gates

Logical universality of a reversible logic gate, and a set of reversible logic gates is
defined as follows.

Definition 4.4. Let S be a finite set of reversible logic gates. If any logical function
f is embedded in a reversible combinatorial logic circuit over S, then the set S is
called logically universal, or functionally complete. If a set S is logically universal,
and S is a singleton, i.e., S = {s} for some reversible logic gate s, then the the gate
s is also called logically universal.

In the case of traditional (irreversible) logic gates and circuits (in this case there
is no notion of garbage outputs), it is well known that the set {AND, NOT} is
logically universal. To prove universality of a given set S of reversible logic gates, it
is sufficient to show each of the functions AND, NOT, and fan-out can be embedded
in a circuit constructed from gates taken from S.
In [5] it is shown that Fredkin gate is logically universal. Figure 4.5 gives circuits
that embed AND, NOT, and fan-out. Note that each of these circuits consists of one
Fredkin gate. Thus, any logical function can be embedded in a circuit composed
only of Fredkin gates. Toffoli gate is also logically universal [16]. Figure 4.6 gives
circuits that embed AND, NOT, and fan-out.

x1 ✲ x1 x1 ✲ x1 x1 ✲ x1
x2 ✲ x1 ·x2 1 ✲ x1 1 ✲ x1
0 ✲ x1 ·x2 0 ✲ x1 0 ✲ x1

AND NOT Fan-out

(a) (b) (c)

Fig. 4.5 Logical universality of Fredkin gate. (a) AND, (b) NOT, and (c) fan-out are embedded
in the circuits by allowing constant inputs and garbage outputs

x1 ✲ x1 1 ✲1 x1 ✲ x1
x2 ✲ x2 1 ✲1 1 ✲1
0 ✲ x1 ·x2 x3 ✲ x3 0 ✲ x1

AND NOT Fan-out

(a) (b) (c)

Fig. 4.6 Logical universality of Toffoli gate. (a) AND, (b) NOT, and (c) fan-out are embedded in
the circuits
4.1 Reversible Logic Gates and Circuits 83

Fredkin gate and Toffoli gate are 3-input 3-output gates. Besides them, there are
many logically universal ones. The total number of 3-input 3-output reversible logic
gates is 8! = 40320, and most of them are logically universal. In fact, it is known that
38976 gates among them are universal [3]. On the other hand, there is no logically
universal n-input n-output reversible logic gate, if n < 3 [3]. Hence, Fredkin gate,
Toffoli gate, and other universal 3-input 3-output gates are the minimal universal
reversible ones for the case that the numbers of inputs and outputs are the same.
However, if we consider the case such that the number of outputs is larger than that
of inputs, then there are slightly simpler logically universal ones.
Switch gate [5] is a 2-input 3-output reversible logic gate shown in Fig. 4.7 (a).
The truth table of the logical function fsw realized by the switch gate is given in
Table 4.3. It is a bit-conserving gate. The input c controls the connection between
the input x and the output y2 or y3 , i.e., if c = 1 then x is connected to y2 , and if
c = 0 then x is connected to y3 . We can see that AND is embedded in the circuit of
Fig. 4.7 (a), and NOT and fan-out are embedded in Fig. 4.7 (b). Hence, the switch
gate is logically universal.

c ✲ ✲ y1 = c c ✲ ✲ c
✲ y2 = c·x ✲ c
x ✲ 1 ✲
✲ y3 = c·x ✲ c

(a) (b)

Fig. 4.7 Switch gate and its logical universality. (a) Here, AND is obtained from y2 . (b) Giving
constant 1 to the input x, NOT and fan-out are obtained

Table 4.3 The truth table of the logical function fsw : (c, x) 7→ (y1 , y2 , y3 ) of switch gate
c x y1 y2 y3
0 0 0 0 0
0 1 0 0 1
1 0 1 0 0
1 1 1 1 0

Interaction gate [5] is a 2-input 4-output reversible and bit-conserving logic gate
shown in Fig. 4.8 (a), which is sometimes called a collision gate. The truth table of
the logical function fint realized by the interaction gate is given in Table 4.4. We can
see that AND is embedded in the circuit of Fig. 4.8 (a), and NOT and fan-out are
embedded in Fig. 4.8 (b). Hence, the interaction gate is also logically universal.
84 4 Reversible Logic Gates
✲ y1 = x1 ·x2 ✲ x1
x1 ✲ ✲ y2 = x1 ·x2 x1 ✲ ✲ x1
x2 ✲ ✲ y3 = x1 ·x2 1 ✲ ✲ 0
✲ y4 = x1 ·x2 ✲ x1

(a) (b)

Fig. 4.8 Interaction gate and its logical universality. (a) Here, AND is obtained from y1 and y4 .
(b) Giving constant 1 to the input x2 , NOT and fan-out are obtained

Table 4.4 The truth table of the logical function fint : (x1 , x2 ) 7→ (y1 , y2 , y3 , y4 ) of interaction gate

x1 x2 y1 y2 y3 y4
0 0 0 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 1 0 0 1

4.1.4 Clearing garbage information

As we saw in the previous subsection, any logical function can be embedded in a

circuit composed of universal reversible logic gates by allowing to supply constant
inputs to the circuit, and to produce garbage outputs from it (see also Fig. 4.4).
However, discarding the garbage outputs is an irreversible process, since it is a kind
of erasure of information. Thus, garbage signals should be minimized by designing
the circuit appropriately. Here, we explain the method of reducing the amount of
garbage information given by Fredkin and Toffoli [5].
We first introduce the notions of an inverse reversible logic gate, and an inverse
reversible combinatorial logic circuit.
Definition 4.5. Let f : {0, 1}m → {0, 1}n be an injective logical function (m ≤ n),
and s be the m-input n-output reversible logic gate that realizes f . The inverse logic
gate of s is an n-input m-output logic gate that realizes the partial logical function
f −1 , the inverse of f .
Inverse switch gate is a 3-input 2-output logic gate depicted as in Fig. 4.9 (a). It
realizes the partial logical function fsw −1 : {0, 1}3 → {0, 1}2 , which is defined only

on the set {(0, 0, 0), (0, 0, 1), (1, 0, 0), (1, 1, 0)} as shown in in Table 4.5 (a). Hence,
for example, (1, 1, 1) should not be given as its input.
Inverse interaction gate is a 4-input 2-output logic gate given in Fig. 4.9 (b). It
−1
realizes the partial logical function fint : {0, 1}4 → {0, 1}2 , which is defined only
on the set {(0, 0, 0, 0), (0, 1, 0, 0), (0, 0, 1, 0), (1, 0, 0, 1)} as shown in in Table 4.5 (b).
Since the inverse switch gate (inverse interaction gate, respectively) realizes a
partial function, it is usually used together with the switch gate (interaction gate).
4.1 Reversible Logic Gates and Circuits 85
y1 ✲ ✲ c y1 ✲
y2 ✲ y2 ✲ ✲ x1
✲ x y3 ✲ ✲ x2
y3 ✲ y4 ✲

(a) (b)

Fig. 4.9 (a) Inverse switch gate, and (b) inverse interaction gate

Table 4.5 The truth tables of the partial logical functions (a) fsw −1 : (y , y , y ) 7→ (c, x) of inverse
1 2 3
−1
switch gate, and (b) fint : (y1 , y2 , y3 , y4 ) 7→ (x1 , x2 ) of inverse interaction gate

y1 y2 y3 c x y1 y2 y3 y4 x1 x2
0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 0 0 1
1 0 0 1 0 0 0 1 0 1 0
1 1 0 1 1 1 0 0 1 1 1
(a) (b)

From Table 4.1, we can see that the inverse Fredkin gate is the Fredkin gate itself.
Therefore, it has the same pictorial representation. Likewise, from Table 4.2, we can
see that the inverse Toffoli gate is the Toffoli gate itself.

Definition 4.6. Let Φ be a reversible combinatorial logic circuit. The inverse re-
versible combinatorial logic circuit Φ −1 is one obtained from Φ by replacing each
occurrence of a reversible logic gate by its inverse reversible logic gate, and thus its
inputs and outputs are exchanged.

We also use Φ to denote the logical function Φ : {0, 1}m → {0, 1}n (m < n)
realized by Φ. Then, the logical function realized by the circuit Φ −1 is the partial
logical function Φ −1 : {0, 1}n → {0, 1}m . Therefore, Φ −1 (Φ(x)) = x holds for all
x ∈ {0, 1}m . We omit its formal proof, since it is clear from the construction of Φ −1 .
In fact, it is apparent from the following examples.
Figure 4.10 (a) shows an example of a reversible combinatorial logic circuit com-
posed of switch gates. Its inverse circuit is obtained by taking a “mirror image” of
it, and exchanging inputs and outputs as shown in Fig. 4.10 (b). Figure 4.11 (a) is
an example of a circuit composed of Fredkin gates. Its inverse circuit is given in
Fig. 4.11 (b).
As explained in Sect. 4.1.3, any logical function can be embedded in some re-
versible logic circuit Φ by allowing to give constant inputs, and to generate garbage
outputs (see also Fig. 4.4). If we connect Φ and Φ −1 serially as in Fig. 4.12, we can
erase all the garbage information reversibly, and get a “clean” constant c that can be
reused. But, since this circuit also changes the actual output y to the actual input x,
we must insert fan-out circuits between Φ and Φ −1 to copy y as shown in Fig. 4.13.
By this method, the actual output y is obtained without generating garbage informa-
tion g. This circuit also gives the actual input x and the complement of the actual
86 4 Reversible Logic Gates

x1 ✲ ✲ y1 y∗1 ✲ ✲ x1∗
✲ y2 y∗2 ✲
x2 ✲ ✲ ✲ y3 y∗3 ✲ ✲ x2∗
✲ y4 y∗4 ✲ ✲
x3 ✲ ✲ x3∗
✲ y5 y∗5 ✲
(a) (b)

Fig. 4.10 (a) A circuit composed of switch gates, and (b) its inverse circuit

x1 ✲ y1 y∗1 ✲ x1∗
x2 ✲ y2 y∗2 ✲ x2∗
x3 ✲ y3 y∗3 ✲ x3∗
✲ y4 y∗4
x4 ✲ x4∗
(a) (b)

Fig. 4.11 (a) A circuit composed of Fredkin gates, and (b) its inverse circuit

output y, which are another kind of garbage information. However, since the num-
ber of bits of garbage g can be an exponential function of that of x, the total number
of bits of x and y is generally much less than that of g. In this sense, a circuit of the
form in Fig. 4.13 is an almost garbage-less logic circuit, and we have the following
proposition (again its formal proof is omitted).

Proposition 4.1. Let s be a logically universal reversible logic gate. Then, for any
logical function f , there is an almost garbage-less reversible combinatorial logic
circuit composed of s and its inverse logic gate in which f is embedded.

We consider an example of a reversible combinatorial logic circuit composed of

switch gates that realizes the logical function x1 ⊕ x2 shown in Fig. 4.14. Combining
this circuit, its inverse circuit, and a fan-out circuit (Fig. 4.7 (b)), we obtain an almost
garbage-less circuit that computes x1 ⊕ x2 given in Fig. 4.15.

Constant Garbage Constatnt

c g c

Φ Φ −1
x y x
Actual Actual Actual
input output input

Fig. 4.12 Cleanup of the garbage information by a reversible combinatorial logic circuit Φ and
its inverse Φ −1
4.1 Reversible Logic Gates and Circuits 87

c g c

Φ Φ −1
x y y x

c′ y

Fan-out
circuit

Fig. 4.13 Construction of an “almost garbage-less” reversible combinatorial logic circuit that
computes a non-injective logical function [5]

✲ ✲ y1 = x1 ·x2
✲ y2 = x1 ·x2
x1 ✲ ✲ ✲ y3 = x1 ·x2

x2 ✲ ✲ y4 = x1 ·x2
✲ ✲ ✲ y5 = x1 ·x2
✲ y6 = x1 ·x2
1 ✲ ✲
✲ y7 = x1 ·x2 · x1 ·x2 = x1 ⊕ x2

Fig. 4.14 A circuit composed of switch gates that computes the logical function x1 ⊕ x2 . This
circuit produces many garbage outputs

✲ ✲
✲
x1 ✲ ✲ ✲ ✲ x1
✲ ✲
x2 ✲ ✲ x2
✲ ✲ ✲ ✲ ✲
✲ ✲
1 ✲ ✲ ✲1
✲ ✲
✲ x1 ⊕ x2
1✲
✲ x1 ⊕ x2

Fig. 4.15 An almost garbage-less circuit composed of switch gates and inverse switch gates that
computes the logical function x1 ⊕ x2
88 4 Reversible Logic Gates

4.1.5 Realization in the billiard ball model

Fredkin and Toffoli [5] first proposed the billiard ball model (BBM), and showed
that Fredkin gate is simulated in it. As explained in Sect. 2.2.3, BBM is a reversible
physical model of computing consisting of ideal balls and reflectors. Collisions of
balls with other balls and reflectors are elastic, and there is no friction.
Interaction gate and switch gate, which are simpler than Fredkin gate, are imple-
mented in BBM. Interaction gate is realized by the collision of two moving balls
as shown in Fig. 4.16 [5]. This is the reason why the gate is also called a collision
gate. Switch gate is realized as in Fig. 4.17 [5]. Inverse interaction gate and inverse
switch gate are obtained by simply inverting the moving directions of balls.

x1 x1 ·x2
✒
❘ x1 ·x2
✒

❘
✒
x1 ·x2
❘
x2 x1 ·x2

Fig. 4.16 Realization of interaction gate in the billiard ball model [5]

c ✒
c·x
❘

❘ ✒
c·x
c·x
❘
✒
x c·x❘
❘
c

Fig. 4.17 Realization of switch gate in the billiard ball model [5]

There are two methods of constructing Fredkin gate. The first one is shown in
Fig. 4.18 in which three interaction gates, and three inverse interaction gates are
used [5]. The second one is in Fig. 4.19 in which two switch gates, and two inverse
switch gates are used. Note that, in [5], it is written that the circuit in Fig. 4.19
was designed by Feynman and Ressler. Thus, placing reflectors appropriately so
that the circuit of Fig. 4.18 or 4.19 is implemented, Fredkin gate is realized as a
configuration in BBM.
By above, we see any reversible combinatorial logic circuit can also be imple-
mented in BBM. Since the circuits in Figs. 4.18 and 4.19 have neither constant
inputs nor garbage outputs, there is no need to use a ball corresponding to them in
the BBM. However, if we construct the almost garbage-less reversible combinato-
4.2 Relation Between Reversible Logic Gates and Reversible Sequential Machines 89

c ✲c
✲
cpq ✲
cpq ✲
pq

p✲ ✲
c ✲
c pq ✲
c pq ✲
cpq ✲
cpq+cpq ✲ c· p + c·q

q✲ ✲
pq ✲
pq c(pq+ p ✲
q) ✲
c(p+q) ✲
cpq+c pq ✲ c· p + c·q
✲
cpq ✲
cpq ✲
pq

Fig. 4.18 Composing Fredkin gate by three collision gates and three inverse collision gates [5]

c ✲ ✲ ✲ ✲ ✲ c
c·q ✲
c· p c· p ✲
p ✲ ✲ ✲ c· p + c·q
c· p c·q c·✲
p c·q ✲
q ✲ ✲ c· p + c·q

Fig. 4.19 Composing Fredkin gate by two switch gates and two inverse switch gates [5]

rial logic circuit by the method discussed in Sect. 4.1.4 (Fig. 4.13), some amount of
constant supply and garbage generation occur in the BBM realization. If such a cir-
cuit is used to compose a computing system like a Turing machine, then it operates
repeatedly, and thus the total amount of garbage grows considerably. Since supply
of constants and disposal of garbage correspond to supply and dissipation of en-
ergy, respectively, it is desirable if we can obtain a completely garbage-less circuit.
In Sect. 2.3, we designed a circuit composed of rotary elements (REs) that simu-
lates a given reversible sequential machine (RSM), and produces no garbage at all.
In Sect. 4.2.3, we shall show that it is also possible to design a completely garbage-
less circuit made of Fredkin gates and delay elements that simulates a given RSM,
and is completely garbage-less.

4.2 Relation Between Reversible Logic Gates and Reversible

Sequential Machines

In this section, we investigate the relation among reversible logic gates, reversible
logic elements with memory (RLEMs), and reversible sequential machines (RSMs).
In particular, we give a method of realizing an RSM as a completely garbage-less
circuit composed of reversible logic gates.
90 4 Reversible Logic Gates

4.2.1 Making Fredkin gate from RE

Fredkin gate is simulated by an RE-circuit, a circuit composed of rotary elements

(REs) [9]. Input signals 0 and 1 in Fredkin gate are represented by absence and
presence of a particle in the RE-circuit. Since Fredkin gate has three input lines at
which signals arrive at the same time, we allow to give two or more particles to the
RE-circuit at the same time. But, they should not arrive at each RE simultaneously.
Thus, we use a delay element shown in Fig. 4.20 to adjust operation timings of each
RE in the RE-circuit. Note that RE itself has a unit time delay.

x(t) y(t) = x(t − 1) x(t) n y(t) = x(t − n)

(a) (b)

Fig. 4.20 (a) A delay element with a unit time delay, and (b) that of n units of time

Figure 4.21 shows RE-circuits (with delay elements) that realize switch gate, and
inverse switch gate. Operations of the RE-circuit for switch gate in the case c = x = 1
is given in Fig. 4.22 (it is easy to verify its operations in other cases). Combining
the circuits for switch gate and inverse switch gate as given in Fig. 4.19, we obtain
an RE-circuit shown in Fig. 4.23 that simulates Fredkin gate.
In an RE-circuit that simulates a reversible logic gate, the time delay between
input and output must be constant for all the combination of inputs. Otherwise,
there arises a problem to connect many logic gates implemented as RE-circuits. The
time delay of the RE-circuit for switch gate given in Fig. 4.21 is 7 units of time if
c = 0, x = 1, while 5 units of time in other cases. Therefore, a delay element of 2
units of time should be inserted at the output line c·x to meet this condition. In the
RE-circuit for Fredkin gate (Fig. 4.23) the delay time is adjusted to be always 20
units of time as a whole.
In [10] it is shown that we can construct a circuit that simulates Fredkin gate not
only by RE but also by any of the 14 non-degenerate 2-state 3-symbol RLEMs (but
we do not give here the circuits).
Although Fredkin gate can be simulated by an RE-circuit as shown in Fig. 4.23,
it is not a good usage of RE. First, eight copies of RE are required to simulate only
one Fredkin gate. Second, as we have already seen in Sect. 2.3, any RSM can be
simulated by an RE-circuit with a simple structure. Therefore, if our objective is to
construct reversible computing systems, we should look for a direct and efficient
method of composing them by RE and by other RLEMs.
4.2 Relation Between Reversible Logic Gates and Reversible Sequential Machines 91
✲ c·x c·x
❄ ❄
✛

x ✲ ✲ c·x c·x ✲ ✲x
✻ ✻
❄ ❄
✛ ✛

c ✲ ✲ c c ✲ ✲c
✻ ✻
3 3

(a) (b)

Fig. 4.21 Realization of (a) switch gate, and (b) inverse switch gate as RE-circuits

t =0 t =1 t =2
✲ c·x ✲ c·x ✲ c·x
✉
❄ ❄ ❄
t t t
x ✉ ✲ ✲ c·x x ✲ ✲ c·x x ✲ ✲ c·x

✉
✻ ✻ ✻
❄ ❄ ❄
t t t
✛ ✛ ✛

c ✉ ✲ ✲ c c ✲ ✲ c c ✲ ✲ c
❍❍✻
3✟ ✉❍❍✻
3✟ 3✉
❍❍✻
✟
✟ ✟ ✟

t =3 t =4 t =5
✲ c·x ✲ c·x ✉ c·x
✲

❄ ❄ ❄
t t t
x ✲ ✲ c·x x ✲ ✲ c·x x ✲ ✲ c·x
✻ ✉
✻ ✻

✛✉
❄ ❄ ❄
t t t
✛ ✛
✲ ✲ ✲ ✲ ✲ ✉
✲
✉
c c c c c c
❍✉✻
3❍
✟
❍
3❍
✟
✻ ❍
3❍
✟
✻
✟ ✟ ✟

Fig. 4.22 Simulation process of a switch gate by a circuit composed of rotary elements and a
delay element in the case c = x = 1

4.2.2 Making RE from Fredkin gate

We consider the problem how rotary element (RE) can be simulated by a circuit
composed of Fredkin gates and delay elements. In the next subsection we shall
show a systematic implementation method of an RSM as a completely garbage-less
circuit composed of Fredkin gates and delay elements. Although RE is a kind of an
RSM, we give here a particular design of a circuit that simulates RE. It is simpler
than the one obtained by the method of the next subsection.
92 4 Reversible Logic Gates

10

1 1

❄ ❄ ❄ ❄
✛ ✛

p ✲ ✲ ✲ ✲ ✲ c· p + c·q
✻ ✻ ✻ ✻

q 5 5 ✲ c· p + c·q
❄ ❄ ❄ ❄
✛ ✛ ✛ ✛

c ✲ ✲ ✲ ✲ ✲c
✻ ✻ ✻ ✻
3 3 3 3

Fig. 4.23 Realization of Fredkin gate by rotary elements and delay elements [9]

Since Fredkin gate itself has no memory, a circuit composed of Fredkin gates
that simulates RE must have loops and delay elements in it. The states of RE must
be distinguished by circulating a signal “1” in the circuit in different ways.
A circuit that simulates RE is given in Fig. 4.24 that consists of 12 Fredkin gates
and many delay elements [8]. Here, we assume that every connecting line between
two Fredkin gates has some delay, and thus a delay element is inserted in it. In fact,
if Fredkin gate is implemented in a physical system like BBM (Sect. 4.1.5), trans-
mission delay of signals is inevitable. Here, signal “1” in this circuit is represented
by a particle in the following figures.
The circuit shown in Fig. 4.24 is in the state H of RE, since a particle exists at the
position of “State H”. If no other particle exists, then it travels along the bold line,
and goes back to the same position after eight units of time. Likewise, if a particle is
put at the position of “State V”, then it means the circuit is in the state V. Also in this
case, the particle travels along a similar loop, and goes back to the same position
after eight steps.
If an input particle is given at the port n, s, e, or w when the circulating particle
is at the position of “State H” or “State V”, then the circuit starts to simulate the
operation of RE. Figures 4.25 and 4.26 show the case that the state is H and the
input is s, the orthogonal case of Fig. 2.3 (b). As shown in Fig. 4.26 (t = 8), it
finally goes to the state V and gives the output e0 , and thus δRE (H, s) = (V, e0 ) is
correctly simulated. The four Fredkin gates in the leftmost column checks if the
orthogonal case occurs. If it is the case, the particle circulating in a loop is moved
to another loop by one of the four Fredkin gate in the center column. Then, by the
gates in the rightmost column, the other particle goes out from the specified output
port. It is easy to follow the operation of the circuit for the parallel case (Fig. 2.3
(a)), since two particles do not interact at the same Fredkin gate.
It should be noted that this circuit is a completely garbage-less logic circuit, i.e.,
it never produces garbage information at all, since the values of the four constant
input lines and the four output lines are all 0’s. In fact, these four output lines can
be connected to the four input lines.
4.2 Relation Between Reversible Logic Gates and Reversible Sequential Machines 93

State H ✲ ✲ ✲
1 5 1

n ✲ 2
Hn ✲ 1 ✲′
Hn
2 ✲ n′
0✲ 7
Vn ✲ 1 ✲
Vn′ ✲0

✲ 1 ✲ 3 ✲ 1

s 1 ✲ 2
Hs ✲ 1
Hs✲
′
1 ✲ s′
0✲ 5
Vs ✲ 1 ✲
Vs′ ✲0

State V ✲ ✲ ✲
1 2 1

e ✲ 4
Ve ✲ 1 ✲
Ve′
2 ✲ e′
0✲ 7
He ✲ 1 ✲
He′ ✲0

✲ 1 ✲ 2 ✲ 1

w 1 ✲ 4
Vw ✲ 1 ✲
Vw′
1 ✲ w′
0✲ 5
Hw ✲ 1 ✲
Hw′ ✲0

Fig. 4.24 Realization of rotary element by a completely garbage-less circuit composed of Fredkin
gates and delay elements [8]. In this figure, the state is H, which is kept by a signal “1” represented
•
by a particle that moves along the loop indicated by the bold line

4.2.3 Making reversible sequential machines from Fredkin gate

In the previous subsection, we presented a completely garbage-less circuit com-

posed of Fredkin gates and delay elements that simulates RE. We can, of course, use
this circuit to construct RSMs by the method given in Sect. 2.3. Replacing each oc-
currence of RE of an RE-circuit, e.g., shown in Fig. 2.14, by the circuit of Fig. 4.24,
we obtain a circuit that simulates a given RSM. In this subsection, however, we show
a direct and systematic method of composing a completely garbage-less circuit out
of Fredkin gates and delay elements that simulates an RSM [7].
We first design several building modules, and then they are combined to make a
larger circuit that simulates an RSM. To represent a symbol or a state of an RSM
in a circuit, we use a “bundle” of decoded lines. That is, for a set of symbols (or
states) X = {x1 , . . . , xn }, we prepare a bundle of n signal lines in the circuit. The
94 4 Reversible Logic Gates

t=0 t=1
✈
State ✲
H ❍❍ ✲ ❍❍ ✲ ❍ ❍
State ✲
H ❍❍ ✲ ❍❍ ✲ ❍
1✟
✟ 5✟
✟ ✟1✟ 1✟
✟ 5✟
✟ ✟1❍
✟
n ✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍2❍✲ n′ n ✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍2❍✲ n′
✟✟ ✟✟ ✟ ✟ ✟✟ ✟✟ ✟ ✟
0✲ ❍❍ ✲ ❍❍ ✲ ✲0 0✲ ❍❍ ✲ ❍❍ ✲ ✲0
✟
7✟ ✟
1✟ ✟
7✟ ✟
1✟

✲ ❍
1❍
✟
✲ ❍
3❍
✟
✲ ❍1❍
✟ ✈
✲ ❍
1❍
✟
✲ ❍
3❍
✟
✲ ❍1❍
✟
✟ ✟ ✟ ✟ ✟ ✟
s ✈❍
1❍✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍1❍✲ s′ s ❍
1❍✈
✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍1❍✲ s′
✟✟ ✟✟ ✟✟ ✟ ✟ ✟✟ ✟✟ ✟✟ ✟ ✟
0✲ ❍❍
5✟ ✲ ❍❍
1✟ ✲ ✲0 0✲ ❍❍
5✟ ✲ ❍❍
1✟ ✲ ✲0
✟ ✟ ✟ ✟

State ✲
V ❍❍ ✲ ❍❍ ✲ ❍ ❍
State ✲
V ❍❍ ✲ ❍❍ ✲ ❍
1✟
✟ 2✟
✟ ✟1✟ 1✟
✟ 2✟
✟ ✟1❍
✟
e ✲ ❍❍ ✲ ❍❍ ✲ ❍ ❍✲ e′ e ✲ ❍❍ ✲ ❍❍ ✲ ❍2❍✲ ′
4✟
✟ 1✟
✟ ✟2✟ 4✟
✟ 1✟
✟ ✟ ✟ e
0✲ ❍
7❍ ✲ ❍
1❍ ✲ ✲0 0✲ ❍
7❍ ✲ ❍
1❍ ✲ ✲0
✟✟ ✟✟ ✟✟ ✟✟

✲ ❍❍
1✟ ✲ ❍❍
2✟ ✲ ❍1❍ ✲ ❍❍ ✲ ❍❍ ✲ ❍1❍
✟ ✟ ✟ ✟ 1✟
✟ 2✟
✟ ✟ ✟
w ❍
1❍✲ ❍
4❍ ✲ ❍
1❍ ✲ ❍1❍✲ w′ w ❍
1❍✲ ❍
4❍ ✲ ❍
1❍ ✲ ❍1❍✲ w′
✟✟ ✟✟ ✟✟ ✟ ✟ ✟✟ ✟✟ ✟✟ ✟ ✟
0✲ ❍❍ ✲ ❍❍ ✲ ✲0 0✲ ❍❍ ✲ ❍❍ ✲ ✲0
✟
5✟ ✟
1✟ ✟
5✟ ✟
1✟

t=2 t=3
State ✲
H ❍❍ ✲ ❍❍ ✲ ❍ ❍
State ✲
H ❍❍ ✲ ❍❍ ✲ ❍
1✟
✟ 5✟
✟ ✟1✟ 1✟
✟ 5✟
✟ ✟1❍
✟
n ✲ ❍
2❍
✟ ✈
✲ ❍
1❍
✟
✲ ❍2❍
✟
✲ n′ n ✲ ❍
2❍
✟
✲ ❍
1❍
✟
✲ ❍2❍
✟
✲ n′
✟ ✟ ✟ ✟ ✟ ✟
0✲ ❍❍ ✲ ❍❍ ✲ ✲0 0✲ ❍❍ ✲ ❍❍ ✲ ✲0
✟
7✟ ✟
1✟ ✟
7✟ ✟
1✟

✲ ❍
1❍ ✲ ❍
3❍ ✲ ❍1❍ ✲ ❍
1❍ ✈
✲ ❍
3❍ ✲ ❍1❍
✟✟ ✟✟ ✟ ✟ ✟✟ ✟✟ ✟ ✟
s ❍
1❍
✟✲
❍✈
2❍
✟ ✲ ❍
1❍
✟ ✲ ❍1❍
✟✲ s′ s ❍
1❍
✟✲
❍
2❍
✟ ✈
✲ ❍
1❍
✟ ✲ ❍1❍
✟✲ s′
✟ ✟ ✟ ✟ ✟ ✟ ✟ ✟
0✲ ❍❍
5✟ ✲ ❍❍
1✟ ✲ ✲0 0✲ ❍❍
5✟ ✲ ❍❍
1✟ ✲ ✲0
✟ ✟ ✟ ✟

State ✲
V ❍ ❍ ❍ State ✲
V ❍ ❍ ❍
1❍
✟✟
✲ 2❍
✟✟
✲
✟1❍
✟ 1❍
✟✟
✲ 2❍
✟✟
✲
✟1❍
✟
e ✲ ❍❍ ✲ ❍❍ ✲ ❍2❍✲ ′ e ✲ ❍❍ ✲ ❍❍ ✲ ❍2❍✲ ′
4✟
✟ 1✟
✟ ✟ ✟ e 4✟
✟ 1✟
✟ ✟ ✟ e
0✲ ❍
7❍ ✲ ❍
1❍ ✲ ✲0 0✲ ❍
7❍ ✲ ❍
1❍ ✲ ✲0
✟✟ ✟✟ ✟✟ ✟✟

✲ ❍❍
1✟ ✲ ❍❍
2✟ ✲ ❍1❍ ✲ ❍❍ ✲ ❍❍ ✲ ❍1❍
✟ ✟ ✟ ✟ 1✟
✟ 2✟
✟ ✟ ✟
❍
1❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍
w ✟✟✲ 4❍
✟✟ ✲ 1❍
✟✟ ✲
✟1❍
✟✲ w′ w 1❍
✟✟✲ 4❍
✟✟ ✲ 1❍
✟✟ ✲
✟1❍
✟✲ w′
0✲ ❍❍ ✲ ❍❍ ✲ ✲0 0✲ ❍❍ ✲ ❍❍ ✲ ✲0
✟
5✟ ✟
1✟ ✟
5✟ ✟
1✟

t=4 t=5
State ✲
H ❍❍ ✲ ❍❍ ✲ ❍ ❍
State ✲
H ❍❍ ✲ ❍❍ ✲ ❍
1✟
✟ 5✟
✟ ✟1✟ 1✟
✟ 5✟
✟ ✟1❍
✟
✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍2❍ ❍ ❍ ❍
n ✟✟ ✟✟ ✟ ✟✲ n′ n ✲ 2❍
✟✟ ✲ 1❍
✟✟ ✲
✟2❍
✟✲ n′
0✲ ❍❍ ✲ ❍❍ ✲ ✲0 0✲ ❍❍ ✲ ❍❍ ✲ ✲0
✟
7✟ ✟
1✟ ✟
7✟ ✟
1✟

✲ ❍
1❍
✟ ✲ ❍✈
3❍
✟ ✲ ❍1❍
✟ ✲ ❍
1❍
✟ ✲ ❍✈
3❍
✟ ✲ ❍1❍
✟
✟ ✟ ✟ ✟ ✟ ✟
s ❍
1❍✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍1❍✲ s′ s ❍
1❍✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍1❍✲ s′
✟✟ ✟✟ ✟✟ ✟ ✟ ✟✟ ✟✟ ✟✟ ✟ ✟
0✲ ❍❍
5✟ ✲ ❍❍
1✟ ✲ ✲0 0✲ ❍❍
5✟ ✲ ❍❍
1✟ ✲ ✲0
✟ ✟ ✟ ✟

State ✲
V ❍ ❍ ❍ State ✲
V ❍ ❍ ❍
1❍
✟✟
✲ 2❍
✟✟
✲
✟1❍
✟ 1❍
✟✟
✲ 2❍
✟✟
✲
✟1❍
✟
e ✲ ❍❍
4✟ ✲ ❍❍
1✟ ✲ ❍ ❍✲ e′
2✟ e ✲ ❍❍
4✟ ✲ ❍❍
1✟ ✲ ❍ ❍✲ e′
2✟
✟ ✟ ✟ ✟ ✟ ✟
0✲ ❍❍
7✟ ✈
✲ ❍❍
1✟ ✲ ✲0 0✲ ❍❍
7✟ ✲ ❍❍
1✟ ✲ ✲0
✟ ✟ ✟ ✟

✲ ❍❍
1✟ ✲ ❍❍
2✟ ✲ ❍1❍ ✲ ❍❍ ✲ ❍❍ ✲ ❍1❍
✟ ✟ ✟ ✟ 1✟
✟ 2✟
✟ ✟ ✟
❍❍✲ ❍❍ ✲ ❍❍ ✲ ❍1❍ ❍ ❍ ❍ ❍
w 1✟
✟ 4✟
✟ 1✟
✟ ✟ ✟✲ w′ w ❍✲
1✟
✟
❍
4✟
✟
✲ ❍
1✟
✟
✲
✟1❍
✟✲ w′
0✲ ❍
5❍
✟
✲ ❍
1❍
✟
✲ ✲0 0✲ ❍
5❍
✟ ✈
✲ ❍
1❍
✟
✲ ✲0
✟ ✟ ✟ ✟

Fig. 4.25 Simulation process of rotary element (RE) by a circuit composed of Fredkin gates and
delay elements for the case δRE (H, s) = (V, e0 )
4.2 Relation Between Reversible Logic Gates and Reversible Sequential Machines 95

t=6 t=7
State ✲
H ❍❍ ✲ ❍❍ ✲ ❍ ❍
State ✲
H ❍❍ ✲ ❍❍ ✲ ❍
1✟
✟ 5✟
✟ ✟1✟ 1✟
✟ 5✟
✟ ✟1❍
✟
n ✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍2❍✲ n′ n ✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍2❍✲ n′
✟✟ ✟✟ ✟ ✟ ✟✟ ✟✟ ✟ ✟
0✲ ❍❍ ✲ ❍❍ ✲ ✲0 0✲ ❍❍ ✲ ❍❍ ✲ ✲0
✟
7✟ ✟
1✟ ✟
7✟ ✟
1✟

✲ ❍
1❍ ✲ ❍
3❍ ✲ ❍1❍ ✲ ❍
1❍ ✲ ❍
3❍ ✲ ❍1❍
✟✟ ✟✟ ✟ ✟ ✟✟ ✟✟ ✟ ✟
s ❍
1❍✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍1❍✲ s′ s ❍
1❍✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍1❍✲ s′
✟✟ ✟✟ ✟✟ ✟ ✟ ✟✟ ✟✟ ✟✟ ✟ ✟
0✲ ❍❍
5✟ ✲ ❍❍
1✟ ✲ ✲0 0✲ ❍❍
5✟ ✲ ❍❍
1✟ ✲ ✲0
✟ ✟ ✟ ✟

✈
State ✲
V ❍❍ ✲ ❍❍ ✲ ❍ ❍
State ✲
V ❍❍ ✲ ❍❍ ✲ ❍
1✟
✟ 2✟
✟ ✟1✟ 1✟
✟ 2✟
✟ ✟1❍
✟
e ✲ ❍❍
4✟ ✲ ❍❍
1✟ ✈
✲ ❍ ❍✲ e′
2✟ e ✲ ❍❍
4✟ ✲ ❍❍
1✟ ✲ ❍ ✈✲ e′
2❍
✟
✟ ✟ ✟ ✟ ✟ ✟
0✲ ❍
7❍ ✲ ❍
1❍ ✲ ✲0 0✲ ❍
7❍ ✲ ❍
1❍ ✲ ✲0
✟✟ ✟✟ ✟✟ ✟✟

✲ ❍❍
1✟ ✲ ❍❍
2✟ ✲ ❍1❍
✟
✲ ❍❍
1✟ ✲ ❍❍
2✟ ✈
✲ ❍1❍
✟
✟ ✟ ✟ ✟ ✟ ✟
w ❍
1❍✲ ❍
4❍ ✲ ❍
1❍ ✲ ❍1❍✲ w′ w ❍
1❍✲ ❍
4❍ ✲ ❍
1❍ ✲ ❍1❍✲ w′
✟✟ ✟✟ ✟✟ ✟ ✟ ✟✟ ✟✟ ✟✟ ✟ ✟
0✲ ❍❍ ✲ ❍❍ ✲ ✲0 0✲ ❍❍ ✲ ❍❍ ✲ ✲0
✟
5✟ ✟
1✟ ✟
5✟ ✟
1✟

t=8
State ✲
H ❍❍ ✲ ❍❍ ✲ ❍
1✟
✟ 5✟
✟ ✟1❍
✟
n ✲ ❍
2❍ ✲ ❍
1❍ ✲ ❍2❍✲ n′
✟✟ ✟✟ ✟ ✟
0✲ ❍❍ ✲ ❍❍ ✲ ✲0
✟
7✟ ✟
1✟

✲ ❍
1❍ ✲ ❍
3❍ ✲ ❍1❍
✟✟ ✟✟ ✟ ✟
❍
1❍ ❍ ❍ ❍
s ✟✟✲ 2❍
✟✟ ✲ 1❍
✟✟ ✲
✟1❍
✟✲ s′
0✲ ❍❍
5✟ ✲ ❍❍
1✟ ✲ ✲0
✟ ✟

✈
State ✲
V ❍ ❍ ❍
1❍
✟✟
✲ 2❍
✟✟
✲
✟1❍
✟
✟ ✈e
e ✲ ❍❍
4✟ ✲ ❍❍
1✟ ✲ ❍2❍✲ ′
✟ ✟ ✟
0✲ ❍
7❍ ✲ ❍
1❍ ✲ ✲0
✟✟ ✟✟

✲ ❍❍
1✟ ✲ ❍❍
2✟ ✲ ❍1❍
✟ ✟ ✟ ✟
❍
1❍ ❍ ❍ ❍
w ✟✟✲ 4❍
✟✟ ✲ 1❍
✟✟ ✲
✟1❍
✟✲ w′
0✲ ❍❍ ✲ ❍❍ ✲ ✲0
✟
5✟ ✟
1✟

Fig. 4.26 Simulation process of rotary element (RE) by a circuit composed of Fredkin gates and
delay elements for the case δRE (H, s) = (V, e0 ) (continued)

i-th line in the bundle uniquely corresponds to xi , and it is also denoted by xi . If the
value of the i-th line is 1, we regard xi is occurring in the RSM. Hence, just one of
the lines x1 , . . . , xn must have the value 1. The building modules designed here are
as follows. Essentially, they are reversible combinatorial logic circuit that realize
injective logical functions. However, they contain delay elements in the circuits,
since they will be combined, and feedback loop will be added.
1. Switch module: SWITCH(n)
It is a building module that branches the input bundle a1 , . . . , an to the output
bundle q·a1 , . . . , q·an or q·a1 , . . . , q·an according to the value of the input q.
It is schematically represented by the Fig. 4.27. Here, we pose the following
constraints to the inputs.
(i) If q = 1, then just one of the inputs a1 , . . . , an is 1.
(ii) q·b = 0.
The circuit for SWITCH(3) is given in Fig. 4.28. It is easily verified that this
96 4 Reversible Logic Gates

circuit has the desired function. It is also easy to draw the circuit of SWITCH(n)
for general n. The total delay between input and output of this module is 2n.

b a1 . . . an
❄ ❄ ❄
✲ q·a1

q✲ SWITCH(n)
..
.
✲ q·an

❄ ❄ ❄
q+b q·a1 · · · q·an

Fig. 4.27 Schematic representation of a switch module SWITCH(n). It is used under the following
constraint: If q = 1 then just one of a1 , . . . , an is 1, and q·b = 0

b a1 a2 a3
1 2 4

q 1 1 4 ✲ q·a1
0 1 1

1 1 1

1 1 1 2 ✲ q·a2
0 1 1

1 1 1

1 1 1 ✲ q·a3
0 1 ✲0 1
4 2 1 1

❄ ❄ ❄ ❄
q+b q·a1 q·a2 q·a3

Fig. 4.28 The circuit of SWITCH(3) composed of Fredkin gates and delay elements [7]

2. Delay module: d-DELAY(n)

The delay module d-DELAY(n) simply consists of n delay elements of d units of
time as shown in Fig. 4.29.
3. Decoder module: DECODER(m, n)
It decodes the combination of values of two input bundles with m and n lines,
which are q1 , . . . , qm , and a1 , . . . , an . The decoded result is put to the bundle
with mn lines q1 ·a1 , . . . , qm ·an . The schematic representation is in Fig. 4.30.
It is used under the constraint that exactly one of q1 , . . . , qm is 1, and exactly
one of a1 , . . . , an is 1. If qh = 1 and ai = 1, then the module will finally give
qh ·ai = 1 and r = 1. This module is built from switch modules and delay mod-
ules as shown in Fig. 4.31. It is clear that this circuit works as above because
of the function of SWITCH(n). The delay between input and output of this
module is 2mn. In the following, we also use the inverse circuit of the decoder
4.2 Relation Between Reversible Logic Gates and Reversible Sequential Machines 97

x1 ✲ d ✲ y1

.. .. ..
. . .

xn ✲ d ✲ yn

Fig. 4.29 A delay module d-DELAY(n)

module, i.e., DECODER(m, n)−1 , which is composed of SWITCH(n)−1 and d-

DELAY(n)−1 . Although these circuits contain delay elements besides Fredkin
gates, their inverse are obtained in a similar manner as in Sect. 4.1.4. For exam-
ple, SWITCH(3)−1 is given in Fig. 4.32. Note that d-DELAY(n)−1 is identical
with d-DELAY(n).

0 a1 . . . an
❄ ❄ ❄
q1 ✲ ✲ q1 ·a1
✲ q1 ·a2
..
. DECODER(m, n) ..
.

qm ✲ ✲ qm ·an

❄ ❄ ··· ❄
r 0 0

Fig. 4.30 Schematic representation of a decoder module DECODER(m, n). It is used under the
following constraint: Exactly one of a1 , . . . , an is 1, and exactly one of q1 , . . . , qm is 1

4. Permutation module: PERM( f )

Let f : {1, . . . , n} → {1, . . . , n} be a bijection (i.e., permutation over {1, . . . , n}).
The circuit PERM( f ) realizes this permutation as shown in Fig. 4.33.
We now show a construction method of RSMs using the building modules de-
scribed above. Let M = (Q, Σ ,Γ , δ ) be a given RSM. We first consider the case
|Σ | = |Γ |. The case |Σ | < |Γ | will be discussed later. We assume Q = {q1 , . . . , qm },
Σ = {a1 , . . . , an }, and Γ = {s1 , . . . , sn }. Let f δ : {1, . . . , mn} → {1, . . . , mn} be a
mapping defined as follows.

∀qh , q j ∈ Q, ∀ai ∈ Σ , ∀sk ∈ Γ ( f δ ((h−1)n+i) = ( j −1)n+k ⇔ δ (qh , ai ) = (q j , sk ))

Since δ is a bijection, f δ is also so, and thus it is a permutation over {1, . . . , mn}.
Then, the RSM M is realized as a circuit given in Fig. 4.34.
98 4 Reversible Logic Gates

0 a1 an
❄ ❄ ··· ❄
✲ ✲ q1 ·a1

q1 ✲ 0-DELAY(1) ✲ SWITCH(n)
..
. 2n(m−1)-DELAY(n)
..
.

✲ ✲ q1 ·an

❄ ❄ ··· ❄
✲ ✲ q2 ·a1

q2 ✲ 2n-DELAY(1) ✲ SWITCH(n)
..
. 2n(m−2)-DELAY(n)
..
.

✲ ✲ q2 ·an

❄ ❄ ··· ❄
.. .. ... ... ... .. ..
. . . .

❄ ❄ ··· ❄
✲ ✲ qm ·a1

qm ✲ 2n(m−1)-DELAY(1) ✲ SWITCH(n)
..
. 0-DELAY(n)
..
.

✲ ✲ qm ·an

❄ ❄ ··· ❄
r 0 0

Fig. 4.31 Composing DECODER(m, n) from switch modules and delay modules

a3 a2 a1 b
✻ ✻ ✻ ✻
4 2 1
q·a1 4 1 1 ✲ q
1 1 ✲0
1 1 1
q·a2 2 1 1 1

1 1 ✲0
1 1 1
q·a3 1 1 1

1 0 1 ✲0
1 1 2 4

q·a3 q·a2 q·a1 q+b

Fig. 4.32 The circuit of the inverse switch module SWITCH(3)−1 [7]. It is an inverse circuit of
the one shown in Fig. 4.28
4.2 Relation Between Reversible Logic Gates and Reversible Sequential Machines 99

x1 ✲ 1 ✲ y1
.. ✲
.. . ..
. ✲ .
1
✲
xi ✲ 1
✲ y f (i)
✲ 1
.. ..
. .. .
.
xn ✲ 1 ✲ yn

Fig. 4.33 A permutation module PERM( f )

0 a1 ... an sn . . . s1 0
❄ ❄ ❄ ✻ ✻ ✻
q1✲ q1 ·a1✲ q1 ·s1✲ q1
q1 ·a2✲ q1 ·s2✲
.. ..
. DECODER(m, n) .. PERM( f δ ) .. DECODER(m, n)−1 .
. .

qm✲ qm ·an✲ qm ·sn✲ qm

❄ ... ❄ ✻ ✻ ✻
r ... r
0 0 0 0
1

..
.

Fig. 4.34 The circuit composed of Fredkin gates and delay elements that simulates the reversible
sequential machine M = ({q1 , . . . , qm }, {a1 , . . . , an }, {s1 , . . . , sn }, δ ) [7]

Assume the present state of M is qh and the current input symbol is ai . Then,
signals 1’s are put on the line qh and ai in Fig. 4.34. All other lines have signal
0’s. By the function of DECODER(m, n), the combination of qh and ai is found,
and a signal 1 will appear on the line qh ·ai . If δ (qh , ai ) = (q j , sk ), then the module
PERM( f δ ) gives a signal 1 on the line q j ·sk . Finally, DECODER(m, n)−1 separates
the signal on the line q j ·sk into q j and sk , and thus the next state and the output is
correctly given. The total delay between input and output is 4mn + 1, and thus input
signal should be given every 4mn + 1 steps.
Next, we consider the case that the given RSM M = (Q, Σ ,Γ , δ ) is one such
that |Σ | < |Γ |. Hence, we assume Σ = {a1 , . . . , an0 }, Γ = {s1 , . . . , sn }, and n0 <
n. In this case, we prepare “dummy” input symbols an0 +1 , . . . , an , and let Σ 0 =
{a1 , . . . , an0 , an0 +1 , . . . , an }. Since δ : Q × Σ → Q ×Γ is an injection, and |Q × Σ 0 | =
|Q × Γ |, we can effectively find a bijection δ 0 : Q × Σ 0 → Q × Γ that is an extension
of δ , i.e., δ 0 (qh , ai ) = δ (qh , ai ) holds for all qh ∈ Q and ai ∈ Σ . Thus, replacing the
100 4 Reversible Logic Gates
0
module PERM( f δ ) by PERM( f δ ) in Fig. 4.34, we obtain a circuit that simulates
M. Here, the input lines an0 +1 , . . . , an are not used.
By above, we obtain the following theorem.
Theorem 4.1. [7] For any RSM M we can construct a completely garbage-less logic
circuit composed of Fredkin gates and delay elements that simulates M.
Combining this method and the one given in Sect. 4.1.5, we can compose a con-
figuration of BBM that simulates a given RSM with only two balls.

4.3 Concluding Remarks

In this chapter, we studied basic properties of reversible logic gates and circuits, in
particular, logical universality, garbage-less logic circuits, implementation in the
billiard ball model, and the relations to reversible logic elements with memory
(RLEMs) and reversible sequential machines (RSMs). There are infinitely many
kinds of reversible logic gates, but here we focused on several typical ones, i.e., the
Fredkin gate, the Toffoli gate, the interaction gate, and the switch gate.
In Sect. 4.2.3, it was shown that any RSM can be simulated by a completely
garbage-less logic circuit composed of Fredkin gates and delay elements. Though
the circuit constructed from rotary elements (REs) given in Sect. 2.3 is simpler than
the above one for simulating an RSM, this result is useful for designing a com-
putationally universal two-dimensional reversible cellular automaton with a small
number of states. This is because the Fredkin gate is further decomposed into inter-
action gates and inverse interaction gates, or switch gates and inverse switch gates,
which are simpler than the Fredkin gate, as in Figs. 4.18 and 4.19. In fact, the switch
gate and its inverse can be embedded in a very simple two-dimensional reversible
cellular automata (Sects. 12.3, 13.2 and 13.3).
Here, we presented only the topics that will be used in the following chapters,
but did not investigate others, especially practical design methods of logic circuits
composed of reversible logic gates. Recently, studies on efficient implementation of
reversible and quantum logic circuits have been done extensively. On this topic, see,
e.g., [1, 3, 6, 12, 13, 14, 15, 18].

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