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SYLLABUS
Computer Organization
(Autonomous) Central Processing Unit: General Register Organization- Control Word, Examples of Micro-operations,
STACK organization – Register Stack, Memory Stack, Reverse Polish Notation, Evaluation of Arithmetic
Expressions, Instruction formats – Three Address Instructions, Two Address Instructions, One Address
UNIT III Instructions, Zero Address Instructions, RISC Instructions, Addressing modes – Numerical Example, Data
Transfer and manipulation – Data Transfer Instructions, Data Manipulation Instructions, Arithmetic
Sections - A & D Instructions, Logical and Bit Manipulation Instructions, Shift Instructions, Program control – Status Bit
Conditions, Conditional Branch Instructions, Subroutine Call and Return, Program Interrupt, Types of
Interrupts, Reduced Instruction Set Computer – CISC Characteristics, RISC Characteristics.

Micro Programmed Control Unit: Control memory, Address sequencing – Conditional Branching,
Prepared by Mapping of Instructions, Subroutines, Micro program example – Computer Configuration, Microinstruction
Anil Kumar Prathipati, Asst. Prof., Dept. of CSE. Format, Symbolic Microinstructions, The Fetch Routine, Symbolic Microprogram, Design of control unit –
Microprogram Sequencer.

MAJOR COMPONENTS OF CPU GENERAL REGISTER ORGANIZATION

Storage Components:
Registers
Clock Input
Flip-flops
R1
Execution (Processing) Components: R2
Arithmetic Logic Unit (ALU): R3
Arithmetic calculations, Logical computations, Shifts/Rotates R4
R5
R6
Transfer Components: R7
Bus Load
(7 lines)
SELA { MUX MUX } SELB
Control Components:
Control Unit 3x8 A bus B bus
Register decoder
File ALU
SELD
OPR ALU

Output
Control Unit

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OPERATION OF CONTROL UNIT ALU CONTROL

The control unit directs the information flow through ALU by: Encoding of ALU operations OPR
- Selecting various Components in the system Select Operation Symbol
00000 Transfer A TSFA
- Selecting the Function of ALU 00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
Example: R1  R2 + R3 00110 Decrement A DECA
[1] MUX A selector (SELA): BUS A  R2 01000
01010
AND A and B
OR A and B
AND
OR
[2] MUX B selector (SELB): BUS B  R3 01100 XOR A and B XOR
[3] ALU operation selector (OPR): ALU to ADD 01110 Complement A COMA
[4] Decoder destination selector (SELD): R1  Out Bus
10000 Shift right A SHRA
11000 Shift left A SHLA
3 3 3 5
Control Word SELA SELB SELD OPR Examples of ALU Microoperations
Symbolic Designation
Encoding of register selection fields
Microoperation SELA SELB SELD OPR Control Word
Binary
Code SELA SELB SELD R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101
000 Input Input None R4  R4 or R5 R4 R5 R4 OR 100 101 100 01010
001 R1 R1 R1 R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
010 R2 R2 R2 R7  R1 R1 - R7 TSFA 001 000 111 00000
011 R3 R3 R3
100 R4 R4 R4 Output  R2 R2 - None TSFA 010 000 000 00000
101 R5 R5 R5 Output  Input Input - None TSFA 000 000 000 00000
110 R6 R6 R6 R4  shl R4 R4 - R4 SHLA 100 000 100 11000
111 R7 R7 R7 R5  0 R5 R5 R5 XOR 101 101 101 01100
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REGISTER STACK ORGANIZATION MEMORY STACK ORGANIZATION

Stack 1000
- Very useful feature for nested subroutines, nested loops control Program
- Also efficient for arithmetic expression evaluation
Memory with Program, Data, PC (instructions)

- Storage which can be accessed in LIFO and Stack Segments

- Pointer: SP AR
Data
(operands)
- Only PUSH and POP operations are applicable
stack Address SP 3000
stack
Register Stack Flags 63

FULL EMPTY 3997

3998
3999
Stack pointer 4000
SP
4 - A portion of memory is used as a stack with a 4001
C 3
B 2 processor register as a stack pointer DR
A 1
Push, Pop operations 0
- PUSH: SP  SP - 1
DR M[SP]  DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */
- POP: DR  M[SP]
PUSH POP SP  SP + 1
SP  SP + 1 DR  M[SP]
M[SP]  DR SP  SP - 1 - Most computers do not provide hardware to check
If (SP = 0) then (FULL  1) If (SP = 0) then (EMPTY  1) stack overflow (full stack) or underflow(empty stack)
EMPTY  0 FULL  0
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REVERSE POLISH NOTATION INSTRUCTION FORMAT

Arithmetic Expressions: A + B Instruction Fields
A+ B Infix notation OP-code field - specifies the operation to be performed
+A B Prefix or Polish notation Address field - designates memory address(s) or a processor register(s)
AB+ Postfix or reverse Polish notation Mode field - specifies the way the operand or the
- The reverse Polish notation is very suitable for stack effective address is determined
manipulation
The number of address fields in the instruction format
Evaluation of Arithmetic Expressions depends on the internal organization of CPU
Any arithmetic expression can be expressed in parenthesis-free Polish notation, - The three most common CPU organizations:
including Reverse Polish notation
Single accumulator organization:
ADD X /* AC  AC + M[X] */
(3 * 4) + (5 * 6)  34*56*+ General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
6 MOV R1, R2 /* R1  R2 */
4 5 5 30 ADD R1, X /* R1  R1 + M[X] */
3 3 12 12 12 12 42 Stack organization:
3 4 * 5 6 * + PUSH X /* TOS  M[X] */
ADD
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THREE and TWO-ADDRESS INSTRUCTIONS ONE and ZERO-ADDRESS INSTRUCTIONS

One-Address Instructions:
Three-Address Instructions: - Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
Program to evaluate X = (A + B) * (C + D) : LOAD A /* AC  M[A] */
ADD R1, A, B /* R1 M[A] + M[B] */ ADD B /* AC  AC + M[B] */
ADD R2, C, D /* R2 M[C] + M[D] */ STORE T /* M[T]  AC */
MUL X, R1, R2 /* M[X] R1 * R2 */ LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
- Results in short programs
STORE X /* M[X]  AC */
- Instruction becomes long (many bits)
Zero-Address Instructions:
Two-Address Instructions: - Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
Program to evaluate X = (A + B) * (C + D) : PUSH A /* TOS  A */
PUSH B /* TOS  B */
MOV R1, A /* R1 M[A] */ ADD /* TOS  (A + B) */
ADD R1, B /* R1 R1 + M[B] */ PUSH C /* TOS  C */
MOV R2, C /* R2 M[C] */ PUSH D /* TOS  D */
ADD R2, D /* R2 R2 + M[D] */ ADD /* TOS  (C + D) */
MUL R1, R2 /* R1 R1 * R2 */ MUL /* TOS  (C + D) * (A + B) */
MOV X, R1 /* M[X] R1 */ POP X /* M[X]  TOS */

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TYPES OF ADDRESSING MODES

ADDRESSING MODES Implied Mode
Address of the operands are specified implicitly
in the definition of the instruction
- No need to specify address in the instruction
Addressing Modes: - EA = AC, or EA = Stack[SP ], EA: Effective Address.

* Specifies a rule for interpreting or modifying the Immediate Mode

address field of the instruction (before the operand Instead of specifying the address of the operand,
is actually referenced) operand itself is specified
- No need to specify address in the instruction
* Variety of addressing modes - However, operand itself needs to be specified
- Sometimes, require more bits than the address
- to give programming flexibility to the user - Fast to acquire an operand
- to use the bits in the address field of the
Register Mode
instruction efficiently Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)
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TYPES OF ADDRESSING MODES TYPES OF ADDRESSING MODES

Register Indirect Mode Direct Address Mode
Instruction specifies a register which contains Instruction specifies the memory address which
the memory address of the operand can be used directly to the physical memory
- Saving instruction bits since register address - Faster than the other memory addressing modes
is shorter than the memory address - Too many bits are needed to specify the address
- Slower to acquire an operand than both the
for a large physical memory space
register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x) - EA = IR(address), (IR(address): address field of IR)

Auto-increment or Auto-decrement features: Indirect Addressing Mode

Same as the Register Indirect, but: The address field of an instruction specifies the address of a memory
- When the address in the register is used to access memory, the location that contains the address of the operand
value in the register is incremented or decremented by 1 (after or before - When the abbreviated address is used, large physical memory can be
the execution of the instruction) addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory
access
- EA = M[IR(address)]

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TYPES OF ADDRESSING MODES ADDRESSING MODES - EXAMPLES

Relative Addressing Modes Address Memory
200 Load to AC Mode
The Address fields of an instruction specifies the part of the address PC = 200 201 Address = 500
(abbreviated address) which can be used along with a 202 Next instruction

designated register to calculate the address of the operand R1 = 400

399 450
XR = 100
PC Relative Addressing Mode(R = PC) 400 700

- EA = PC + IR(address) AC
- Address field of the instruction is short 500 800
- Large physical memory can be accessed with a small number of
address bits 600 900
Addressing Effective Content
Mode Address of AC
Indexed Addressing Mode Direct address 500 /* AC  (500) */ 800 702 325
XR: Index Register: Immediate operand - /* AC  500 */ 500
- EA = XR + IR(address) Indirect address 800 /* AC  ((500)) */ 300
Relative address 702 /* AC  (PC+500) */ 325 800 300
Base Register Addressing Mode Indexed address 600 /* AC  (XR+500) */ 900
BAR: Base Address Register: Register - /* AC  R1 */ 400
Register indirect 400 /* AC  (R1) */ 700
- EA = BAR + IR(address) Autoincrement 400 /* AC  (R1)+ */ 700
Autodecrement 399 /* AC  -(R) */ 450

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DATA TRANSFER INSTRUCTIONS DATA MANIPULATION INSTRUCTIONS

Typical Data Transfer Instructions Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Name Mnemonic Shift instructions
Load LD Arithmetic Instructions
Store ST
Name Mnemonic
Move MOV
Increment INC
Exchange XCH Decrement DEC
Input IN Add ADD
Output OUT Subtract SUB
Multiply MUL
Push PUSH Divide DIV
Pop POP Add with Carry ADDC
Subtract with Borrow SUBB
Data Transfer Instructions with Different Addressing Modes Negate(2’s Complement) NEG

Assembly Logical and Bit Manipulation Instructions Shift Instructions

Mode Convention Register Transfer
Name Mnemonic Name Mnemonic
Direct address LD ADR AC M[ADR] Logical shift right SHR
Clear CLR
Indirect address LD @ADR AC  M[M[ADR]] Logical shift left SHL
Complement COM
Relative address LD $ADR AC  M[PC + ADR] AND AND Arithmetic shift right SHRA
Immediate operand LD #NBR AC  NBR OR OR Arithmetic shift left SHLA
Index addressing LD ADR(X) AC  M[ADR + XR] Exclusive-OR XOR Rotate right ROR
Register LD R1 AC  R1 Clear carry CLRC Rotate left ROL
Register indirect LD (R1) AC  M[R1] Set carry SETC Rotate right thru carry RORC
Autoincrement LD (R1)+ AC  M[R1], R1  R1 + 1 Complement carry COMC Rotate left thru carry ROLC
Autodecrement LD -(R1) R1  R1 - 1, AC  M[R1] Enable interrupt EI
Disable interrupt DI
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PROGRAM CONTROL INSTRUCTIONS CONDITIONAL BRANCH INSTRUCTIONS

+1
In-Line Sequencing
(Next instruction is fetched from the Mnemonic Branch condition Tested condition
PC next adjacent location in the memory)
BZ Branch if zero Z=1
Address from other source; Current Instruction, Stack, etc BNZ Branch if not zero Z=0
Branch, Conditional Branch, Subroutine, etc BC Branch if carry C=1
BNC Branch if no carry C=0
Program Control Instructions BP Branch if plus S=0
Name Mnemonic BM Branch if minus S=1
Branch BR BV Branch if overflow V=1
Jump JMP BNV Branch if no overflow V=0
Skip SKP Unsigned compare conditions (A - B)
Call CALL * CMP and TST instructions do not retain their BHI Branch if higher A> B
Return RTN results of operations(- and AND, respectively). BHE Branch if higher or equal A B
Compare(by - ) CMP They only set or clear certain Flags. BLO Branch if lower A< B
Test (by AND) TST BLOE Branch if lower or equal A B
BE Branch if equal A= B
Status Flag Circuit A B BNE Branch if not equal A B
8 8
c7 Signed compare conditions (A - B)
8-bit ALU BGT Branch if greater than A> B
c8 BGE Branch if greater or equal A B
F7 - F0
BLT Branch if less than A< B
V Z S C BLE Branch if less or equal A B
F7
BE Branch if equal A= B
Check for 8 BNE Branch if not equal A B
zero output
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PROGRAM INTERRUPT
SUBROUTINE CALL AND RETURN Types of Interrupts:
SUBROUTINE CALL Call subroutine External interrupts
Jump to subroutine
Branch to subroutine External Interrupts initiated from the outside of CPU and Memory
Branch and save return address - I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure
Two Most Important Operations are Implied;

* Branch to the beginning of the Subroutine

Internal interrupts (traps)
Internal Interrupts are caused by the currently running program
- Same as the Branch or Conditional Branch
- Register, Stack Overflow
- Divide by zero
* Save the Return Address to get the address - OP-code Violation
of the location in the Calling Program upon - Protection Violation
exit from the Subroutine CALL
- Locations for storing Return Address: SP  SP - 1 Software Interrupts
• Fixed Location in the subroutine(Memory) M[SP]  PC
Both External and Internal Interrupts are initiated by the computer Hardware.
PC  EA
• Fixed Location in memory Software Interrupts are initiated by executing an instruction.
• In a processor Register RTN - Supervisor Call -> Switching from a user mode to the supervisor mode
• In a memory stack PC  M[SP] -> Allows to execute a certain class of operations
- most efficient way SP  SP + 1 which are not allowed in the user mode

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INTERRUPT PROCEDURE COMPLEX INSTRUCTION SET COMPUTERS: CISC

Interrupt Procedure and Subroutine Call
- The interrupt is usually initiated by an internal or High Performance General Purpose Instructions
an external signal rather than from the execution of
an instruction (except for the software interrupt) Characteristics of CISC:
1. A large number of instructions (from 100-250 usually)
- The address of the interrupt service program is 2. Some instructions that performs a certain tasks are not used frequently.
determined by the hardware rather than from the 3. Many addressing modes are used (5 to 20)
address field of an instruction 4. Variable length instruction format.
5. Instructions that manipulate operands in memory.
- An interrupt procedure usually stores all the
information necessary to define the state of CPU
rather than storing only the PC.

The state of the CPU is determined from;

Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state depending on the CPU architectures
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CHARACTERISTICS OF RISC
CONTROL MEMORY
RISC Characteristics
- Relatively few instructions Microprogram
- Relatively few addressing modes - Program stored in memory that generates all the control signals required to execute the instruction
- Memory access limited to load and store instructions set correctly
- All operations done within the registers of the CPU - Consists of microinstructions
- Fixed-length, easily decoded instruction format
- Single-cycle instruction format
Microinstruction
- Contains a control word and a sequencing word
- Hardwired rather than microprogrammed control Control Word - All the control information required for one clock cycle
More RISC Characteristics Sequencing Word - Information needed to decide the next microinstruction address
- Vocabulary to write a microprogram
-A relatively large numbers of registers in the processor unit.
-Efficient instruction pipeline Control Memory(Control Storage: CS)
-Compiler support: provides efficient translation of high-level language - Storage in the microprogrammed control unit to store the microprogram
programs into machine language programs.
Advantages of RISC Writeable Control Memory(Writeable Control Storage: WCS)
- CS whose contents can be modified
- VLSI Realization -> Allows the microprogram can be changed
- Computing Speed -> Instruction set can be changed or modified
- Design Costs and Reliability
- High Level Language Support 28
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ADDRESS SEQUENCING
Dynamic Microprogramming Instruction code

- Computer system whose control unit is implemented with Mapping

logic
a microprogram in WCS
- Microprogram can be changed by a systems programmer or a user Status Branch MUX Multiplexers
bits logic select
Subroutine
Sequencer (Microprogram Sequencer) Control address register
register
(CAR) (SBR)

A Microprogram Control Unit that determines the Microinstruction Address to be executed in the Incrementer
next clock cycle
Control memory (ROM)
- In-line Sequencing select a status
- Branch bit
Microoperations
- Conditional Branch Branch address

- Subroutine Sequencing Capabilities Required in a Control Storage

- Loop
- Instruction OP-code mapping - Incrementing of the control address register
- Unconditional and conditional branches
- A mapping process from the bits of the machine instruction to an address for control memory
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MAPPING OF INSTRUCTIONS MAPPING OF INSTRUCTIONS TO MICROROUTINES

Direct Mapping Address Mapping from the OP-code of an instruction to the address of the Microinstruction which is the
OP-codes of Instructions 0000 ADD Routine starting microinstruction of its execution microprogram.
0001 AND Routine
ADD 0000
. 0010 LDA Routine
AND 0001 Machine OP-code
. 0011 STA Routine
1 0 1 1 Address
LDA 0010 . 0100 BUN Routine Instruction
STA 0011
BUN 0100 Control Mapping bits 0 x x x x 0 0
Storage
Microinstruction
Mapping address 0 1 0 1 1 0 0
Bits 10 xxxx 010 Address
10 0000 010 ADD Routine
Mapping function implemented by ROM or PLA
10 0001 010 AND Routine OP-code
10 0010 010 LDA Routine
Mapping memory
(ROM or PLA)
10 0011 010 STA Routine

10 0100 010 BUN Routine

Control address register

Control Memory
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MICROPROGRAM EXAMPLE MACHINE INSTRUCTION FORMAT

Computer Configuration
Machine instruction format
15 14 11 10 0
MUX
10 0 I Opcode Address
AR
Address Memory Sample machine instructions
10 0 2048 x 16
Symbol OP-code Description
PC EA is the effective address
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC EA)
MUX STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC
15 0
6 0 6 0 DR
SBR CAR Microinstruction Format
3 3 3 2 2 7
Control memory Arithmetic
128 x 20 logic and F1 F2 F3 CD BR AD
shift unit
Control unit F1, F2, F3: Microoperation fields
15 0
AC CD: Condition for branching
BR: Branch field
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AD: Address field

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3 MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR

CD Condition Symbol Comments

F1 Microoperation Symbol F2 Microoperation Symbol 00 Always = 1 U Unconditional branch
000 None NOP 000 None NOP 01 DR(15) I Indirect address bit
001 AC  AC + DR ADD 001 AC  AC - DR SUB 10 AC(15) S Sign bit of AC
AC  0 11 AC = 0 Z Zero value in AC
010 CLRAC 010 AC  AC  DR OR
011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR
BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
F3 Microoperation Symbol
CAR  CAR + 1 if condition = 0
000 None NOP
10 RET CAR  SBR (Return from subroutine)
001 AC  AC  DR XOR
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved
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SYMBOLIC MICROINSTRUCTIONS SYMBOLIC MICROPROGRAM - FETCH ROUTINE

• Symbols are used in microinstructions as in assembly language During FETCH, Read an instruction from memory
• A symbolic microprogram can be translated into its binary equivalent by a microprogram assembler. and decode the instruction and update PC

Sample Format Sequence of microoperations in the fetch cycle:

five fields: label; micro-ops; CD; BR; AD AR PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0
Label: may be empty or may specify a symbolic address terminated with a colon

Micro-ops: consists of one, two, or three symbols Symbolic microprogram for the fetch cycle:
separated by commas ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
CD: one of {U, I, S, Z}, where
U: Unconditional Branch DRTAR U MAP
I: Indirect address bit
S: Sign of AC Binary equivalents translated by an assembler
Z: Zero value in AC Binary
BR: one of {JMP, CALL, RET, MAP} address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
AD: one of {Symbolic address, NEXT, empty} 1000010 101 000 000 00 11 0000000

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SYMBOLIC MICROPROGRAM BINARY MICROPROGRAM

• Control Storage: 128 20-bit words Address Binary Microinstruction
• The first 64 words: Routines for the 16 machine instructions Micro Routine Decimal Binary F1 F2 F3 CD BR AD
• The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) ADD 0 0000000 000 000 000 01 01 1000011
• Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are 1 0000001 000 100 000 00 00 0000010
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60 2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
Partial Symbolic Microprogram BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
Label Microops CD BR AD 6 0000110 000 000 000 01 01 1000011
ORG 0 7 0000111 000 000 110 00 00 1000000
ADD: NOP I CALL INDRCT
READ U JMP NEXT STORE 8 0001000 000 000 000 01 01 1000011
ADD U JMP FETCH 9 0001001 000 101 000 00 00 0001010
ORG 4 10 0001010 111 000 000 00 00 1000000
BRANCH: NOP S JMP OVER 11 0001011 000 000 000 00 00 1000000
NOP U JMP FETCH
OVER: NOP I CALL INDRCT EXCHANGE 12 0001100 000 000 000 01 01 1000011
ARTPC U JMP FETCH 13 0001101 001 000 000 00 00 0001110
ORG 8 14 0001110 100 101 000 00 00 0001111
STORE: NOP I CALL INDRCT 15 0001111 111 000 000 00 00 1000000
ACTDR U JMP NEXT
WRITE U JMP FETCH
FETCH 64 1000000 110 000 000 00 00 1000001
ORG 12 65 1000001 000 100 101 00 00 1000010
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT 66 1000010 101 000 000 00 11 0000000
ACTDR, DRTAC U JMP NEXT INDRCT 67 1000011 000 100 000 00 00 1000100
WRITE U JMP FETCH
68 1000100 101 000 000 00 10 0000000
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC
DRTAR
U
U
JMP
MAP
NEXT This microprogram can be implemented using ROM
INDRCT: READ U JMP NEXT
DRTAR U RET
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