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Chapter 01

The document discusses the von Neumann architecture and its implementation in the IAS computer. It describes the key components of the von Neumann architecture including memory to store both data and instructions, an ALU, control unit, and interconnections. It then provides details about the implementation of these components in the IAS computer such as its memory organization, registers, instruction cycle, and instruction set.

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0% found this document useful (0 votes)
22 views

Chapter 01

The document discusses the von Neumann architecture and its implementation in the IAS computer. It describes the key components of the von Neumann architecture including memory to store both data and instructions, an ALU, control unit, and interconnections. It then provides details about the implementation of these components in the IAS computer such as its memory organization, registers, instruction cycle, and instruction set.

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LECTURE – 01

COMPUTER ARCHITECTURE COMPUTER ORGANIZATION


It refers to those attributes that have a direct It refers to the organizational units and their
impact on the execution of a program. interconnection that realize the architectural
specifications.
It refers to those attributes of a system visible to The organizational attributes are those
a programmer. hardware features and details which are
transparent to the programmer.
Examples of architectural attributes: the Examples of organizational attributes:
instruction set, the number of bits used to interfaces between the computer and
represent various data types, I/O mechanisms peripherals, and the memory technology used.
and techniques for addressing memory.
It is an architectural design issue whether a It is an organizational issue whether that
computer will have multiply instruction. instruction will be implemented using a simple
multiply unit or by a mechanism that makes
repeated use of the add unit of the system.
An architecture may survive for long. An organization changes more frequently than
the architecture.

Evolution:
- Increase in processor size, memory size, I/O speed and capacity
- Decrease in component size
Ways to improve performance:
- By improvement in computer organization
- By heavy use of pipelining, use of parallel execution techniques, speculative execution
techniques etc.
COMPUTER STRUCTURE AND FUNCTION:
Structure: The way in which the components are
interrelated
Function: The operation of each individual component as
part of the structure.
Four main functions:
- Data processing
- Data storage
- Data movement
- Control
Four main structural components:
- Central Processing Unit: Controls the operation of the computer and performs its data
processing functions.
- Main memory: Stores data.
- I/O: Moves the data between the computer and its external environment.
- System interconnection: Some mechanism that provides for communication among CPU,
main memory and I/O.
Major structural components of CPU:
- Control Unit: Controls the operation of the processor and hence the computer.
- Arithmetic and Logic Unit: Performs the computer’s data processing functions.
- Registers: Provides storage internal to the CPU.
- CPU interconnection: Some mechanism that provides for communication among the CU,
ALU, and registers.
LECTURE – 02
In 1946, von Neumann and his colleagues began the design of a new stored program computer,
referred to as the IAS computer.
The IAS computer, although not completed until 1952, is the prototype of all subsequent general-
purpose computers.

The IAS computer consists of:


- A main memory, which stores both data and instructions in the same form.
- An arithmetic and logic unit capable of operating on binary data.
- A control unit, which interprets the instructions in memory and causes them to be executed.
- I/O equipment operated by the control unit.
- Interconnections.

Key points of the Von Neumann Architecture:


- Data and instructions are stored in a single read write memory.
- The contents of this memory is addressable by location without regard to the type of data it
contains.
- Execution occurs in a sequential order (unless explicitly modified) from one instruction.
- Memory of IAS consists of 1000 storage locations, called words, of 40 binary digits each.
- Numbers are represented in binary form and each instruction is a binary code.
- Each number is represented by a sign bit and 39 bit value (Fig 2.2a)
- A word may also contain two 20-bit instructions, with each instruction consisting of 8 bit
operation code specifying the instruction to be performed and a 12 (total memory locations:
212 = 4096) bit designating one of the words in the memory (ranging from 0 to 999)

Both the control unit and the ALU contain storage locations, called registers.
- Memory buffer registers (MBR): Contains a word to be sent to the memory or the I/O unit,
or is used to receive a word from the memory or the I/O unit.
- Memory address registers (MAR): Specifies the address in the memory of the word to
written from or read into the MBR.
- Instruction register (IR): Contains the 8-bit opcode instruction being executed.
- Instruction buffer register (IBR): Employed to store temporarily the right hand instruction
from a word in memory.
- Program counter (PC): Contains the address of the next instruction pair to be fetched from
the memory.
- Accumulator (AC) and multiplier quotient (MQ): Employed to hold the temporarily
operands and results of ALU operations.
 IAS operates by repetitively performing an instruction cycle.
 Each instruction cycle consists of two sub cycles: fetch cycle and execute cycle.

The IAS computer had a total of 21 instructions. These can be grouped as follows:
- Data transfer: Move data between memory and ALU registers or between two ALU
registers.
- Unconditional branch: Normally, the CU executes instruction in sequence from memory.
This sequence can be changed by a branch instruction, which facilitates repetitive operations.
- Arithmetic: Operations performed by the ALU.
- Address modify: Permits addresses to be computed in the ALU and then inserted into
instructions stored in memory. This allows a program considerable addressing flexibility.

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