ASIC DESIGN TYPES

ASIC is mainly Divided into two

Divisions
1)Logical Design(LD)
2)Physical Design(PD)

Physical Design is Physical implementation of Design

 In Physical Design mainly Six inputs are present
1. Logical libraries --> format is .lib --->given by Vendors
2. Physical libraries -->format is .lef --->given by vendors
3. Technology file -->format is .tf --->given by fabrication peoples
4. TLU+ file -->format is .TLUP-->given by fabrication people
5. Netlist --->format is .v -->given by Synthesis People
6. Synthesis Design Constraints -->format is .SDC -->given by Synthesis People

PHYSICAL DESIGN PROCESS.

1. DATA PREPARATION.
2. FLOOR PLAN.
3. POWER PLAN-->POWER ROUTING [PRE ROUTE]
4. PLACEMENT.
5. CLOCK TREE SYNTHESIS.-->CLOCK ROUTING.
6. ROUTING.-->DATA ROUTING.-->[POST ROUTE]
7. CHIP FINISHING.
8. VERIFICATION.
9. GDSII FILE.

LOGIC LIBRARIES
Logical libraries :Format is .lib(liberty)
1. Timing information of Standard cells,Soft macros,Hard macros.
2. Functionality information of Standard cells,Soft macros.
3. And design rules like max transition ,max capacitance, max fanout.
4. In timing information Cell delays ,Setup,Hold,Recovery,Removal time are present.
5. Cell delay is Function of input transition and output load.
6. Cell delay is calculated based on lookup tables.
7. Cell delays are calculated by using linear delay models,Non linear delay models,CCS models.
8. Functionality is used for Optimization Purpose.
9. And also Contain Power information.
10. And contains Leakage power for Default cell,Leakage Power Density for cell,Default Input
voltage , Out put voltage.
And PVT contains ------------>On Chip Variations(BC,WC)
------------>Cell leakage Power
---------->Internal Power
 ---------->Rise Transition
----------->Fall transition
---------->>Setup rise
----------->Setup fall
----------->Hold rise
------------>Hold fall
------------>Minimum pulse width high
------------->Minimum pulse width low
------------->Recovery rise
-------------->Removal fall
--------------->Cell rise
-------------->Cell fall
-------------->Pin Capacitance

Cell level information

1. Cell name
2. Area(represent with Nand Equ Area)
3. Power (Funtion of input transition, Total output net Cap )
4. Funtionality
5. Delay
6. Max Cap
7. Max Trans
8. Foot Print
And it also Contains K-Factor

And it also contain WIRE LOAD MODELS

And it contains A view(sub directory) i.e. LM(Logical Model view)view.

It contains logical libraries.

PHYSICAL LIBRARIES
Physical libraries: format is .lef(Layout Exchange
Format):
1. physical information of std cells,macros,pads.
2. Pin information.
3. Define unit tile(sites) placement.
4. Minimum Width of Resolution.
5. Hight of the placement Rows .
6. Preferred routing Directions.
7. Pitch of the routing tracks.
8. Antena Rules.
9. Routing Blockages,Macro Blockage
Macro/Stad Cells :-------------->Cell neame
 -------------->Size(Dimensions,Area)
------------->Pin
------------->Port
------------->Layer
------------->Direction

Pins information : --------------->Direction(Input,Output,INOUT)

--------------->Use(Signal,Power,Ground)
--------------->Antena Gate Area
--------------->layer

LEFs are 3 Types : .Macro lef (Macro Info)

.StdCell lef(Standard Cell Info )
.Tech lef(Layer,Via Info)

In physical info height,area,width are present.

and also it contains two views
1)Cell View:
In this all layout information is present,it is used at the time of tapeout
2)FRAM view:
Fram view is abstract view, it is used at the Place & Route

TECHNOLOGY FILE
Technology file: format is .tf:
1. It contains Name,Number conventions of layer and via
2. It contains Physical,electrical characteristics of layer and via
3. In Physical characteristics Min width,Min Spacing,Min Hight are present.
4. In Electrical characteristics Max Current Density is present.
5. Units and Precisions of layer and via .
6. Colors and pattern of layer and via .
7. Physical Design rules of layer and via
8. In Physical Design rules Wire to Wire Spacing,Min Width between Layer and via are present.

Layer Info :
1. Mask Name
2. Visible
3. Selectable
4. Line Style(Solid)
5. Patteren
6. Pitch
7. Cut Layer
 TLU+
TLU+ files: format is .TLUP:
1. R,C parasitics of metal per unit length.
2. These(R,C parasitics) are used for calculating Net Delays.
3. If TLU+ files are not given then these are getting from .ITF file.
4. For Loading TLU+ files we have load three files .
5. Those are Max Tlu+,Min TLU+,MAP file.
6. MAP file maps the .ITF file and .tf file of the layer and via names.

NETLIST
Netlist: Format is .V
It contains Logical connectivity Of all Cell(Std cells,Macros).
It contain List of nets.
In the design, for Knowing the connectivity by using Fly lines.

.V ---------->Logical Connectivity
.ddc-------->logical connectivity,Scan chain info, .Scandef file info,Gate level Description

SDC
SDC :Format is .SDC :
These Constraints are timing Constraints .
These Constraints are used for to meet timing requirements.

Constraints are
1. CLOCK DEFINITIONS:Create Clock Period.
2. Generated Clock Definitions
3. Input Delay
4. Output Delay
5. I/O delay
6. Max delay
7. Min Delay
8. --------------->Exceptions<-------------------------
9. Multi cycle path
10. False path
11. Half cycle path
12. Disable timing arcs
13. Case Analysis
Multi cycle path, False path are Exceptions.

And it also contains

--------------->Clock latency
--------------->Clock Uncertainity
--------------->Clock Transition

--------------->Clock Gating setup

--------------->Clock Gating Hold
--------------->Clock Driving cell

FLOOR PLAN
FLOOR PLAN:
AT CHIP LEVEL:

FLOOR PLAN IS A STEP WHERE WE CREATING THE PAD CELLS .

AND SPACIFYING POSITIONS, PLACING PAD CELLS.

AND INSERTING PAD FILLER CELLS,FOR WELL CONTINITY.

WELL CONTINITY , WELL CONTINITY MEANS IF THE WELL IS NOT CONTINOUS THEN WE
HAVE TO CREATE SPECIAL MASKS.

IF WELL IS CONTINOUS THEN THERE IS NO NEED OF CREATING SPECIAL MASKS.

IN FLOOR PLAN MAIN IMPORTANT IS MACRO PLACEMENT.

MACROjkbkb S NOTHING BUT IP'S, MEMORY CELLS.

IF WE HAVE A LARGE CIRCUIT THEN THERE IS NO NEED OF CREATING EVERY TIME.

THE CIRCUIT IS AVAILABLE IN THE MARKET IN THE FORM OF MACRO OR IP.

MACROS ARE TWO TYPES:(i)HARD MACRO.

(ii)SOFT MACRO.
HARD MACRO:THE CIRCUIT IS FIXED. AND WE DON'T NO WHICH TYPE OF GATES USING
INSIDE.WE KNOW THE ONLY TIMING INFORMATION.WE DON'T KNOW THE FUNCTIONALITY
INFORMATION.

SOFT MACRO:THE CIRCUIT IS NOT FIXED.WE KNOW WHICH TYPE OF GATES USING
INSIDE.WE KNOW THE TIMING INFORMATION. WE KNOW THE FUNCTIONALITY
INFORMATION.

AND IN FLOORPLAN WE ALSO CREATING THE BLOCKAGES.

BLOCKAGES:BLOCKAGES ARE THE IF LET TAKE WE WANT SOME AREA WHERE

NO ONE STD CELL PLACE. FOR THAT PURPOSE WE ARE USING BLOCKAGES.

BLOCKAGES ARE TWO TYPES:(i)SOFT BLOCKAGES

(ii)HARD BLOCKAGES.

SOFT BLOCKAGES MEANS NO ONE STD CELLS PLACED FIRST, BUT AT THE TIME OF
OPTIMIZATION ONLY BUFFERS ARE PLACED, AND THESE ARE USED AT (i)BETWEEN TWO
MACROS,
(ii)AND BETWEEN MACRO AND BOARDERS.

HARD BLOCKAGES MEANS NO ONE STD CELLS PLACED.AND THESE ARE USED AT THE
AROUND THE MACRO.BECAUSE PIN ACCESSING.

IN THE FLOOR PLAN MAIN OBJECTS ARE MACRO PLACEMENT.,

DEFINE ASPECT RATIO(HEIGHT/WIDTH).
I/O PLACEMENTS.
CORE AREA INITIALIZATION.

CORE AREA :CORE AREA IS DEFINED FOR THE PLACEMENT OF STD CELLS,AND
MACROS.

CORE AREA DEPENDS ON (i)ASPECT RATIO

(ii)UTILIZATION.

UTILIZATION=(STD CELL AREA+MACRO AREA+BLOCKAGE AREA)/TOTAL AREA.

STD CELL UTILIZATION=(STD CELL AREA)/

(TOTAL CORE AREA -(MACRO AREA+BLOCKAGE AREA)).

THESE STD CELLS ARE PLACED IN ROWS.

 ----->I/O PLACEMENT.
IN I/O PLACEMENT WE HAVING PADS.

PADS ARE USED FOR INTERFACING PURPOSE,AND THESE ARE USED FOR
PROVIDING POWER SUPPLY, DATA SIGNAL,CLOCK SIGNAL.

EASILY THESE CAN BE USED AS PORTS.

PADS ARE DIFFERENT TYPES:(i)POWER PADS,

(ii)SIGNAL PADS.
(iii)CORNER PADS.
(iv)I/O PADS.

MACRO PLACEMENT (GUIDE LINES)

Macro Placement Depend On
1. FLY LINES
2. PORTS COMMUNICATIONS.
3. MACRO'S ARE PLACED AT BOUNDARIES-->Uniform area for Stad cells
4. MACRO GROUPING [LOGICAL HIERARCHY]
5. SPACING BETWEEN MACRO'S
6. MACRO ALIGNMENT
7. NOTCHES AVOIDING
8. ORIENTATION
9. BLOCKAGES
10. AVOID CRIS CROSS PLACEMENT OF MACROS
 MACROS ARE ROTATED AS REQUIRED TO OPTIMIZE WIRE LENGTH DURING AUTOMATIC
MACRO PLACEMENT.
 TYPICALLY , MACROS ARE PLACED AROUND EDGES OF BLOCKS,KEEPING ARE LARGE
MAIN AREA FOR STD CELLS
 LEAVE A HALO SPACE BETWEEN MACROS ON ALL SIDES
 FOR A NON PIN SIDES OF MACROS A MINIMAL SEPARATION .IS ADEQUATE.
 FOR PIN SIDES OF MACROS A LARGER SEPARATION IS APPROPRIATE.
 ALLOW CHANNELS FOR ROUTING PIN ACCESS AND POSSIBLE BUFFER INSERTION
 LEAVE SPACE BETWEEN MACRO AND THE EDGE OF CHIP/BLOCK, TO ALLOW FOR
BUFFERS INSERTION AND POWER STRIPES TO FEED STD CELL ROWS BETWEEN MACRO
AND BLOCK EDGE.

CALCULATION FOR DISTANCE BETWEEN MACROS:

 NO.OF PINS (X) PITCH
DISTANCE BETWEEN MACROS= ------------------------------------------------------
AVAILABLE LAYERS/TOTAL LAYERS

FLOOR PLAN (PAD CELLS)

IN FLOOR PLAN

1. CREATE PHYSICAL ONLY PAD CELLS. PHYSICAL ONLY CELLS MEANS ONLY THOSE
HAVING PHYSICAL INFORMATION ONLY. NO LOGICAL INFORMATION PRESENT. AND THEY
DON'T HAVE TIMING INFORATION ALSO.
2. PHYSICAL ONLY PAD CELLS ARE (i)VDD,VSS PADC CELLS,(ii)CORNER PAD CELLS.
3. PAD CELLS ACTS LIKE AS PORTS AT THE CHIP LEVEL.
4. CHIP OUTSIDE PINS ARE CONNECTED TO THE INNER CHIP PADS.
5. PADS TYPES:(i)POWER PADS, (ii)DATA PADS .
6. FOR THE POWER SUPPLY TO THE ALL PADS CREATING A PAD POWER RING .
7. VDD,VSS PADS ARE CONNECTED TO THE CORE VDD,VSS POWER RINGS.
8. FOR FILLING THE GAPS BETWEEN THE PADS FILLED BY PAD FILLER CELLS.
9. THESE PAD FILLER CELLS ARE FOR WELL CONTINUITY.

PHYSICAL ONLY CELLS ARE:

1. PAD CELLS.
2. END CAP CELLS.
3. TAP CELLS.
4. DECAP CELLS.

POWER PLANNING
IN POWER PLANNING
IR DROP :VOLTAGE TRANSFER IN METAL A DROP OCCURS DUE TO RESISTANCE OF
METAL.THIS IS KNOWN AS IR DROP.

IR DROPS ARE TWO TYPES (i)STATIC IR DROP,(ii)DYNAMIC IR DROP.

STATIC IR DROP:INDEPENDENT OF THE CELL SWITCHING THE DROP IS CALCULATED

WITH THE HELP OF WIRE RESISTANCE.

IMPROVE STATIC IR DROP:(i)WIDTH OF WIRE INCREASE, OR (ii) INCREASE THE

NO.OF WIRES

DYNAMIC IR DROP:IR DROP IS CALCULATED WITH THE HELP OF THE SWITCHING OF

THE CELLS.

IMPROVE DYNAMIC IR DROP:(i)PLACING DCAP CELLS IN BETWEEN

THEM,(iii)INCREASE THE NO OF STRAPS.
 ELECTROMIGRATION: WHEN HIGH CURRENT DENSITY CONTINUOUSLY PASSING
THROUGH A METAL DUE TO THE HIGH CURRENT, THE ATOMS ARE MOVING WITH KINETIC
ENERGY AND THEY TRANSFER THE ENERGY TO ANOTHER ATOMS DUE THESE DAMAGE
THE METAL.

IMPROVE:INCREASE METAL WIDTH.

1. FIRST SAVE THE DESIGN, BEFORE GOING TO POWER PLAN.

2. DEFINE LOGICAL P/G CONNECTIONS.
3. APPLY POWER NETWORK CONSTRAINTS.
4. POWER NETWORK CONSTRAINTS ARE
5. (i)NO.OF POWER STRAPS,(ii)POWER STRAPS WIDTH,(iii)NO.OF POWER PADS, (iii)POWER
RING WIDTH.
6. SYNTHESIZE THE POWER NETWORK,ANALYZE POWER NET WORK .
7. ANALYZE POWER NETWORK :(i) P/G NETPAIR (ii) POWER BUDGET OF SYNTHESIZED
NETS(iii)PNS CALCULATES THE REQUIRED NO.OF STRAPS BASED ON PROVIDED
CONSTRAINTS. (iv) IR DROP. (v) ELECTROMIGRATION.
8. ANALYZE IR DROP.
9. IF IR DROP IS MORE THEN MODIFY POWER NETWORK CONSTRAINTS ,AND
RESYNTHESIZE POWER NETWORK.
10. IF IR DROP IS NOT SATISFIED ADD P/G PADS.
11. COMMIT THE POWER NETWORK, HERE STRAPS AND RINGS ARE ROUTED ,SO WE CAN'T
MODIFY THE DESIGN.
12. CONNECT THE MACRO P/G PINS AND PAD P/G PINS TO THE CORE RINGS.
13. CREATE POWER RAILS.ALONG THE STD CELL ROWS.
14. AND RE ANALYZE IR DROP.IF STRAPS ARE NOT SUFFICIENT THEN ADD.
15. APPLY P-NET OPTIONS . WHEN A POWER STRAPS IN METAL 7,POWER STRAPS ARE
CONNECTED TO THE POWER RAILS THROUGH VIA'S. SO IF ANY PLACED INN THAT AREA
THEN SHORTS OCCURRED .FOR AVOIDING THESE PROBLEM WE ARE ADDING P-NET
OPTIONS.
16. AFTER THIS INCREMENTAL PLACEMENT:IT MEANS EFFECTIVELY CELLS MOVING

POWER PLANNING IS ALSO CALLED AS THE PREROUTES.

BECAUSE IN THE CHIP FIRST POWER NETS ROUTED FIRST.

POWER CALCULATIONS:
----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF CHIP=(TOTAL
CORE POWER)/{(NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM ALLOWABLE CURRENT
FOR A I/O PAD)} .

----->CORE RING WIDTH:

CORE CURRENT(mA)=(CORE POWER)/(CORE VOLTAGE )

CORE P/G RING WIDTH =(TOTAL CORE CURRENT)/{(N0.OF.SIDES)*(MAXIMUM CURRENT
DENSITY OF THE METAL LAYER USED FOR PG RING)}

------->MAXIMUM CURRENT DENSITY Rj mA.

-------->SHEET RESISTANCE :Rs OHMS/SQUARE.

-------->TOTAL CURRENT =TOTAL POWER CONSUMPTION OF CHIP(P)/VOLTAGE(V).

-------->NO.OF POWER PADS(Npads)=Itotal/Ip

------->Itotal =TOTAL CURRENT

------->Ip OBTAINED FROM IO LIBRARY SPACIFICATION.

-------->NO.OF POWER PINS = Itotal/Ip

-------->MAXIMUM CURRENT SPACIFICATION OF EACH METAL LAYER FROM LIBRARY(Rj).

---------->TOTAL METAL WIDTH REQUIRED ON LAYER1=LAYER2=

Wtotalstrap = Itotal/(2*Rj)

----------->ASSUMING SPACINGS BETWEEN STRAPS=Lspace

L<(Vmax)/(Rj*Rs)

Vmax = MAX ALLOWABLE IR DROP

Rj=MAX CURRENT DENSITY
Rs=SHEET RESISTANCE

---------->TOTAL CORE AREA=Wcore*Hcore

H=HEIGHT
W=WIDTH

----------->NUMBER OF VERTICAL STRAPS=Nv=Wcore/L

----------->NUMBER OF HORIZONTAL STRAPS=NH=Hcore/(2*L)

------------> MIN STRAP WIDTH REQUIRED=Wring/(Nv*Nh)

IR DROP:
------>AVG CURRENT THROUGH EACH STRAP=IstrapAvg=(Itotal)/(2*Nstraps)mA

-------->APPROPRIATE IR DROP AT THE CENTER OF THE STRAP=Vdrop or IRdrop

=IstrapAvg*Rs*(W/2)*(1/Wstrap)

--------->NUMBER OF STRAPS BETWEEN TWO POWER PADS

Nstrappinspace = Dpadspacing/Lspace.
 ---------->MIN RING WIDTH = Wring = Ip/Rj microm

POWER
-------->TOTAL POWER=STATIC POWER+DYNAMIC POWER
=LEAKAGE POWER+[INTERNAL POWER+EXT SWITCHING POWER]
=LEAKAGE POWER+[{SHORTCKT+INT POWER}]+EXT SWITCHING POWER]
=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]

Isc=SHORT CIRCUIT POWER

C=LOAD CAP
S=SWITCHING ACTIVITY FACTOR.

FLOORPLAN (CONGESTION)

CONGESTION: REQUIRED NO.OF ROUTING RESOURCES ARE GREATER THAN

THE NO.OF AVAILABLE ROUTING RESOURCES

1. FOR THE CONGESTION ANALYSIS WE HAVE TO DO FIRST PERFORM GLOBAL ROUTING.

2. BY USING GLOBAL ROUTING CALCULATING CONGESTION.
3. ANALYZE THE CONGESTION [IF WE HAVE CONGESTION MEANS ROUTING PROBLEM(MAY
CAUSES SHORTS)].
4. IF THE CONGESTION IS PRESENT THEN MODIFY THE PLACEMENT STRATEGY
PARAMETERS LIKE BLOCKAGES,OFFSET,KEEP OUT MARGINS,SLIVER SIZE AND MACRO,
STD CELL CONSTRAINTS.
5. PERFORM CONGESTION DRIVEN VIRTUAL FLAT PLACEMENT.CONGESTION DRIVEN
MEANS MOVING STD CELLS FAR AWAY.
6. REANALYZE THE CONGESTION. IF CONGESTION IS NOT SATISFIED.
7. PERFORM HIGH EFFORT CONGESTION DRIVEN VIRTUAL FLAT PLACEMENT.
8. REANALYZE THE CONGESTION.
9. IF CONGESTION IS NOT SATISFIED.
10. MODIFY THE FLOOR PLAN.
11. IF CONGESTION IS SATISFIED.
12. FIX MACRO PLACEMENT.

CONGESTION CAUSES :
1. MISSING PLACEMENT BLOCKAGES
2. IMPROPER MACRO PLACEMENT AND MACRO CHANNEL
3. HIGH CELL DENSITY(HIGH LOCAL UTILIZATION)
4. VERY ROUBUST POWER NETWORK
5. EXCESS POWER STACK VIAS
6. PIN DENSITY OF CELLS, MACROS
7. DUE TO PORTS

MORE FIXES :
1. HIGH CELL DENSITY PROBLEM---->BY USING CO-ORDINATES WE REDUCE UTILIZATION
2. PARTIAL PLACEMENT BLOCKAGES
3. MAX UTILIZATION %
4. INCREASING SPACING BETWEEN MACROS
5. FLIP MACRO(DO NOT FLIP 90 DEGREES)
6. MODIFY KEEP OUT CONSTRAINTS
7. GIVING HARD KEEP CHANNEL WIDTH

FLOOR PLAN(VIRTUAL FLAT PLACEMENT)

VIRTUAL FLAT PLACEMENT:

1. APPLY PLACEMENT STRATEGY PARAMETERS.

2. PERFORM VIRTUAL FLAT PLACEMENT.
PLACEMENT STRATEGY PARAMETERS ARE (i)VIPO(VIRTUAL IN PLACEMENT
OPTIMIZATION),(ii)CONGESTION EFFORT,(iii)SLIVER SIZE,(iv)MACRO
PLACEMENT,(v)OPTIMIZATION ALGORITHMS AND EFFORT.
VIRTUAL FLAT PLACEMENT MEANS VIRTUALLY PLACING THE STD CELLS.AND
ANALYZE THE CONGESTION AND TIMING.

FLOORPLAN(TIMING)
FLOOR PLAN [TIMING]:
IN FLOOR PLAN TIMING IS ALSO IMPORTANT.

1. BEFORE GOING TO TIMING , PERFORM GLOBAL ROUTING AND ANALYZE CONGESTION.

2. BY PERFORMING THE GLOBAL ROUTING EXTRACT APPROPRIATE R,C VALUES.
3. IF IN THE DESIGN CONGESTION PRESENT, GO TO THE CONGESTION STEP AND MODIFY
THE P - NET OPTIONS FULL TO PARTIAL.
4. PERFORM GLOBAL ROUTING AND ANALYZE CONGESTION.
5. IF IN THE DESIGN CONGESTION PRESENT MODIFY THE P-NET OPTIONS PARTIAL TO
COMPLETE.
6. EXTRACT R,C VALUES , ANALYZE THE TIMING.
EXTRACT PARASITIC NET R,C VALUES AND GENERATE A TIMING REPORT.

OPTIMIZE TIMING [DEFAULT]-->IF THE TIMING IS NOT ACCEPTED REPEAT

GLOBAL ROUTING, ANALYZE CONGESTION , TIMING IF NOT ACCEPTED.

PERFORM OPTIMIZE TIMING[HIGH EFFORT]---->OPTIMIZE HIGH EFFORT.

IF THE TIMING IS NOT ACCEPTED , MODIFY THE FLOOR PLAN /RESYNTHESIZE.

 AFTER ACCEPTING THE CONGESTION, TIMING THEN WRITE OUT THE .def file

SAVE THE DESIGN .AND THESE .def FILE IS GIVEN AS INPUT TO THE PLACEMENT.

PLACEMENT
IN PLACEMENT STEPS ARE
1. PLACEMENT CHECKS,
2. AHFNS
3. DFT SETUP.
4. POWER SETUP.
5. PLACEMENT OPTIMIZATION.

PLACEMENT :
AFTER GOING TO PLACEMENT WE HAVE TO CHECKS ,FIX

1. FIX MACRO PLACEMENT.(AGAIN)

2. VERIFY THE P-NET, IGNORED ROUTING LAYERS.
3. VERIFY KEEPOUT VARIABLE SETTINGS.
4. SPECIFY NON DEFAULT ROUTING RULES.
5. CHECK PLACEMENT READINESS.
-->FIX MACRO PLACEMENT AGAIN, BECAUSE AFTER INSERTING THE DESIGN IF MACROS
ARE MOVED THE CHECK.

-->P-NET, IGNORED ROUTING LAYERS ALSO.

-->MAINTAIN KEEPOUT VARIABLE SETTINGS FURTHER STEPS ALSO

-->NON DEFAULT RULES ARE SPECIAL RULES. LIKE DOUBLE SPACING, DOUBLE
WIDTHING. THESE ARE APPLIED FOR CLOCK WIRES. BECAUSE THOSE HIGH ACTIVITY
NETS.

-->BUT HERE WE ARE ONLY SPECIFYING NON DEFAULT ROUTING RULES[NDR'S].

--->SPACIFYING NDR'S BECAUSE AVOIDING CONGESTION AND TIMIMG PROBLEMS AT

THE STAGE OF CLOCK TREE SYNTHESIS

-->CHECK PLACEMENT READINESS IN WE ARE CHECK

1. FLOOR PLAN ,
2. NETLIST,
3. NARROW PLACEMENT REGIONS,
4. R,C FOR ROTING LAYERS,
5. DESIGN CONSTRAINTS.
 AHFNS (AUTOMATIC HIGH FANOUT NET SYNTHESIS):

 HFNS FOR RESET AND SCAN ENABLE AND ETC....

 HFNS ARE SYNTHESIZED IN FRONT END ALSO BUT AT THAT MOMENT NO PLACEMENT
INFO STAND CELLS IS AVIALABLE.
 HENCE BACKEND TOOL COLLAPSE SYNTHESIZED HFNS.
 IT RESYNTHESIS HFNS BASED ON PLACEMENT INFO AND APPROPRIATELY "INSERT
BUFFERS".
 TARGET OF THIS SYNTHESIS IS TO MET DELAY REQUIREMENTS i.e. SETUP AND HOLD.

SCENARIO'S
SCENARIO
SCENARIO = MODE + CORNER.

MODE: MODE IS DEFINED AS A SET OF CLOCKS , SUPPLY VOLTAGES ,TIMING

CONSTRAINTS AND LIBRARIES.

MODES TYPE:

1. FUNCTIONAL MODE.
2. TEST MODE.
IT CONTAINS SDC CONSTRAINTS.
IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.

CONSTRAINTS IN TEST MODE WHILE THE CHIP IS A DEVICES UNDER TEST:

 TESTER CLOCK PERIOD AND CLOCK SOURCES.

 MODEL TESTER SKEW ON THE INPUT PORTS.
 DIFFERENT TIMING EXCEPTIONS.
 DIFFERENT SETUP/HOLD ON THE OUTPUT PORTS.
 THE SCAN CHAIN IS EXCERSIED IN TEST MODE.(NOT IN FUNCTIONAL MODE).
CORNERS:

CORNERS CONTAINS PVT'S.

_____________ BEST CASE CORNER

|
PVT -------------

|
______________WORST CASE CORNER.
 FOR SETUP :

Arrival Path-------- |
|--------------------->Max Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

FOR HOLD :

Arrival Path-------- |
|--------------------->Min Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

BEST CASE : --------->FASTEST<-------->MIN DELAYS<------->Early<-----------> FOR HOLD

 MIN DELAYS IN ARRIVAL PATH,DATA PATH .

 MAX DELAYS IN CLOCK PATH.
PVT: PROCESS---------------------->FAST
VOLTAGE--------------------->HIGH
TEMPERATURE------------>LOW

WORST CASE: --------->SLOWEST<-------->MAX DELAYS<------------> FOR SETUP

 MAX DELAYS IN ARRIVAL PATH, DATA PATH.
 MIN DELAYS IN CLOCK PATH.
PVT: PROCESS-------------------->SLOW
VOLTAGE-------------------->LOW
TEMPERATURE----------->HIGH

PLACEMENT (POWER SET UP)

POWER SETUP:
WE HAVE TWO TYPE OF THE POWER DISSIPATIONS:

1. STATIC POWER DISSIPATION

2. DYNAMIC POWER DISSIPATION
STATIC POWER DISSIPATION:
STATIC POWER DISSIPATION IS, IF THE CELLS ARE PRESENT AT THE "OFF" STATE THEN
DUE TO THE LEAKAGE OF CELLS STATIC POWER DISSIPATION OCCURRS.

THE LEAKAGE IS DUE TO THE JUNCTION LEAKAGE, TUNNELING , SUB THRESHOLD

LEAKAGE.

FOR REDUCING THE STATIC POWER DISSIPATION REPLACING THE LVT CELLS WITH HVT
CELLS.

HVT CELLS ARE SLOWER,AND LOW LEAKAGE ,HIGH Vt .

LVT CELLS ARE FASTER ,AND HIGH LEAKAGE,LOW Vt.

REPLACING THE LVT CELLS WITH HVT CELLS.

LVT CELLS ARE USED AT CRITICAL PATHS.

IN THE MOST OF THE ARCHITECTURES WE WILL USE THE POWER GATING FOR
REDUSING THE STATIC POWER DISSIPATION.

DYNAMIC POWER DISSIPATION:

DYNAMIC POWER DISSIPATION IS DUE TO THE SHORT CIRCUIT , INTERNAL LOAD,HIGH
SWITCHING.

FOR REDUCING THE DYNAMIC POWER DISSIPATION WE HAVE LOT OF TECHNIQUES

THOSE ARE :

REDUCING THE HIGH TOGGLE RATE NET NET LENGTHS. THESE TOGGLE RATE IS
GETTING FROM SWITCHING FILE(.SAIF ) THIS IS GETTING FROM SIMULATION PEOPLE.
AND FOR AVOIDING THIS WHICH CELLS HAVING HIGH TOGGLE RATE NET LENTHS
CONNECTED NEARER TO CONNECTED CELLS.

ANOTHER TECHNIQUE IS ADDING THE BUFFER IN BETWEEN THE HIGH NET LENGTH
NETS. FOR REDUCING THE HIGH COUPLING CAPACITANCE.(REDUCE THE LOAD
CAPACITANCE)

ANOTHER TECHNIQUE IS CONNECT HIGH COUPLING CAPACITANCE NET TO THE LOW

CAPACITANCE PIN OF THE CELL.(SWAPPING THE PIN).

ANOTHER TECHNIQUE IS CLONING , IT IS CREATING THE SAME CELL AND CONNECT THE
SOME OF THE OUTPUT NET TO THESE.(SHARING THE LOAD)

AND ANOTHER TECHNIQUE IS CELL SIZING.

ANOTHER TECHNIQUE IS GATE LEVEL LOGIC OPTIMIZATION.

MOSTLY IN DESIGN WE WILL USE THE CLOCK GATING TO REDUSING THE DYNAMIC
POWER DISSIPATION

PLACEMENT OPTIMIIZATION
PLACEMENT OPTIMIZATION:
PLACEMENT OPTIMIZATION WITH WE HAVE OPTIONS (i)CONGESTION,(ii)AREA RECOVERY
,(iii)POWER,(iv)DFT,(v)TIMING.

BY USING THE CONGESTION OPTION WE CAN REDUCE THE CONGESTION.

BY USING THE POWER OPTION WE CAN REDUCE THE STATIC POWER

DISSIPATION,DYNAMIC POWER DISSIPATION.

BY USING THE AREA RECOVERY OPTION WE CAN REDUCE THE CELLS , POWER, TIMING.

BY USING THE DFT OPTION WE CAN REDUCE THE ROUTING RESOURECES BY REORDER
THE SCAN CHAINS.

AND IF TIMING IS CRITICAL LOGICAL TIMING DRIVEN PLACEMENT.

AND CONGESTION IS CRITICAL CONGESTION DRIVEN PLACEMNT.

CTS (CLOCK TREE SYNTHESIS)

CLOCK TREE SYNTHESIS :
----->CTS IS THE CONNECT THE CLOCKS TO THE ALL CLOCK PIN OF SEQUENTIAL
CIRCUITS.

------->ALL CLOCK PINS ARE DRIVEN BY A SINGLE CLOCK SOURCE.

------->CTS TARGETS :(i)skew ,

(ii)insertion delay
-------->CTS GOALS :(i)max transition,
(ii)max capacitance,
(iii)max fanout,
(iv)max buffer levels.

------->A BUFFER TREES IS BUILT TO BALANCE THE LOADS AND MINIMIZE THE SKEW.

-------->A CLOCK TREE WITH BUFFER LEVELS BETWEEN THE CLOCK SOURCE AND CLOCK
SINKS(END POINTS).

-------->CTS STARTING POINT IS CLOCK SOURCE (SDC DEFINED CREATE_CLOCK)

-------->CTS END POINTS ARE CLOCK PINS OF SEQUENTIAL CELLS.

CTS (START POINTS AND END POINTS)

IN DESIGN WE HAVING

STATIC TIMING ANALYSIS

STATIC TIMING ANALYSIS DO NOT DEPEND ON INPUTS AND WEATHER IT IS PRESENT IN
ON STATE (OR) OF STATE,SWITCHING.

STATIC TIMING ANALYSIS IS PURELY DEPEND ON THE DELAYS.

SETUP TIME :THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE BEFORE
ARRIVAL OF SENSITIVE CLOCK.

HOLD TIME :THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE AFTER
ARRIVAL OF SENSITIVE CLOCK.

SETUP CHECK:THE DATA LAUNCHED AT SENSITIVE EDGE OF THE LAUNCH FLOP SHOULD
BE CAPTURED AT NEXT SENSITIVE EDGE OF THE CAPTURED FLOP.

BELOW IS THE SETUP CHECK EQ :

Tcq + Tcomb < Tclk-Tsu

HOLD CHECK:THE DATA LAUNCHED AT SENSITIVE EDGE OF THE LAUNCH FLOP
SHOULD NOT BE CAPTURED AT THE SAME SENSITIVE EDGE OF THE CAPTURED FLOP.

BELOW IS THE HOLD CHECK EQ :

Tcq + Tcomb > Thold

 IN THE BASING TIMING DIAGRAM
START POINTS ARE (i)INPUT PORT
(ii)CLOCK PIN OF LAUNCH FLOP.

END POINTS ARE (i)DATA INPUT PIN OF CAPTURE FLOP.

(ii)OUTPUT PORT.

BY THE COMBINATION OF THE THESE START AND END POINTS WE HAVE THE PATHS LIKE
ARE

1. INPUT PORT TO DATA INPUT PIN OF LAUNCH FLOP

2. CLOCK PIN OF THE LAUNCH FLOP TO DATA INPUT PIN OF CAPTURE FLOP
3. INPUT PORT TO OUTPUT PORT
4. CLOCK PIN OF THE LAUNCH FLOP TO OUTPUT PORT.

BY DEPENDING ON THE START POINTS AND END POINTS WE HAVE FOUR TIMING GROUPS
PRESENT.

1. INPUT GROUP
2. REGISTER GROUP
3. FEED THROUGH GROUP.
4. OUTPUT GROUP.

THIS IS BASIC TIMING DIAGRAM

 REGISTER GROUP:
 START POINT IS CLOCK PIN OF LAUNCH FLOP.
 END POINT IS DATA INPUT PIN OF CAPTURE FLOP
SETUP CHECK EQUATION IS :

Tcq + Tcomb < Tclk-Tsu

HOLD CHECK EQUATION IS :

Tcq + Tcomb > Thold

INPUT GROUP:
 START POINT IS INPUT PORT.
 END POINT IS DATA INPUT PIN OF CAPTURE FLOP.
SETUP CHECK EQUATION IS :

Tinputdelay + Tcomb < Tclk -Tsu

HOLD CHECK EQUATION :

Tinputdelay + Tcomb > Thold

OUTPUT GROUP:
 START POINT IS CLOCK PIN OF LAUNCH FLOP.
 END POINT IS OUTPUT PORT.
SETUP CHECK EQUATION IS :

Tcq + Toutputdelay < Tcq.

HOLD CHECK EQUATION IS :

Tcq + Toutputdelay > Thold.

FEED THROUGH GROUP:

 START POINT IS INPUT PORT .

 END POINT IS OUTPUT GROUP.

SETUP CHECK EQUATION IS :
 Tinputdelay + Toutputdelay < Tcq
HOLD CHECK EQUATION IS :

Tinputdelay + Toutputdelay > Thold

UNCERTAINITY:

UNCERTAINTY = SKEW + ZITTER + MARGIN

ZITTER: IT IS THE VARIATIONS IN THE CLOCK CYCLE AT THE CLOCK EDGES

BEFORE (OR) AFTER

SKEW:
SKEW IS THE DIFFERENCE IN THE ARRIVALS TIMES AT THE END POINTS OF THE CLOCK
TREE.

Tl + Tcq + Tcomb < Tclk - Tsu + Tc

Tcq + Tcomb < Tclk - Tsu + (Tc - Tl)

Tcq + Tcomb < Tclk - Tsu + Tskew

Tcq + Tcomb < Tclk - Tsu + SKEW

SKEW = Tc - Tl = Tskew

SKEW TYPES:

1. POSITIVE SKEW
2. NEGATIVE SKEW
POSITIVE SKEW:
Tcq + Tcomb < Tclk - Tsu + (Tc - Tl)
Tcq + Tcomb < Tclk - Tsu + Tskew
Tcq + Tcomb < Tclk - Tsu + SKEW
WHEN (Tc > Tl) IT IS POSITIVE SKEW

IT IS USEFUL FOR SETUP TIME

IT IS BAD FOR HOLD TIME.

NEGATIVE SKEW:
Tcq + Tcomb < Tclk - Tsu + (Tc - Tl)
Tcq + Tcomb < Tclk - Tsu - Tskew
Tcq + Tcomb < Tclk - Tsu - SKEW
WHEN (Tc < Tl) IT IS NEGATIVE SKEW.

IT IS USEFUL FOR HOLD TIME.

IT IS BAD FOR SETUP TIME.
 CALCULATION OF SLACK:
IT IS THE MAIN IMPORTANT FOR THE TIMING ANALYSIS

THERE ARE MAINLY TWO TIMES ARE PRESENT

1. ARRIVAL TIME
2. REQUIRED TIME
SETUP----------->SLACK = REQUIRED TIME - ARRIVAL TIME
 HOLD----------->SLACK = ARRIVAL TIME - REQUIRED TIME

POSITIVE SLACK IS GOOD FOR DESIGN

NEGATIVE SLACK IS BAD FOR DESIGN

IF IN THE DESIGN WE HAVE NEGATIVE SLACK THEN WE HAVING TIMING VIOLATIONS IN

THE DESIGN.

LATENCY'S:
IT IS DELAY DIFFERENCE FROM THE CLOCK GENERATION POINT TO THE CLOCK END
POINTS.

THERE ARE TWO TYPES OF LATENCY'S PRESENT:

1. SOURCE LATENCY
2. NETWORK LATENCY
SOURCE LATENCY :IT IS THE DELAY DIFFERENCE FROM THE CLOCK GENERATION POINT
TO THE CLOCK DEFINITION POINTS.

NETWORK LATENCY:IT IS THE DELAY DIFFERENCE FROM THE CLOCK DEFINITION

POINTS TO THE CLOCK END POINTS.
 CTS (APPLYIN NDRS ON CLOCK NETS)
NDR'S:
NDR'S ARE NOTHING BUT NON DEFAULT ROUTING .

THESE ARE APPLIED ON THE CLOCK NETS .

CLOCK NETS ARE LESS SENSITIVE TO CROSSTALK AND ELECTROMIGRATION.

CLOCK NETS ARE HIGH SWITCHING ACTIVITY NETS.

 NDR RULES ARE (i)DOUBLE WIDTH,
(ii)DOUBLE SPACING.
(iii)SHEILDING

BY APPLYING DOUBLE WIDTH WE CAN AVOID THE ELECTROMIGRATION EFFECT.

BY APPLYING DOUBLE SPACING WE CAN AVOID CROSS TALK EFFECT.

BY DEFAULT, NON DEFAULT ROUTING RULE APPLIES ON ALL LEVELS CLOCK TREE. BUT
USING NDR RULES AT THE CLOCK SINK PIN POINTS IS BETTER TO AVOID.
HELPS TO AVOID CONGESTION AT LOWER METAL LAYERS
IMPROVES PIN ACCESSIBILITY OF STD CELLS

----------->ALWAYS ROUTE CLOCK ON METAL 3 AND ABOVE

----------->AVOID NDR ON CLOCK SINKS

----------->AVOID NDR ON METAL 1.

---- -MAY HAVE TROUBLE ACCESSINING METAL 1 PINS ON BUFFERS AND
GATES
-----CONSIDER DOUBLE WIDTH TO REDUCE RESISTANCE.

SCENARIO'S
SCENARIO
SCENARIO = MODE + CORNER.

MODE: MODE IS DEFINED AS A SET OF CLOCKS , SUPPLY VOLTAGES ,TIMING

CONSTRAINTS AND LIBRARIES.

MODES TYPE:

1. FUNCTIONAL MODE.
2. TEST MODE.
IT CONTAINS SDC CONSTRAINTS.
IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.

CONSTRAINTS IN TEST MODE WHILE THE CHIP IS A DEVICES UNDER TEST:

 TESTER CLOCK PERIOD AND CLOCK SOURCES.

 MODEL TESTER SKEW ON THE INPUT PORTS.
 DIFFERENT TIMING EXCEPTIONS.
 DIFFERENT SETUP/HOLD ON THE OUTPUT PORTS.
 THE SCAN CHAIN IS EXCERSIED IN TEST MODE.(NOT IN FUNCTIONAL MODE).
CORNERS:

CORNERS CONTAINS PVT'S.

_____________ BEST CASE CORNER

|
PVT -------------

|
______________WORST CASE CORNER.

FOR SETUP :

Arrival Path-------- |
|--------------------->Max Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

FOR HOLD :

Arrival Path-------- |
|--------------------->Min Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

BEST CASE : --------->FASTEST<-------->MIN DELAYS<------->Early<-----------> FOR HOLD

 MIN DELAYS IN ARRIVAL PATH,DATA PATH .

 MAX DELAYS IN CLOCK PATH.
PVT: PROCESS---------------------->FAST
VOLTAGE--------------------->HIGH
TEMPERATURE------------>LOW

WORST CASE: --------->SLOWEST<-------->MAX DELAYS<------------> FOR SETUP

 MAX DELAYS IN ARRIVAL PATH, DATA PATH.
 MIN DELAYS IN CLOCK PATH.
PVT: PROCESS-------------------->SLOW
VOLTAGE-------------------->LOW
TEMPERATURE----------->HIGH
 ROUTING

ROUTING:
---->CREATE PHYSICAL CONNECTIONS TO ALL DATA SIGNAL PINS,CLOCK PINS
THROUGH METAL INTERCONNECTIONS.

---->PATHS MUST MET TIMINGS.

IN THE ROUTING MAINLY THREE STAGES ARE PRESENT:

(i)GLOBAL ROUTING

(ii)TRACK ASSIGNMENT

(iii)DETAIL ROUTING

EXTRA ONE

(iv)SEARCH AND REPAIR

SCENARIO'S
SCENARIO
SCENARIO = MODE + CORNER.

MODE: MODE IS DEFINED AS A SET OF CLOCKS , SUPPLY VOLTAGES ,TIMING

CONSTRAINTS AND LIBRARIES.

MODES TYPE:

1. FUNCTIONAL MODE.
2. TEST MODE.
IT CONTAINS SDC CONSTRAINTS.
IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.

CONSTRAINTS IN TEST MODE WHILE THE CHIP IS A DEVICES UNDER TEST:

 TESTER CLOCK PERIOD AND CLOCK SOURCES.

 MODEL TESTER SKEW ON THE INPUT PORTS.
 DIFFERENT TIMING EXCEPTIONS.
 DIFFERENT SETUP/HOLD ON THE OUTPUT PORTS.
 THE SCAN CHAIN IS EXCERSIED IN TEST MODE.(NOT IN FUNCTIONAL MODE).
CORNERS:

CORNERS CONTAINS PVT'S.

_____________ BEST CASE CORNER

|
PVT -------------

|
______________WORST CASE CORNER.

FOR SETUP :

Arrival Path-------- |
|--------------------->Max Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

FOR HOLD :

Arrival Path-------- |
|--------------------->Min Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

BEST CASE : --------->FASTEST<-------->MIN DELAYS<------->Early<-----------> FOR HOLD

 MIN DELAYS IN ARRIVAL PATH,DATA PATH .

 MAX DELAYS IN CLOCK PATH.
PVT: PROCESS---------------------->FAST
VOLTAGE--------------------->HIGH
TEMPERATURE------------>LOW

WORST CASE: --------->SLOWEST<-------->MAX DELAYS<------------> FOR SETUP

 MAX DELAYS IN ARRIVAL PATH, DATA PATH.
 MIN DELAYS IN CLOCK PATH.
PVT: PROCESS-------------------->SLOW
VOLTAGE-------------------->LOW
TEMPERATURE----------->HIGH
 ROUTING (TRACK ASSIGNMENT)

TRACK ASSIGNMENTS :
---->ASSIGNS EACH NET TO THE SPACIFIC TRACKS.

---->NETS ARE LAYDOWN THE METAL TRACES.

----->TRACES=METAL CONNECTIVITY..

ROUTING (DETAIL ROUTING)

DETAIL ROUTING:
---->DETAIL ROUTE DONES ACTUAL ROUTING.

----->MEANS ACTUAL ROUTING METAL CONNECTIONS.

----->CHECK ALSO PHYSICAL DRC'S.

----->DETAIL ROUTING DOES NOT WORK ON THE ENTIRE CHIP AT THE SAME TIME LIKE
TRACK ASSIGNMENT.

------>INSTEAD IT WORKS BE REROUTING WITHIN THE CONFINES OF A SMALL AREA

CALLED AN "SBOX".

SBOX : DIVIDE THE BLOCK INTO MINI BOXES THESE ARE USED FOR THE DETAIL ROUTE.

ROUTING (SEARCH AND REPAIR)

SEARCH AND REPAIR :

---->SEARCH AND REPAIR FIXES REMAINING DRC VIOLATIONS THROUGH MULTIPLE
LOOPS USING PROGRESSIVLY LARGE SBOX.

ECO (ENGINEERING CHANGE ORDER)

ECO:
 ECO'S ARE TWO TYPE :1)TIMING ECO'S(TO IMPROVE TIMING)
2)FUNCTIONAL ECO'S(TO ADD FUNCTIONALITY)

TIMING ECO FUNCTIONAL ECO

| |
----------------------------- ---------------------------
| | | |
FREEZE NON-FREEZE FREEZE NON-FREEZE

--------->IT IS THE LATE CHANGE IN THE FLOW.

---------->AFTER ROUTING IF WE WANT ANY CHANGES OR ADDING NEW CELLS , THESE

ALL ARE DONE AT THE ECO STAGE.

HERE TWO TYPE OF ECO'S PRESENT :

(i)FREEZE SILICON ECO

(ii)NON FREEZE SILICON ECO

--------->IN FREEZE SILICON ECO WE HAVE NO CHANCE OF ADDING CELL, HERE SPARE
CELLS ARE USED FOR THESE.

----------->IN NON FREEZE SILICON ECO WE CAN ADD THE CELLS AFTER ROUTING.

Spare cells are just that.They are extra cells placed in your layout in anticipation of a future ECO.When I
say future, I mean after you taped out and got your silicon back.After silicon tests complete, it might
become necessary to have some changes to the design.There might be a bug, or a very easy feature that
will make the chip more valuable.This is where you try to use the existing “spare” cells in your design to
incorporate the design change.For example, if you need a logic change that requires addition of an AND
cell, you can use an existing spare AND to make this change.

CHIP FINISHING

CHIP FINISHING:
IN THE CHIP FINISHING:
WE NEED TO DO:

1. ANTENA FIXING:AS TOTAL AREA OF WIRE INCREASE DURING PROCESSING,THE

VOLTAGE STRESSING THE GATE OXIDE INCREASE IT MAY DAMAGE OXIDE LAYER.
2. RANDOM PARTICAL DEFECTS:RANDOM PARTICAL EFFECT IS (i)WIRES AT MINIMUM
SPACING ARE MOST SUSCEPTABLE TO SHORTS.(ii)WIRES AT MAXIMUM WIDTH ARE
MOST SUSCEPTABLE TO OPENS.
3. REDUNDANT VIA INSERTION:VOID IN VIAS IS A SERIOUS ISSUE IN MANUFACTURING.
4. FILLER CELL INSERTION:SOME PLACEMENT SITES REMAIN EMPTY ON SOME ROWS.
5. METAL FILL INSERTION:METAL OVER ETCHING.
6. METAL SLOTTING :METAL EROSION,METAL LIFT OFF.
ANTENA FIXING TECHNIQUES
(THESE ARE FIX AT THE TIME OF THE SEARCH AND REPAIR)
 SPLITTING METAL(LAYER JUMPING).
 ADDING DIODE IN REVERSE BIAS MANNER.
RANDOM PARTICAL DEFECT FIXING TECHNIQUES
 SPREADING (OR) JOG(PUSH ROUTES OFF-TRACKS BY 1/2 PITCH)-------->REDUCE SHORTS
 WIDENING(INCREASE THE WIRE WIDTH)------------>THIS MAY REDUCE OPENS.
REDUNDANT VIA INSERTION
 REDUNDANT VIA IS THE TECHNIQUE FOR REDUCING VOIDS IN THE METAL LAYER.
FILLER CELL INSERTION
 FILLER CELL INSERTION IS THE ONE OF THE TECHNIQUE FOR UTILIZING THE TOTAL
AREA WITH OUT GAPS .
 IT IS GOOD TECHNIQUE BECAUSE IN THE FUTURE WE CAN REPLACE FILLER CELLS WITH
SPARE CELLS WITH A LOGIC.
METAL FILL INSERTION
 AT THE TIME OF ETCHING THEY USE SOME TYPE OF CHEMICALS DUE TO THAT
CHEMICALS METAL LOSSES MORE FOR THAT ONE WE ARE INSERTING THE METAL FILLS.
METAL SLOTTING
 METAL SLOTTING IS TECHNIQUE FOR AVOIDING THE PROBLEMS LIKE METAL LIFT OFF ,
METAL EROSION.

FINAL VERIFICATION GDS FILE EXPORT

FINAL VERIFICATION:
1. PARASITICS EXTRACTION:IT EXTRACT R,C VALUES FOR GETTING ORIGINAL DELAYS.
TOOL:STAR RC XT LICENCE
2. TIMING VERIFICATION:IT IS FIND BY USING PRIME TIME TOOL.
3. LVS ,ERC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.
4. DRC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.

AFTER VERIFICATION:
1. AFTER THIS WE RELEASE THE GDS FILE
2. IN THIS WE HAVE ALL POLYGONS INFORMATION IS PRESENT.

AFTER GDS
AFTER THIS WE ARE FINALLY BASE TAPE OUT(BTO).

AFTER BASE TAPE OUT WE WILL DO METAL TAPE OUT(MTO).

 CALCULATIONS:
POWER CALCULATIONS:
----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF CHIP=(TOTAL
CORE POWER)/{(NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM ALLOWABLE CURRENT
FOR A I/O PAD)} .

----->CORE RING WIDTH:

CORE CURRENT(mA)=(CORE POWER)/(CORE VOLTAGE )

CORE P/G RING WIDTH =(TOTAL CORE CURRENT)/{(N0.OF.SIDES)*(MAXIMUM CURRENT

DENSITY OF THE METAL LAYER USED FOR PG RING)}

------->MAXIMUM CURRENT DENSITY Rj mA.

-------->SHEET RESISTANCE :Rs OHMS/SQUARE.

-------->TOTAL CURRENT =TOTAL POWER CONSUMPTION OF CHIP(P)/VOLTAGE(V).

-------->NO.OF POWER PADS(Npads)=Itotal/Ip

------->Itotal =TOTAL CURRENT

------->Ip OBTAINED FROM IO LIBRARY SPACIFICATION.

-------->NO.OF POWER PINS = Itotal/Ip

-------->MAXIMUM CURRENT SPACIFICATION OF EACH METAL LAYER FROM LIBRARY(Rj).

---------->TOTAL METAL WIDTH REQUIRED ON LAYER1=LAYER2=

Wtotalstrap = Itotal/(2*Rj)

----------->ASSUMING SPACINGS BETWEEN STRAPS=Lspace

L<(Vmax)/(Rj*Rs)

Vmax = MAX ALLOWABLE IR DROP

Rj=MAX CURRENT DENSITY
Rs=SHEET RESISTANCE

---------->TOTAL CORE AREA=Wcore*Hcore

H=HEIGHT
W=WIDTH

----------->NUMBER OF VERTICAL STRAPS=Nv=Wcore/L

----------->NUMBER OF HORIZONTAL STRAPS=NH=Hcore/(2*L)

------------> MIN STRAP WIDTH REQUIRED=Wring/(Nv*Nh)

IR DROP:
------>AVG CURRENT THROUGH EACH STRAP=IstrapAvg=(Itotal)/(2*Nstraps)mA

-------->APPROPRIATE IR DROP AT THE CENTER OF THE STRAP=Vdrop or IRdrop

=IstrapAvg*Rs*(W/2)*(1/Wstrap)

--------->NUMBER OF STRAPS BETWEEN TWO POWER PADS

Nstrappinspace = Dpadspacing/Lspace.

---------->MIN RING WIDTH = Wring = Ip/Rj microm

POWER
-------->TOTAL POWER=STATIC POWER+DYNAMIC POWER
=LEAKAGE POWER+[INTERNAL POWER+EXT SWITCHING POWER]
=LEAKAGE POWER+[{SHORT CIRCUIT POWER + POWER+INT POWER}]+EXT
SWITCHING POWER]
=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]

Isc=SHORT CIRCUIT POWER

C=LOAD CAP
S=SWITCHING ACTIVITY FACTOR.

-----CORE RING WIDTH:

CORE CURRENT=(CORE POWER)/(CORE VOLTAGE).

CORE P/G RING WIDTH=(TOTAL CURRENT)/(NO OF SIDES *MAXIMUM CURRENT DENSITY

OF THE METAL LAYER USED FOR P/G PAD RING)

DIFFERENT FILES IN PHYSICAL DESIGN

 FILES:

1. LOGICAL LIBRARIES---------------------------> .lib, .db

2. PHYSICAL LIBRARIES ------------------------->.lef, .milkyway (OR) .volcano (OR), .plib(OR).enc
3. TECHNOLOGY FILE ----------------------------> .tf
4. TLU+ -------------------------------------------------->.tlup
5. INTER CONNECT TECHNOLOGY FILE ------> .itf
6. MAPPING FILE ------------------------------------> .map
7. NETLIST ---------------------------------------------> .v,(OR) .ddc ,(OR) .db, (OR) .EDIF
8. SDC-----------------------------------------------------> .sdc
9. PHYSICAL ONLY PAD CELLS PLACEMENT FILE ---------------------> .tdf
10. SCAN CHAIN FILE -------------------------------> .scandef
11. TOGGLE RATE FILE------------------------------>.saif, (OR) .vcd
12. ECO FILE ----------------------------------------->.eco
13. GDS FILE------------------------------------------>.gds
14. LOG FILE------------------------------------------>.log
15. REPORT FILE-------------------------------------->.rep
16. DESIGN EXCHANGE FORMAT------------------>.def
17. STANDARD DELAY FORMAT------------------->.sdf
18. STANDARD PARASITIC EXCHANGE FORMAT---------> .spef

DIFFERENT TYPE OF CELLS

DIFFERENT TYPE OF CELLS:

 STDCELLS:
 Nothing But Base cells(Gates,flops).

 TAP CELLS:
 Avoids Latch up Problem(Placing these cells with a particular distance).
 Cells are physical-only cells that have power and ground pins and dont have signal pins.
 Tap cells are well-tied cells that bias the silicon infrastructure of n-wells or p-wells.
 They are traditionally used so that Vdd or Gnd are connected to substrate or n-well
respectively.
 This is to Help TIE Vdd and Gnd which results in lesser drift and prevention from latchup.
 Required by some technology libraries to limit resistance between Power or Ground
connections to well of the substrate.

 TIE CELLS :
 It is used for preventing Damage of cells; Tie High cell(Gate One input is connected to Vdd,
another input is connected to signal net);Tie low cells Gate one input is connected to Vss,
another input is connected to signal .
 Tie - high and Tie - low cells are used to connect the gate of the transistor to either Power and
Ground.
 In lower technology nodes, if the gate is connected to Power or Ground. The transistor might
be turned "ON/OFF" due to Power or Ground Bounce.
 These cells are part of the std cell library.
 The cells which require Vdd(Typically constant signals tied to 1) conncet to tie high cells.
 The cells which require Vss/Vdd (Typically constant signals tied to 0) connect to tie low cells.

 END CAP CELLS:

 To Know the end of the row,and At the edges endcap cells are placed to avoid the cells
damages at the end of the row to avoid wrong laser wavelength for correct manufacturing.
 You can add Endcap cells at both Ends of a cell row.
 Endcap cells surrounding the core area features which serve as second poly to cells
 placed at the edge of row.
 The library cells do not have cell connectivity as they are only connected to Power and
Ground rail,
 Thus ensure that gaps do not occure between "WELL" and "IMPLANT LAYER" and to prevent
the DRC violations by satisfying "WELL TIE - OFF" requirements for core rows we use End
cap cells.
 Usually adding the "Well Extension" for DRC correct designs.
 End caps are a "POLY EXTENSION" to avoid drain source SHORT

 DECAP CELLS:
 Charge Sharing;To avoid the Dynamic IR drop ,charge stores in the cells and release the
charge to Nets.
 Decoupling capacitor cells , or Decap cells, are cells that have a capacitor placed.
 Between the Power rail and Ground rail to Over come Dynamic voltage drop.
 Dynamic IR Drop happens at the active edge of the clock at which a High currents is drawn
from the Power Grid for a small Duration.
 If the Power is far from a flop the chances are there that flop can go into Metastable State.
 To overcome decaps are added , when current requirements is High this Decaps discharges
and provide boost to the power grid.

 FILLER CELLS:
 Filler cells are used to connect the gaps between the cells after placement.
 Filler cells are ussed to establish thecontinuity of the N-Wells and the IMPLANT LAYERS on
the standard cells rows, some of the cells also don't have the Bulk Connection (Substrate
connection) Because of their small size (thin cells).
 In those cases, the abutment of cells through inserting filler cells can connect those
substrates of small cells to the Power/Ground nets.
 i.e. those tin cells can use the Bulk connection of the other cells(this is one of the reason why
you get stand alone LVS check failed on some cells)

 ICG CELLS:
 Clock gating cells ,to avoid Dynamic power Dissipation.
 Register banks disabled during some clock cycles.
 During idle modes, the clocks can be gated-offs to save Dynamic power dissipation on
flipflops.
 Proper circuit is essential to achive a gated clock state to prevent false glithes on the clock
paths

 POWER GATING CELLS:

 In Power gating to avoid static power Dissipation.
 Power Gating Cells:
 Power switches
 Level Shifters
 Retention registers
 Isolation cells
 Power controler

 PAD CELLS:
 To Interface with outside Devices;Input to of Power,Clock,Pins are connected to pad cells
and outside also.

 CORNER CELLS:
 Corner Pads are used for Well Continity.
 To lift the chip.

 MACRO CELLS:
 Memories.
 The memory cells are called Macros.
 To store information using sequntial elements takes up lot of area.
 A single flipflop could take up 15 to 20 transistors to store one bit store the data efficiently
and also do not occupy much space on the chip comparatively by using macros.

 SPARE CELLS:
 Used at the ECO.
 Spare cells are standard cells in a design that are not used by the netlist.
 Placing the spare cells in your design provides a margin for correcting logical error that
might be detected later in the design flow, or for adjusting the speed of your design.
 Spare cells are used by the fix ECO command during ECO process.

 PAD FILLER CELLS:

 Used for Well Continity, Placed in between Pads.

 JTAG CELLS:
 These are used to check the IO connectivity.
 FIXING DRC'S
DRC'S FIXING
DRC'S ARE DIFFERENT TYPES :
1. LOGICAL DRC'S.
2. PHYSICAL DRC'S.
LOGICAL DRC'S:
1. MAX TRANSITION
2. MAX CAPACITANCE
3. MAX FANOUT
MAX TRANSITION:
FIXING TECHNIQUES:
 ADD A BUFFER IN MIDDLE OF THE LONG LENGTH WIRE.
 REDUCE THE WIRE LENGTH.
 ADDING A CHAIN OF BUFFERS.
MAX CAPACITANCE:
FIXING TECHNIQUES:
 DECREASE WIRE LENGTH AT OUTPUT SIDE.
MAX FANOUT:
FIXING TECHNIQUES:

 CLONNING=ADDING A SAME CELL LOAD WILL BE DIVIDED.

 SHARING THE LOAD

PHYSICAL DRC'S:
1. WIRE TO WIRE SPACING(MIN SPACING)
2. MIN WIDTH OF WIRES
3. VIA TO VIA SPACINGS
4. NOTCH AVOIDING
FIXING TECHNIQUES:
 SEARCH AND REPAIR

FIXING CROSSTALK
CROSS TALK:
THE VOLTAGE TRANSFER FROM HIGHLY SWITCHING NET(AGGRESSOR NET) TO
ANOTHER NET (LOW SWITCHING (OR) HIGH SWITCHING (OR) VICTIM NET (OR) CONSTANT
NET ) THROUGH COUPLING CAPACITANCE THESE MAY CAUSE CROSS TALK .

REDUCING TECHNIQUES:
 VICTIM NET WIDTH INCREASING THEN RESISTANCE DECREASE IT IS USED AT ROUTING
ALSO.
 SPACING BETWEEN AGGRESSOR NET AND VICTIM NET INCREASE.
 BUFFERING ON CONSTANT NETS (OR) VICTIM NETS.
 PLACING AN GROUND NETS ON BETWEEN THE AGGRESSOR NET AND VICTIM NET THEN
VOLTAGE DISCHARGE ON GROUND NET THEN NO SIGNAL INTEGRITY PROBLEM.THIS IS
CALLED SHIELDING .
 MAINTAIN STABLE SUPPLY.
 FAST SLEW RATE.
 JOGING(INCRAESE HALF TRACK BY HALF ITCH).
 LAYER JUMPING(JUMP ONE LAYER ABOVE LAYER AND COMES TO SAME LAYER)
 INCREASE DRIVE STRENTH OF CELL
 CELL SIZING(UP SIZING)
 DEEP N-WELL.
 GUARD RING.

FIXING ELECTRO MIGRATION

ELECTRO MIGRATION :

WHEN HIGH CURRENT DENSITY TRANSFERRING THROUGH A LONG WIRE FOR A LONG
TIME DUE TO THIS ELECTRONS MOVED WITH HIGH ACCELARATIONS ,DUE TO THIS
THOSE ARE TRANSFERRING THEIR MOMENTUM TO THE METAL ATOMS.DUE TO THESE
CAN MIGRATE AND MOVE AWAY FROM THE METAL .

THIS CAN CAUSES THE SHORTS AND OPENS.

FIXES

BY AVOIDING THIS PROBLEM DOUBLE THE WIDTH OF NETS.

AVOID THE BIG DRIVERS AND LARGE BUFFERS.

FIXING SETUP AND FIXING HOLD TIME

SETUP TIME: THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE BEFORE
ARRIVAL OF SENSITIVE CLCK.

SETUP CHECK:THE DATA LAUNCHED AT THE SENSITIVE EDGE OF THE LAUNCH FLOP
SHOULD BE CAPTURED AT THE NEXT SENSITIVE EDGE OF THE CAPTURED FLOP.

HOLD TIME: THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE AFTER
ARRIVAL OF SENSITIVE CLOCK.
 HOLD CHECK: THE DATA LAUNCHED AT THE SENSITIVE EDGE OF THE LAUNCH FLOP
SHOULD NOT BE CAPTURE AT THE SAME SENSITIVE EDGE OF CAPTURED FLOP.

SETUP FIXES:

1. BUFFER INSERTION
2. UPSIZING THE DRIVER CELL
3. REDUCE NET LENGTH
4. CELL UP SIZING.
5. DRIVE STRENGTH OF LAUNCH FLOP INCREASE.
6. LOGICAL OPTIMIZATION ON DATA PATH.
7. USEFUL SKEW.
8. PIPELINING.
9. USE SYNC CELLS.
10. NET WIDTH INCREASE.
11. USE LVT CELLS.
12. SPLITTING THE COMBINATIONAL LOGIC.
13. INCREASE CLOCK PERIOD.
14. USING DOUBLE SYNCHRONIZER USING FLIP FLOPS.
15. REDUNDANT VIA.
16. REDUCE THE MORE FANOUT NETS WITHIN THE LOGIC
17. DOUBLE VIA
18. LAYER JUMPING
HOLD FIXES:
1. DELAY BUFFER INSERTION.
2. CELL DOWN SIZING.
3. INCREASE NET LENGTH.
4. USE HVT CELLS.
5. SCAN CHAIN REORDERING.
6. ADJUSTING TIMING PATHS
7. CAN BE FIXED BY ADDING DELAYS ON INPUT PORTS.
8. CLOCK SIZING
9. ONE CAN ADD LOOK UP LATCHES
10. REDUCE CLOCK SKEW
11. CAN BE FIXED BY ADDING DELAYS ON INPUT PPORTS
12. INCREASE NETLENGTH ( JOG)

VERIFICATION'S
PHYSICAL VERIFICATION:
IN PHYSICAL VERIFICATION IT CHECKS:

1. LVS(LAYOUT VERSUS SCHEMATIC)

2. DRC(DESIGN RULE CONSTRAINTS CHECK)
3. ERC(ELECTRICAL RULE CHECK)
LAYOUT VERSUS SCHEMATIC(LVS):

INPUTS ARE (.LVS.V) AND (.GDSII) FILES AND RULE DECK FILES.

COMPARISION TWO ELECTRICAL CIRCUITS EQUIVALENT WITH RESPECT TO THEIR

 "CONNECTIVITY" AND "TOTAL TRANSISTOR COUNT".

COMPARISION BETWEEN (.GDSII) FILE AND EXTRCTED NETLIST (.LVS.V) FILE.

FINALLY BOTH ARE CONVERTED INTO A SPICE LEVEL .

LVS CHECKS ARE:

EXTRACT ERRORS :

 SHORTS
 OPENS
 FLOATING NETS.

COMPARE ERRORS:

 PIN ERRORS
 PARAMETRIC ERRORS
 DEVICE MISMATCH
 NET MISMATCH
 MALFORMED DEVICES
 PORTS MISMATCH

DESIGN RULE CONSTARINTS CHECK(DRC):

INPUT IS .GDSII FILE AND RULE DECK FILE.

CHECKS:

 ACTIVE TO ACTIVE SPACINGS.

 WELL TO WELL SPACINGS.
 MINIMUM CHANNEL LENGTH OF THE TRANSISTOR.
 MINIMMUM METAL WIDTH.
 METAL TO METAL SPACINGS.
 ESD(ELECTRO STATIC DISCHARGE).
 I/O RULES.
 METAL FILL DENSITY.
ELECTRICAL RULE CHECK(ERC):

INPUT IS (.GDSII) FILE .

INVOLVES CHECKING A DESIGN FOR ALL ELECTRICAL CONNECTIONS.

CHECKS ARE:

 WELL AND SUBSTRATE AREAS FOR PROPER CONTACTS AND SPCINGS THERE BY
ENSURING CORRECT POWER CONTACTS AND GROUND CONNECTIONS.
 TO LOCATE FLOATING DEVICES AND FLOATING WELLS.
 TO LOCATE DEVICE WICH ARE SHORTED.
 TO LOCATE DEVICES WITH MISSING CONNECTIONS.
 GATE CONNECTRD DIRECTLY TO SUPPLIES.
 FLOATING INPUTS.
 FORMAL VERIFICATIONS:
IN FORMAL VERIFICATION CHECKS ARE LEC(LOGICAL EQUIVALENCE CHECK).

CHECKING BETWEEN FINALLY EXTRCCTED NETLIST(.V) AND SYNTHESIZED NETLIST(.V).

INPUTS ARE EXTRCCTED NETLIST(.V) AND SYNTHESIZED NETLIST(.V).

HERE CHECKING FOR FUNCTIONALITY CORRECTNESS.

SCENARIO'S
SCENARIO
SCENARIO = MODE + CORNER.

MODE: MODE IS DEFINED AS A SET OF CLOCKS , SUPPLY VOLTAGES ,TIMING

CONSTRAINTS AND LIBRARIES.

MODES TYPE:

1. FUNCTIONAL MODE.
2. TEST MODE.
IT CONTAINS SDC CONSTRAINTS.
IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.

CONSTRAINTS IN TEST MODE WHILE THE CHIP IS A DEVICES UNDER TEST:

 TESTER CLOCK PERIOD AND CLOCK SOURCES.

 MODEL TESTER SKEW ON THE INPUT PORTS.
 DIFFERENT TIMING EXCEPTIONS.
 DIFFERENT SETUP/HOLD ON THE OUTPUT PORTS.
 THE SCAN CHAIN IS EXCERSIED IN TEST MODE.(NOT IN FUNCTIONAL MODE).
CORNERS:

CORNERS CONTAINS PVT'S.

_____________ BEST CASE CORNER

|
PVT -------------

|
______________WORST CASE CORNER.

FOR SETUP :
 Arrival Path-------- |
|--------------------->Max Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

FOR HOLD :

Arrival Path-------- |
|--------------------->Min Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

BEST CASE : --------->FASTEST<-------->MIN DELAYS<------->Early<-----------> FOR HOLD

k

 MIN DELAYS IN ARRIVAL PATH,DATA PATH .

 MAX DELAYS IN CLOCK PATH.
PVT: PROCESS---------------------->FAST
VOLTAGE--------------------->HIGH
TEMPERATURE------------>LOW

WORST CASE: --------->SLOWEST<-------->MAX DELAYS<------------> FOR SETUP

 MAX DELAYS IN ARRIVAL PATH, DATA PATH.
 MIN DELAYS IN CLOCK PATH.
PVT: PROCESS-------------------->SLOW
VOLTAGE-------------------->LOW
TEMPERATURE----------->HIGH

OPTIMIZATION CONTROLS
Design Optimization Controls :

1. Enable multiple clocks per register

2. Enable constant propagation
3. Enable multiple port net buffering
4. Enable Constant net buffering
5. Apply timing derating for On-Chip variations
6. Define Don't use or preferred cells
7. Keep Spare cells and unloaded cells
8. Apply area constraints and area recovery
9. Apply area and power cricalranges.
10. Organize paths into groups
11. Prevent clock as data networks
12. modify optimization priorities if needed
13. Enable recovery and removal check.

Sanity checks for Physical Design

Chip Design

Sanity checks for Physical Design

May 10, 2017 argha chakraborty

The very first step of physical design is to validate the

input data going to be used for layout creation (Physical
Design) . In Physical Design world this term is known as
SANITY CHECKS.

The very two important SANITY CHECKS is to do sanity on below two inputs :

1) Sanity on design (netlist)

Synopsys Command for design sanity : check_design -summary

The check_design command checks the internal representation of the current design for
consistency, and issues error and warning messages as appropriate.

2) Sanity on constraints (sdcs)

Synopsys Command for constraints sanity : check_timing

The above command checks for following things :

clock crossing
clock_no_period
data_check_multiple_clock
data_check_no_clock
gated_clock
generated_clock
ideal_clocks
ideal_timing
loops
multiple_clock
net_no_driving_info
no_driving_cell
no_input_delay
unconstrained_endpoints

3) Sanity on tluplus files (RC files)

4) Sanity between consistency between logical and physical libraries

-> This is already being done by foundary vendor

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 Interview Focused Questions

1. Tell me about Your self (Do Yourself in simple manner)

2. Can u explain the Pd Flow?
3. What contain in .Lib
4. Where setup and hold values locates
5. What is the use of Tlu+ file
6. What is the use of Technology file
7. What IT Contain in .SDC ?
8. What is the use of Lef file
9. After getting the inputs from synthesis team what u will do?
10.What are the sanity checks after taking the data setup?
11.If any error then you will continue?
12.Before floor plan we are doing zero wire load model why we will do it?
13.If I want my block should be square how much aspect ratio I want to give?
14.If I want rectilinear mean what I have to do how I can calculate it?
15.If aspect ratio is not given what will be the block shape?
16.What is mean by utilization?
17.How you will do the macro placement?
18.What will happen when I use the command mode for placing the Macros?
19.If your Macro is power Hungry Device where you will put it?
20.If my macro is very power hungry device can I use separate power rings?
21.What is Die area? Core Area?
22.What is mean by Pad area Design and Core Limited Design?
23.Any idea about Heraclea and Flat Design? For run time which is better?
24.What you will do exactly in floor plan?
25.What is channel width? Why we should give this?
26.When you will use the Hard Blockage and Soft Blockages?
27.Will allow the Hard Blockage inverters and Buffers?
28.What is meaning by Keep out margin why we will use it?
29.Difference between keep out margin and Blockage?
30.After Floor Plan what you will do?
31.Why you will use the Power Plan?
32.Which Physical Cell is used for IR Drop?
33.What is Macro?
34.After power plan what you will do?
35.How you will do the Placement? What exactly it will do when u run the place
opt?
36.Have you seen the Place_opt Log file what it contains?
37.Why HFSN?
38.In HFSN we will Synthesizing some particular Nets what they?
39.What is mean by unit tile area?
40.Is the height of Stand’s cells?
41.What will be Height macro?
a. It will be integral multiple of the site Row
42.When you will place the physical only cells
43.What is mean by physical only cells?
44.Is there any .lib for physical only cells?
45.Can u name some physical only cells?
46.Why we need tie cells?
47.What is the use of tap cells?
48.Practically what in Latch up?
49.Tap cells will place regular interval or near
50.What is the use of filler cells?
51.In which stage you will do the filler cells
52.What you will do the after Placement
53.What is showing in the timing report?
54.Why you are checking the setup in hold?
55.What is the other check in Placement?
56.How u will reduce the congestion?
57.What is mean by partial Blockage
58.After placement what will you do
59.What are the inputs if cts
60.What in contain clock speck file
61.What are the goals of cts
62.What are the clock trees?
63.Which tree you’re using in your design?
64.After cts what you will do?
65.Can I balance the zero skew? Why?
66.By default tool what tool report local or global skew?
67.How you will build the clock tree?
68.What is the difference between clock buffers and normal buffers
69.Why we need equal rise and fall?
70.Clock buffers requires more area
71.Which is better clock inv or buff?.
72.After cts what you will do
73.How you fix the Hold?
74.Uncertainty on which what factor it will depend
75.Uncertainty Percentage?
76.What are cts exceptions?
77.What is mean by nonstop pin?
a. Clock reaching to D pin of the ports so it will think like it is sink pin on
that time we have intimate the tool there is another flop is available
consider that flop as a sink pin.
78.Why we call it is generated clock? Why we are using this?
79.What is mean by false path and MCP?
80.Half cycle path?
81.Is hold depended on time period Half Cycle path?
a. Yes. T period/2. Hold depends on timepeiod in HCP.
82.What is mean Virtual clock?
83.Where it will use in constraints?
a. In – Reg and Reg to out to define set input delay and to define set out put
delay
84.When you will use the set max delay?
a. In to out path
85.What are the timing Paths?
86.After cts whichVoilation your perform?
87.Routing what it will exactly do?
88.What Is mean by search and repair?
89.What are the goals of routing?
90.After routing which file your creating?
91.Why we will give routing?
92.Where you analysis the cross talk in data path or clock path?
93.In my Design 9 metal are there which metal you use for differ section?
94.HV VH HH? Why I don’t use the HH VV?
95.How to avoid the cross talk?
96.You have any idea for antenna effect?
97.How you will reduce it?
98.What is mean by electron migration?
99.You have any idea about ECO Stage?
100. For scan chain which file you need?
101. You know anything on sign off stage?
102. What is mean by LVS?
103. What is DRC s in PV?
104. Tell the basic PD flow?
105. Tell me the what are the inputs for Icc1?
106. What are OCV concepts?
107. On which corner Setup /Hold Depends?
108. What are the parasitic corners?
109. What file u need when your design is Multivoltage Design?
110. In reg – reg which clock you use?
111. Is there any library for physical only cells?
112. What is mean by clock gating why we use it?
113. What is the use of Scan chain Reorder?
114. What is your clock frequency in your design?
115. How many master clocks in your design?
116. What is your block shape?
117. What is the utilization on each stage?
118. What is the congestion value in each stage?
119. What is the area of your block?
120. What is the height of your block and standard cell and Macros?
121. In placement stage when to timing report it will show the report for max
by default what it is?
122. What is mean by gating?
123. What is the use of clock spec file?
124. What are clock Tress? Which clock you’re using in your design?
125. In industry which clock we are using mostly?
126. What is the utilization factor for design?
127. What does spef file contain?
128. For which input we are using the SPEF?
129. Check timing command which file it will check?
130. Tlu + file which command will use for checking sanity checks in before
placement?
131. How you will fix the setup by command?
132. How may macros in your design how you will find it?
133. How many clocks are there in your design?
134. How you will connect from M1 standard cell to M9 routing?
135. Actual routing which metal layer we are use?
136. In which corner you will find the setup and hold?
137. What exactly Slow Slow Corner shows?
138. Have you seen Slow slow corners in your design ?
139. Check _timing what it will give?
140. How you will do the your floor plan ?
141. What it contain pg routing .tcl file ?
142. What contain in def file ?
143. What contain in technology file ?
144. What contain in lib file ?
145. What contain tlu pluse file ?
146. What contain in sdc ?
147. What contain tdf file ?
148. What is the meaning of scan chain reorder ?
149. Why we will do the power paln ?
150. How you will fix the macros tell me command ?
151. How you will palace the macros ?
152. How did you do the power plan?
153. What is mean by ocv?
154. What is the formula for channel width between the macros ?
155. Explain routing?
156. What u did in placement stage ?
157. What are the sanity checks in after floor plan ?
158. Is setup violation accrued after floor paln ?
159. How will fix the setup violation after cts ?
160. What it will do the check_design sanity check? Which file it is going to
check?
161. What exactly check_timing do? Which file it is going to check?
162. What exactly it will do Check_library, check_mv_design, check_netlist
which type of errors it will report and which files it is going to check and if u
have any errors in this file for whom you have to report?
163. Can u tell me the PD full flow in Short?
164. Why STA? Why not DTA?
165. On which is we will find setup and Hold? Why?
166. Why we are closing at Multiple PVT Corners?
167. What are the timing/SDC Constraints?
168. What is mean by case analysis how we will use it?
169. What the equation for setup and hold?
170. How to make a chip work that has setup violation after Tape Out?
171. How to make a chip work that has Hold Violation after Tape out?
172. What are the clock gating checks?and related constraint commands?
173. What are reset recovery removal and related commands?
174. How to find the max frequency in the design?
175. How to find the setup and Hold slack?
176. What is OCv how we will account it for timing violations?
177. How you will reduce the DRC with End cap cells?
178. How to tell the tool to use usefullskew for fixing the violation?
179. How you will do cell swapping? And write command?
180. How you will do Buffer insertion? And write command?
181. What are ways to reduce the setup hold DRV Physical DRC violations?
182. How the relation for leakage and delay for HVT LVT RVT cells?
183. If timing is more critical which cells I have to use why?
184. If leakage is more which cells I have to use why?
185. What is mean MCP, FP how you will Constrain it?
186. What are the NDR Rules why this rules?
187. What are the inputs and outputs for Prime time?
188. What are the input and output files for each stage in physical design?
189. What are the input and output files for Star RC?
190. Why parasitics are extracted what are the commands to do it?
191. What is mean by
1. Skew
2. Insertion Delay
3. Global skew
4. Positive /Negative skew
5. Uncertainty
6. Jitter
7. Arrival/required path
8. Propagation delay
9. Latency – source – networkLatecny
10.Useful skew
11.HCP
12.Slack
192. What is Tcl why we use it ?
193. What are the TCL files you use what it contain exactly in that tcl at each
stage?
194. What is cell and pin density how you will resolve it?
195. What are timing exceptions?
196. Which buffers and inverters you used in While building the clock tree?
197. Who have a setup violation 1ps after doing all ways to fix it what you will
do you will fix or leave?
198. Explain the setup and Hold with D flipflop? And with wave forms?
199. How you will calculate the cell delay and net delay?
200. What is mean By CRPR where you use it why?
201. What is the difference between normal pulse width minimum pulse width?
202. What is mean by NLDM,CCS,WLM? Why we using this?
203. What is Antenna Effect and EM and ESD?
204. How you will fix the opens and shorts?
205. How you fix the timing violations in cts stage?
206. Tell the which commands you used in Unix?
207. What is 28nm ? what is the difference to other nm to use 28nm only in
your design?
208. Count of gates , instances, macros, Input and output ports?
209. Difference between Pin and port?
210. How you will synthesis your clock tree?
211. Have you meet the skew which you targeted if not how you will met?
212. What the reports you generated in each stage?
213. What it contains the information of each report when you generate the
reports at each report?
214. Go for all Formulas Stdcell Utlization, channel width, Congetion…E.t.c
215. What is the operating voltage for your design?
216. How many corners you used in you design?
217. Why setup at SS?
218. Why Hold at FF?
219. What are the Placement Bounds? How will use?
220. If u have a congestion macro macro which blockage u will use now?
221. If u have a congestion of macro to Core Boundary which blockage you will
use?
222. Why your using IO Buffers?

Please Go to all commands ones some companies will ask only commands
also some will ask both at each stage don’t skip any topic if u skipped mean they
will ask on that only.
 Company1:-
1. Tell me about your exp.?
2. What are the inputs and sanity checks for your design?
3. In netlist sanity checks, what about output floating?
4. If input floating is there, what kind of functionality failures we will get?
5. What kind of glitches we will get in netlist sanity checks if we have input floating?
6. What are the effect of empty module in your design and how you will remove it?
7. From where you will get your clock related information and timing exceptions?
8. What is meant by set_input_delay and set_output_delay in SDC?
9. How to check the multiclocks driven by a single flop in ur design?
10. What kind of library checks you will do in your sanity checks?
11. What type of material we will use for welltap cells?
12. Tell me about macros placement guidelines?
13. What you will do in your tool for efficient usage of your macros channel?
14. What are the floorplan checks we will do?
15. What about dynamic power consumption when we are coming down to lower
technologies from higher technologies?
16. What is the minimum distance between tap cells in your block?
17. What is Latch-up & how tap cell will avoid latchup?
18. What is the usage of tie-high & tie-low cells?
19. Tell me about timing @placement level?
20. Tell about congestion in between macros and how to avoid that?
21. Tell me about placement congestion in your design?
22. What are the placement quality checks we will perform?
23. What are the inputs for CTS(Clock Tree Synthesis)?
24. Tell me about NDR rules?
25. What is crosstalk delay and crosstalk noise?
26. Tell me about timing window?
27. What is congestion?
28. Tell me about cross-talk fixes?
29. What are the skew otimization techniques you did in your design?
30. How we will improve Insertion Delay?
31. What is Uncertainity, Jitter & Extra Margin?
32. Positive skew helps in what? Is Setup or Hold?
33. Negative skew helps in what? Is Setup or Hold?
34. Why we are not taking care about hold before CTS? Why only Setup?
35. Tell me about setup & Hold fixing techniques?
36. How you will improve transition?
37. What is HFNS and why we need it?
38. Tell me about H-Tree based CTS and tree balancing?
39. Why CTS is required?
40. What are major parameters did you saw in your timing report?
41. What is LEC & What you will check it from formaity tool?
42. What kind of DRC & LVS checks did you performed?
43. What are the challenges you gone through your design?
44. What is IR Drop and fixes for IR-Drop? (Static & Dynamic)
45. What is Antenna Violation and you will fix it?
46. Why we are not doing layer hopping with lower metal layers for Antenna violation
fixing?
47. What is CPPR & CRPR?
48. In which corner you did your CTS?
49. How many corners you used in your design?
50. What is MMMC?
51. If you are having setup & Hold in same path what you will do?
52. In shielding, why we are not doing with VDD?
53. What is negative setup time? How it will be useful for your setup slack calculation?
54. If cell overlapping (or) Redundancy is there in your design @placement level, what
you will do?
55. What is bound (or) Region? And ICC commands for creating and removing of
bounds?
56. What is path group & What are path groups you used in your design?
57. What is Multicycle Path & False Path?
58. What is a HALO?
59. What are differences between OCV, AOCV & POCV?
60. What kind of cells you used in your desingn @CTS stage?
61. Tell me about manual ecos at prects stagee?
62. How will you apply derating for your block?
63. What is min.pulse width?
64. Tell me about different models which you gone through?

Company 2:-
1. Why NDR for clock nets?
2. What will happen if your skew is zero?
3. Tell me about DPT(Double Patterning Technology) issue?
4. Fast to slow & slow to fast approach in multicycle path?
5. At which stage we will use our TLU+ files? What it is having?
6. create_placement, what it do?
7. Why we are having macros placement rules?
8. How will you make that your setup is good @placement level?
9. Timing is good Congestion is good Which is good placement approach?
Congestion is bad Timing is bad
10. What is slew rate?
11. Tell me about Interclock skew balancing?
12. In placement stage, what is 2-pass approach?
13. Why we are placing the macros @boundary of core ony?
14. What is your skew target and ID target?
15. Tell me about routing blockages?
16. How to calculate channel length in between your macros?
17. How many number os shorts & opens you have in your design?
18. Tell me about violation min. spacing rule?
19. ICC command for power straps creation?
20. If you have 500 shorts in your design after routing, what is your approach to fix it?
21. Why we are using clock BUFF/INV over normal BUFF/INV in CTS?
22. In Half cycle path, where you will check your Setup & Hold?
23. What could be reason for Setup & Hold on same path?
24. Why we are getting clock transition in clock spec. file, if we have already this in
SDC file?
25. What are different types of complex cells you have in your design?
26. Is Hold is frequency dependent or independent?
27. How many delay corners have in your design?
28. What is buffering and What is Cloning?
29. Tell me about CTS flow?
30. What are the different timing fixes you gone through?
31. How your input delay will effect your Setup & Hold slacks?
32. Tell me about timing ecos and functional ecos?
33. What is std. cell abutted placement?
34. Tell me about timing driven and congestion driven placement?
35. What kind of reliable checks you will perform for your block?
36. Why keepout margin for macros?
37. What kind of manual fixes you did @physical DRC fixes?
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Interview Questions:

Qualcomm: (IN: DINESH, NAVEEN - MODEM TEAM) & (IN: PAVAN, SRIKAR
MOVVA & SATEESH - GPU & SOC TEAM)

1. Tell me about your exp.?

2. What are the inputs and sanity checks for your design?
3. In netlist sanity checks, what about output floating?
4. If input floating is there, what kind of functionality failures we
will get?
5. What kind of glitches we will get in netlist sanity checks if we
have input floating?
6. What are the effect of empty module in your design and how you will
remove it?
7. From where you will get your clock related information and timing
exceptions?
8. What is meant by set_input_delay and set_output_delay in SDC?
9. How to check the multiclocks driven by a single flop in ur design?
10. What kind of library checks you will do in your sanity checks?
11. What type of material we will use for welltap cells?
12. Tell me about macros placement guidelines?
13. What you will do in your tool for efficient usage of your macros
channel?
14. What are the floorplan checks we will do?
15. What about dynamic power consumption when we are coming down to
lower technologies from higher technologies?
16. What is the minimum distance between tap cells in your block?
17. What is Latch-up & how tap cell will avoid latchup?
18. What is the usage of tie-high & tie-low cells?
19. Tell me about timing @placement level?
20. Tell about congestion in between macros and how to avoid that?
21. Tell me about placement congestion in your design?
22. What are the placement quality checks we will perform?
23. What are the inputs for CTS(Clock Tree Synthesis)?
24. Tell me about NDR rules?
25. What is crosstalk delay and crosstalk noise?
26. Tell me about timing window?
27. What is congestion?
28. Tell me about cross-talk fixes?
29. What are the skew otimization techniques you did in your design?
30. How we will improve Insertion Delay?
31. What is Uncertainity, Jitter & Extra Margin?
32. Positive skew helps in what? Is Setup or Hold?
33. Negative skew helps in what? Is Setup or Hold?
34. Why we are not taking care about hold before CTS? Why only Setup?
35. Tell me about setup & Hold fixing techniques?
36. How you will improve transition?
37. What is HFNS and why we need it?
38. Tell me about H-Tree based CTS and tree balancing?
39. Why CTS is required?
40. What are major parameters did you saw in your timing report?
41. What is LEC & What you will check it from formaity tool?
42. What kind of DRC & LVS checks did you performed?
43. What are the challenges you gone through your design?
44. What is IR Drop and fixes for IR-Drop? (Static & Dynamic)
45. What is Antenna Violation and you will fix it?
46. Why we are not doing layer hopping with lower metal layers for
Antenna violation fixing?
47. What is CPPR & CRPR?
48. In which corner you did your CTS?
49. How many corners you used in your design?
50. What is MMMC?
51. If you are having setup & Hold in same path what you will do?
52. In shielding, why we are not doing with VDD?
53. What is negative setup time? How it will be useful for your setup
slack calculation?
54. If cell overlapping (or) Redundancy is there in your design
@placement level, what you will do?
55. What is bound (or) Region? And ICC commands for creating and
removing of bounds?
56. What is path group & What are path groups you used in your design?
57. What is Multicycle Path & False Path?
58. What is a HALO?
59. What are differences between OCV, AOCV & POCV?
60. What kind of cells you used in your desingn @CTS stage?
61. Tell me about manual ecos at prects stagee?
62. How will you apply derating for your block?
63. What is min.pulse width?
64. Tell me about different models which you gone through?

Rambus: (IN: NAVEEN, LAKSHMI PARVATHI & ANKIT - DDR TEAM)

1. Why NDR for clock nets?

2. What will happen if your skew is zero?
3. Tell me about DPT(Double Patterning Technology) issue?
4. Fast to slow & slow to fast approach in multicycle path?
5. At which stage we will use our TLU+ files? What it is having?
6. create_placement, what it do?
7. Why we are having macros placement rules?
8. How will you make that your setup is good @placement level?
9. Timing is good Congestion is good Which is
good placement approach?
Congestion is bad Timing is bad
10. What is slew rate?
11. Tell me about Interclock skew balancing?
12. In placement stage, what is 2-pass approach?
13. Why we are placing the macros @boundary of core ony?
14. What is your skew target and ID target?
15. Tell me about routing blockages?
16. How to calculate channel length in between your macros?
17. How many number os shorts & opens you have in your design?
18. Tell me about violation min. spacing rule?
19. ICC command for power straps creation?
20. If you have 500 shorts in your design after routing, what is your
approach to fix it?
21. Why we are using clock BUFF/INV over normal BUFF/INV in CTS?
22. In Half cycle path, where you will check your Setup & Hold?
23. What could be reason for Setup & Hold on same path?
24. Why we are getting clock transition in clock spec. file, if we
have already this in SDC file?
25. What are different types of complex cells you have in your design?
26. Is Hold is frequency dependent or independent?
27. How many delay corners have in your design?
28. What is buffering and What is Cloning?
29. Tell me about CTS flow?
30. What are the different timing fixes you gone through?
31. How your input delay will effect your Setup & Hold slacks?
32. Tell me about timing ecos and functional ecos?
33. What is std. cell abutted placement?
34. Tell me about timing driven and congestion driven placement?
35. What kind of reliable checks you will perform for your block?
36. Why keepout margin for macros?
37. What kind of manual fixes you did @physical DRC fixes?
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1.Wi
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tualclock?How we can sayanycl
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l
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me
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gn.
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chpar
asi
ti
cint
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ner
sar
echeckedf
orset
up
andhold?
7.Dr
awt
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oll
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ng

 Cr
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20ps 50ps 60ps

10.
How sy
nthesi
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li
sti
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.v)i
sini
/pst
ageofFl
oor
plani
sdi
ff
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rom
RTLnet
li
st?
11.
Whati
scl
ockl
atency
?Expl
ainsour
ce&n/
wdel
ay.
12.
Whati
sdi
ff
erenceb/
waHal
o&aBl
ockage?
13.
Whati
sset
up&hol
dti
ming?Der
iveequat
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ndset
up&hol
dsl
ack.
14.
Whatar
eti
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ions?Whyt
heyshoul
dbegi
venasconst
rai
nts?
15.
Expl
ainPDf
low,
i/p&o/
pfi
l
esi
neachst
age.
16.
Whati
suncer
tai
nty
?Expl
aini
ntercl
ockuncer
tai
nty
.
17.
Cant
her
ebeset
up&hol
dvi
olat
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orsamepat
h?Just
if
yyouranswer
.
18.
Whati
sscanchai
nreor
der
ing?
19.
Expl
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oll
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ngt
ermsandway
stof
ixt
hem:
-

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 El
ect
romi
grat
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 Cr
osst
alk

 CMOSLat
ch-
up
20.
Whati
scr
osst
alkdel
ayandCr
osst
alknoi
se?
21.
Expl
ainv
ari
ouski
ndofpr
epl
acedcel
l
s.
22.
Whati
sNDR?Whi
chst
ageofPDweappl
yNDRandwhy
?
23.
Whatar
ethemai
ngoal
sofCTS?
24.
Wri
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oper
for
mfol
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ngoper
ati
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 Makeadi
rect
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x2,
andx3.

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it
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ndi
a”.

 Makeaf i
l
ewi thgivenpermissi
ont
oread& wr
it
etoal
lbutnoone
shoul
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epermissi
ons.
25.
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ofi
nd“
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aisagoodt
eacher
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il
enamedXYZ.
26.
Creat
eahi
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avour
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imeser
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By Bhavani:

1. What we need to start Floor plan?

Ans: To start a floor plan first we need inputs like .v, .lib, .lef, .SDC

This is the first major step in getting your layout done. Your floor plan determines your chip quality. At this
step, you define the size of your chip/block, allocates power routing resources, place the hard macros, and reserve
space for standard cells

2. Tell about input files?

Ans: NETLIST:

It is the combination of sequential elements and their logical connectivity.

Netlist contains-

• Input and output information of the design.

• Wire information.
• Cell and instance information.
• Module information.
• Hierarchy information.
• Port information.

LIBRARY file:

It has time, power and functionality of a cell

Time- input delays, output delays, setup and hold

Power- leakage power and internal power

Cell functionality

For eg:- (A+B)*(B+C)

PVT(process voltage and temperature) conditions

LEF(library exchange format)

It has physical information of the design

Two types

1. Technology lef
2. Cell/macro lef
1. Technology lef
It contains metal layer and via information like
Metal layer:
 • Direction
• Pitch
• Width
• Area
• Spacing table
• Min enclosure area
• Diag spacing
• Diag min edge length
• Resistance
• Capacitance
• Thickness
• Antenna model and antenna area ratio
• DC current density

VIA information:

• Spacing
• Width
• Antenna model
• Antenna area ratio
• DC current Density
2. Cell/Macro lef
• Class
• Origin
• Size
• Symmetry
• Pin:
o Antenna gate area
o Direction
o Usage
o Port

SDC (Synopsys design constraint)

➢ Clock definition
Create clock
Create virtual clock
Create generated clock
Create clock uncertainty

➢ External delays
Input delays
Output delays
➢ DRV’s
 Max tran, max cap and max fanout

➢ Timing path exceptions

False path
Multi cycle path
Max delay
Min delay

3. What are the guidelines to place macros?

Ans: 1.Place macros around chip periphery.

If you don’t have reasonable rationale to place the macro inside the core area, then place macros around the chip
periphery. Placing a macro inside the core can invite serious consequence during routing due to a lot of detour
routing, because macros are equal to a large obstacle for routing. Another advantage to placing the hard macros
around the core periphery is it's easier to supply power to them, and reduces the change of IR drop problems to
macros consuming high amounts of power.
2. Consider connections to fixed cells when placing macros.
When you decide macro position, you have to pay attention to connections to fixed elements such as I/O and
perplaced macros. Place macros near their associate fixed element. Check connections by displaying flight lines in
the GUI.
3. Orient macros to minimize distance between pins.
When you decide the orientation of macros, you also have to take account of pins positions and their connections.
4. Reserve enough room around macros.
For regular net routing and power grid, you have to reserve enough routing space around macros. In this case
estimating routing resources with precision is very important. Use the congestion map from trialRoute to identify hot
spots between macros and adjust their placement as needed.
5. Reduce open fields as much as possible.
Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing different
aspect ratio (if that option is available) can eliminate open fields.
6. Reserve space for power grid.
The number of power routes required can change based on power consumption. You have to estimate the power
consumption and reserve enough room for the power grid. If you underestimate the space required for power
routing, you can encounter routing problems.

4.what happens if pins assign to left and right.(if you have IO pins at top and bottom)?

Ans: Actually top level chip will be divided into some blocks, IO pins will be placed according to the
communication between surrounding blocks.

If we assign pins to left and right rather than top and bottom we will face routing issues in further
stages.

5. How we will assign spacing between two macros?

Ans: channel spacing= no of pins*pitch/ total number of metal layers

6. In placement what are the congestion types, how to resolve congestion?

Ans: we will see congestion where available tracks are less than required tracks.
 We may see congestion because of

• Cell density
• Pin density
• Bad floorplan

There are two types of congestion

1. horizontal congestion and

2. vertical congestion

we will see horizontal congestion when horizontal tracks are less and similarly for vertical congestion if
vertical tracks are less

prevention techniques:

• we can avoid congestion by placing blockages.

• Cell padding
• Scan chain reordering.

7. What happens if cell density and pin density is more, how to resolve it?

Ans: if cell density and pin density is more we will see congestion and routing issues.

By placing partial blockage we can avoid cell density and by cell padding we can avoid pin
density.

8. what happens if cells place closer to macros?

Ans: if cells are placed close to macros we will see routing issues near macros, to avoid this we are
placing Halo around the macro.

9. explain about power planning?

Ans: Power Planning is one of the most important stage in Physical design. Power network is being
synthesized, It is used provide power to macros and standard cells within the given IR-Drop limit. Steady
state IR Drop is caused by the resistance of the metal wires comprising the power distribution network.
By reducing the voltage difference between local power and ground, steady-state IR Drop reduces both
the speed and noise immunity of the local cells and macros.
Power planning management can be divided in two major category first one is core cell power
management and second one I/O cell power management. In core cell power planning power rings are
formed around the core and macro.In IO cell power planning power rings are formed for I/O cells and
trunks are created between core power ring and power pads.
In addition trunks are also created for macros as per the power requirement.
power planning is part of floor plan stage. In power plan, offset value for rings around the core and
vertical and horizontal straps is being define
I/O cell library contains I/O cell and VDD/VSS pad cell libraries. It also contain IP libraries for reusable
IP like RAM, ROM and other pre designed, standard, complex blocks.
10. what happens if IO pins placed at core boundary?

Ans: nothing happen, we can place IO pins in core boundary

11. what are the timing issues after placement?

Ans: DRV’s and setup.

12. what is path timing and data path?

Ans: Timing Path

Timing path is defined as the path between start point and end point where start point and end
point is defined as follows:

Start Point:

All input ports or clock pins of a sequential element are considered as valid start point.

End Point:

All output port or D pin of sequential element is considered as End point

For STA design is split into different timing path and each timing path delay is calculated based
on gate delays and net delays. In timing path data gets launched and traverses through combinational
elements and stops when it encounter a sequential element. In any timing path, in general (there are
exceptions); delay requirements should be satisfied within a clock cycle.

In a timing path wherein start point is sequential element and end point is sequential element, if
these two sequential elements are triggered by two different clocks(i.e. asynchronous) then a common
least common multiple (LCM) of these two different clock periods should be considered to find the
launch edge and capture edge for setup and hold timing analysis.

Different Timing Paths

Any synchronous design is split into various timing paths and each timing path is verified for its
timing requirements. In general four types of timing paths can be identified in a synchronous design. They
are:

Input to Register

Input to Output

Register to Register

Register to Output
Data path:

The path wherein data traverses is known as data path. Data path is a pure combinational path. It can have
any basic combinational gates or group of gates.

13. Explain about PD flow?

Ans: INPUTS:

.v, .lib, .lef, .SDC

NETLIST:

It is the combination of sequential elements and their logical connectivity.

Netlist contains-

• Input and output information of the design.

• Wire information.
• Cell and instance information.
• Module information.
• Hierarchy information.
• Port information.

LIBRARY file:

It has time, power and functionality of a cell

Time- input delays, output delays, setup and hold

Power- leakage power and internal power

Cell functionality

For eg:- (A+B)*(B+C)

PVT(process voltage and temperature) conditions

LEF(library exchange format)

It has physical information of the design

Two types

3. Technology lef
4. Cell/macro lef
3. Technology lef
It contains metal layer and via information like
 Metal layer:
• Direction
• Pitch
• Width
• Area
• Spacing table
• Min enclosure area
• Diag spacing
• Diag min edge length
• Resistance
• Capacitance
• Thickness
• Antenna model and antenna area ratio
• DC current density

VIA information:

• Spacing
• Width
• Antenna model
• Antenna area ratio
• DC current Density
4. Cell/Macro lef
• Class
• Origin
• Size
• Symmetry
• Pin:
o Antenna gate area
o Direction
o Usage
o Port

SDC (Synopsys design constraint)

➢ Clock definition
Create clock
Create virtual clock
Create generated clock
Create clock uncertainty

➢ External delays
 Input delays
Output delays
➢ DRV’s
Max tran, max cap and max fanout
➢ Timing path exceptions
False path
Multi cycle path
Max delay
Min delay

SANITY CHECKS:
1. Library checks
• Missing cell information
• Missing pin information
• Duplicate cells
2. Design checks
• Inputs with floating pins
• Nets with tri-state drivers
• Nets with multiple drivers
• Combinational loops
• Empty modules
• Assign statements
3. Constraint checks
• All flops are clocked or not
• There should not be unconstraint paths
• Input and output delays
FLOORPLAN:
1. Utilization factor decides the size of the block.
2. Aspect ratio gives shape of the block.
3. After utilization and aspect ratio we go for pin placement.
In pin placement we have to place pins legally
4. Macros should be placed according to guidelines
a.Place macros around chip periphery.
If you don’t have reasonable rationale to place the macro inside the core
area, then place macros around the chip periphery. Placing a macro inside
the core can invite serious consequence during routing due to a lot of detour
routing, because macros are equal to a large obstacle for routing. Another
advantage to placing the hard macros around the core periphery is it's easier
to supply power to them, and reduces the change of IR drop problems to
macros consuming high amounts of power.
b. Consider connections to fixed cells when placing macros.
When you decide macro position, you have to pay attention to connections to
fixed elements such as I/O and perplaced macros. Place macros near their
associate fixed element. Check connections by displaying flight lines in the
GUI.
c. Orient macros to minimize distance between pins.
When you decide the orientation of macros, you also have to take account of
pins positions and their connections.
 d. Reserve enough room around macros.
For regular net routing and power grid, you have to reserve enough routing
space around macros. In this case estimating routing resources with
precision is very important. Use the congestion map from trialRoute to identify
hot spots between macros and adjust their placement as needed.
e. Reduce open fields as much as possible.
Except for reserved routing resources, remove dead space to increase the
area for random logic. Choosing different aspect ratio (if that option is
available) can eliminate open fields.
f. Reserve space for power grid.
The number of power routes required can change based on power
consumption. You have to estimate the power consumption and reserve
enough room for the power grid. If you underestimate the space required for
power routing, you can encounter routing problems
5. After macro placement we will place physical cells like endcap and welltap
cells
POWER PLANNING:
Power planning is to supply power to the standard cells and macros.
Power pads
↓
Power rings
↓
Power stripes→ Macros
↓
Follow pins
↓
Standard cells
PLACEMENT:
Two stages- 1. Course placement 2. Detail placement
1. Course placement:
a. First tool will place standard cells based on hierarchy
b. It will do High fanout net synthesis
Adding buffers to the high fanouts
c. Scan chain reordering
In a less complex design, you don’t usually do scan reordering. However,
sometimes it may become difficult to pass scan timing constraints once the
placement is done. The scan flip flop placements may create lengthier routes
if the consecutive flops in scan chain are placed far apart due to a functional
requirement. In this case, the PnR tool can
reconnect the scan chains, to make routing easier. A prerequisite for this
option is a scan DEF for the tool to recognize the chains.

d. Logical optimization
Sizing
VT swapping
Buffering
 Logic restructuring
Pin swapping
Cloning
Rebuffering
Trail route
2. Detail placement
a. Area recovery
b. Congestion driven
c. Time driven
PLACEMENT OPTIMIZATION:
In optimization tool will optimize DRV’s and setup timing
Here we will not see hold because clock is ideal.
Checks in placement:
Cells legalization
Utilization
Area
Timing
Congestion

CLOCK TREE SYNTHESIS:

Before CTS we need to check:

1. All cells should be legalized.

2. All power nets are prerouted.

3. All pins should legalized.

4. Congestion, timing should control.

GOALS OF CTS:

1. To minimize the logical DRCs.

2. Balancing the skew.
3. Minimum Insertion Delay.

INPUTS OF CTS:

1. SDC
2. SPEC FILE
3. PLACEMENT DATABASE

WHAT IS CTS?

To distribute a clock from Clock port to Clock pin

WHY CTS?

To minimize skew and insertion delay to build the clock tree.

 Here we are generating SPEC file using clockbuffers and clock inverters.

SPEC file consists of

1. Buffers list
2. Max skew
3. Min and Max Insertion delay
4. Max trans, Cap, Fanout
5. Inverters list
6. Clock tree leaf pin, exclude pin, stop pin
7. Clock name
8. Clock period

COMMANDS USED IN CTS:

clockdesign

optDesign -postCTS

CHECKS IN CTS:

1. Timing numbers
2. Utilization numbers
3. Congestion
4. All cells should legalize

ROUTING:

INPUTS:

CTS database

Captables

GOAL:

We need to interconnect all the nets without leaving shots and Spacing violations.

STEPS INVOLVED IN ROUTING:

1. Global Routing
2. Track Assignment
3. Detailed Routing

GLOBALROUTING:
Router breaks the routing portion of the design into rectangles called gcells and
assigns signalnets to gcells.
 The global router attempts to find shortest path through gcells but does not make
actual connection or assign nets to specific nets and to specific track within gcell.
TRACKASSIGNMENT:
In this step the nets are properly assigned on tracks.
DETAILED ROUTING:
Nanoroute follows global routing plan and lays down actual wires that connect pins to
their corresponding nets.
It creates shorts and opens or spacing violations rather than leaving unconnected nets.
We can route detailed routing on entire design, a specified area of design on selected
nets.
Router runs SEARCH AND REPAIR ROUTING during detail routing.
It locates shorts and opens and spacing violations so, it reroutes the effected area to
eliminate violations.
CHECKS:
1 .Verify connectivity
2. Verify geometry
3. timing numbers
4. utilization numbers
5. All cells should legalize
6. Congestion
Commands:
Routedesign
optDesign –postRoute

14. how will you place macros according to hierarchy?

Ans: According to hierarchy communicating macros will be in same color, based on that we can place
macros .

15. if we do macro abutment, what happens?

Ans: There are two cases

1. If two macros communicating only with each other we can abutment the macros

2. If the macros communicating with other cells(std cells and IO ports) then we must should
provide a proper channel spacing between the macros or else we can see the routing issue

16. Can we place macros 90 and 270dergees orientation?

Ans: It depends on which technology you are working on. 45nm & below there are orientation
requirements by foundry. Poly orientation should be same throughout the chip. So Macro poly orientation
should match with the poly orientation of the standard cells.

17. In power planning for rings and stripes which metal layers used and why?

Ans: For rings and stripes we use top metal layers because for top metal layers we have low resistivity.
18. Can we place cells between the space of IO and core boundary?

Ans: No, we cannot place cells between the space of IO and core boundary because in between IO and
core boundary power rings will be placed and we may see routing issues.

19. How did you placed standard cells with command and tool?

Ans: command: placeDesign

Tool: place →place standard cells

20. what type of congestion you seen after placement?

Ans: 1. Congestion near Macro corners due to insufficient placement blockage.

2. Standard cell placement in narrow channels led to congestion.
3. Macros of same partition which are placed far apart can cause timing violation.
4. Macro placement or macro channels is not proper.
5. Placement blockages not given
6. No Macro to Macro channel space given.
7. High cell density
8. High local utilization
9. High number of complex cells like AOI/OAI cells which has more pin count are placed
together.
10. Placement of std cells near macros
11. Logic optimization is not properly done.
12. Pin density is more on edge of block
13. Buffers added too many while optimization
14. IO ports are crisscrossed; it needs to be properly aligned in order.
21. what are the physical cells?
Ans: End Cap cells:
1. These cells prevent the cell damage during fabrication.
2. Used for row connectivity and specifying row ending.
3. To avoid drain and source short.
4. These are used to address boundary N-Well issues for DRC cleanup.
Well Tap cells:
1. These are used to connect VDD and GND to substrate and N-Well respectively because it
results in lesser drift to prevent latch-up.
2. If we keep well taps according to the specified distances, N-Well potential leads to proper
electrical functioning.
3. To limit the resistance between power and ground connections to wells of the substrate.
De-cap Cells:
1. They are temporary capacitors which are added in the design between power and ground rails
to counter the functional failure due to dynamic IR drop.
 2. To avoid the flop which is far from the power source going into metastable state.

Filler Cells:
To fill the empty space and provide connectivity of N-wells and implant layers.
22. Tell about Non Default Rules?
Ans: Double width and double space.
After PNR stage if u will get timing /crosstalk/noise violations which are difficult to fix at ECO
stage we can try this NDR option at routing stage.
USAGE OF NDRs and Example:

When we are routing special nets like clock we would like to provide more width and
more spacing for them. Instead of default of 1unit spacing and 1unit width specified in tech
file;But NDR having double spacing and double width .When clocknet is routed using NDR it has
better Signal integrity, lesser crosstalk,lessernoise,but we cannot increase the spacing and width
because it effects the area of the chip.
Double spacing: It is used to avoid the crosstalk.

Double width: It is used to avoid the EM.

23. What is setup and hold?

Ans: SETUP: Minimum time required for data stability before the clock edge.

HOLD: Minimum time required for data stability after the clock edge.

24. Can we do setup check at placement?

Ans: Yes, we will check setup in placement stage, where as we won’t bother about hold because clock
is idea in placement stage.

25. what is trail route and global route?

Ans: Trail route:

Trial Route performs quick global and detailed routing for estimating routing-related congestion
and capacitance values. It also incorporates any changes made during placement, such as scan reorder.
You can use Trial Route results to estimate and view routing congestion, and to estimate parasitic values
for optimization and timing analysis. When used during prototyping, Trial Route creates actual wires, so
you can get a good representation of RC and coupling for timing optimization at an early stage in the
flow. Trial Route also produces a congestion map you can view to get early feedback on whether the
design is routable. Trial Route results can also be used for pin assignment when you commit partitions.

Detaile route:

Detailed routing is where we specify the exact location of the wires/interconnects in the channels
specified by the global routing. Metal Layer information of the interconnects are also specified here.

26. What is the cell height?

Ans: It is the height between two rows.

27. how to fix hold?

Ans: Hold fixing techniques:

• Downsizing
• VT swapping
• Pulling capture clock path
• Pushing launch clock path
• Insert buffer in data path

28. what is max tran range?

Ans: It is the range given in SDC file, if transition delay crosses that range we will see tran violations.

29. which technology is yours?

Ans: 45nm.

30. What is macro count, standard cell count and how many clocks in your design?

Ans: 4 macros, 36k standard cells and 3 clocks.

31. Already you placed macros, then you got core size X-10 and Y+10. How you place macros with
command and from tool?

Ans: By command:
placeInst <macro name> {llx lly urx ury}
llx – Lower Left X co-ordinate
lly – Lower Left Y co-ordinate
urx – Upper Right X co-ordinate
ury – Upper Left Y co-ordinate
With Tool:
Go to Floorplan > Resize Floorplan and make the required changes to core and place the macros with the
toolbar.
32. How to fix setup?
Ans: setup techniques:
• Downsizing
• VT swapping
• Pulling launch clock path
• Pushing capture clock path

33. Explain about isolation cells?

Ans: Isolation cells are used to isolate the output signals of a powered down domain. Output signals of a
powered down domain has an intermediate voltage levels because of power gating effect. When such intermediate
voltage signals are feed as input to powered up domain, it could result in crowbar currents which affects the proper
functioning of the powered up domain. Isolation cells helps to drive a valid logic value either zero or one.

Types
(1) Rentention cells
(2)clamp cells

Clamp cells:
They are used to clamp the signals to a specified logic state.
 Clamp ‘0’ type isolation cell is used to clamp the powered down output signal to the logic value of ‘0’.
The circuit which can be used for this purpose can be something similar to a multiplexer. One input being
the clamp value and other input being the signal to be isolated. Isolation Enable is the one which decides
when to clamp the powered down signal hence it can be the select input to the multiplexer. The final
optimal function which does this clamp ‘0’ type Isolation is an AND gate with active low Isolation Enable.
 considering an active high isolation enable, an OR gate can be used as a clamp ‘1’ Isolation cell. When the
Isolation enable is high, the OR gate output is pulled to high irrespective of the other input signal. Again
what makes it different from the normal OR gate is it is supplied with always ON supply or the power
supply of the sink power domain.
 Retention cells: In majority of the cases the clamp value of the signal in the power down domain is
determined by its RESET value. But there are some scenarios which warrant the clamp value to be same as
the last logic state of the signal. This can be accomplished by using the retention type Isolation cells. A
latch is required to store the last state value of the signal. Since the last state value can be either zero or
one, the function required to implement the Isolation cell cannot be simplified further as we did for clamp
0 and clamp 1 type.

34. What is functional design and logical design?

Ans: Any chip designing can be subdivided in 2 steps

1.Front end or logic design- Based on specification provided, functionalities are created at RTL
level abstraction to meet all the requirements. Generally Uses Gated logic. It is basically coding
of digital design.

2. Back end or Physical design- After ligic design and front end verification, in order to tape-out,
the RTL abstraction is converted in form of transistors. They need to be optimised for low area,
power and quality. This is physical or say analog design.
35. Setup calculation?

36. what are the inputs of all stages in PD flow?

Ans: Floorplan: .v and .lef

Placement: floorplan data base, lib.

CTS: placement database, SDC and spec.

Routing: CTS database, captables.

37. ASIC flow
Ans:

38. What spec file contains?

Ans: spec file contains:

• Clock name
• Clock period
• Max and min delay
• Max skew
• Sink max tran
• Buffer max tran
• Clock buffers and clock inverters information
• Exclude pin
• Through pin
• Information about Metal layers used
 • Leaf route type

39. What is LVS?

Ans: Layout verses schematic

Inputs: .LVS.V, GDS II and rule deck file.

• Source netlist(physical) and reference netlist(logical) are converted in spice netlist

• LAYOUT: it takes source netlist into spice netlist
• SCHEMATIC: It takes reference netlist into spice netlilst.
• LVS means comparison of layout and schematic spice netlist
• Spice netlist will count transistors and connectivity
• If layout and schematic netlist are equal we can proceed atherwise it will give below
violations
o Shorts
o Opens
o Floating nets
o Pin mismatches
o Component mismatch

40. Write setup and hold equations?

Ans: setup= require time – arrival time

Where require time= clock period+capture clock path latency – library setup – setup uncertainty

Arrival time= launch clock path latency + clock to Q delay + comb delay

Hold = arrival time – required time

Where require time= capture clock path latency+library hold +hold uncertainty

Arrival time = launch clock path latency + clock to Q delay + comb delay

41. How many master and generated clocks in your design?

Ans: 2master clocks and 1 generated clock

42. Explain latchup in CMOS?

Ans: Latch is the generation of a low-impedance path in CMOS chips between the power supply and
the ground rails due to interaction of parasitic pnp and npn bipolar transistors. These BJTs for a
silicon-controlled rectifier with positive feedback and virtually short circuit the power and the
ground rail.

• This causes excessive current flows and potential permanent damage to the devices.
 Analysis of the a CMOS Inverter CMOS depicting the parasitic

• The equivalent circuit shown has Q1 being a vertical double emmitter pnp transistor whose base
is formed by the n-well with a high base to collector current gain (β1).

• Q2 is a lateral double emitter npn transistor whose base is formed by the p-type substrate.

• Rwell represents the parasitic resistance in the n-well structure whose value ranges from 1KW to
20kW.

• The substrate resistance Rsub depends on the substrate structure.

• Assume the Rwell and Rsub are significantly large so that they cause open circuit connections,
this results in low current gains and the currents would be reverse leakage currents for both the
npn and pnp transistors.
• If some external disturbance occurs, causing the collector current of one of the parasitic
transistors to increase, the resulting feedback loop causes the current perturbation to be multiplied
by β1, β2
• This event triggers the silicon-controlled rectifier and each transistor drives the other with
positive feedback eventually creating and sustaining a low impedance path between power and
the ground rails resulting in latch-up.
For this condition if β1 *β1 is greater than or equal to 1 both transistors will continue to conduct
saturation currents even after the triggering perturbation is no longer available.
• Some causes for latch-up are:
– Slewing of VDD during start-up causing enough displacement currents due to well
junction capacitance in the substrate and well.
– Large currents in the parasitic silicon-controlled rectifier in CMOS chips can occur when
the input or output signal swings either far beyond the VDD level or far below VSS level,
injecting a triggering current. Impedance mismatches in transmission lines can cause such
disturbances in high speed circuits.
– Electrostatic Discharge stress can cause latch-up by injecting minority carriers from the
clamping device in the protection circuit into either the substrate or the well.
– Sudden transient in power or ground buses may cause latch-up.
Guidelines For Avoiding Latch-Up
• Reduce the BJT gains by lowering the minority carrier lifetime through Gold doping of the
substrate (solution might cause excessive leakage currents).
• Use p+ guard band rings connected to ground around nMOS transistors and n+ guard rings
connected to VDD around pMOS transistors to reduce Rw and Rsub and to capture injected minority
carriers before they reach the base of the parasitic BJT.
Place substrate and well contacts as close as possible to the source connections of the MOS
transistors to reduce the values of Rw and Rsub. (Solution to be used in your designs)
• Place source diffusion regions for the pMOS transistors so that they lie along equipotentials lines
when currents flow between VDD and p-wells.
• Avoid forward biasing of the source/drain junctions so as not to inject high currents , this
solution calls for the use of slightly doped epitaxial layer on top of the heavily doped substrate
and has the effect of shunting the lateral currents from the vertical transistor through the low
resistance substrate.

43. What are universal gates and why they are called as universal gates?

Ans: NOR gate and NAND gates have the particular property that any one of them can create
any logical Boolean expression if designed in a proper way.

44. Implement AND gate with NAND gate?

Ans:

45. Full adder and its uses?

Ans: This type of adder is a little more difficult to implement than a half-adder. The main
difference between a half-adder and a full-adder is that the full-adder has three inputs and two
outputs. The first two inputs are A and B and the third input is an input carry designated as CIN.
When a full adder logic is designed we will be able to string eight of them together to create a
byte-wide adder and cascade the carry bit from one adder to the next.

The output carry is designated as COUT and the normal output is designated as S. Take a look at
the truth-table.

INPUTS OUTPUTS

A B CIN COUT S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

From the above truth-table, the full adder logic can be implemented. We can see that the output S
is an EXOR between the input A and the half-adder SUM output with B and CIN inputs. We
must also note that the COUT will only be true if any of the two inputs out of the three are HIGH.

Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will
half adder will be used to add A and B to produce a partial Sum. The second half adder logic can
be used to add CIN to the Sum produced by the first half adder to get the final S output. If any of
the half adder logic produces a carry, there will be an output carry. Thus, COUT will be an OR
function of the half-adder Carry outputs. Take a look at the implementation of the full adder
circuit shown below.
 Uses of full adder:

Full adder reduces circuit complexibility. It can be used to construct a ripple carry counter to add
an n-bit number. Thus it is used in the ALU also. It is used in Processor chip like Snapdragon,
Exynous or Intel pentium for CPU part . Which consists of ALU (Arithmetic Block unit) . This
Block is used to make operations like Add, subtract, Multiply etcA full adder adds binary
numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit
numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in
from the previous less significant stage.The full adder is usually a component in a cascade of
adders, which add 8, 16, 32, etc. bit binary numbers.

46. whar are sequential and combinational circuits?

Combinational Logic Circuits Sequential Logic Circuits

Output is a function of clock, present

Output is a function of the present inputs
inputs and the previous states of the
(Time Independent Logic).
system.

Have memory to store the present states

Do not have the ability to store data
that is sent as control input (enable) for
(state).
the next operation.

It does not require any feedback. It simply It involves feedback from output to input
outputs the input according to the logic that is stored in the memory for the next
designed. operation.

Used mainly for Arithmetic and Boolean Used for storing data (and hence used in
operations. RAM).

Logic gates are the elementary building Flip flops (binary storage device) are the
blocks. elementary building unit.

Independent of clock and hence does not Clocked (Triggered for operation with
require triggering to operate. electronic pulses).

Example: Counter [Previous O/P

Example: Adder [1+0=1; Dependency only
+1=Current O/P; Dependency on present
on present inputs i.e., 1 and 0].
input as well as previous state].
47. binary to gray and gray to binary converstion?

48. CMOS inverter

49. CMOS transistor explanation

Ans: The main advantage of CMOS over NMOS and BIPOLAR technology is the much smaller power
dissipation. Unlike NMOS or BIPOLAR circuits, a Complementary MOS circuit has almost no static
power dissipation. Power is only dissipated in case the circuit actually switches. This allows integrating
more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.
Complementary Metal Oxide Semiconductor transistor consists P-channel MOS (PMOS) and N-channel
MOS (NMOS).

NMOS

NMOS is built on a p-type substrate with n-type source and drain diffused on it. In NMOS, the majority
carriers are electrons. When a high voltage is applied to the gate, the NMOS will conduct. Similarly,
when a low voltage is applied to the gate, NMOS will not conduct. NMOS are considered to be faster
than PMOS, since the carriers in NMOS, which are electrons, travel twice as fast as the holes.

PMOS

P- channel MOSFET consists P-type Source and Drain diffused on an N-type substrate. Majority carriers
are holes. When a high voltage is applied to the gate, the PMOS will not conduct. When a low voltage is
applied to the gate, the PMOS will conduct. The PMOS devices are more immune to noise than NMOS
devices.
CMOS Working Principle

In CMOS technology, both N-type and P-type transistors are used to design logic functions. The same
signal which turns ON a transistor of one type is used to turn OFF a transistor of the other type. This
characteristic allows the design of logic devices using only simple switches, without the need for a pull-
up resistor.

In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down network between the
output and the low voltage power supply rail (Vss or quite often ground). Instead of the load resistor of
NMOS logic gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up network
between the output and the higher-voltage rail (often named Vdd).

Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type
MOSFET will be ON when the n-type MOSFET is OFF, and vice-versa. The networks are arranged such
that one is ON and the other OFF for any input pattern as shown in the figure below.

CMOS offers relatively high speed, low power dissipation, high noise margins in both states, and will
operate over a wide range of source and input voltages (provided the source voltage is fixed).

50. why we should not place macros in middle?

Ans: we will see more RC net delays and congestion.

51. In power plan, flip chip process?

Ans: Flip-chip is a method for interconnecting chips to external circuitry with solder bumps that have
been deposited onto the chip pads. The solder bumps are deposited on the chip pads on the top side of the
wafer during the final wafer processing step. In order to mount the chip to external circuitry (e.g., a circuit
board or another chip or wafer), it is flipped over so that its top side faces down, and aligned so that its
pads align with matching pads on the external circuit, and then the solder is flowed to complete the
interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and wires are used
to interconnect the chip pads to external circuitry

52. Why top layers for power, below layers for std. cells and middle layers for clock?
Ans: Top metals layers: The resistivity of top metal layers are less and hence less IR drop is seen in
power distribution network. If power stripes are routed in lower metal layers this will use good amount of
lower routing resources and therefore it can create routing congestion.

Middle metal layers: Middle routing layers such as 4,5 and 6 tend to have the same characteristics so the
clock can be more predictable on those layers .Also ,fewer vias are required to connect to the metal to
clock pin on the flop. It also require to metal layers but they are already reserved for power and GND.
Lower metal layers: Std cell require less power it will be available in lower metal layers. And some std
cell are made up of lower metal layers. So no need to connect vias between std cell pins and metal layers.

53. What are the targets of placement?

Ans: 1.Utilization

2. Timing

3. Congestion
4. Area

54. Is SDC mandatory in floorplan?

Ans: no, because SDC contains clock definitions, delays, DRV’s and exceptional paths so in floorplan we
don’t need all these information.

55. What information you see in SFEC and SPEF files?

Ans: SPEC contains:

• Clock name
• Clock period
• Max and min delay
• Max skew
• Sink max tran
• Buffer max tran
• Clock buffers and clock inverters information
• Exclude pin
• Through pin
• Information about Metal layers used
• Leaf route type

SPEF contains: RC values

56. What is the difference between normal buff & inverter and clock buff & clock inverter?

Ans: compare to normal buffers & inverters clock buffers & inverters have equal rise and fall time.

57. What are the outputs of powerplan?

Ans: power rings, power stripes, follow pins

 We have to check DRC’s

58. What is formal verification?

Ans:

59. Multi cycle path calculation?

Ans: By default, we expect every timing path to meet setup time in a single clock cycle. However, we
can also specify that some data is captured only after a specified number of clock cycles. Till then, the
data at the capturing flop will not be used. Of course your circuit should be designed in such a way for
this kind of behaviour to be valid. This is usually a large combinational block between two registers. It is
important to specify the multicycle paths to synthesis and place&route tools, as the tools will otherwise
try to fix these paths.

This timing exception is specified by the SDC command “set_multicycle_path”. This lets you specify the
number of clock cycles required for the path.

Let us take the timing path from the previous post setup and hold. Let us say the datapath requires 3 clock
cycles.

The clock diagram is given below. Assume the launch is at edge 1 of CLK.

Once you have this specification, the STA tool takes the clock edge 4 as the capturing edge for FF2. By
default, the hold is always checked one clock edge prior to setup edge. Hence the hold will be checked at
edge 3. If you want the hold check to be done at another edge, say the launch edge itself,
a set_multicycle_path -hold should also be given along with the setup specification. set_multicycle_path 1
-hold -from FF1/CP -to FF2/D will move the hold edge by one clock cycle from the default hold edge. i.e.
to 2. set_multicycle_path 2 -hold will move the hold checking edge 2 cycles from the default hold edge.
i.e. to clock edge 1, which is the default hold edge without any set_multicycle_path specified.

60. Draw a clock waveform. What is the time period of the clock with 500MHZ frequency?

Ans: If frequency is 500MHZ,

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By Chandu:

1. Write a perl program to print sum of the digits from 1 to 10

A. For($i=0;$i<=10;$i=$i+1)

$sum=$sum+1;

Print “ the total sum is : $sum”;

2. What are all the fixing methods for setup and hold violations
A. Setup:
 Upsizing the cells
 Replace buffer with two inverters
 HVT to LVT
 If the net delay is more than break the net and insert the buffer
 Pin swapping
 Pulling the launch and pushing the capture
 Cloning

Hold:

 Inserting the buffers

 Downsizing the cells
 LVT to HVT
 Pushing the launch and pulling the capture

3. What is OCV
A. OCV – On Chip Variation
The variations are mainly caused by the three factor. They are
 Process variation
 Voltage variation
 Temperature variation
Process variation: The process of fabrication includes diffusion, drawing out of
metal wires, gate drawing etc. The diffusion density is not uniform throughout
wafer. Also, the width of metal wire is not constant. Let us say, the width is 1um
+- 20 nm. So, the metal delays are bound to be within a range rather than a single

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value. Similarly, diffusion regions for all transistors will not have exactly same
diffusion concentrations. So, all transistors are expected to have somewhat
different characteristics.
Voltage variation: Power is distributed to all transistors on the chip with the help
of a power grid. The power grid has its own resistance and capacitance. So, there
is voltage drop along the power grid. Those transistors situated close to power
source (or those having lesser resistive paths from power source) receive larger
voltage as compared to other transistors. That is why, there is variation seen across
transistors for delay.
Temperature variation: Similarly, all the transistors on the same chip cannot have
same temperature. So, there are variations in characteristics due to variation in
temperatures across the chip.

4. What is AOCV and POCV

A. AOCV – Advanced On Chip Variation
This methodology hinges on three major concepts
Cell type: variations should take into account the cell type. Surely an AND gate
and an OR gate can’t exhibit the same variation pattern. Nor could an AND3X and
an AND6X cell. The impact of variation should be calculated for each individual
cell.
Distance: As the distance in x-y coordinates increase, the systematic variation
would increase and we might need to use a higher derate value to reflect the
uncertainty in timing analysis to mitigate any surprises on silicon.
Path Depth: If within a given distance, path depth is more, the impact of
systematic variations would be constant, but the random variations would tend to
cancel each other, Therefore as the path depth increases (within the same uniform
distance), the AOCV derates tend to decrease.

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While performing the reg2reg timing analysis, AOCV methodology finds the
bounding box containing the sequential, clock buffers between two sequentials
and all the data cells. Now within a unit distance, if the path depth increases, the
AOCV derate decreases due to cancelling of random variations. However, if the
distance increases, AOCV derates increases due to increase in the systematic
variations. These variations are modeled in form of LUT.

POCV – Parametric On Chip Variation

POCV uses a statistical approach, but it doesn’t do a full SSTA analysis.

Instead, it calculates delay variation by modeling the intrinsic cell delay and load
parasitic (line resistance, line capacitance, and load capacitance) to determine both
the mean and “sigma” (variation) of a logic stage. The cell delay can be further
broken into an n-channel component and a p-channel component. They then
assume that all the cells along a path have the same mean and sigma.

This means that a given path doesn’t have to be analyzed stage-by-stage;

the number of stages can be counted, with the basic stage delay mean and sigma
then used to calculate the path delay and accumulated variation. They claim that

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this keeps the run times down to just over what standard STA tools require, far
faster than SSTA. They also claim speedier execution and greater accuracy than
AOCV, and no derating tables are required.

POCV is a technique that has been proposed as a means of reducing pessimism

further by taking elements of SSTA and implementing them in a way that is less
compute-intensive.
POCV provides the following:
•Statistical single-parameter derating for random variations
•Single input format and characterization source for both AOCV and POCV table
data
•Non statistical timing reports
•Limited statistical reporting (mean, sigma) for timing paths

5. How did you open the prime time

A. pt_shell

6. what will you ask pd team in order to do STA

A. SPEF
DEF

7. If PD team has generated 10 spefs after routing, which spef will you ask for?
A. Worst RC corner spef

8. PD inputs
A.
 lib (timing, functionality, power)
 Lef (physical info)
 V (logical connectivity)
 Sdc (clock definitions)
 Cpf/upf (consists of power domain info)
 Cap table (RC values for every net)

9. What is Netlist and what type of information contains it

A.
 logical connectivity information
 Design name,

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 Hierarchy information,
 Modules information,
 Io ports,
 Instances,
 Input and output pins

10. What is Lib and what type of information contains it

A.
 Timing, power and cell functionality information
 Power supply information
 Operating conditions
 PVTs
 Look up tables
 Cell area, functionality, timing, power
11. What is Lef and what type of information contains it
A. Physical information of the metals, cells and macros.
Tech. lef:
 layer name,
 Type,
 Pitch,
 Width,
 Spacing,
 Area,
 Resistance,
 Capacitance,
 Thickness,
 Edge capacitance,
 Min density
 Max density
 Antenna area ratio
 Current density
 Vias,
 Via rules

Cell/Macro lef:

 Name,
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 Class,
 Origin,
 Size,
 Symmetry
 Pins direction, use, antenna gate area

12. What is Sdc and what type of information contains it

A.
Clock definitions:
 Create clock,
 Create generate clock,
 Virtual clock
I/O delays:
 Input delay
 Output delay
DRVs:
 max tran,
 max cap,
 max fanout

Timing exceptions:

 false path,
 multicycle path,
 max delay,
 min delay
 case analysis
 uncertainity

13. What are all the sanity checks

A.
Library checks:
 missing cells
 Mismatched pins
 Duplicate cell name
Design checks:
 combinational loops

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 Assign statements
 Multidriven nets
 Floating inputs
 Tristate buffers
Constraint checks:
 All flops are clocked are not
 no unconstrained paths
 IO delays

14. What are all the commands used in P&R flow

A.
Inputs:
 set_init_verilog
 set_init_leffile
 set_init_mmmc
 set_init_pwrnet
 set_init_gndnet
 init_design

Sanity Checks:

 checkNetlist
 checkDesign -physicalLibrary
 checkDesign –timingLibrary

Floor Planning:

 checkPinAssignment
 addEndCap –preCap FILL8 –postCap FILL8
 addWellTap –cell FILL8 –cellInterval 40
 checkDesign –floorplan

Power Planning:

 globalNetConnect
 addRing
 addStripe
 sRoute

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Placement:

 placeDesign
 setPlaceMode
 optDesign –preCTS
 report_timing

CTS:

 createClockTreeSpec
 clockDesign
 optDesign –postCTS –hold

15. What do you mean by PVT conditions and how cell delays varies with PVT
A. PVT – Process Voltage and Temperature.
Process: You must have heard people talking in terms of process values like 90nm,
65nm, 45nm and other technology nodes. These values are characteristic of any
technology and represent the length between the Source and Drain of a MOS
transistor that you might have studied in your under-grad courses. While
manufacturing any die, it has been seen that the dies that are present at the center
are pretty accurate in their process values. But the ones lying on the periphery tend
to deviate from this process value. The deviation is not big, but can have
significant impact on timing.

Voltage: The voltage that any semiconductor chip works upon is given from
outside. Recall while working on breadboards in your labs, you used to connect a
5V supply to the Vcc pin of your IC. Modern chips work on very less voltage than
that. Typically around 1V-1.2V.

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Temperature: The ambient temperature also impacts the timing. Let's say you are
working on a gadget in Siachen glacier where temperature can drop down to -40
degrees centigrade in winters and you expect your device to be working fine. Or
maybe you are in Sahara desert, where ambient temperature is +50 degrees and
your car engine temperature is +150 degrees and again you expect your chip to
working fine. While designing, therefore, STA engineers need to make sure that
their chip will function correctly in the temperatures between -40 to +150 degrees.

16. How do you know you have max cap violation

A. report_timing –all_violators

17. What is static power

A. Analyzing the power and IR drop consumed in design when there is a constant
current flow because of instances consuming average current in the design is call
static power

18. What is dynamic power

A. Analyzing the power consumed and IR drop in design when the instances draws a
transient current flow due to the instances switching
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19. What is clock gating

A. Clock gating is a popular technique used in many synchronous circuits for
reducing dynamic power dissipation. Clock gating saves power by adding more
logic to a circuit to prune the clock tree. Pruning the clock disables portions of the
circuitry so that the flip-flops in them do not have to switch states. Switching
states consumes power. When not being switched, the switching power
consumption goes to zero, and only leakage currents are incurred.

20. What is setup

A. Minimum amount of time the data must be stable before the active edge of the
clock pluse.

21. What is cross talk

A. Crosstalk is any phenomenon by which a signal transmitted on one circuit or
channel of a transmission system creates an undesired effect in another circuit or
channel. Crosstalk is usually caused by undesired capacitive, inductive,
or coupling from one circuit or channel to another.

22. Write a setup and hold equations

A. Setup:
Arrival Time (AT) = launch clklatency + clk-q delay + combo delay

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Required Time (RT) = clk+ capture clklatency -lib setup time –(Uncertainty) +
CRPR
Hold:

Arrival Time (AT) = launch clklatency + clk-q delay + combo delay

Required Time (RT) = clk+ capture clklatency + lib hold time+ Uncertinity–
(CRPR)

23. What do you mean by aggressor net

A. Aggressor net creates impact to the neighboring nets

24. Difference between latches and flip flops

A.

25. What are the disadvantages of latches over flipflops

A.

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 Latch less predictable because there is more chance to affect to race

conditions.
 Level sensitive devices and hence more chance of metastability.
 Analyzing of Latch circuits is difficult because of its level sensitive
property.

26. What is cross talk noise and cross delay

A. Cross talk noise: When w2 is having a constant signal, and when w1 signal is
having a transition, it produces a spike at the w2 signal. This glitch is called
crosstalk noise. This is also referred to as bump violation. This glitch if wide and
large enough, can get propagated through the logic, and can create a logical
failure. The bump violations in clock network should be totally under control.
Refer to the below figure for cross talk noise.

Cross talk delay: When w2 signal is having a transition, this transition time can be
affected by the signal transition at w1. If the transition at w1 is in the same
direction as w2 signal transition, it will make w2 signal transition slower. ie,. the
net delays of the victim net will change with respect to the signal transition in the
aggressor net, this should be taken care in the timing analysis for proper timing
closure. But keep in mind, that the victim net will get affected, only if the
transitions in both the nets happen in the same timing window. Also the delay
change in the victim depends on the type of transition (rise or fall) in the aggressor
net. See the below figures for more understanding.

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27. Draw the cmos inverter circuit

28. Draw 2X1 mux using AND OR gates and truth table
A. AND gate:

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OR gate:

29. What do you mean by Mux and Demux

A. MUX: A multiplexer of 2n inputs has n select lines, which are used to select which
input line to send to the output. Multiplexers are mainly used to increase the
amount of data that can be sent over the network within a certain amount of time
and bandwidth. A multiplexer is also called a data selector. Multiplexers can also
be used to implement Boolean functions of multiple variables.
DEMUX: A demultiplexer of 2n outputs has n select lines, which are used to select
which output line to send the input. A demultiplexer is also called a data
distributor.

30. What is counter

A. Counter is a sequential circuit. A digital circuit which is used for a counting pulses
is known counter. Counter is the widest application of flip-flops. It is a group of
flip-flops with a clock signal applied. Counters are of two types.

 Asynchronous or ripple counters.

 Synchronous counters.

31. Write a perl code to copy a one file into another file
A. Open(M1,”file1”);
Open (M2,”>file2”);
@l=<M1>;
Print M2 “@l \n”;

32. What is signal integrity

A. Signal integrity or SI is a set of measures of the quality of an electrical signal. In
digital electronics, a stream of binary values is represented by a voltage (or
current) waveform

33. Write the sample verilog code

1 //-----------------------------------------------------
2 // Design Name : encoder_using_if

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3 // File Name : encoder_using_if.v

4 // Function : Encoder using If
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module encoder_using_if(
8 binary_out , // 4 bit binary output
9 encoder_in , // 16-bit input
10 enable // Enable for the encoder
11 );
12 //-----------Output Ports---------------
13 output [3:0] binary_out ;
14 //-----------Input Ports---------------
15 input enable ;
16 input [15:0] encoder_in ;
17 //------------Internal Variables--------
18 reg [3:0] binary_out ;
19 //-------------Code Start-----------------
20 always @ (enable or encoder_in)
21 begin
22 binary_out = 0;
23 if (enable) begin
24 if (encoder_in == 16'h0002) begin
25 binary_out = 1;
26 end if (encoder_in == 16'h0004) begin
27 binary_out = 2;
28 end if (encoder_in == 16'h0008) begin
29 binary_out = 3;
30 end if (encoder_in == 16'h0010) begin
31 binary_out = 4;
32 end if (encoder_in == 16'h0020) begin
33 binary_out = 5;
34 end if (encoder_in == 16'h0040) begin
35 binary_out = 6;
36 end if (encoder_in == 16'h0080) begin
37 binary_out = 7;
38 end if (encoder_in == 16'h0100) begin
39 binary_out = 8;
40 end if (encoder_in == 16'h0200) begin
41 binary_out = 9;
42 end if (encoder_in == 16'h0400) begin
43 binary_out = 10;
44 end if (encoder_in == 16'h0800) begin
45 binary_out = 11;

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46 end if (encoder_in == 16'h1000) begin

47 binary_out = 12;
48 end if (encoder_in == 16'h2000) begin
49 binary_out = 13;
50 end if (encoder_in == 16'h4000) begin
51 binary_out = 14;
52 end if (encoder_in == 16'h8000) begin
53 binary_out = 15;
54 end
55 end
56 end
57
58 endmodule

34. How can you fix max cap violations

A.
 Upsizing
 Adding the buffer

35. What is synthesis and what are the inputs to synthesis

A. Synthesis is the process of transforming your HDL design into a gate-level netlist,
given all the specified constraints and optimization settings.

Inputs:
 Lib
 RTL
 Sdc
36. What is STA
A. STA is a method of validating the timing performance of a design by checking all
possible paths for timing violations under worst case conditions.

37. Create a clock with 10ps period and rise edge 4ps and fall edge 8ps
A. create_clock [get_ports{clk}] –name pclk –period 10 –waveform{4 8}

38. what are mandatory things for generate clock

A. .
 Source master pin
 Divided by /multiple by factor

39. Write a command for generating clock

A. Create_generated_clock –name clk –source PLL –divided_by 2 [get_pins uff0/q]

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40. What type of library did you use in your design

A. .
 Fast Lib
 Slow Lib

41. What are asynchronous circuits

A. The circuit in which the change in the input signals can affect memory elements at
any instants of the time is call asynchronous circuit

In this circuit, clock is absent and hence the state changes can occur
according to delay time of the logic.

42. Why do you need the virtual clock

A. To address the IO delays

43. What is recovery and removal

A. Recovery:
The recovery time is the minimum time that an asynchronous input is stable
after being de-asserted before next active clock edge

Removal:
The removal time is the minimum time after an active clock edge that the
asynchronous pin must remain active before it can be de-asserted

44. What does report_constraints –all_violators contain

A. It show all the violations
 Max_transition
 Max_fanout
 Max_capacitance
 Setup
 Hold

45. In sanity checks if we have floating inputs, can we move forward

A. No, we don’t move forward because the floating inputs can take any input value
from the neighboring switching nets. Then the undesired output will appear. so,
we don’t move forward if there is any floating input.

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46. While giving the inputs to the floorplan, which LEF(tech lef or cell lef) we
have to give first
A. First, we give the tech lef. Whenever the tech lef is loaded after all other inputs are
loaded

47. Is .lib is mandatory inut for floorplan, and what information you take from
lib
A. No , .lib is not mandatory for floorplan

48. What are the floorplan inputs

A. Lef and .v

49. Guidelines of floorplan

A.
 IO ports must be placed.
 communication between macros and io ports
 macro to macro communication should be checked
 macros should be placed around the core boundary only
 macro pins should be towards the core area only
 crisscrossing should not be there between macros
 proper channel spacing should be given between the macro
 spacing between macros should be covered with the macros

50. what is overshoot glitch and undershoot glitch

A. There is still a glitch which takes the victim net voltage above its steady high
value. Such a glitch is called an overshoot glitch. Similarly, a falling aggressor
when coupled to a steady low victim net causes an undershoot glitch on the victim
net.

51. What are the mandatory things for creating clocks

A.
 Period
 Source

52. Why do you required setup checks and hold checks

A.
 To meet the timing
 Proper functionality of the device

53. If I increases power supply, what happen to cell delay

A. The cell delay will decrease

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54. If I increase my metal width, what happens to it’s height

A. The height remains same

55. Why we are using different metal width for different layers
A. For supply the different currents inside the design. Top metal layers have high
current flow and low metal layers have low current flow

56. What happens if in my design have a same metal width for all 9 layers
A. If the width is high the current flow is high. Due to high current flow standard
cells will damage.
If the width is low then we see more IR drop

57. How cell delay depends on channel length

A. If the channel length is more than the cell delay is more and vice versa

58. If top level guys had not mentioned the aspect ratio, then how will you take
the core area
A. (Std.cell area+12%(PD overload)+Analog IP+12%(Analog to digital
space)+Macros+4%)/ Utilization

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213. Based on what we will place the macros?

A. Hierarchy, macro to macro communication, macro to IO communication and guidelines.

214. If macros are placed at the center, what are the problems we get?
A. Congestion, net lengths will be more due to detouring, timing issues, IR drop.

215. How will you give spacing between macros?

A. Spacing = (no. of pins * pitch of routing layer)/no. of available layers in the preferred direction

216. To avoid congestion in between macros, what are the cares we take?
A. proper channel spacing should be provided between macro to macro and the halo should be provided around the macro,
there should not be crisscrossing between macro to macro.

217. What are the types of blockages?

A. placement blockages:
1. Hard blockage: It will not allow any cells inside the blockage.
2. Soft blockage: It will not allow std cell but it will allow buffers and inverters during optimization.
3. Partial blockage: It will allow only certain specified percentage of cells.
Routing blockage: It will allow only some specified metal layers inside the blockage.

218. If we place soft blockage in between the macros it will allow the buffers and inverters, in that, then how will the
power will get to that cells?
A. Stripe should be added to get the power to those cells.

219. What are all the targets after power plan?

A. Checks after power planning:
1. Connectivity should be verified.
2. Any open, floating or dangling nets in the design.

220. Inputs of placement?

A. Design database upto power plan, lib, sdc, scandef

221. What are contents in SDC?

A. Sdc: clock definitions: create clock, create generate clock, virtual clock
Input delay
Output delay
DRVs: max tran, max cap, max fanout
Timing exceptions: false path, multicycle path, max delay, min delay

222. What is multicycle path and false path?

A. The combinational data path between two flip-flops can take more than one clock cycle to propagate through the
logic. In such cases, the combinational path is declared as a multicycle path.

Some certain timing paths are not real (or not possible) in the actual functional operation of the design. Such paths can
be turned off during STA by setting these as false paths. A false path is ignored by the STA for analysis.

223. At the placement stage what are all the different types of congestion you see? And how you overcome that
congestion
in your design?
A. 1. Using hard blockages in case of congestion due to notches.
 2. Using partial blockage, in case of high cell density.
3. Using cell padding, in case of congestion due to pin density.

224. Explain different techniques to overcome the congestion?

A. same as above

225. At placement stage, if we have the utilization of 95%, can we move forward and why?
A. No, we should not proceed with that utilization. We have to check the reason for the jump in the utilization number.

226. What are the timing checks we do after placement?

A. DRVs and setup checks

227. If the design had violated by 500ps of setup then will you move forward and why?
A. No, we have to fix the setup violation. If we proceed at this stage by the next stage the setup will be violated more there
may
not be chance to fix.

228. What are inputs of CTS?

A. placement database, sdc, lib, spec.

229. What exactly the spec will contain?

A. Clock grouping,
Through pin,
Exclude pin,
Clocks,
Period,
Sink pin,
Min. delay,
Max. delay,
Min. skew,
Clock buffers and inverters,
Routing layers,
NDRs

230. What is the use of clock groups in the spec file?

A. clock groups that are mutually exclusive or asynchronous with each other in a design so that the paths between these
clocks
are not considered during the timing analysis.

231. What are the targets of CTS?

A. balanced skew and minimum insertion delay.

232. What is the skew?

A. Skew is the difference in timing between two or more signals, maybe data, clock or both. Clock skew is the difference in
arrival times at the end points of the clock tree. Clock latency is the total time it takes from the clock source to an end
point.
Skew is the difference between capture flop latency and launch flop latency.

233. Explain setup and hold with equation.

A. Setup: The minimum time before the active clock when the data input must remain stable is called the setup time.
Setup time = Required Time - Arrival Time
Required time = Clock period + capture clock latency – lib setup – setup uncertainity
Arrival time = launch clock latency + C to Q delay + combo delay

Hold: The minimum time the data input must remain stable just after the active edge of the clock.
Hold time = Arrival Time – Required Time
Required time = Capture clock latency – lib setup – setup uncertainity
Arrival time = launch clock latency + C to Q delay + combo delay
234. If launch clock is 20ns and capture clock is 10ns then where do we check the setup and hold? and vice versa?
A.

235. How to fix the setup and hold violations?

A. setup:
upsizing,
Vt swapping (HVT to LVT)
Pushing capture flop (adding delay)
Pulling launch flop(reducing delay)
Hold:
downsizing
 Vt swapping (LVT to HVT)
Pulling capture flop (reducing delay)
Pushing launch flop (adding delay)
Buffering for net delays

236. What is the resistor, capacitor and current formulae?

A. Capacitance, C = ∈ 𝐴/𝑑,
Where, ∈ is the permittivity, A is area and d is distance.
Resistance, R = ρl/A,
Where, ρ is resistivity, l is length and A is area.
Current, I = V/R,
Where, V is voltage and R is resistance.

237. What is antenna violation? On what basis antenna violation will affect the cell.
A. It is also called “Plasma induced gate effect damage”. It will occur at manufacturing stage. It is a gate damage that can
occur due to charge accumulation on metals and discharge to a gate through gate oxide. These are normally expressed
as an allowable ratio of metal area to gate area greater than allowable area.

238. What is cloning?

A.

239. On what tool and technology, you have worked? Have you ever seen PT and calibre tools?

241. What happens if we have setup and hold violations in our design?
A. setup and hold timings are to be met in order to ensure that data launched from one flop is captured properly at
another and in
accordance to the state machine designed. In other words, no timing violations means that the data launched by one
flip-flop at one clock edge is getting captured by another flip-flop at the desired clock edge. If the setup check is
violated, data will not be captured properly at the next clock edge. Similarly, if hold check is violated, data intended to
get captured at the next edge will get captured at the same edge. Moreover, setup/hold violations can lead to data
getting captured within the setup/hold window which can lead to metastability of the capturing flip-flop. So, it is very
important to have setup and hold requirements met for all the registers in the design and there should not be any
setup/hold violations.

242. What will you do if your design has setup violation and how will you meet setup in such cases where there are
no
margins available?
A. We can meet the setup violations by adding buffers and downsizing the buffers present in the clock path.

243. What is time borrowing?

A. The time borrowing technique, which is also called cycle stealing, occurs at a latch. In a latch, one edge of the clock
makes
the latch transparent, that is, it opens the latch so that output of the latch is the same as the data input; this clock edge
is called the opening edge. The second edge of the clock closes the latch, that is, any change on the data input is no
longer available at the output of the latch; this clock edge is called the closing edge.
244. What are the concepts involved in STA?
A. modeling of cells, propagation delay, slew of waveform, skew between signals, Timing arcs, Timing paths, Clock
domains,
Operating conditions.

245. What is signal integrity?

A. The ability of the signal to with stand the interference from the nearby signal.

246. What is aggressor net? Why it’s called aggressor net?

A. The net in which high switching activity is performed is aggressor. It is the affecting net so that it is called as aggressor
net.

247. Both nets are having same drive strength, but voltage is different, capacitance is occurred or not?
A. yes, the capacitance occurs due to different voltage levels.

248. Both nets are having same voltage, but voltage is same, capacitance is occurred or not?
A. No, the capacitance does not occur because the voltage levels are same.

249. Both nets having same voltage capacitance is occurred or not?

A. No

250. What is cross coupling capacitance? Why it occurs?

A. The capacitance formed between two different nets in which one of the net is having high switching activity and other
net is
containing low level signal. The capacitance is formed because of different voltage levels in the nets and different
switching.

251. What is dielectric? Do know dielectric formula?

A. A dielectric (or dielectric material) is an electrical insulator that can be polarized by an applied electric field. When a
dielectric is placed in an electric field, electric charges do not flow through the material as they do in an electrical
conductor but only slightly shift from their average equilibrium positions causing dielectric polarization. Because
of dielectric polarization, positive charges are displaced in the direction of the field and negative charges shift in the
opposite direction.

Dielectric constant, κ = C/C0

Where, C is value of the capacitance of a capacitor filled with a given dielectric
C0 is the capacitance of an identical capacitor in a vacuum

253. What is cross talk? Explain in detail.

A. The interference of the high switching signal on the low level signal due to the formation of coupling capacitor between
the
nets. The net in which high switching activity is there and affecting the idle net is called aggressor net. The net which is
having low switching activity and affected by aggressor is called victim net.
When aggressor net is switching and victim net is idle, we may get cross talk noise.
When aggressor net and victim net both are switching, we may get cross talk delay.

254. How to avoid crosstalk?

A. Applying NDRs, downsizing aggressor, upsizing victim, shielding victim net.

257. What is data path?

A. The path between Q pin of the launch flop and D pin of the capture flop is called data path.

258. What is OCV?

A. The process and environmental conditions may not be uniform across the different portions of the chip. Due to process
variations, identical transistors may not have similar characteristics in different portions of the chip.

259. What is process?

A. Process variation is the naturally occurring variation in the attributes of transistors (length, widths, oxide thickness)
 when integrated circuits are fabricated. The amount of process variation becomes particularly pronounced at smaller
process nodes (<65 nm) as the variation becomes a larger percentage of the full length or width of the device and as
feature sizes approach the fundamental dimensions such as the size of atoms and the wavelength of usable light for
patterning lithography masks.

260. Explain the corners.

A. Parasitics can be extracted at many corners. These are mostly governed by the variations in the metal width and metal
etch in
the manufacturing process. Some of these are:
• Typical: This refers to the nominal values for interconnect resistance and capacitance.
• Max C: This refers to the interconnect corner which results in maximum capacitance. The interconnect resistance is
smaller
than at typical corner. This corner results in largest delay for paths with short nets and can be used for max path
analysis.
• Min C: This refers to the interconnect corner which results in minimum capacitance. The interconnect resistance is
larger
than at typical corner. This corner results in smallest delay for paths with short nets and can be used for min path
analysis.
• Max RC: This refers to the interconnect corner which maximizes the interconnect RC product. This typically
corresponds to
larger etch which reduces the trace width. This results in largest resistance but corresponds to smaller than typical
capacitance. Overall, this corner has the largest delay for paths with long interconnects and can be used for max path
analysis.
• Min RC: This refers to the interconnect corner which minimizes the interconnect RC product. This typically
corresponds to
smaller etch which increases the trace width. This results in smallest resistance but corresponds to larger than
typical capacitance. Overall, this corner has the smallest path delay for paths with long interconnects and can be
used for min path analysis.
By Nandini:

262. Tell me about STA?

Ans: It is a method of validating the timing performance of the design by checking all
possible paths for timing violations under worstcase conditions.

Read lib
Read netlist
(Link the design and check any unresolved references and black box)
Read SDC
(check_timing(we should not get any unconstrained end points; clock
notfound; No drive Assertion))
Read spef
(report_annotated parasitics)
Report timing
(we need to generate timing reports for all variable paths in the design)
Analysis
(After generating the reports we should analyse all the slack, setup, hold
values)

263. Tell me about PD?

Ans: A. Inputs for PD are

1. lib (timing, functionality, power)
2. lef (physical info)
3. v (logical connectivity)
4. sdc (clock definitions)
5. cpf/upf (consists of power domain info)
6. cap table (RC values for every net)
B. Sanity checks
a)Library sanity checks (physical and logical library)
1. Missing cells and pins
2. Mismatched pins
3. Duplicate cell name
b)Design sanity checks (checkNetlist)
1. Floating pins
2. Combinational loops
3. Assign statements
4. Tristate buffers
5. Empty modules
6. Multi Driven nets
c) Constraint sanity checks
1. All flops are clocked or not
2. No unconstrained path
3. Input and Output delays
 • Floorplan (defining core and die area based on Aspect ratio and Utilization factor and
placing macros physical cells )
• Power Plan (supplying power from Pads to the Design)
• Placement (finding the appropriate location of the std cells)
• Place opt (to meeting area congestion and timing [setup])
• CTS (Distributing clock from clock port to clock pin)
• opt CTS (balancing skew and latency also DRC's to meet the timing[setup, hold])
• Routing (Connecting components physically and finding optimized net length with
introduced net delays)
• opt Routing (Assigning the track for every net and fixing the timings )
• Signoff (meeting the all requirements timing, functionality, power, area and DRC.)
264. Inputs of STA?
Ans: 1. Lib
2. netlist
3. sdc
4. Spef
265. Inputs of PD?
Ans: Technology Related inputs:
1. .lib
2. Lef
3. captables
Design Related inputs:
1. .v
2. SDC
3. CPF
266. What is Setup? How you fix setup?

Ans: The time taken by the data to be stable before the clock edge called Setup.

How to fix setup :

1. Upsizing the cell.

2. Vt swapping.
3. Pulling the launch.
4. Pushing the capture.

267. what is hold? How u fix hold?

Ans: The time taken by the data to be stable before the clock edge called hold.

How to fix hold:

1. Downsizing the cell.

2. Vt swapping.
3. Pulling the capture.
4. Pushing the launch.
5. Inserting the buffer in the data path.

271. What is BlackBox?

Ans: It consists of input and output but we cannot see the inside functionality.

272. What are the commands using entire pd flow?

Ans:

FloorPlan:

1. floorPlan -site CoreSite -r 1 0.698983 1.0 1.14 1.0 1.0

2. editPin -fixedPin 1 -fixOverlap 1 -unit MICRON -spreadDirection
clockwise -side Top -layer 4 -spreadType start -spacing 0.4 -start 4.337
750.8455 -pin {pin names}
3. addHaloToBlock 1 1 1 1 -allBlock
4. addEndCap -preCap FILL2 -postCap FILL2 -prefix ENDCAP
5. addWellTap -cell FILL8 -cellInterval 40 -fixedGap -prefix WELLTAP
PowerPlan:
1. for global net connection
globalNetConnect VDD -type pgpin -pin VDD -inst *
globalNetConnect VSS -type pgpin -pin VSS -inst *
globalNetConnect VDD -type tiehi -pin VDD -inst *
globalNetConnect VSS -type tielo -pin VSS -inst *
Placement:
1. placeDesign
2. for hard blockage (createPlaceBlockage -box <area> )
3. softblockage (createDensityArea <area> <percentage>)
4. placeDesign -incremental
5. optDesign -preCTS
CTS:
1. clockDesign
2. optDesign -postCTS
Routing:
1. RouteDesign
2. optDesign -postRoute
273. what are the commands using CTS level?

Ans: 1. clockDesign

2. optdesign-postCTS

3. report_timing

4. report_constraints –all _violators

274. Tell me ten ways to fix Setup and hold?

Ans: To fix SETUP:

1. Upsizing the cell.

 2.Vt Swapping.

3. Pulling the launch.

4. Pushing the capture.

5. Logical Restructuring.

6. Pin Swapping.

7.Cloning.

8. If net delay dominates the cell delay :

Break the net and adding buffers.

To fix HOLD:

1. Downsize the cell

2. Vt Swapping
3. Pulling the capture
4. Pushing the launch
5. Insert the buffer in the data path

276. What is OCV and AOCV?

Ans: : OCV:

Minor changes in delays due to the variations in PVT conditions.As cell delays
are varying we will apply a global derating factor then every cell having min and max delay.
All the cells are applying with same derating factor.

AOCV:

Here we r applying a derating factor based on logical depth and distance.OCV is

more pessimistic than AOCV so we r going for AOCV.

277. Create Clock Command?

Ans: create_clock -name top – period 10 -waveform (0 5) –get_ports[scan clk]

278. What is Dutycycle?

Ans: A duty cycle is the fraction of one period in which a signal or system is active known as
Duty cycle.

Duty cycle = (Ton/Ton+Toff)*100

275. What is PVT?

Ans: PVT- Process Voltage Temperature

 Best case: fast process, highest voltage and lowest temperature

 Worst case: slow process, lowest voltage and highest temperature

 Normal case: normal process, normal voltage, normal temperature

279. Make a waveform 30./. dutycycle?

Ans:

280. How many spef files used in your project?

Ans: 6 spef files

281. Cell Delay Vs VTH?

Ans: If temperatute increases mobility decreases and Vth decreases.

If temperature decreases mobility increases and Vth increases.

In lower technologies temperature decreases delay increases because it depends on threshold

voltage.

I
Because of Drain current i.e., d is inversely proportional to Vth if vth increases Id
decreases then process is slow then delay also increases.

282. which is being used currently AOCV or POCV?

Ans: POCV [Parametric On Chip Variation]:

It uses a statistical approach, it calculates delay variation by modeling the intrinsic cell delay
and parasitic of load which determines sigma and mean of a logic stage.

283. Draw a clock waveform. What is the time period of a clock with 1GHZ frequency?
Ans:

284.What is netlist? What it contains?

Ans: Logical connectivity information between combinational and sequential cells known as
Netlist. It contains 1. Module information

2. Hierarichal information

3. Input Output Notations

4. port information
 5. Instance and net names

285. What .lib contains?

Ans: It contains

1. Power Information

2. Timing Information

3. cell Functionality

4. PVT

286. Where will the data get launched and captured?

Ans:

290. What is Setup Equation?

Ans: SETUP:

R.T – A.T
R.T = Clkperiod+Capture clock latency-lib.setup time-uncertainity

A.T= Launch Clock latency+ Clk-Q delay+ combinational path

HOLD:

A.T - R.T

A.T = Launch Clock latency+ Clk-Q delay+ combinational path

R.T= Capture clock latency+lib.hold time+hold uncertainity

291. If setup checks and hold checks not done what happened? If it necessary why?

Ans: Timing doesn’t meet if we do not do setup and hold check.

292. Why NMOS is Called NMOS?

Ans: N-type metal-oxide-semiconductor logic uses N type field effect transistors

MOSFETs to implement logic gates and other digital circuits. These NMOS transistors
operate by creating an inversion layer in a p-type transistor body. This inversion layer, called
the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-
channel is created by applying voltage to the third terminal, called the gate.

293. What is NMOS and PMOS ?

Ans: NMOS: N-type metal oxide semiconductor

A NMOS transistor is made up of n-type source and drain and a p-type substrate.
When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away
from the gate. This allows forming an n-type channel between the source and the drain and a
current is carried by electrons from source to the drain through an induced n-type channel.

PMOS: P-type Metal oxide Semiconductor

A PMOS transistor is made up of p-type source and drain and a n-type substrate.
When a positive voltage is applied between the source and the gate (negative voltage between
gate and source) a p-type channel is formed between the source and the drain with opposite
polarities. A current is carried by holes from source to the drain through an induced p-type
channel. A high voltage on the gate will cause a PMOS not to conduct, while a low voltage
on the gate will cause it to conduct .

294. What is MOSFET? Draw the MOSFET Diagram?

Ans: MOSFET: Metal Oxide Semiconductor

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET,

or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by
the controlled oxidation of silicon. It has an insulated gate, whose voltage determines the
conductivity of the device. This ability to change conductivity with the amount of applied
voltage can be used for amplifying or switching electronic signals.

295. What is Transistor?

Ans: Transfer of Resistance

A transistor is a semiconductor device used to amplify or switch electronic signals

and electrical power. It is composed of semiconductor material usually with at least
three terminals for connection to an external circuit .
296. What is Inverter? Explain in Cmos Inverter logic?

Ans: It is an electronic device which changes Direct current to Alternating current.

297. What is buffer explanation in CMOS logic?

Ans:

By interchanging the positions of the NMOS and PMOS transistors in the NOT circuit can
give a Buffer and this technique uses only two transistors.

(OR)
A BUF gate is essentially constructed from two NOT gates connected in series

298. What is the function of AND,NAND,NOT?

Ans: AND: A*B

NAND: AB Bar

NOT : A Bar

299. What are opens and shots? How u fix?

Ans: Opens: Different metals with same name known as Opens.

How to fix opens:

1. Stretching the metal layers.

2. Metal jogging

Shorts: Same metal with different name known as shorts.

How to fix shorts:

1. Metal shorts:
Metal Jogging (or) change the metal layers.
2. Via shorts:
Changes the vias.

300. What is FV?

Ans: FV (Or) LEC:

It checks the functionality of the netlists

LEC Flow :

Read lib

Read golden netlist

Read revised netlist

Mapping(Names are mapping here)

Comparing

302. What kind of errors u seen in LEC?

Ans: 1. Unmapped names

303. What is Congestion? If congestion is there what happened?

Ans: Available tracks are less than Required tracks known as Congestion.

1. First we need to do set uniform density then also if we observe congestion

2. If Global congestion is there:

• The congestion which is occurring at every g-cell in the design is called global
congestion
• Due to this global congestion we are facing the improper routing (it will generate
opens)
• This is mainly occurred due to improper placement of macros and bad floor plan
To reduce the global congestion change the core size(increase area) and fixing the proper
placement area for std cells.

3. If there are notches congestion there is a possibility to apply hard blockage.

4. If there is more cell density at particular stage we r applying partial blockage and also
cell padding.

304. What is CrossTalk?Explain CrossTalk?

Ans: The voltage transition from one net to another net through coupling capacitor known as
Crosstalk.

There are two types:

1. Crosstalk Noise
2. Crosstalk Delay

Crosstalk Noise:
 If aggressor switches victim is constant known as Crosstalk noise.

If bump is above 50% it goes to metastable state(or) functionality failure.

Crosstalk Delay:

If aggressor and victim both in same direction delay decreases.

If aggressor and victim both in opposite direction delay increases.

305. What is Coupling Capacitor?

Ans:

A coupling capacitor is a capacitor which is used to couple or link together only the AC
signal from one circuit element to another. The capacitor blocks the DC signal from entering
the second element and, thus, only passes the AC signal.
306. Capacitance Formula? Explain in detail?

Ans: It is a passive element that has ability to store the charge in the form of potential
difference between plates known as capacitor.

Effect of capacitor is called capacitance.

/
C= permitivitty of dielectric* Area of plate overlap in sq.mt Distance between 2
plates

307. Tell me the manufacture process of metals?

Ans: Metal Manufacturing Processes: Production

1. CASTING
Depending on the metal and its purpose, the metal may simply be melted down and molded to
shape. This process is known as casting. Casting is best for small or intricate parts. Casting
SHOULD NOT be used for products that require high strength, high ductility, or tight
tolerances.

Dies, jewelery, plaques, and machine components all benefit from this simple production process.

2. POWDER PROCESSING

Powder processing treats powdered metals with pressure (pressing) and heat (sintering) to form
different shapes. Powdered metallurgy is known for its precision and output quality -- it keeps tight
tolerances and often requires no secondary fabrications.

However, it's incredibly costly and generally only used for small, complex parts. Powder
processing is NOT appropriate for high-strength applications.

3. FORMING

Metal forming takes a raw metal (usually in sheet metal form) and mechanically manipulates it into a
desired shape. Unlike casting, metal forming allows for higher strength, ductility, and
workability for additional fabrications.

Metal Manufacturing Processes: Fabrication

1. DEFORMATION

Deformation includes bending, rolling, forging, and drawing.

2. MACHINING

Machining refers to any fabrication method that removes a section of the metal. Machining is also
known as material removal processing. Cutting, shearing, punching, and stamping are all
common types of machining fabrication.

When planning for machining in your supply chain, hardening processes should happen AFTER
machining processes. Hardened metals have a high shear strength and are more difficult to cut.

3. JOINING

Joining, or assembly, is one of the last steps of the metal manufacturing process. This category
includes welding, brazing, bolting, and adhesives. Assembly can be done by machine or by hand.

4. FINISHING

Depending on your material and application, you may also need finishing services. Finishing includes
everything from galvanization to powder coating, and can take place throughout the manufacturing
process.

308. Why metals are placed in horizontal and vertical fasion?

Ans: At routing stage if we place metals in horizontal and vertical manner it leads to metals lays
exactly on tracks.

309. What is CTS? Explain CTS?

Ans: Before CTS we need to check:

1. All cells should be legalized.

2. All power nets are prerouted.
3. All pins should legalized.
4. Congestion, timing should control.
GOALS OF CTS :
1. To minimize the logical DRCs.
2. Balancing the skew.
3. Minimum Insertion Delay.
INPUTS OF CTS:
1. SDC
2. SPEC FILE
3. PLACEMENT DATABASE
WHAT IS CTS ?:
To distribute a clock from Clockport to Clockpin
WHY CTS?:
To minimize skew and insertion delay to build the clock tree.
Here we are generating SPEC file using clock buffers and clock inverters.
SPEC file consists of
1. Buffers list
2. Max skew
3. Min and Max Insertion delay
4. Max trans, Cap, Fanout
5. Inverters list
6. Clock tree leaf pin, exclude pin, stop pin
7. Clock name
8. Clock period
COMMANDS USED IN CTS:
clockdesign
optDesign -postCTS
CHECKS IN CTS:
1. Timing numbers
2. Utilization numbers
3. Congestion
4. All cells should legalize

311. What is CD in shell command?

Ans: change directory

312. how you make a directorie?

Ans: makedirectory(mkdir)
313. Tell me the command for directory with in a directory?
Ans: mkdir dir1
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Why physical design?
The design-cycle of VLSI-chips consists of different consecutive steps from high-level
synthesis (functional design) to production (packaging).

 The physical design is the process of transforming a circuit description into the
physical layout, which describes the position of cells and routes for the
interconnections between them.
 The main concern in the physical design of VLSI-chips is to find a layout with
minimal area, further the total wire length has to be minimized. For some critical nets
there are hard limitations for the maximal wire length.

Physical design flow

FLOORPLAN
PLACEMENT
CTS
ROUTING
SIGNOFF
Conncet putty and vncserver
FLOORPLAN
FP Inputs: .V /.SDC/.TF/.LIB/.LEF/.TLU+/TDF/
OUTPUT: DEF
mkdir project1
cd project1
cp –rf /home/vlsiguru_old/PHYSICAL_DESIGN/Trainer1/pd_training
cd pd_training
ls
cd lab_1 _import_design
csh
source /home/tools/sysnopsys/cshrc_sysnopsys
icc_shell -output_log_file ./logs/import.log
source ./scripts/import_design.tcl
copy one by one command and run it. Observe the changes in gui
start_gui

check_design
check_timing
collection of design

 sizeof_collection [get_ports] 237

  sizeof_collection [all_macros_cells] 40
 sizeof_collection [get_clocks] 8

save_mw_cel –as design imported

close_mw_cel

LAB_2_FLOORPLAN
pwd
cd lab_2_floorplan
csh
source /home/tools/sysnopsys/cshrc_sysnopsys
icc_shell –output_log_file ./logs/floorplan.log
open_mw_lib ./../lab_1_import_design/mwdb/volcano.mw
list_mw_cels
open_mw_cel design imported
sanity_checks
duming reports in file
check_design > ./reports/checkdesign.rpt
check_timing > ./reports/checktiming.rpt

 create_floorplan –core_utilisation 0.7 core_apect_ratio 2 –left_io2_core 1 –

bottom_io2core 1 –right_io2_core 1 –top_io2_core 1

To get block size

 Get_attribute[get_core_area] –bbox
Get_attribute [get_die_area] -bbox
To differentiating cells hierarchy

 set_hierarchy_colour –cycle_colour
Tool wise placing macros and standard cells

 set_fp_placement {automatic}
remove_placement –object_type -macro
 read_def /home/pd_training/pd_proj_1/inputs/volcano_fp_v1.def

If macros are more than 100 viz u can’t place manually

 set_fp_macro_array –name Aa\ -elements [list [get_cells “A11 A12”] [get_cells

“A21 A22”] -x_offset 10 –y_offset 10

using flyline analysis check the connectivity of macros and place near to core boundary

To fixing and get to know whether fixed or not

 set_attribute [get_port * ] is_fixed true

  get_attribute [get_port * ] is_fixed
 set_attribute [all_macro_cells] is_fixed true
 get_attribute [all_macro_cells] is_fixed
apply keepoutmarign

 set_keepout_marign –all_macros –type hard –outer { 1 1 1 1 }

POWER PLAN
source ./home/pd_training/pd_proj_1/pg_routing/

>> if we want to remove pg _nets

 remove_net_routing {vdd vss}

 verify_pg_nets
save_mw_cel –as fpdone
write_def – output ./outputs/fp.def

Lab_3_ Placement
cd project1
cp –rf /home/vlsiguru_old/PHYSICAL_DESIGN/Trainer1/pd_training
cd pd_training
ls
cd lab_3 _placement
csh
source /home/tools/sysnopsys/cshrc_sysnopsys
icc_shell -output_log_file ./logs/placement.log
open_mw_lib ./../lab_1_import_design/mwdb/volcano.mw
list_mw_cels
open_mw_cel fpdone
read_def ./../lab_2_floorplan/outputs/fp.def
physical only cells (tap and endcap cells)
source ./home/pd_training/pd_proj_1/insert_physical.tcl

 sizeof_collection[all_physical_only_cells]
 sizeof_collection[get_cells –hierarchical –all *tap*]
 change_selection [get_cells –hierarchical –all *tap*]
 sizeof_collection[get_cells –heirarchical –all *endcap*]
 change_selection [get_cells –hierarchical –all *endcap*]

save_mw_cel –as physical_done

Enable siterows
 source ./../lab_1_import_design/scripts/cut.row.tcl
sizeof_collection [get_site_rows]

 source ./home/pd_training/pd_proj_1/palce.tcl
>> if we want to remove standard cell
remove_placement –object_type standard cell
if no of standard pins are 5 apply

 set_keepout_margin –outer { 1 1 1 1 } [get_cells –filter “number_of_pins >5”]

>> in gui check pin density cell density and congestion.
sanity_check:
report_congestion
report_design –physical
psynopt –area_recovery –congestion
check_legality –verbose
check_mv_design –verbose
report_placement_utilization
>>all report all information cleanly observer
Report_timing –delay_type –max
if setup violation comes try to fix setup violation

 Get_lib_cells */*INV*
Swapping HVT TO LVT

 Size_cell {pin name} cell name

Size_cell {U1059} INVX4_LVT
Increase drive strength
Size_cell {U11} INVX16_HVT
save_mw_cel –as place_done
open_mw_cel –as place_done

global_congestion

Apply blockage around macro manually and Partial blockage

Bounds

 create_bound -name “I_SDRAM_TOP” –cooridanate{ 100 140 130 158 } –type hard

Write_def -output ./outputs/place.def

Save_mw_cel –as placement

Clock
cd project1
cp –rf /home/vlsiguru_old/PHYSICAL_DESIGN/Trainer1/pd_training
cd pd_training
ls
cd lab_4_cts
csh
source /home/tools/sysnopsys/cshrc_sysnopsys
icc_shell -output_log_file ./logs/cts.log
source ./../lab_1_import_design/script/library_setting_28nm.tcl
open_mw_lib ./../lab_1_import_design/mwdb/volcano.mw
list_mw_cels
open_mw_cel placementdone
or
read_def ./../lab_2_floorplan/outputs/place.def
start_gui
copy one by one command and run it. See the changes in gui
source ./script/prects
save_mw_cel –as prects
source ./script/postcts

 change_selection [get_nets *clk*]

Save_mw_cel -as postcts

Write_def -output ./outputs/ctsdone

Lab_5_ROUTING
mkdir project1
cd project1
cp –rf /home/vlsiguru_old/PHYSICAL_DESIGN/Trainer1/pd_training
cd pd_training
ls
cd lab_5_import_design
csh
source /home/tools/sysnopsys/cshrc_sysnopsys
icc_shell -output_log_file ./logs/routing.log
source ./script/routing.script
copy one by one command and run it. Observe the changes in gui
>>all report all information cleanly observe
save_mw_cel –as routing_done
open_mw_cel –as routing_done

for to get operating condition >report_scenarios

for each stage utilisation >report_placement_utilisation
icc_shell > check_physical_design -design_statistics

Information: Short Summary for Design : volcano

************************************************************************
1) Number of Std cells in design : 52965
2) Number of Inv/Buf cells in design : 7339 13 % of Std
3) Number of ICG cells in design : 23 0 % of Std
4) Number of Macro cells in design : 40
5) Number of Physical Only cells in design : 8961
6) Number of dont_touch cells in design : 0 0 % of Std
7) Number of size_only cells in design : 24 0 % of Std
8) Number of fixed_placement cells in design : 0 0 % of Std
9) Number of dont_use Std cells in design : 0 0 % of Std
10) Number of Always On cells in design : 0
11) Number of Buffers Avail in libraries : 33
12) Number of Buffers with dont_use : 0
13) Number of Inverters Avail in libraries : 45
14) Number of Inverters with dont_use : 0
15) Number of Sequential cells in design : 5387 10 % of Std
16) Number of Hierarchical cells in design : 54
17) Number of ILMs in design : 0
18) Number of Nets in design : 58087
19) Number of Ideal Nets in design : 0 0 of them Clocks
20) Number of Nets with dont_touch in design : 0 0 % of Nets
21) Number of Tristate Nets in design : 0 0 % of Nets
22) Number of Tie Nets in design : 1 H: 0 - L: 1
23) Number of Nets with NDR in design : 0 0 % of Nets
24) Number of Master Clocks in design : 5
25) Number of Generated Clocks in design : 3
26) Number of Path Groups in design : 9 0 of them Non Default
27) Number of Active Scenarios in design : Single Scenario
28) Number of Scan Chains in design : 0
29) Number of Voltage Areas in design : 0
30) Number of Bounds in design : 0
31) Number of Routing Layers in design : 10 5 of them Ignored
 Interview Focused Questions

1. Tell me about Your self (Do Yourself in simple manner)

2. Can u explain the Pd Flow?
3. What contain in .Lib
4. Where setup and hold values locates
5. What is the use of Tlu+ file
6. What is the use of Technology file
7. What IT Contain in .SDC ?
8. What is the use of Lef file
9. After getting the inputs from synthesis team what u will do?
10.What are the sanity checks after taking the data setup?
11.If any error then you will continue?
12.Before floor plan we are doing zero wire load model why we will do it?
13.If I want my block should be square how much aspect ratio I want to give?
14.If I want rectilinear mean what I have to do how I can calculate it?
15.If aspect ratio is not given what will be the block shape?
16.What is mean by utilization?
17.How you will do the macro placement?
18.What will happen when I use the command mode for placing the Macros?
19.If your Macro is power Hungry Device where you will put it?
20.If my macro is very power hungry device can I use separate power rings?
21.What is Die area? Core Area?
22.What is mean by Pad area Design and Core Limited Design?
23.Any idea about Heraclea and Flat Design? For run time which is better?
24.What you will do exactly in floor plan?
25.What is channel width? Why we should give this?
26.When you will use the Hard Blockage and Soft Blockages?
27.Will allow the Hard Blockage inverters and Buffers?
28.What is meaning by Keep out margin why we will use it?
29.Difference between keep out margin and Blockage?
30.After Floor Plan what you will do?
31.Why you will use the Power Plan?
32.Which Physical Cell is used for IR Drop?
33.What is Macro?
34.After power plan what you will do?
35.How you will do the Placement? What exactly it will do when u run the place
opt?
36.Have you seen the Place_opt Log file what it contains?
37.Why HFSN?
38.In HFSN we will Synthesizing some particular Nets what they?
39.What is mean by unit tile area?
40.Is the height of Stand’s cells?
41.What will be Height macro?
a. It will be integral multiple of the site Row
42.When you will place the physical only cells
43.What is mean by physical only cells?
44.Is there any .lib for physical only cells?
45.Can u name some physical only cells?
46.Why we need tie cells?
47.What is the use of tap cells?
48.Practically what in Latch up?
49.Tap cells will place regular interval or near
50.What is the use of filler cells?
51.In which stage you will do the filler cells
52.What you will do the after Placement
53.What is showing in the timing report?
54.Why you are checking the setup in hold?
55.What is the other check in Placement?
56.How u will reduce the congestion?
57.What is mean by partial Blockage
58.After placement what will you do
59.What are the inputs if cts
60.What in contain clock speck file
61.What are the goals of cts
62.What are the clock trees?
63.Which tree you’re using in your design?
64.After cts what you will do?
65.Can I balance the zero skew? Why?
66.By default tool what tool report local or global skew?
67.How you will build the clock tree?
68.What is the difference between clock buffers and normal buffers
69.Why we need equal rise and fall?
70.Clock buffers requires more area
71.Which is better clock inv or buff?.
72.After cts what you will do
73.How you fix the Hold?
74.Uncertainty on which what factor it will depend
75.Uncertainty Percentage?
76.What are cts exceptions?
77.What is mean by nonstop pin?
a. Clock reaching to D pin of the ports so it will think like it is sink pin on
that time we have intimate the tool there is another flop is available
consider that flop as a sink pin.
78.Why we call it is generated clock? Why we are using this?
79.What is mean by false path and MCP?
80.Half cycle path?
81.Is hold depended on time period Half Cycle path?
a. Yes. T period/2. Hold depends on timepeiod in HCP.
82.What is mean Virtual clock?
83.Where it will use in constraints?
a. In – Reg and Reg to out to define set input delay and to define set out put
delay
84.When you will use the set max delay?
a. In to out path
85.What are the timing Paths?
86.After cts whichVoilation your perform?
87.Routing what it will exactly do?
88.What Is mean by search and repair?
89.What are the goals of routing?
90.After routing which file your creating?
91.Why we will give routing?
92.Where you analysis the cross talk in data path or clock path?
93.In my Design 9 metal are there which metal you use for differ section?
94.HV VH HH? Why I don’t use the HH VV?
95.How to avoid the cross talk?
96.You have any idea for antenna effect?
97.How you will reduce it?
98.What is mean by electron migration?
99.You have any idea about ECO Stage?
100. For scan chain which file you need?
101. You know anything on sign off stage?
102. What is mean by LVS?
103. What is DRC s in PV?
104. Tell the basic PD flow?
105. Tell me the what are the inputs for Icc1?
106. What are OCV concepts?
107. On which corner Setup /Hold Depends?
108. What are the parasitic corners?
109. What file u need when your design is Multivoltage Design?
110. In reg – reg which clock you use?
111. Is there any library for physical only cells?
112. What is mean by clock gating why we use it?
113. What is the use of Scan chain Reorder?
114. What is your clock frequency in your design?
115. How many master clocks in your design?
116. What is your block shape?
117. What is the utilization on each stage?
118. What is the congestion value in each stage?
119. What is the area of your block?
120. What is the height of your block and standard cell and Macros?
121. In placement stage when to timing report it will show the report for max
by default what it is?
122. What is mean by gating?
123. What is the use of clock spec file?
124. What are clock Tress? Which clock you’re using in your design?
125. In industry which clock we are using mostly?
126. What is the utilization factor for design?
127. What does spef file contain?
128. For which input we are using the SPEF?
129. Check timing command which file it will check?
130. Tlu + file which command will use for checking sanity checks in before
placement?
131. How you will fix the setup by command?
132. How may macros in your design how you will find it?
133. How many clocks are there in your design?
134. How you will connect from M1 standard cell to M9 routing?
135. Actual routing which metal layer we are use?
136. In which corner you will find the setup and hold?
137. What exactly Slow Slow Corner shows?
138. Have you seen Slow slow corners in your design ?
139. Check _timing what it will give?
140. How you will do the your floor plan ?
141. What it contain pg routing .tcl file ?
142. What contain in def file ?
143. What contain in technology file ?
144. What contain in lib file ?
145. What contain tlu pluse file ?
146. What contain in sdc ?
147. What contain tdf file ?
148. What is the meaning of scan chain reorder ?
149. Why we will do the power paln ?
150. How you will fix the macros tell me command ?
151. How you will palace the macros ?
152. How did you do the power plan?
153. What is mean by ocv?
154. What is the formula for channel width between the macros ?
155. Explain routing?
156. What u did in placement stage ?
157. What are the sanity checks in after floor plan ?
158. Is setup violation accrued after floor paln ?
159. How will fix the setup violation after cts ?
160. What it will do the check_design sanity check? Which file it is going to
check?
161. What exactly check_timing do? Which file it is going to check?
162. What exactly it will do Check_library, check_mv_design, check_netlist
which type of errors it will report and which files it is going to check and if u
have any errors in this file for whom you have to report?
163. Can u tell me the PD full flow in Short?
164. Why STA? Why not DTA?
165. On which is we will find setup and Hold? Why?
166. Why we are closing at Multiple PVT Corners?
167. What are the timing/SDC Constraints?
168. What is mean by case analysis how we will use it?
169. What the equation for setup and hold?
170. How to make a chip work that has setup violation after Tape Out?
171. How to make a chip work that has Hold Violation after Tape out?
172. What are the clock gating checks?and related constraint commands?
173. What are reset recovery removal and related commands?
174. How to find the max frequency in the design?
175. How to find the setup and Hold slack?
176. What is OCv how we will account it for timing violations?
177. How you will reduce the DRC with End cap cells?
178. How to tell the tool to use usefullskew for fixing the violation?
179. How you will do cell swapping? And write command?
180. How you will do Buffer insertion? And write command?
181. What are ways to reduce the setup hold DRV Physical DRC violations?
182. How the relation for leakage and delay for HVT LVT RVT cells?
183. If timing is more critical which cells I have to use why?
184. If leakage is more which cells I have to use why?
185. What is mean MCP, FP how you will Constrain it?
186. What are the NDR Rules why this rules?
187. What are the inputs and outputs for Prime time?
188. What are the input and output files for each stage in physical design?
189. What are the input and output files for Star RC?
190. Why parasitics are extracted what are the commands to do it?
191. What is mean by
1. Skew
2. Insertion Delay
3. Global skew
4. Positive /Negative skew
5. Uncertainty
6. Jitter
7. Arrival/required path
8. Propagation delay
9. Latency – source – networkLatecny
10.Useful skew
11.HCP
12.Slack
192. What is Tcl why we use it ?
193. What are the TCL files you use what it contain exactly in that tcl at each
stage?
194. What is cell and pin density how you will resolve it?
195. What are timing exceptions?
196. Which buffers and inverters you used in While building the clock tree?
197. Who have a setup violation 1ps after doing all ways to fix it what you will
do you will fix or leave?
198. Explain the setup and Hold with D flipflop? And with wave forms?
199. How you will calculate the cell delay and net delay?
200. What is mean By CRPR where you use it why?
201. What is the difference between normal pulse width minimum pulse width?
202. What is mean by NLDM,CCS,WLM? Why we using this?
203. What is Antenna Effect and EM and ESD?
204. How you will fix the opens and shorts?
205. How you fix the timing violations in cts stage?
206. Tell the which commands you used in Unix?
207. What is 28nm ? what is the difference to other nm to use 28nm only in
your design?
208. Count of gates , instances, macros, Input and output ports?
209. Difference between Pin and port?
210. How you will synthesis your clock tree?
211. Have you meet the skew which you targeted if not how you will met?
212. What the reports you generated in each stage?
213. What it contains the information of each report when you generate the
reports at each report?
214. Go for all Formulas Stdcell Utlization, channel width, Congetion…E.t.c
215. What is the operating voltage for your design?
216. How many corners you used in you design?
217. Why setup at SS?
218. Why Hold at FF?
219. What are the Placement Bounds? How will use?
220. If u have a congestion macro macro which blockage u will use now?
221. If u have a congestion of macro to Core Boundary which blockage you will
use?
222. Why your using IO Buffers?

Please Go to all commands ones some companies will ask only commands
also some will ask both at each stage don’t skip any topic if u skipped mean they
will ask on that only.
 Company1:-
1. Tell me about your exp.?
2. What are the inputs and sanity checks for your design?
3. In netlist sanity checks, what about output floating?
4. If input floating is there, what kind of functionality failures we will get?
5. What kind of glitches we will get in netlist sanity checks if we have input floating?
6. What are the effect of empty module in your design and how you will remove it?
7. From where you will get your clock related information and timing exceptions?
8. What is meant by set_input_delay and set_output_delay in SDC?
9. How to check the multiclocks driven by a single flop in ur design?
10. What kind of library checks you will do in your sanity checks?
11. What type of material we will use for welltap cells?
12. Tell me about macros placement guidelines?
13. What you will do in your tool for efficient usage of your macros channel?
14. What are the floorplan checks we will do?
15. What about dynamic power consumption when we are coming down to lower
technologies from higher technologies?
16. What is the minimum distance between tap cells in your block?
17. What is Latch-up & how tap cell will avoid latchup?
18. What is the usage of tie-high & tie-low cells?
19. Tell me about timing @placement level?
20. Tell about congestion in between macros and how to avoid that?
21. Tell me about placement congestion in your design?
22. What are the placement quality checks we will perform?
23. What are the inputs for CTS(Clock Tree Synthesis)?
24. Tell me about NDR rules?
25. What is crosstalk delay and crosstalk noise?
26. Tell me about timing window?
27. What is congestion?
28. Tell me about cross-talk fixes?
29. What are the skew otimization techniques you did in your design?
30. How we will improve Insertion Delay?
31. What is Uncertainity, Jitter & Extra Margin?
32. Positive skew helps in what? Is Setup or Hold?
33. Negative skew helps in what? Is Setup or Hold?
34. Why we are not taking care about hold before CTS? Why only Setup?
35. Tell me about setup & Hold fixing techniques?
36. How you will improve transition?
37. What is HFNS and why we need it?
38. Tell me about H-Tree based CTS and tree balancing?
39. Why CTS is required?
40. What are major parameters did you saw in your timing report?
41. What is LEC & What you will check it from formaity tool?
42. What kind of DRC & LVS checks did you performed?
43. What are the challenges you gone through your design?
44. What is IR Drop and fixes for IR-Drop? (Static & Dynamic)
45. What is Antenna Violation and you will fix it?
46. Why we are not doing layer hopping with lower metal layers for Antenna violation
fixing?
47. What is CPPR & CRPR?
48. In which corner you did your CTS?
49. How many corners you used in your design?
50. What is MMMC?
51. If you are having setup & Hold in same path what you will do?
52. In shielding, why we are not doing with VDD?
53. What is negative setup time? How it will be useful for your setup slack calculation?
54. If cell overlapping (or) Redundancy is there in your design @placement level, what
you will do?
55. What is bound (or) Region? And ICC commands for creating and removing of
bounds?
56. What is path group & What are path groups you used in your design?
57. What is Multicycle Path & False Path?
58. What is a HALO?
59. What are differences between OCV, AOCV & POCV?
60. What kind of cells you used in your desingn @CTS stage?
61. Tell me about manual ecos at prects stagee?
62. How will you apply derating for your block?
63. What is min.pulse width?
64. Tell me about different models which you gone through?

Company 2:-
1. Why NDR for clock nets?
2. What will happen if your skew is zero?
3. Tell me about DPT(Double Patterning Technology) issue?
4. Fast to slow & slow to fast approach in multicycle path?
5. At which stage we will use our TLU+ files? What it is having?
6. create_placement, what it do?
7. Why we are having macros placement rules?
8. How will you make that your setup is good @placement level?
9. Timing is good Congestion is good Which is good placement approach?
Congestion is bad Timing is bad
10. What is slew rate?
11. Tell me about Interclock skew balancing?
12. In placement stage, what is 2-pass approach?
13. Why we are placing the macros @boundary of core ony?
14. What is your skew target and ID target?
15. Tell me about routing blockages?
16. How to calculate channel length in between your macros?
17. How many number os shorts & opens you have in your design?
18. Tell me about violation min. spacing rule?
19. ICC command for power straps creation?
20. If you have 500 shorts in your design after routing, what is your approach to fix it?
21. Why we are using clock BUFF/INV over normal BUFF/INV in CTS?
22. In Half cycle path, where you will check your Setup & Hold?
23. What could be reason for Setup & Hold on same path?
24. Why we are getting clock transition in clock spec. file, if we have already this in
SDC file?
25. What are different types of complex cells you have in your design?
26. Is Hold is frequency dependent or independent?
27. How many delay corners have in your design?
28. What is buffering and What is Cloning?
29. Tell me about CTS flow?
30. What are the different timing fixes you gone through?
31. How your input delay will effect your Setup & Hold slacks?
32. Tell me about timing ecos and functional ecos?
33. What is std. cell abutted placement?
34. Tell me about timing driven and congestion driven placement?
35. What kind of reliable checks you will perform for your block?
36. Why keepout margin for macros?
37. What kind of manual fixes you did @physical DRC fixes?
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