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Comp206 Inclass8

The document discusses the processor architecture and pipelining. It covers topics like datapath elements, control units, hazards, forwarding, and improving performance through pipelining. It provides examples of MIPS code and pipeline diagrams.

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huseyinefekaragoz
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22 views20 pages

Comp206 Inclass8

The document discusses the processor architecture and pipelining. It covers topics like datapath elements, control units, hazards, forwarding, and improving performance through pipelining. It provides examples of MIPS code and pipeline diagrams.

Uploaded by

huseyinefekaragoz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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COMP206 – Computer Architecture

Inclass #8

Chapter 4 — The Processor — 1


Buse Yılmaz, PhD.
Dept. of Computer Engineering, MEF University
buses
several
CPU Overview lines

next inst.
branch write data from ALU/mem.
back into reg.

addr. calcul. read/write data


op. exec. for load/store

Chapter 4 — The Processor — 2


Multiplexers

can’t just join wires together:


use multiplexers

Chapter 4 — The Processor — 3


PC = (PC + 4 or the branch destination address)
zero output of the ALU AND a control signal that indicates that the instruction is a branch

output of the ALU (arithmetic- Control Unit


logical instruction) or
the output of the data memory
(load) for writing into the register
file

second ALU input = from the


registers (arithmetic-logical
instruction/branch) or from the
offset field of the instruction
(for a load or store)
Datapath Elements
• Datapath: the combination of a set of registers with a shared ALU and
interconnecting paths performing an operation
• Combinatorial datapath elements
 Operates on data values & elements
 Output depends on current input, no internal memory, deterministic (same inputs → same
output)
 e.g. ALU

• State elements

Chapter 4 — The Processor — 5


 Internal storage
 Instruction & data memories & registers
 Inputs: data value & clock (determines when the value will be written)
Datapath With Control

Chapter 4 — The Processor — 6


Review Questions
• Identify the pipeline
stages and portions of the
processor that are
involved in these pipeline
stages.

Chapter 4 — The Processor — 7


Single-Cycle Pipeline Diagram
• State of pipeline in a given cycle

Chapter 4 — The Processor — 8


Identifying the Datapath for a MIPS Instruction

Chapter 4 — The Processor — 9


Homework
• What does the MIPS code snippet do?

• With the help of the data & control paths you’ve seen in
the lecture and MARS X-Ray, identify the full data &
control path of this MIPS snippet.

• The X-Ray components are available on BB

Chapter 4 — The Processor — 10


Performance Issues
• Longest delay determines clock period (cycle time)
 Critical path: load instruction
 Instruction memory → register file → ALU → data memory → register file

• Pipelining improves the performance by


 Executing multiple instructions simultaneously
 Multiple instructions are overlapped in execution

Chapter 4 — The Processor — 11


MIPS Pipeline
• Five stages, one step per stage
 IF: Instruction fetch from memory
 ID: Instruction decode & register read
 EX: Execute operation or calculate address
 MEM: Access memory operand
 WB: Write result back to register

Chapter 4 — The Processor — 12


• Pipeline depth:
 the number of simultaneous stages that may be completed at once
Pipeline Performance
Single-cycle (Tc= 800ps)
write register:
• first half of a cycle
read register:
• second half of a cycle
Time for stages:
• 100ps for register read or
write
• 200ps for other stages
Pipelined (Tc= 200ps)
Multi-Cycle Pipeline Diagram
• Same diagram but
in the form
showing resource
usage

Chapter 4 — The Processor — 14


Hazards
• Situations that prevent starting the next instruction in the next cycle
• Structure hazards
 A required resource is busy

• Data hazard
 Need to wait for previous instruction to complete its data read/write

Chapter 4 — The Processor — 15


• Control hazard
 Deciding on control action depends on previous instruction
Data Hazards
• Occurs when the pipeline must be stalled because one step must wait or another to
complete
• Data hazards arise from the dependence of one instruction on an earlier one that is
still in the pipeline
 add $s0, $t0, $t1
sub $t2, $s0, $t3

Chapter 4 — The Processor — 16


Without intervention, a data hazard could severely stall the pipeline: the
add instruction doesn’t write its result until the fifth stage, meaning that
we would have to waste three clock cycles in the pipeline
Forwarding (aka Bypassing)
• Use result in ALU when it is computed
 Don’t wait for it to be stored in a register
 Requires extra connections in the datapath
 There cannot be a valid forwarding path from the output of the memory access stage
in the first instruction to the input of the execution stage of the following

Forwarding: EX → EX

Chapter 4 — The Processor — 17


replaces the value from register
$s0 read in the second stage of sub
Load-Use Data Hazard
• Can’t always avoid stalls by forwarding
 If value not computed when needed

Forwarding: MEM → EX

Chapter 4 — The Processor — 18


Exercise #1
• Describe the dependencies in the given code block
add $t1, $t2, $t3
sub $t4, $t1, $t5
and $t6, $t1, $t7
or $t8, $t1, $t9
xor $t10, $t4, $t11
Draw multi-cycle diagram of the code with and without forwarding

Chapter 4 — The Processor — 19


•
Exercise #2
• How many cycles does the following code block take with forwarding?
lw $t1, 0($v0)
add $t1, $t1, $t1
lw $t2, 4($v0)
mul $t1, $t1, $t2
lw $t2, 8($v0)
mul $t1, $t1, $t2

Chapter 4 — The Processor — 20


lw $t2, 12($v0)
mul $t1, $t1, $t2
sw $t1, 16($v0)

• How many cycles does the code block take with forwarding and reordering?

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