Scribd
Upload
17 views

Data Flow Model

The document describes the components and data flow of an ARM processor core. It has functional units connected by data buses that process instructions and data through registers. The core uses a load-store architecture where load instructions copy data from memory to registers and store instructions copy from registers to memory, with all data processing done in registers.

Uploaded by

Jyothsna
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
17 views

Data Flow Model

The document describes the components and data flow of an ARM processor core. It has functional units connected by data buses that process instructions and data through registers. The core uses a load-store architecture where load instructions copy data from memory to registers and store instructions copy from registers to memory, with all data processing done in registers.

Uploaded by

Jyothsna
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

A programmer can think of an ARM core as functional units connected by data

buses,
as shown in Figure 2.1, where, the arrows represent the flow of data, the lines
represent the
buses, and the boxes represent either an operation unit or a storage area. The figure
not only the flow of data but also the abstract components that make up an shows
ARM core.
Data enters the processor core through the Data bus. The data may be an instruction to
execute or a data item. Figure 2.1 shows a Von Neumann implementation of the ARM
data items and instructions share the same bus. In contrast, Harvard
the ARM use two different buses. implementations of
The instruction decoder translates instructions before they are
instruction executed belongs to a particular instruction set.
executed. Each
The ARM processor, like all RISC processors, uses a load-store
architecture. This
means it has two instruction types for transferring data in and out of the
instructions copy data from memory to registers in the core, and conversely processor: load
the store

19
Data
Instruction
decoder
Sign extcnd
Write Read
rl5
Register file Rd
pc
Result
Rn A Rm B

AB|Acc
Barrel shifter
N MAC

ALU

Address register
Incrementer
Address

2.1 ARM core dataflow model.

instructionscopy data from registers to memory. There are nodata


that directly manipulate data in memory.
Thus,
processing instructions
registers. data processing carried out solely in
is
Data items are placed in the register file-a
Since the ARM core is a 32-bit processor, most storage bank made up of 32-bit registers.
signed or unsigned 32-bit values. The sign extend instructions treat the registers as holding
numbers to 32-bit values as they are read from hardware converts signed 8-bit and l6-bit
ARM instructions typically have two source memory and placed in aregister.
destination register, Rd. registers, Rn and Rn, and a single result or
buses Aand B, Source operands are read from the register file using the internal
respectively.logic unit) or MAC
The ALU (arithmetic
ter values Rn and Rm
from the Aand Bbuses (multiply-accumulate unit) takes the regis
instructions write the result in Rddirectly to the and computes a result. Data processing
use the ALUtogenerate an
address to be
register file. Load and store instructions
Address bus. heldin the address register and broadcast on the
One important feature of the ARM is that register Rm alternatively can be preprocessed
in the barrel shifter before it enters the ALU. Together the barrel shifter and ALU can
calculate a wide range of expressions and addresses.
After passing through the functional units, the result in Rdis written back to the register
ile using the Result bus. For load and store instructions the incrementer updates the address
register before the core reads or writes the next register value from or to the next sequential
memory location. The processor continues executing instructions until an exception or
interrupt changes the normal execution flow.
Now that you have an overview of the processor core we'l take a more detailed look
at some of the key components of the processor: the registers, the current program status
register (psr), and the pipeline.

You might also like