Bangladesh University of Engineering and Technology

Course: EEE 106(S)

Experiment No: 02
Experiment Name: Steady State Analysis , Frequency Response and Filters

Date of experiment: 13-07-2023

Date of submission: 28-07-2023

Submitted by:
Muhammad Al Mustakim
Student ID: 2106023
Section: A1
Department: Electrical and Electronic Engineering
Lab Partner’s ID: 2106024

Instructed by:
1. Dr. Ahmed Zubair
2. Sadman Sakib Ahbab
Example circuit – 1:
Manual Calculation:

For practice circuit in the second experiment , there is a task to determine the different parameter’s
value of that circuit such as Capacitor’s voltage-phase and so on . For completing that , I did hand
calculation regarding the parameters of that circuit and found the values of Voltage of particular node ,
Capacitor current magnitude and phase , Current through the resistance ( magnitude and phase ) . The
hand calculation for the first circuit is shown below :

and later I verified it from the probe of schematics and netlist coding . They are gradually below .
Schematics Diagram: I used frequency sweeping here thus the graph wouldn’t come a point –
therefore – it is easy to understand the values using toggle cursor .

circuit-1 ( Steady State Analysis )

Schematics Result :

1.
 Fig-1 : Capacitor’s Voltage Magnitude

Explanation : At 60 Hz steady state condition – the magnitude of capacitor voltage is shown here
120.277 V – which corresponds to the manual calculation and netlist result (later) . Thus the circuit
calculation gets verified .

2.

Fig-2 : Capacitor’s Voltage Phase

Explanation : Here by using toggle cursor – placing it to the x axis domain 60Hz , I found the phase of
Capacitor’s voltage ( or node-3 voltage ) is -3.33° . Which completely corresponds with the manual and
netlist result .
3.

Fig-3: Capacitor’s Current Magnitude

 Fig-4 : Capacitor’s Current Phase

Explanation : Here both magnitude and phase correspond with the manual and netlist result . The
magnitude and phase of capacitor’s current are gradually 6.0125 A , phase 86.67°. Thus the circuit is
verified.

4.

Fig-5 : The magnitude of Resistor Current

 Fig-6 : The phase of Resistor Current

Explanation : Here we got the magnitude and the phase of resistor current 6.0139 A and -40.201° .
These both correspond to the manual calculation and netlist result . Hence , The circuit is verified .
1. Input Coding in notepad for the circuit :

2. Output from netlist :

Explanation : Here we can see all the parameters of the circuit those were required to be verified
correspond with the manual calculation and schematics result . Hence the steady state analysis has
become successful and verified . Job Concluded for circuit-1 .

Exercise-2 : Constructing a highpass filter and calculating cutoff frequency .

Verifying that with the schematics diagram .
Manual Calculation: A At first the given circuit has been solved by the pen-paper . By solving that I got
the cutoff frequency 1001 Hz . Thus I calculated voltage magnitude and phase in that particular
frequency . The voltage came 0.707 Volt having angle 45° . Then I had constructed that circuit to the
schematics and observed the graph . By the help of cursor , I pointed to the voltage magnitude and
found the cutoff frequency of this circuit 1001 Hz (approx) . I again checked by taking the criteria phase
in the y axis and I pointed the range 45° - consequently – again the same result came . Thus the circuit is
verified .

.
Schematics Diagram :

1.

2.
 Fig-7 : Schematics Diagram and Results

Explanation: From the graphs we can easily notice that the results correspond to the manual calculation.
In the 2nd graph , It indicates high-pass filter that actually does allow to pass the upper frequencies than
a particular frequency to pass – and – resists the lower frequencies of that particular level . Theoritically
That particular voltage level is 0.707V . However , it is not an ideal high pass filter – if so – that wouldn’t
allow the lower frequencies to pass which are less than 1001 Hz. It is clearly seen from the 2nd graph . As
for unable to be an ideal high-pass filter , It also prohibits to pass some of the frequeny ranges despite
they are higher than 1001 Hz. So the slope of the graph is not actually ∞ , whereas , the slope of an
ideal filter must be ∞ . We consider the filter to pass (1/√2) portion of the provided voltage and as that
we can see from the 2nd graph – 0.707V . Again if we discuss about the phase of the voltage at cutoff
frequeny theoritically , that should be 45° . We see from the 3rd graph ,it is also verified that at the
1000Hz point of domain x , the phase is approximately 45° in the range correspondingly . Hence the pen-
paper calculation does match with the schematical diagram and hence our experiment is right . Job
concluded .
Exercise-1: Devising an interpretational formula to use a different magnitude of
AC Voltage Source and explanation about cutoff frequency.
Manual Calculation:

According to the theory , Output does not depend on the magnitude and Phase of Voltage source . The
maximum gain would be changed if the magnitude is changed , But the cutoff frequency would be
shown up as previous when I used 1V AC source . Where to occur cuttoff frequency is indeed
independent of Voltage magnitude .

The method through which we can calculate the cutoff frequency in terms of plot (dB vs frequency) is
shown in the hand calculation . In brief , Cutoff frequency can be found when the dB level drops down
3dB from it’s peak value . If we use toogle cursor to point that value – automatically the x co-ordinate (
frequency ) would be shown at the probe window . Hence determinig cutoff frequency is relatively easy
– and – according to the theory that should be remained constant irrespective of the magnitude. Now
it’s time to verify the result of theory .

Schematical Diagram :

Fig-8: Schematical Diagram of the required circuit

Here I take 6V AC source having 0° phase angle as the question states .

 Fig-9: The desibel graph of the circuit

Explanation : Here we can see from the output of schematical frequency sweep probe window , The
graph has initially started from it’s peak and started to decay continiously . When the graph decays -3dB
then pointing the toogle cursor , we can see from the graph that the cutoff freuency is 12.771 kHz –
Which is pretty much near to it’s original value . Hence our circuit is verified .
Exercise-3: Constructing a band-pass filter by cascading a high-pass and a low-
pass filter.
Here our task is to construct a band-pass filter . Band-pass filter allows certain amount of signal to pass –
and other’s to attenuet . We shall do this by combining a high-pass and a low pass filter . According to
the question , I used RC circuits combination as the filter . The filter’s schematic diagram is shown below.
The frequency where the gain is maximum , that frequency is called center frequency .

Schematic Diagram:

Fig-10: Cascaded Band-pass Filter

Here first part is a low-pass filter and second part is a high-pass filter.
Fig-11: Determination of center frequency

Fig-12: Determination of cutoff frequencies

Explanation : Here from the circuit output we can easily notice the maximum point of the graph is at the
frequency of 3.5847 kHz . And that is our required center frequency . In that point , the gain ( ratio of
output and input ) is maximum . Again , we recall that where the dB level drops down -3dB that
corresponding frequency is known as cutoff frequency . Now a band-pass filter contains two cutoff
frequenies. Pointing the toogle cursor to the exact desibel level , we can easily find out the required
frequencies . From the graph , We can see those are respectively 778 Hz and 16.505 kHz . Job
concluded.

Exercise-4: Checking the second order filters and analysing those which to be
low-pass , band-pass and high-pass.
I constructed the given circuits to the schematics and analysed the results – and – identified those which
to be low pass and which to be high-pass and so on .

1. Schematic Diagram:

Fig-13: 1st RLC circuit

Schematic Result:

Fig-14: Verification graph

Explanation: We can easily see this RLC circuit allows to pass low frequency signal to pass and
further it attenuetes higher frequency . Thus , the filter is a low-pass filter .
2. Schematic Diagram:

Fig-15: 2nd RLC circuit

Schematic Result :

Fig-16: Verification graph

Explanation: Here we can see the circuit allows to pass high frequency signal and inhibits low
frequency signals . And so our 2nd circuit is High-pass filter.
 3. Schematic Diagram:

Fig-17: 3rd RLC circuit

Schematic Result:

Fig-18 : Verification Graph

Explanation : Here the circuit allows to pass certain amount of frequency signal . It attenuetes other
frequencies . So , the filter is a band-pass filter .
4. Schematic Diagram:

Fig-19 : 4th RLC circuit

Schematic Result :

Fig-20: Verification graph

Explanation : Here – Alike the 3rd graph – this is also a band-pass filter . I think all the values of
circuit elements of both circuits have been taken the same and so the graph is very identical to
each other .
5. Schematic Diagram:

Fig-21: 5th RLC circuit

Schematic Result:

Fig-22: Verification graph

Explanation: This circuit attenuetes a certain amount of signal having particular frequency and
allows to pass else signal . So the filter is band-stop filter .
Conclusion.