Scribd
Upload
11 views20 pages

Lab6 Wlos Baseline - Workbook

The document describes a workload optimized SOC baseline project. It details firmware implementations of matrix multiplication, quick sort, FIR and UART/ISR. It provides instructions for simulation and FPGA implementation, including block design, verification steps and submission guidelines.

Uploaded by

洪啟恩
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
11 views20 pages

Lab6 Wlos Baseline - Workbook

The document describes a workload optimized SOC baseline project. It details firmware implementations of matrix multiplication, quick sort, FIR and UART/ISR. It provides instructions for simulation and FPGA implementation, including block design, verification steps and submission guidelines.

Uploaded by

洪啟恩
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 20

Lab6

Workload optimized SOC – baseline


Content
● Specification
○ Firmware
■ Matrix Multiplication
■ Quick Sort
■ FIR
■ ISR – UART/rx & tx
○ Hardware
■ Lab4-1 – exmem
■ UART
● Verification
○ Simulation
○ FPGA Implementation
■ Block Design
■ Notebook
Firmware – Matrix Multiplication
● 4*4 matrix matrix multiplication

1 cd ~/caravel-soc_fpga-lab/lab-wlos_baseline/testbench/counter_la_mm
2 source run_clean
3 source run_sim
Firmware – Quick Sort
● 10-elements quick sort

1 cd ~/caravel-soc_fpga-lab/lab-wlos_baseline/testbench/counter_la_qs
2 source run_clean
3 source run_sim
Firmware – FIR
● Same as Lab4-1

1 cd ~/caravel-soc_fpga-lab/lab-wlos_baseline/testbench/counter_la_fir
2 source run_clean
3 source run_sim
Firmware – UART
Firmware – UART
Firmware – UART
Firmware – UART
Firmware – UART
Firmware – ISR (UART/rx & tx)
● As receiving rx, user project needs generate interrupt to make CPU jump to
Interrupt Service Routine (ISR)
○ Setting CSR
■ https://github.com/bol-edu/caravel-soc_fpga-lab/blob/main/lab-wlos_
baseline/firmware/crt0_vex.S#L102-L104
○ After interrupt triggers, CPU jump to trap_entry
■ https://github.com/bol-edu/caravel-soc_fpga-lab/blob/main/lab-wlos_
baseline/firmware/crt0_vex.S#L15-L53
○ And then call function isr()
■ https://github.com/bol-edu/caravel-soc_fpga-lab/blob/main/lab-wlos_
baseline/firmware/isr.c
● On ISR, it receives rx and send tx
○ https://github.com/bol-edu/caravel-soc_fpga-lab/blob/main/lab-wlos_baseli
ne/firmware/isr.c#L37-L38
Firmware – ISR (UART/rx & tx)
● No Parity bit in our design
● Baud rate = 9600
User Project Memory Starting: 3800_0000
Hardware Scope & Hierarchy User Project UART Base Address : 3000_0000

User project (Synthesize the User Project)

Module to design
WB Decode Recall from Lab4-1
WB-interface WB-interface RAM module provided

UART top module exmem-FIR From previous project


IRQ to CPU
UART_RX UART_CTRL UART_TX bram.v
(ram_style)
● Refer to
https://github.com/bol-edu/
caravel-soc_fpga-lab/tree/
main/lab-wlos_baseline/rtl/
user

from mprj_io[5] to mprj_io[6]


Simulation

1 cd ~/caravel-soc_fpga-lab/lab-wlos_baseline/testbench/uart
2 source run_clean
3 source run_sim
FPGA Implementation – Block Design
● The workflow is similar to Lab5, but different block design

Caravel ReadROM
spiflash BRAM
code

CPU Reset Control


PS
Interconnect
Wishbone Caravel PS
mprj[6](tx)
UART axi-uartlite
mprj[5](rx)
irq
Interrupt
Control
FPGA Implementation – Block Design

caravel_uart – rx
caravel_uart – tx axi_uartlite – rx

axi_uartlite – tx
FPGA Implementation – Notebook
● Refer to
https://github.com/bol-edu/caravel-soc_fpga-lab/blob/main/lab-wlos_baseline/vivado/jupyter_notebook/
caravel_fpga_uart.ipynb
What you need to do
● Replicate baseline experiment
○ Simulation on Matrix Multiplication, Quick Sort, FIR and UART separately
○ UART FPGA
● Firmware code integrates Matrix Multiplication, Quick Sort, FIR and UART
● Hardware integrates exmem-fir with UART design in user project area, like Lab4-2.
● Simulation
○ Modify testbench to include the test for Matrix Multiplication, Quick Sort, FIR and UART
● Run on FPGA
○ Verify if the firmware code can execute on FPGA
Notice
● 40Mhz on axi-uartlite and caravel
● It will take 15 minutes on synthesis and implementation
● 5 slave channel on axi-interconnect
● Only support for non-continuous tx/rx on our UART design.
● If you finished hardware, copy the files under rtl/user folder to vivado/vvd_src/caravel_soc/rtl/user
● For verification on FPGA, you need the following files uploading to PYNQ
○ caravel_fpga.bit
○ caravel_fpga.hwh
○ caravel_fpga_uart.ipynb
○ uartlite.py
○ uart.hex
Submission Guideline
● Report
○ How do you verify your answer from notebook
○ Block design
○ Timing report/ resource report after synthesis
○ Latency for a character loop back using UART
○ Suggestion for improving latency for UART loop back
○ What else do you observe
● Required files for FPGA
● Firmware code that you integrate all task
● Github link

You might also like