A B C D E

1 1

NBQAA
2
Bordeaux 10G 2

LA-6072P REV 1.0 Schematic

3
Intel Arrandale CPU / Intel 5 Series Chipset 3

2010-03-22 Rev 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 1 of 61
A B C D E
 A B C D E

Compal Confidential Fan Control VGA Thermal Sensor Clock Generator

Intel Arrandale APL5607 ADM1032ARMZ-2 SLG8SP587VTR
Model Name : NBQAA PCIE-Express 16X 2.5GHz page 6 page 14 page 25

File Name : LA-6072P (2C,35W)

1 1

rPGA-989 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

VGA (DDR3) Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5,6,7,8,9,10 1.5V DDRIII 800/1066 MT/s

N11M-OP1,64bit with 512MB/1GB
N11P-LP1,128bit with 1GB USB Conn Fringer Printer
page 13,14,15,16,17,18,19,20,21,22,23,24 FDI X8 DMI X4 USB port 0,1 USB port 8
page 37 page 38
2.7GHz 2.5GHz

Int. Camera BT conn

USB USB port 11 USB port 5
EC_SMB 5V 480MHz page 25 page 38
HDMI-CEC LCD Conn. CRT
page 27 page 25 page 26

2 2

PCIeMini Card PCIeMini Card

WiMax 3G Express Card
Intel 5 Series Chipset USB PCIe port 2
USB port 13
USB port 10
5V 480MHz page 39 page 39
PCIe 1x PCIeMini Card PCIeMini Card USB port 4
HDMI Conn. HM57,HM55 1.5V 2.5GHz(250MB/s) WLAN JET
PCIe port 2 PCIe port 4 PCIe port 3
USB port 13
page 39 page 39 page 39
page 27

LAN SATA port 1 SATA HDD

RTL8105E 10/100M 5V 3GHz(300MB/s) page 37
RJ45
page 40 RTL8111E 10/100/1000M PCIe 1x
RTC CKT. PCIe port 1 page 40 1.5V 2.5GHz(250MB/s) SATA port 4 SATA ODD
page 28 BGA-1071 5V 3GHz(300MB/s) page 37
3
4 in 1 Card Reader SATA port 5
3

DC/DC Interface JMB389C/385C PCIe 1x 5V 3GHz(300MB/s)

PCIe port 5 page 41 1.5V 2.5GHz(250MB/s) page 28,29,30,31,32,33,34,35,36 eSATA USB
page 47 USB port 3 PCIe port 5 USB port 3
page 37 page 37
5V 480MHz

Power Circuit DC/DC 3.3V 33 MHz

LPC BUS

page 48~58 HD Audio 3.3V/1.5V 24MHz

NBQAA Sub-board Conn HDA Codec

SPI ROM Debug Port ENE KB926 E0 ALC269
page 42
page 28 page 45 page 44
Power Membrane Touch Pad
page 46 FP/LOGO LED
page 38
Int.
4 Slot ODD G-Sensor Int.KBD EC ROM MIC CONN MIC CONN HP CONN SPK CONN 4
page 25 page 43 page 43 page 43
page 37 page 45 page 35 page 45
Cap Sensor
Light Sensor
TP LED page 38
Security Classification Compal Secret Data Compal Electronics, Inc.
page 38 Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 2 of 61
A B C D E
 5 4 3 2 1

NBQAA Bordeaux Intel Arrandale (Discrete)

VR_ON
B+ DESIGN CURRENT 48A +CPU_CORE
B+ ISL62883HRZ-T
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 1.7A +5VALW Ipeak=48A, Imax=33.6A, Iocp min=57.19A

GFXVR_EN
SUSP
D DESIGN CURRENT 22A +GFX_CORE D
N-CHANNEL DESIGN CURRENT 2.2A +5VS ADP3211AMNR2G
SI4800 Ipeak=22A, Imax=15.4A, Iocp min=26A
ODD_EN#
P-CHANNEL DESIGN CURRENT 1100mA +5VS_ODD
AO-3413 GFXVR_EN
RT8205EGQW DESIGN CURRENT 24.1A +VGA_CORE
APW7138NITRL
Ipeak=5A, Imax=3.5A, Iocp min=8.6 DESIGN CURRENT 0.5A +3VALW Ipeak=24.10A, Imax=16.87A, Iocp min=28.65A

WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413

SUSP
N-CHANNEL DESIGN CURRENT 3A +3VS
SI4800 UMA_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
C C

BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413

DGPU_PWR_EN#
DESIGN CURRENT 780mA +3VS_DGPU
P-CHANNEL
AO-3413
VTTP_EN
Ipeak=20A, Imax=14A, Iocp min=29.73A DESIGN CURRENT 15A +VTT
APW7138NITRL

DESIGN CURRENT 5A +1.05VS

DGPU_PWR_EN#
DESIGN CURRENT 2.87A +1.05VS_DGPU
P-CHANNEL
AO-3413
B B

SYSON
Ipeak=20.15A, Imax=14.11A, Iocp min=21.73A DESIGN CURRENT 9A +1.5V
RT8209BGQW
SUSP
N-CHANNEL DESIGN CURRENT 3A +1.5V_CPU
SI4856
SUSP
DESIGN CURRENT 4.75A +1.5VS
N-CHANNEL
SI4800
VGA_PWROK#
N-CHANNEL DESIGN CURRENT 6.4A +VRAM_1.5VS
SI4856

0.75VR_EN#
DESIGN CURRENT 1.3A +0.75VS
SUSP# G2992F1U
A A
DESIGN CURRENT 1.7A +1.8VS
MP2121DQ-LF-Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 3 of 61
5 4 3 2 1
 A B C D E

( O MEANS ON X MEANS OFF )

Voltage Rails BTO Option Table
Function Bluetooth Card Reader HDMI-CEC LAN CAM+MIC
+RTCVCC +B +5VALW +1.5V +5VS
+3VALW +3VS description B Y U V X
+VSB +1.5VS
1 power explain Bluetooth JMB389 JMB385 HDMI HDMI+CEC 10/100 10/100/1000 CAM 1

plane +VGA_CORE
+CPU_CORE BTO BT@ JMB389@ JMB385@ IHDMI@ IHDMI@+CEC@ 8105E@ 8111E@ CAM@
+VTT
+1.05VS
+1.8VS Function ODD KB LED Mini Card GPU
+1.1VS
description T K G J W P M
State +0.75VS
explain Normal Slot KB LED 3G JET 3G/JFT WiMAX N11P-LP1 N11M-OP1

BTO ODD0@ ODD1@ KBL@ 3G@ JET@ 3GJFT@ WiMAX@ N11P@ N11P@

Function PCH VRAM

S0
O O O O O
description H5 H7 512 1G
2 S1 2
O O O O O explain HM55 HM57 512M 1G

S3 BTO HM55@ HM57@ 4pcs@ 4pcs@+8pcs@

O O O O X
S5 S4/AC
O O O X X
S5 S4/ Battery only SIGNAL
O O X X X STATE SLP_S3# SLP_S4# SLP_S5#

S5 S4/AC & Battery Full ON HIGH HIGH HIGH

don't exist
O X X X X
S1(Power On Suspend) HIGH HIGH HIGH

S3 (Suspend to RAM) LOW HIGH HIGH

S4 (Suspend to Disk) LOW LOW HIGH

3
EC SM Bus1 address EC SM Bus2 address S5 (Soft OFF) LOW LOW LOW 3

Power Device Address Power Device Address G3 LOW LOW LOW

+3VL EC KB926 D3 +3VS EC KB926 D3
+3VL HDMI-CEC +3VS AMD GPU Thermal Sensor
+3VL Smart Battery 0001 011x b +3VS Ambient Ligh Sensor
+3VALW PCH
+3VS G-Sensor

PCH SM Bus address

Power Device Address
+3VALW PCH

+3VS Clock Generator 1101 001x b

4 +3VS DDR DIMMA 1001 000x b 4

+3VS DDR DIMMB 1001 010x b

+3VS Express

+3VS Slot#1--WLAN/Wimax
Security Classification Compal Secret Data Compal Electronics, Inc.
+3VS Slot#2--JET/3G Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 4 of 61
A B C D E
 5 4 3 2 1

JCPUB
1 2 H_COMP3 AT23
R1 20_0402_1% COMP3
BCLK A16 CLK_CPU_BCLK 33

MISC
1 2 H_COMP2 AT24 B16 CLK_CPU_BCLK# 33
R2 20_0402_1% COMP2 BCLK#
H_COMP1 G16 CLK_CPU_XDP_R 1 CLK_CPU_XDP

CLOCKS
1 2 COMP1 BCLK_ITP AR30 2
R4 49.9_0402_1% AT30 CLK_CPU_XDP#_R 1 R41 @ 2 0_0402_5% CLK_CPU_XDP#
H_COMP0 AT26 BCLK_ITP# R42 @ 0_0402_5%
1 2 COMP0
R3 49.9_0402_1% E16 CLK_PEG 29
PEG_CLK
PEG_CLK# D16 CLK_PEG# 29
PAD T41 TP_SKTOCC# AH24
+VTT SKTOCC#
DPLL_REF_SSCLK A18 Unused by Clarksfield rPGA989
DPLL_REF_SSCLK# A17
D 1 2 CATERR# AK14 D
+VTT CATERR#

THERMAL
R18 49.9_0402_1%

F6 SM_DRAMRST#_CPU
SM_DRAMRST#
33 PECI AT15 PECI
2

AL1 SM_RCOMP_0 R6 1 2 100_0402_1% +VTT

SM_RCOMP[0]
R10
SM_RCOMP[1] AM1 SM_RCOMP_1 R7 1 2 24.9_0402_1% DDR3 Compensation Signals
Layout Note:Please these
68_0402_5% SM_RCOMP[2] AN1 SM_RCOMP_2 R8 1 2 130_0402_1% resistors near Processor
@ +VTT 1 2 H_PROCHOT#_D AN26 PM_EXTTS#0 R15 2 1 10K_0402_5%
PROCHOT#
R9 68_0402_5% AN15 PM_EXTTS#0

DDR3
MISC
1

PM_EXT_TS#[0]
PM_EXT_TS#[1] AP15 PM_EXTTS#_R 2 1 PM_EXTTS# 11,12 PM_EXTTS#_R R13 2 1 10K_0402_5%
H_CPURST# R12 0_0402_5%
33 H_THERMTRIP# AK15 THERMTRIP#

AT28 XDP_PRDY#
PRDY# XDP_PREQ# XDP_TDI_R XDP_TDI
PREQ# AP27 1 2
R20 0_0402_5%
AN28 XDP_TCK
XDP_RST#_R H_CPURST# TCK XDP_TMS XDP_TDO_M XDP_TDO
1 2 AP26 RESET_OBS# TMS AP28 1 @ 2

PWR MANAGEMENT
R36 1K_0402_5% AT27 XDP_TRST# Routed as a single daisy chain R21 0_0402_5%
TRST#

1
JTAG & BPM
C482 AL15 AT29 XDP_TDI_R R23
30 PMSYNCH PM_SYNC TDI
2 1 H_PWRGOOD AR27 XDP_TDO_R 0_0402_5%
TDO XDP_TDI_M
TDI_M AR29 2 1 +3VS
1000P_0402_50V7K 2 1 H_PWRGOOD1_R AN14 AP29 XDP_TDO_M R312 1K_0402_5%

2
0_0402_5% R25 VCCPW RGOOD_1 TDO_M XDP_TDI_M 1 @ 2
AN25 R26 0_0402_5%
DBR# XDP_DBRESET# 30
to avoid noise H_PWRGOOD AN27
33 H_PWRGOOD VCCPW RGOOD_0
C XDP_TDO_R 1 2 C
AJ22 XDP_BPM#0 XDP_PRDY# 1 2 XDP_PRDY#_R R27 0_0402_5%
DRAMPWROK BPM#[0] XDP_BPM#1 R40 @ 0_0402_5%
30 DRAMPWROK AK13 SM_DRAMPW ROK BPM#[1] AK22
AK24 XDP_BPM#2 XDP_PREQ# 1 2 XDP_PREQ#_R
BPM#[2] XDP_BPM#3 R54 @ 0_0402_5%
BPM#[3] AJ24
52 VTTPWROK_CPU 1 AM15 AJ25 XDP_TCK 1 2 XDP_TCK_R
VTTPW RGOOD BPM#[4] R449@ 0_0402_5%
BPM#[5] AH22
C426 AK23 XDP_TMS 1 2 XDP_TMS_R
TAPPWRGD BPM#[6] R450@ 0_0402_5%
1000P_0402_50V7K AM26 TAPPW RGOOD BPM#[7] AH23
2
JTAG MAPPING
AL14 XDP_BPM#0 1 2 XDP_BPM#0_R
32 BUF_PLT_RST# RSTIN#
1.5K_0402_1% R30 R454@ 0_0402_5% Scan Chain STUFF -> R20, R23, R27
XDP_BPM#1 1 2 XDP_BPM#1_R (Default) NO STUFF -> R21, R26
R31 R452@ 0_0402_5%
750_0402_1% IC,AUB_CFD_rPGA,R0P9 XDP_BPM#2 1 2 XDP_BPM#2_R
@ R451@ 0_0402_5% CPU Only STUFF -> R20, R21
XDP_BPM#3 1 2 XDP_BPM#3_R NO STUFF -> R23, R26, R27
R455@ 0_0402_5%
XDP_DBRESET# 1 2 XDP_DBRESET#_R
R456@ 0_0402_5% GMCH Only STUFF -> R26, R27
NO STUFF -> R20, R21, R23
Reserved for EMI;don't open solder if placing under H=0

XDP Connector
B +1.5V_CPU SFF-24Pin B
For S3 Power Reduction
JXDP
XDP_PREQ#_R 1 1
2

XDP_PRDY#_R 2
R28 2
3 3
@ 1.1K_0402_1% XDP_BPM#0_R 4
@ XDP_BPM#1_R 4
2 1 5 5
R19 0_0402_5% 6
1

XDP_BPM#2_R 6
7 7
DRAMPWROK XDP_BPM#3_R 8
R29 @ R32 1K_0402_5% 8
9 9
S

SM_DRAMRST#_CPU 3 1 750_0402_1% H_PWRGOOD 1 2 H_PWRGOOD_R 10

SM_DRAMRST# 11,12 10
2

TAPPWRGD 1 2 TAPPWRGD_R 11
Q41 R29 @ R35 0_0402_5% CLK_CPU_XDP 11
12 12
BSS138_NL_SOT23-3 3K_0402_1% CLK_CPU_XDP#
G

13
2

13
1

+VTT 14 14
1 @ XDP_RST#_R 15
RST_GATE 33
1

R123 C160 XDP_DBRESET#_R 15

16 16
100K_0402_5% 0.047U_0402_25V6K 17
XDP_TDO 17
1 2 1 18
2

2 +3VALW 51_0402_5% R14 XDP_TRST# 18

19 19

1
C1 XDP_TDI 20
0.1U_0402_10V6K XDP_TMS_R 20
21 21
1 2 @ 2 R11 22
C253 0.1U_0402_16V4Z 51_0402_5% 22
23 23 GND 25
5

U10 XDP_TCK_R 24 26

2
VTTPWROK 24 GND
47,52 VTTPWROK 1
P

IN1 DRAMPWROK MOLEX_52435-2472

A O 4 A
2 R33 1.5K_0402_1% @
IN2
G

1
SN74AHC1G08DCKR_SC70-5
3

C414
1000P_0402_50V7K
2
2 1
Security Classification Compal Secret Data Compal Electronics, Inc.
0_0402_5% @ R52 2009/11/13 2010/01/23 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU CLK/MISC/JTAG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 5 of 61
5 4 3 2 1
 5 4 3 2 1

FAN Control Circuit

+5VS

1A
JFAN @
2 1 +FAN1 1 1
2 2
C3 C428 3
10U_0805_10V4Z 1000P_0402_50V7K 3
D D
U1 1 @ 2
4 GND
1 EN GND 8 5 GND
2 VIN GND 7
+FAN1 3 6 ACES_85204-0300N
VOUT GND
44 EN_DFAN1 4 VSET GND 5
1
10mil APL5607KI-TRG_SO8 R34 10K_0402_5%
C5 2 1 +3VS
10U_0805_10V4Z
2
FAN_SPEED1 44
2
C6
JCPUA 0.01U_0402_16V7K
PEG_COMP 1 1 @
PEG_ICOMPI B26 2
A26 R38 49.9_0402_1%
PEG_ICOMPO
30 DMI_PTX_CRX_N0 A24 DMI_RX#[0] PEG_RCOMPO B27
C23 A25 PEG_RBIAS 1 2
30 DMI_PTX_CRX_N1 DMI_RX#[1] PEG_RBIAS
B22 R39 750_0402_1%
30 DMI_PTX_CRX_N2 DMI_RX#[2] PCIE_GTX_C_CRX_N[0..15] 13
A21 K35 PCIE_GTX_C_CRX_N0
30 DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0]
J34 PCIE_GTX_C_CRX_N1
PEG_RX#[1] PCIE_GTX_C_CRX_N2
30 DMI_PTX_CRX_P0 B24 DMI_RX[0] PEG_RX#[2] J33
D23 G35 PCIE_GTX_C_CRX_N3
30 DMI_PTX_CRX_P1 DMI_RX[1] PEG_RX#[3]
30
30
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
B23
A22
DMI_RX[2] DMI PEG_RX#[4] G32
F34
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_N5
DMI_RX[3] PEG_RX#[5] PCIE_GTX_C_CRX_N6
PEG_RX#[6] F31
D24 D35 PCIE_GTX_C_CRX_N7
30 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
G24 E33 PCIE_GTX_C_CRX_N8
30 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
C F23 C33 PCIE_GTX_C_CRX_N9 C
30 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
H23 D32 PCIE_GTX_C_CRX_N10
30 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
B32 PCIE_GTX_C_CRX_N11
PEG_RX#[11] PCIE_GTX_C_CRX_N12
30 DMI_CTX_PRX_P0 D25 DMI_TX[0] PEG_RX#[12] C31
F24 B28 PCIE_GTX_C_CRX_N13
30 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
E23 B30 PCIE_GTX_C_CRX_N14
30 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
G23 A31 PCIE_GTX_C_CRX_N15
30 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_GTX_C_CRX_P[0..15] 13
J35 PCIE_GTX_C_CRX_P0
PEG_RX[0] PCIE_GTX_C_CRX_P1
PEG_RX[1] H34
H33 PCIE_GTX_C_CRX_P2
PEG_RX[2] PCIE_GTX_C_CRX_P3
30 FDI_CTX_PRX_N0 E22 FDI_TX#[0] PEG_RX[3] F35
D21 G33 PCIE_GTX_C_CRX_P4
30 FDI_CTX_PRX_N1 FDI_TX#[1] PEG_RX[4]
D19 E34 PCIE_GTX_C_CRX_P5
30 FDI_CTX_PRX_N2 FDI_TX#[2] PEG_RX[5]
D18 F32 PCIE_GTX_C_CRX_P6
30 FDI_CTX_PRX_N3 FDI_TX#[3] PEG_RX[6]
G21 D34 PCIE_GTX_C_CRX_P7
30 FDI_CTX_PRX_N4 FDI_TX#[4] PEG_RX[7]
PCI EXPRESS -- GRAPHICS

E19 F33 PCIE_GTX_C_CRX_P8

30 FDI_CTX_PRX_N5 FDI_TX#[5] PEG_RX[8]
F21 B33 PCIE_GTX_C_CRX_P9
30 FDI_CTX_PRX_N6 FDI_TX#[6] PEG_RX[9]
Intel(R) FDI

G18 D31 PCIE_GTX_C_CRX_P10

30 FDI_CTX_PRX_N7 FDI_TX#[7] PEG_RX[10]
A32 PCIE_GTX_C_CRX_P11
PEG_RX[11] PCIE_GTX_C_CRX_P12
PEG_RX[12] C30
D22 A28 PCIE_GTX_C_CRX_P13
30 FDI_CTX_PRX_P0 FDI_TX[0] PEG_RX[13]
C21 B29 PCIE_GTX_C_CRX_P14
30 FDI_CTX_PRX_P1 FDI_TX[1] PEG_RX[14]
D20 A30 PCIE_GTX_C_CRX_P15
30 FDI_CTX_PRX_P2 FDI_TX[2] PEG_RX[15]
30 FDI_CTX_PRX_P3 C18 FDI_TX[3] PCIE_CTX_C_GRX_N[0..15] 13
G22 L33 PCIE_CTX_GRX_N0 C39 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N0
30 FDI_CTX_PRX_P4 FDI_TX[4] PEG_TX#[0]
E20 M35 PCIE_CTX_GRX_N1 C40 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N1
30 FDI_CTX_PRX_P5 FDI_TX[5] PEG_TX#[1]
F20 M33 PCIE_CTX_GRX_N2 C41 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N2
30 FDI_CTX_PRX_P6 FDI_TX[6] PEG_TX#[2]
G19 M30 PCIE_CTX_GRX_N3 C42 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N3
B 30 FDI_CTX_PRX_P7 FDI_TX[7] PEG_TX#[3] B
L31 PCIE_CTX_GRX_N4 C43 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N4
PEG_TX#[4] PCIE_CTX_GRX_N5 C44 0.1U_0402_16V7K PCIE_CTX_C_GRX_N5
30 FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32 1 2
30 FDI_FSYNC1 E17 M29 PCIE_CTX_GRX_N6 C45 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N6
FDI_FSYNC[1] PEG_TX#[6] PCIE_CTX_GRX_N7 C46 0.1U_0402_16V7K PCIE_CTX_C_GRX_N7
PEG_TX#[7] J31 1 2
30 FDI_INT C17 K29 PCIE_CTX_GRX_N8 C47 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N8
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N9 C48 0.1U_0402_16V7K PCIE_CTX_C_GRX_N9
PEG_TX#[9] H30 1 2
30 FDI_LSYNC0 F18 H29 PCIE_CTX_GRX_N10 C49 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N10
FDI_LSYNC[0] PEG_TX#[10] PCIE_CTX_GRX_N11 C50 0.1U_0402_16V7K PCIE_CTX_C_GRX_N11
30 FDI_LSYNC1 D17 FDI_LSYNC[1] PEG_TX#[11] F29 1 2
E28 PCIE_CTX_GRX_N12 C51 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N12
PEG_TX#[12] PCIE_CTX_GRX_N13 C52 0.1U_0402_16V7K PCIE_CTX_C_GRX_N13
PEG_TX#[13] D29 1 2
D27 PCIE_CTX_GRX_N14 C53 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N14
PEG_TX#[14] PCIE_CTX_GRX_N15 C54 0.1U_0402_16V7K PCIE_CTX_C_GRX_N15
PEG_TX#[15] C26 1 2
PCIE_CTX_C_GRX_P[0..15] 13
L34 PCIE_CTX_GRX_P0 C55 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P0
PEG_TX[0] PCIE_CTX_GRX_P1 C56 0.1U_0402_16V7K PCIE_CTX_C_GRX_P1
PEG_TX[1] M34 1 2
M32 PCIE_CTX_GRX_P2 C57 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P2
PEG_TX[2] PCIE_CTX_GRX_P3 C58 0.1U_0402_16V7K PCIE_CTX_C_GRX_P3
PEG_TX[3] L30 1 2
M31 PCIE_CTX_GRX_P4 C59 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P4
PEG_TX[4] PCIE_CTX_GRX_P5 C60 0.1U_0402_16V7K PCIE_CTX_C_GRX_P5
PEG_TX[5] K31 1 2
M28 PCIE_CTX_GRX_P6 C61 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P6
PEG_TX[6] PCIE_CTX_GRX_P7 C62 0.1U_0402_16V7K PCIE_CTX_C_GRX_P7
PEG_TX[7] H31 1 2
K28 PCIE_CTX_GRX_P8 C63 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P8
PEG_TX[8] PCIE_CTX_GRX_P9 C64 0.1U_0402_16V7K PCIE_CTX_C_GRX_P9
PEG_TX[9] G30 1 2
G29 PCIE_CTX_GRX_P10 C65 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P10
PEG_TX[10] PCIE_CTX_GRX_P11 C66 0.1U_0402_16V7K PCIE_CTX_C_GRX_P11
PEG_TX[11] F28 1 2
E27 PCIE_CTX_GRX_P12 C67 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P12
PEG_TX[12] PCIE_CTX_GRX_P13 C68 0.1U_0402_16V7K PCIE_CTX_C_GRX_P13
PEG_TX[13] D28 1 2
C27 PCIE_CTX_GRX_P14 C69 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P14
PEG_TX[14] PCIE_CTX_GRX_P15 C70 0.1U_0402_16V7K PCIE_CTX_C_GRX_P15
A PEG_TX[15] C25 1 2 A

IC,AUB_CFD_rPGA,R0P9
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU DMI/FDI/PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 6 of 61
5 4 3 2 1
 5 4 3 2 1

JCPUC JCPUD

11 DDR_A_D[0..63] 12 DDR_B_D[0..63]

SA_CK[0] AA6 DDRA_CLK0 11 SB_CK[0] W8 DDRB_CLK0 12

SA_CK#[0] AA7 DDRA_CLK0# 11 SB_CK#[0] W9 DDRB_CLK0# 12
P7 DDR_B_D0 B5 M3
SA_CKE[0] DDRA_CKE0 11 SB_DQ[0] SB_CKE[0] DDRB_CKE0 12
DDR_A_D0 A10 DDR_B_D1 A5
DDR_A_D1 SA_DQ[0] DDR_B_D2 SB_DQ[1]
C10 SA_DQ[1] C3 SB_DQ[2]
D DDR_A_D2 C7 DDR_B_D3 B3 V7 D
SA_DQ[2] SB_DQ[3] SB_CK[1] DDRB_CLK1 12
DDR_A_D3 A7 Y6 DDR_B_D4 E4 V6
SA_DQ[3] SA_CK[1] DDRA_CLK1 11 SB_DQ[4] SB_CK#[1] DDRB_CLK1# 12
DDR_A_D4 B10 Y5 DDR_B_D5 A6 M2
SA_DQ[4] SA_CK#[1] DDRA_CLK1# 11 SB_DQ[5] SB_CKE[1] DDRB_CKE1 12
DDR_A_D5 D10 P6 DDR_B_D6 A4
SA_DQ[5] SA_CKE[1] DDRA_CKE1 11 SB_DQ[6]
DDR_A_D6 E10 DDR_B_D7 C4
DDR_A_D7 SA_DQ[6] DDR_B_D8 SB_DQ[7]
A8 SA_DQ[7] D1 SB_DQ[8]
DDR_A_D8 D8 DDR_B_D9 D2
DDR_A_D9 SA_DQ[8] DDR_B_D10 SB_DQ[9]
F10 SA_DQ[9] SA_CS#[0] AE2 DDRA_SCS0# 11 F2 SB_DQ[10] SB_CS#[0] AB8 DDRB_SCS0# 12
DDR_A_D10 E6 AE8 DDR_B_D11 F1 AD6
SA_DQ[10] SA_CS#[1] DDRA_SCS1# 11 SB_DQ[11] SB_CS#[1] DDRB_SCS1# 12
DDR_A_D11 F7 DDR_B_D12 C2
DDR_A_D12 SA_DQ[11] DDR_B_D13 SB_DQ[12]
E9 SA_DQ[12] F5 SB_DQ[13]
DDR_A_D13 B7 DDR_B_D14 F3
DDR_A_D14 SA_DQ[13] DDR_B_D15 SB_DQ[14]
E7 SA_DQ[14] SA_ODT[0] AD8 DDRA_ODT0 11 G4 SB_DQ[15] SB_ODT[0] AC7 DDRB_ODT0 12
DDR_A_D15 C6 AF9 DDR_B_D16 H6 AD1
SA_DQ[15] SA_ODT[1] DDRA_ODT1 11 SB_DQ[16] SB_ODT[1] DDRB_ODT1 12
DDR_A_D16 H10 DDR_B_D17 G2
DDR_A_D17 SA_DQ[16] DDR_B_D18 SB_DQ[17]
G8 SA_DQ[17] J6 SB_DQ[18]
DDR_A_D18 K7 Unused by Clarksfield rPGA989 DDR_B_D19 J3
DDR_A_D19 SA_DQ[18] DDR_B_D20 SB_DQ[19]
J8 SA_DQ[19] G1 SB_DQ[20] DDR_B_DM[0..7] 12
DDR_A_D20 G7 DDR_B_D21 G5 D4 DDR_B_DM0
SA_DQ[20] DDR_A_DM[0..7] 11 SB_DQ[21] SB_DM[0]
DDR_A_D21 G10 DDR_B_D22 J2 E1 DDR_B_DM1
DDR_A_D22 SA_DQ[21] DDR_A_DM0 DDR_B_D23 SB_DQ[22] SB_DM[1] DDR_B_DM2
J7 SA_DQ[22] SA_DM[0] B9 J1 SB_DQ[23] SB_DM[2] H3
DDR_A_D23 J10 D7 DDR_A_DM1 DDR_B_D24 J5 K1 DDR_B_DM3
DDR_A_D24 SA_DQ[23] SA_DM[1] DDR_A_DM2 DDR_B_D25 SB_DQ[24] SB_DM[3] DDR_B_DM4
L7 SA_DQ[24] SA_DM[2] H7 K2 SB_DQ[25] SB_DM[4] AH1
DDR_A_D25 M6 M7 DDR_A_DM3 DDR_B_D26 L3 AL2 DDR_B_DM5
DDR_A_D26 SA_DQ[25] SA_DM[3] DDR_A_DM4 DDR_B_D27 SB_DQ[26] SB_DM[5] DDR_B_DM6
M8 SA_DQ[26] SA_DM[4] AG6 M1 SB_DQ[27] SB_DM[6] AR4
DDR_A_D27 L9 AM7 DDR_A_DM5 DDR_B_D28 K5 AT8 DDR_B_DM7
DDR_A_D28 SA_DQ[27] SA_DM[5] DDR_A_DM6 DDR_B_D29 SB_DQ[28] SB_DM[7]
L6 SA_DQ[28] SA_DM[6] AN10 K4 SB_DQ[29]
DDR_A_D29 K8 AN13 DDR_A_DM7 DDR_B_D30 M4 Unused by Clarksfield rPGA989
DDR_A_D30 SA_DQ[29] SA_DM[7] DDR_B_D31 SB_DQ[30]
N8 SA_DQ[30] N5 SB_DQ[31]
C DDR_A_D31 P9 DDR_B_D32 AF3 C
DDR_A_D32 SA_DQ[31] DDR_B_D33 SB_DQ[32]
AH5 SA_DQ[32] AG1 SB_DQ[33] DDR_B_DQS#[0..7] 12
DDR_A_D33 AF5 DDR_B_D34 AJ3 D5 DDR_B_DQS#0
SA_DQ[33] DDR_A_DQS#[0..7] 11 SB_DQ[34] SB_DQS#[0]
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR SYSTEM MEMORY A

DDR_A_D35 SA_DQ[34] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2

AK7 SA_DQ[35] SA_DQS#[1] F8 AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D36 AF6 J9 DDR_A_DQS#2 DDR_B_D37 AG3 L4 DDR_B_DQS#3
DDR_A_D37 SA_DQ[36] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D38 SB_DQ[37] SB_DQS#[3] DDR_B_DQS#4
AG5 N9 AJ4 AH2

DDR SYSTEM MEMORY - B

DDR_A_D38 SA_DQ[37] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D39 SB_DQ[38] SB_DQS#[4] DDR_B_DQS#5
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AH4 SB_DQ[39] SB_DQS#[5] AL4
DDR_A_D39 AJ6 AK9 DDR_A_DQS#5 DDR_B_D40 AK3 AR5 DDR_B_DQS#6
DDR_A_D40 SA_DQ[39] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D41 SB_DQ[40] SB_DQS#[6] DDR_B_DQS#7
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AK4 SB_DQ[41] SB_DQS#[7] AR8
DDR_A_D41 AJ9 AT13 DDR_A_DQS#7 DDR_B_D42 AM6
DDR_A_D42 SA_DQ[41] SA_DQS#[7] DDR_B_D43 SB_DQ[42]
AL10 SA_DQ[42] AN2 SB_DQ[43]
DDR_A_D43 AK12 DDR_B_D44 AK5
DDR_A_D44 SA_DQ[43] DDR_B_D45 SB_DQ[44]
AK8 SA_DQ[44] AK2 SB_DQ[45]
DDR_A_D45 AL7 DDR_B_D46 AM4
SA_DQ[45] DDR_A_DQS[0..7] 11 SB_DQ[46]
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D47 AM3
SA_DQ[46] SA_DQS[0] SB_DQ[47] DDR_B_DQS[0..7] 12
DDR_A_D47 AL8 F9 DDR_A_DQS1 DDR_B_D48 AP3 C5 DDR_B_DQS0
DDR_A_D48 SA_DQ[47] SA_DQS[1] DDR_A_DQS2 DDR_B_D49 SB_DQ[48] SB_DQS[0] DDR_B_DQS1
AN8 SA_DQ[48] SA_DQS[2] H9 AN5 SB_DQ[49] SB_DQS[1] E3
DDR_A_D49 AM10 M9 DDR_A_DQS3 DDR_B_D50 AT4 H4 DDR_B_DQS2
DDR_A_D50 SA_DQ[49] SA_DQS[3] DDR_A_DQS4 DDR_B_D51 SB_DQ[50] SB_DQS[2] DDR_B_DQS3
AR11 SA_DQ[50] SA_DQS[4] AH8 AN6 SB_DQ[51] SB_DQS[3] M5
DDR_A_D51 AL11 AK10 DDR_A_DQS5 DDR_B_D52 AN4 AG2 DDR_B_DQS4
DDR_A_D52 SA_DQ[51] SA_DQS[5] DDR_A_DQS6 DDR_B_D53 SB_DQ[52] SB_DQS[4] DDR_B_DQS5
AM9 SA_DQ[52] SA_DQS[6] AN11 AN3 SB_DQ[53] SB_DQS[5] AL5
DDR_A_D53 AN9 AR13 DDR_A_DQS7 DDR_B_D54 AT5 AP5 DDR_B_DQS6
DDR_A_D54 SA_DQ[53] SA_DQS[7] DDR_B_D55 SB_DQ[54] SB_DQS[6] DDR_B_DQS7
AT11 SA_DQ[54] AT6 SB_DQ[55] SB_DQS[7] AR7
DDR_A_D55 AP12 DDR_B_D56 AN7
DDR_A_D56 SA_DQ[55] DDR_B_D57 SB_DQ[56]
AM12 SA_DQ[56] DDR_A_MA[0..15] 11 AP6 SB_DQ[57]
DDR_A_D57 AN12 DDR_B_D58 AP8
DDR_A_D58 SA_DQ[57] DDR_A_MA0 DDR_B_D59 SB_DQ[58]
AM13 SA_DQ[58] SA_MA[0] Y3 AT9 SB_DQ[59]
DDR_A_D59 AT14 W1 DDR_A_MA1 DDR_B_D60 AT7
B DDR_A_D60 SA_DQ[59] SA_MA[1] DDR_A_MA2 DDR_B_D61 SB_DQ[60] B
AT12 SA_DQ[60] SA_MA[2] AA8 AP9 SB_DQ[61]
DDR_A_D61 AL13 AA3 DDR_A_MA3 DDR_B_D62 AR10
SA_DQ[61] SA_MA[3] SB_DQ[62] DDR_B_MA[0..15] 12
DDR_A_D62 AR14 V1 DDR_A_MA4 DDR_B_D63 AT10 U5 DDR_B_MA0
DDR_A_D63 SA_DQ[62] SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[0] DDR_B_MA1
AP14 SA_DQ[63] SA_MA[5] AA9 SB_MA[1] V2
V8 DDR_A_MA6 T5 DDR_B_MA2
SA_MA[6] DDR_A_MA7 SB_MA[2] DDR_B_MA3
SA_MA[7] T1 SB_MA[3] V3
Y9 DDR_A_MA8 R1 DDR_B_MA4
SA_MA[8] DDR_A_MA9 SB_MA[4] DDR_B_MA5
11 DDR_A_BS0 AC3 SA_BS[0] SA_MA[9] U6 12 DDR_B_BS0 AB1 SB_BS[0] SB_MA[5] T8
AB2 AD4 DDR_A_MA10 W5 R2 DDR_B_MA6
11 DDR_A_BS1 SA_BS[1] SA_MA[10] 12 DDR_B_BS1 SB_BS[1] SB_MA[6]
U7 T2 DDR_A_MA11 R7 R6 DDR_B_MA7
11 DDR_A_BS2 SA_BS[2] SA_MA[11] 12 DDR_B_BS2 SB_BS[2] SB_MA[7]
U3 DDR_A_MA12 R4 DDR_B_MA8
SA_MA[12] DDR_A_MA13 SB_MA[8] DDR_B_MA9
SA_MA[13] AG8 SB_MA[9] R5
T3 DDR_A_MA14 AC5 AB5 DDR_B_MA10
SA_MA[14] 12 DDR_B_CAS# SB_CAS# SB_MA[10]
AE1 V9 DDR_A_MA15 Y7 P3 DDR_B_MA11
11 DDR_A_CAS# SA_CAS# SA_MA[15] 12 DDR_B_RAS# SB_RAS# SB_MA[11]
AB3 AC6 R3 DDR_B_MA12
11 DDR_A_RAS# SA_RAS# 12 DDR_B_W E# SB_WE# SB_MA[12]
AE9 AF7 DDR_B_MA13
11 DDR_A_W E# SA_WE# SB_MA[13]
P5 DDR_B_MA14
SB_MA[14] DDR_B_MA15
SB_MA[15] N1

IC,AUB_CFD_rPGA,R0P9
@

A A
IC,AUB_CFD_rPGA,R0P9
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 7 of 61
5 4 3 2 1
 5 4 3 2 1

Material Note (+VTT):

JCPUF
330uF/ 6mohm, number are 3,
power x1, HW x2

+CPU_CORE Clarksfield: 65A Clarksfield: 21A (Place these capacitors under CPU socket Edge, top layer) (Place these capacitors between inductor and socket on Bottom)
+VTT
Auburndale:48A Auburndale:18A +CPU_CORE
AG35 AH14
VCC1 VTT0_1 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
AG34 VCC2 VTT0_2 AH12
D D
AG33 VCC3 VTT0_3 AH11
AG32 VCC4 VTT0_4 AH10 1 1 1 1 1 1 1 1 1
C144 1 2 330U_2.5V_M_R17 C81 1 2 10U_0805_10V4K

+
AG31 VCC5 VTT0_5 J14
AG30 J13
VCC6 VTT0_6 C159 1 2 330U_2.5V_M_R17 C83 1 2 10U_0805_10V4K C71 C72 C73 C74 C75 C76 C77 C78 C79

+
AG29 H14
VCC7 VTT0_7 2 2 2 2 2 2 2 2 2
AG28 VCC8 VTT0_8 H12
AG27 G14 C85 1 2 10U_0805_10V4K
VCC9 VTT0_9 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
AG26 VCC10 VTT0_10 G13
AF35 G12 SF000002Z00 C89 1 2 10U_0805_10V4K
VCC11 VTT0_11
AF34 G11
AF33
VCC12 VTT0_12
F14 H=4.5 C88 1 2 10U_0805_10V4K
VCC13 VTT0_13
AF32 F13
VCC14 VTT0_14 C90 1
AF31 VCC15 VTT0_15 F12 2 10U_0805_10V4K
AF30 F11 C87 1 2 22U_0805_6.3V6M (Place these capacitors under CPU socket, top layer)
VCC16 VTT0_16 C92 1
AF29 E14 2 10U_0805_10V4K
VCC17 VTT0_17 C91 1
AF28 E12 2 22U_0805_6.3V6M
VCC18 VTT0_18 C94 1 +CPU_CORE
AF27 VCC19 VTT0_19 D14 2 10U_0805_10V4K@
AF26 D13
VCC20 VTT0_20
1.1V RAIL POWER
AD35 D12 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC21 VTT0_21
AD34 D11
VCC22 VTT0_22
AD33 C14 1 1 1 1 1 1 1
VCC23 VTT0_23
AD32 C13
VCC24 VTT0_24
AD31 VCC25 VTT0_25 C12
AD30 C11 C98 C99 C100 C101 C102 C103 C104
VCC26 VTT0_26 2 2 2 2 2 2 2
AD29 B14
VCC27 VTT0_27
AD28 VCC28 VTT0_28 B12
AD27 A14 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC29 VTT0_29
AD26 A13
VCC30 VTT0_30
AC35 VCC31 VTT0_31 A12
AC34 VCC32 VTT0_32 A11
AC33
VCC33
C
AC32
VCC34 Add on 2/8 to improve ESD (Place these capacitors on CPU cavity, Bottom Layer) C
AC31 VCC35
AC30 AF10
VCC36 VTT0_33 +CPU_CORE +CPU_CORE
AC29 AE10
VCC37 VTT0_34
AC28 VCC38 VTT0_35 AC10
CPU CORE SUPPLY

AC27 AB10 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

VCC39 VTT0_36
AC26 Y10
VCC40 VTT0_37
AA35 VCC41 VTT0_38 W10 1 1 1 1 1 1 1 1 1 1 1 1 1
AA34 U10 C105 C106 C107 C108 C109 C110
VCC42 VTT0_39 C128 C127 C120 C118 C119 C117 C129
AA33 VCC43 VTT0_40 T10
AA32 J12
VCC44 VTT0_41 2 2 2 2 2 2 2 2 2 2 2 2 2
AA31 VCC45 VTT0_42 J11
AA30 J16
VCC46 VTT0_43 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AA29 VCC47 VTT0_44 J15
AA28
VCC48
AA27
VCC49
AA26
VCC50 +CPU_CORE
Y35
VCC51
Y34
VCC52 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
Y33
VCC53
Y32 VCC54
Y31 1 1 1 1 1 1
VCC55 C111 C112 C113 C114 C115 C116
Y30
VCC56
Y29
VCC57
Y28
VCC58 2 2 2 2 2 2
Y27
VCC59
Y26
V35
VCC60
AN33
CRB default setting: 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC61 PSI# H_PSI# 56
V34 VID[6:0]=[0100111]
POWER

VCC62
V33
VCC63
V32 AK35 CPU_VID0 56
VCC64 VID[0]
V31 AK33 CPU_VID1 56
VCC65 VID[1]
V30 AK34 CPU_VID2 56
B VCC66 VID[2] B
V29 VCC67 VID[3] AL35 CPU_VID3 56 VTT Rail
CPU VIDS

V28 VCC68 VID[4] AL33 CPU_VID4 56 TOP side (under inductor)

V27 AM33 CPU_VID5 56
VCC69 VID[5]
V26 VCC70 VID[6] AM35 CPU_VID6 56 Auburndale +1.1VS_VTT=1.05V +CPU_CORE
U35 AM34 H_DPRSLPVR_R 1 2 SGA00002680
U34
VCC71 PROC_DPRSLPVR R62 0_0402_5%
H_DPRSLPVR 56 Clarksfield +1.1VS_VTT=1.1V
VCC72 330U_D2_2.5VM_R9M 330U_D2_2.5VM_R9M
U33
VCC73
U32 1 1 1 1
VCC74 H_VTTSELECT
U31 G15 T56 PAD
VCC75 VTT_SELECT + + + +
U30 VCC76 H_VTTSELECT = low, 1.1V C121 C122 C123 C124
U29 VCC77
U28
VCC78 H_VTTSELECT = high, 1.05V 330U_D2_2.5VM_R9M
2 2
330U_D2_2.5VM_R9M
2 2
U27 VCC79
U26
VCC80
R35 VCC81
R34
VCC82
R33
VCC83
R32 AN35 IMVP_IMON 56
VCC84 ISENSE
R31
VCC85
R30 1 2 +CPU_CORE
VCC86 R64 100_0402_1%
R29
VCC87 VCCSENSE_R R65 VCCSENSE
2 0_0402_5%
SENSE LINES

R28 VCC88 VCC_SENSE AJ34 1 VCCSENSE 56

VSSSENSE_R R66 2 0_0402_5% VSSSENSE
R27
R26
VCC89 VSS_SENSE
AJ35 1 VSSSENSE 56 Check list:
VCC90
P35 1 2
VCC91 R67 100_0402_1%
P34
P33
VCC92 VTT_SENSE
B15
A15
VTT_SENSE 52 +CPU_CORE: 6x 470uF, 12x 22uF, 17x 10uF
VCC93 VSS_SENSE_VTT VSS_SENSE_VTT 52
P32
VCC94 near CPU
P31
P30
VCC95 +VTT: 4x 330uF, 7x 22uF, 8x 10uF
VCC96
P29
VCC97
P28 VCC98
A A
P27
VCC99
P26 VCC100

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title
IC,AUB_CFD_rPGA,R0P9
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU POWER-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 8 of 61
5 4 3 2 1
 5 4 3 2 1

For S3 Power Reduction

+1.5V_CPU +1.5V
Q33
1 S D 8
2 S D 7

2
1 3 S D 6
R424 C179 4 5
+GFX_CORE 470_0805_5% G D
VCC_AXG_SENSE 1 2 10U_0805_10V4K
R509 100_0402_1% 2 FDS6676AS_SO8
1 R418 2 +VSB

3 1
VSS_AXG_SENSE 1 2 220K_0402_5%
D R510 100_0402_1% D

6
Close to CPU Q46B 1
C472 R417 Q46A
SUSP 5 820K_0402_5%
0.1U_0402_25V6 2 SUSP
2 SUSP 47,55
2N7002DW -T/R7_SOT363-6

2
2N7002DW -T/R7_SOT363-6

1
+GFX_CORE JCPUG

22U_0805_6.3V6M 1U_0402_6.3V4Z AT21 VAXG1 VCC_AXG_SENSE

AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE 57
SGA00002680 VSS_AXG_SENSE

SENSE
LINES
1 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE 57
1 1 1 1 1 1 AT16 VAXG4
C218 + C140 C150 C125 C158 C148 C126 AR21
10U_0805_6.3V6M VAXG5
AR19 VAXG6
330U_D2_2.5VM_R9M AR18
2 2 2 2 2 2 2 VAXG7
AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 57
AP21 VAXG9 GFX_VID[1] AP22 GFXVR_VID_1 57

GRAPHICS VIDs
22U_0805_6.3V6M 1U_0402_6.3V4Z 10U_0805_6.3V6M AP19 AN22 C205 1 2 0.1U_0402_16V4Z
VAXG10 GFX_VID[2] GFXVR_VID_2 57
AP18 VAXG11 GFX_VID[3] AP23 GFXVR_VID_3 57
AP16 AM23 C186 1 2 0.1U_0402_16V4Z
VAXG12 GFX_VID[4] GFXVR_VID_4 57
AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 57

GRAPHICS
AN19 AN24 C185 1 2 0.1U_0402_16V4Z
VAXG14 GFX_VID[6] GFXVR_VID_6 57
AN18 VAXG15
To prevent glitch issue
AN16 1 2 C180 1 2 0.1U_0402_16V4Z
VAXG16 R86 330_0402_5%
AM21 VAXG17 GFX_VR_EN AR25 GFXVR_EN 57
AM19 AT25 GFXVR_DPRSLPVR PAD T8
VAXG18 GFX_DPRSLPVR
AM18 VAXG19 GFX_IMON AM24 GFXVR_IMON 57
AM16 PJ30 @
VAXG20 R687 2
C AL21 VAXG21 1 1K_0402_5% 2 2 1 1 C
AL19 @
VAXG22 +1.5V_CPU JUMP_43X79
AL18 VAXG23
Reserved for Clarksfield
AL16 PJ31 @
VAXG24 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
AK21 VAXG25 VDDQ1 AJ1 2 2 1 1 +1.5V
AK19 VAXG26 VDDQ2 AF1 1
AK18 AE7 1 1 1 1 1 1 1 C216 JUMP_43X79

- 1.5V RAILS
VAXG27 VDDQ3 +
AK16 VAXG28 Clarksfield: 5A VDDQ4 AE4
C133 C134 C135 C136 C137 C138 C139 330U_D2_2.5VM_R9M
AJ21 VAXG29 VDDQ5 AC1
AJ19 VAXG30 Auburndale:3A VDDQ6 AB7
2 2 2 2 2 2 2 2
AJ18 VAXG31 VDDQ7 AB4 SGA00002680
AJ16 VAXG32 VDDQ8 Y1
AH21 VAXG33 VDDQ9 W7

POWER
AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
VAXG34 VDDQ10
AH18 VAXG35 VDDQ11 U1
AH16 VAXG36 VDDQ12 T7
VDDQ13 T4
VDDQ14 P1
+VTT N7
VDDQ15
VDDQ16 N4

DDR3
VDDQ17 L1
J24 VTT1_45 VDDQ18 H1
FDI

J23 VTT1_46
H25 +VTT
1 1 VTT1_47
C141 C142
(Place these capacitors under CPU socket Edge, top layer)
22U_0805_6.3V6M 22U_0805_6.3V6M P10 1
2 2 VTT0_59 C143
VTT0_60 N10
VTT0_61 L10
B 10U_0805_10V4K B
VTT0_62 K10
2
Clarksfield: 21A
+VTT
+VTT Auburndale:18A
1.1V

VTT1_63 J22
K26 VTT1_48 VTT1_64 J20
J27 VTT1_49 VTT1_65 J18 1
PEG & DMI

1 1 J26 H21 C145

C146 C147 VTT1_50 VTT1_66
J25 VTT1_51 VTT1_67 H20
H27 H19 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
G27 VTT1_54 (Place these capacitors under CPU socket, top layer)
G26 VTT1_55
F26 +1.8VS
VTT1_56
E26 VTT1_57 VCCPLL1 L26
1.8V

E25 VTT1_58 VCCPLL2 L27

M26 +1.8VS_H_PLL 1U_0402_6.3V4Z 4.7U_0603_6.3V6K 2 1
VCCPLL3 R71 0_0805_5%
1 1 1 1
(Place these capacitors under CPU socket, top layer) Clarksfield: 1.35A C151 C152 C153 C154 C155
Auburndale:1.35A 1U_0402_6.3V4Z
2 2 2 2 22U_0805_6.3V6M

IC,AUB_CFD_rPGA,R0P9 2.2U_0603_6.3V4Z
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU POWER-2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 9 of 61
5 4 3 2 1
 5 4 3 2 1

JCPUI JCPUH JCPUE

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
K27 VSS161 AR31 VSS3 VSS83 AE32
K9 VSS162 AR28 VSS4 VSS84 AE31 AP25 RSVD1
K6 VSS163 AR26 VSS5 VSS85 AE30 AL25 RSVD2 RSVD34 AH25
D K3 VSS164 AR24 VSS6 VSS86 AE29 AL24 RSVD3 RSVD35 AK26 D
J32 VSS165 AR23 VSS7 VSS87 AE28 AL22 RSVD4
J30 VSS166 AR20 VSS8 VSS88 AE27 AJ33 RSVD5 RSVD36 AL26
J21 VSS167 AR17 VSS9 VSS89 AE26 AG9 RSVD6 RSVD_NCTF_37 AR2
J19 VSS168 AR15 VSS10 VSS90 AE6 M27 RSVD7
H35 VSS169 AR12 VSS11 VSS91 AD10 L28 RSVD8 RSVD38 AJ26
H32 VSS170 AR9 VSS12 VSS92 AC8 T54 PAD J17 RSVD9 (SA_DIMM_VREF) RSVD39 AJ27
H28 VSS171 AR6 VSS13 VSS93 AC4 T55 PAD H17 RSVD10(SB_DIMM_VREF)
H26 VSS172 AR3 VSS14 VSS94 AC2 G25 RSVD11
H24 VSS173 AP20 VSS15 VSS95 AB35 G17 RSVD12
H22 VSS174 AP17 VSS16 VSS96 AB34 E31 RSVD13 RSVD_NCTF_40 AP1
H18 VSS175 AP13 VSS17 VSS97 AB33 E30 RSVD14 RSVD_NCTF_41 AT2
H15 VSS176 AP10 VSS18 VSS98 AB32
H13 VSS177 AP7 VSS19 VSS99 AB31 RSVD_NCTF_42 AT3
H11 VSS178 AP4 VSS20 VSS100 AB30 RSVD_NCTF_43 AR1
H8 VSS179 AP2 VSS21 VSS101 AB29 WW41 Recommend not pull down
H5 VSS180 AN34 VSS22 VSS102 AB28 PCIE2.0 Jitter is over on ES1
H2 VSS181 AN31 VSS23 VSS103 AB27
G34 VSS182 AN23 VSS24 VSS104 AB26 RSVD45 AL28
G31 AN20 AB6 3.01K_0402_1% 1 @ R74 2 CFG0 AM30 AL29
VSS183 VSS25 VSS105 CFG1 CFG[0] RSVD46
G20 VSS184 AN17 VSS26 VSS106 AA10 AM28 CFG[1] RSVD47 AP30
G9 AM29 Y8 CFG2 AP31 AP32
VSS185 VSS27 VSS107 3.01K_0402_1% 1 @ R75 CFG3 CFG[2] RSVD48
G6 VSS186 AM27 VSS28 VSS108 Y4 2 AL32 CFG[3] RSVD49 AL27
G3 AM25 Y2 3.01K_0402_1% 1 @ R76 2 CFG4 AL30 AT31
VSS187 VSS29 VSS109 CFG5 CFG[4] RSVD50
F30 VSS188 AM20 VSS30 VSS110 W35 AM31 CFG[5] RSVD51 AT32
F27 AM17 W34 CFG6 AN29 AP33
VSS189 VSS31 VSS111 CFG7 CFG[6] RSVD52
F25 VSS190 AM14 VSS32 VSS112 W33 AM32 CFG[7] RSVD53 AR33
F22 AM11 W32 CFG8 AK32 AT33
VSS191 VSS33 VSS113 CFG9 CFG[8] RSVD_NCTF_54
F19 AM8 W31 AK31 AT34

RESERVED
C VSS192 VSS34 VSS114 CFG10 CFG[9] RSVD_NCTF_55 C
F16 VSS193 AM5 VSS35 VSS115 W30 AK28 CFG[10] RSVD_NCTF_56 AP35
E35 AM2 W29 CFG11 AJ28 AR35
VSS194 VSS36 VSS116 CFG[11] RSVD_NCTF_57
E32 AL34 W28 AN30 AR32
E29
E24
VSS195
VSS196
VSS197
VSS AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
CFG13
CFG14
AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58

E21 AL20 W6 CFG15 AJ29 E15

VSS198 VSS40 VSS120 CFG16 CFG[15] RSVD_TP_59
E18 VSS199 AL17 VSS41 VSS121 V10 AJ30 CFG[16] RSVD_TP_60 F15
E13 AL12 U8 CFG17 AK30 A2
VSS200 VSS42 VSS122 CFG18 CFG[17] KEY
E11 VSS201 AL9 VSS43 VSS123 U4 H16 RSVD_TP_86 RSVD62 D15
E8 VSS202 AL6 VSS44 VSS124 U2 RSVD63 C15
E5 AL3 T35 AJ15 RSVD64
VSS203 H_NCTF1 VSS45 VSS125 RSVD64 RSVD65
E2
D33
VSS204 VSS_NCTF1 AT35
AT1 H_NCTF2
PAD T4
PAD T5
AK29
AK27
VSS46 VSS126 T34
T33
Reserve via for test RSVD65 AH15
VSS205 VSS_NCTF2 VSS47 VSS127
D30 VSS206 VSS_NCTF3 AR34 AK25 VSS48 VSS128 T32 B19 RSVD15
D26 VSS207 VSS_NCTF4 B34 AK20 VSS49 VSS129 T31 A19 RSVD16
D9 B2 AK17 T30
NCTF

VSS208 VSS_NCTF5 H_NCTF6 VSS50 VSS130 RSVD17

D6 VSS209 VSS_NCTF6 B1 PAD T6 AJ31 VSS51 VSS131 T29 A20 RSVD17
D3 A35 H_NCTF7 PAD T7 AJ23 T28 RSVD18 B20
VSS210 VSS_NCTF7 VSS52 VSS132 RSVD18
C34 VSS211 AJ20 VSS53 VSS133 T27 RSVD_TP_66 AA5
C32 VSS212 AJ17 VSS54 VSS134 T26 U9 RSVD19 RSVD_TP_67 AA4
C29 VSS213 AJ14 VSS55 VSS135 T6 T9 RSVD20 RSVD_TP_68 R8
C28 VSS214 AJ11 VSS56 VSS136 R10 RSVD_TP_69 AD3
C24 VSS215 AJ8 VSS57 VSS137 P8 AC9 RSVD21 RSVD_TP_70 AD2
C22 VSS216 AJ5 VSS58 VSS138 P4 AB9 RSVD22 RSVD_TP_71 AA2
C20 VSS217 AJ2 VSS59 VSS139 P2 CFG0 - PCI-Express Configuration Select RSVD_TP_72 AA1
C19 VSS218 AH35 VSS60 VSS140 N35 RSVD_TP_73 R9
C16 VSS219 AH34 VSS61 VSS141 N34 RSVD_TP_74 AG7
B31 AH33 N33 *1:Single PEG C1 AE3
VSS220 VSS62 VSS142 RSVD_NCTF_23 RSVD_TP_75
B
B25 VSS221 AH32 VSS63 VSS143 N32 0:Bifurcation enabled A3 RSVD_NCTF_24 B
B21 VSS222 AH31 VSS64 VSS144 N31
B18 VSS223 AH30 VSS65 VSS145 N30 RSVD_TP_76 V4
B17 VSS224 AH29 VSS66 VSS146 N29 RSVD_TP_77 V5
B13 VSS225 AH28 VSS67 VSS147 N28 RSVD_TP_78 N2
B11 VSS226 AH27 VSS68 VSS148 N27 CFG3 - PCI-Express Static Lane Reversal J29 RSVD26 RSVD_TP_79 AD5
B8 VSS227 AH26 VSS69 VSS149 N26 J28 RSVD27 RSVD_TP_80 AD7
B6 VSS228 AH20 VSS70 VSS150 N6 RSVD_TP_81 W3
B4 AH17 M10 *1 :Normal Operation A34 W2
VSS229 VSS71 VSS151 RSVD_NCTF_28 RSVD_TP_82
A29 VSS230 AH13 VSS72 VSS152 L35 0 :Lane Numbers Reversed A33 RSVD_NCTF_29 RSVD_TP_83 N3
A27 VSS231 AH9 VSS73 VSS153 L32 15 -> 0, 14 -> 1, ... RSVD_TP_84 AE5
A23 VSS232 AH6 VSS74 VSS154 L29 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
A9 VSS233 AH3 VSS75 VSS155 L8 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34
AF4 VSS78 VSS158 K34 CFG4 - Display Port Presence
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30
*1:Disabled; No Physical Display Port
attached to Embedded Display Port IC,AUB_CFD_rPGA,R0P9
0:Enabled; An external Display Port @

IC,AUB_CFD_rPGA,R0P9 IC,AUB_CFD_rPGA,R0P9
device is connected to the Embedded
@ @ Display Port

*:Default

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU GND/RESERVED/XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 10 of 61
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

1
JDDRH
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_A_D4
DDR_A_D5
Reverse Type 7 DDR_A_DQS[0..7]

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z
DQ0 DQ5 7 DDR_A_DQS#[0..7]
1 1 DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 7 DDR_A_D[0..63]
+1.5V
C156

C157
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 VSS VSS 14 7 DDR_A_DM[0..7]
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16

1
DDR_A_D3 17 18 DDR_A_D7 7 DDR_A_MA[0..15]
DQ3 DQ7 R80
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12 1K_0402_1%
DDR_A_D9 DQ8 DQ12 DDR_A_D13
D 23 DQ9 DQ13 24 D
25 26

2
DDR_A_DQS#1 VSS VSS DDR_A_DM1
close to JDDRH.1 27 DQS1# DM1 28
DDR_A_DQS1 29 30
DQS1 RESET# SM_DRAMRST# 5,12
31 VSS VSS 32
DDR_A_D10 DDR_A_D14
DDR_A_D11
33
35
DQ10
DQ11
DQ14
DQ15
34
36 DDR_A_D15 For S3 Power Reduction
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
+1.5V
43 VSS VSS 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48

1
49 50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23 +V_DDR3_DIMM_REF R79
51 DQ18 DQ23 52
DDR_A_D19 53 54 1K_0402_1%
DQ19 VSS DDR_A_D28
55 VSS DQ28 56
DDR_A_D24 57 58 DDR_A_D29

2
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS 60 +VREF_DQA 2 1
61 62 DDR_A_DQS#3 0_0402_5% R92
VSS DQS3#

1
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3 R81
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30 1K_0402_1%
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 72 +VREF_DQB 2 1

2
VSS VSS 0_0402_5% R93

7 DDRA_CKE0 73 CKE0 CKE1 74 DDRA_CKE1 7

75 VDD VDD 76
C 77 78 DDR_A_MA15 C
NC A15 DDR_A_MA14
7 DDR_A_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD VDD 100
7 DDRA_CLK0 101 CK0 CK1 102 DDRA_CLK1 7
7 DDRA_CLK0# 103 CK0# CK1# 104 DDRA_CLK1# 7
105 VDD VDD 106
DDR_A_MA10 107 108
A10/AP BA1 DDR_A_BS1 7
7 DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# 7
111 VDD VDD 112
7 DDR_A_W E# 113 WE# S0# 114 DDRA_SCS0# 7
7 DDR_A_CAS# 115 CAS# ODT0 116 DDRA_ODT0 7
117 VDD VDD 118
DDR_A_MA13 +V_DDR3_DIMM_REF
119 A13 ODT1 120 DDRA_ODT1 7
7 DDRA_SCS1# 121 S1# NC 122
123 124 R89
VDD VDD +DDR_VREF_CA_DIMMA
125 TEST VREF_CA 126 1 2
127 128 0_0402_5%
DDR_A_D32 VSS VSS DDR_A_D36
129 DQ32 DQ36 130
DDR_A_D33 131 132 DDR_A_D37
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

DQ33 DQ37
133 VSS VSS 134
B DDR_A_DQS#4 DDR_A_DM4 B
135 DQS4# DM4 136
DDR_A_DQS4 137 138 1 1 Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DQS4 VSS DDR_A_D38
139 VSS DQ38 140
Place near JDDRH Command and Control signals of DIMMA Place near JDDRH.203 and 204
C161

C162

DDR_A_D34 141 142 DDR_A_D39

DDR_A_D35 DQ34 DQ39
143 DQ35 VSS 144
DDR_A_D44 2 2
145 VSS DQ44 146
DDR_A_D40 147 148 DDR_A_D45 +1.5V
DDR_A_D41 DQ40 DQ45 +1.5V +0.75VS
149 DQ41 VSS 150 SGA00002680
DDR_A_DQS#5

+
151 VSS DQS5# 152 1 2
DDR_A_DM5 153 154 DDR_A_DQS5 close to JDDRH.126 C163 330U_D2_2.5VM_R9M
DM5 DQS5 C164 1
155 VSS VSS 156 2 0.1U_0402_16V4Z C165 1 2 10U_0805_6.3V6M
DDR_A_D42 157 158 DDR_A_D46 C166 1 2 10U_0805_6.3V6M
DDR_A_D43 DQ42 DQ46 DDR_A_D47 C167 1
159 DQ43 DQ47 160 2 0.1U_0402_16V4Z
161 162 C168 1 2 10U_0805_6.3V6M C169 2 1 1U_0402_6.3V4Z
DDR_A_D48 VSS VSS DDR_A_D52 C170 1
163 DQ48 DQ52 164 2 0.1U_0402_16V4Z
DDR_A_D49 165 166 DDR_A_D53 C171 1 2 10U_0805_6.3V6M C172 2 1 1U_0402_6.3V4Z
DQ49 DQ53 C173 1
167 VSS VSS 168 2 0.1U_0402_16V4Z
DDR_A_DQS#6 169 170 DDR_A_DM6 C174 1 2 10U_0805_6.3V6M C175 2 1 1U_0402_6.3V4Z
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_A_D54 C176 1 2 10U_0805_6.3V6M C177 2 1 1U_0402_6.3V4Z
DDR_A_D50 VSS DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178 C178 1 2 10U_0805_6.3V6M
DQ51 VSS DDR_A_D60
179 VSS DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS DQS7# DDR_A_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
A
DDR_A_D58 191 192 DDR_A_D62 A
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
R90 1 2 195 196
10K_0402_5% VSS VSS
197 SA0 EVENT# 198 PM_EXTTS# 5,12
+3VS 199 VDDSPD SDA 200 PM_SMBDATA 12,25,29,39
201 202
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

SA1 SCL PM_SMBCLK 12,25,29,39

10K_0402_5%

1 1 +0.75VS 203 VTT VTT 204 +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
1

C182
C181 205 206 2009/11/13 2010/01/23 Title
GND1 BOSS1 Issued Date Deciphered Date
R91

2 2
207 GND2 BOSS2 208
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM0
Size Document Number Rev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FOX_AS0A626-UARN-7F_204P Custom 1.0
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 11 of 61
5 4 3 2 1
 A B C D E

+1.5V +1.5V

1
JDDRL
2
DDR3 SO-DIMM B
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_B_D4
DDR_B_D5
Reverse Type
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS 8 7 DDR_B_DQS#[0..7]
9 10 DDR_B_DQS#0

0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
DDR_B_DM0 VSS DQS0# DDR_B_DQS0
11 DM0 DQS0 12 7 DDR_B_DQS[0..7]
1 1 13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6 7 DDR_B_D[0..63]
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
C183

C184
19 VSS VSS 20 7 DDR_B_DM[0..7]
2 2 DDR_B_D8 DDR_B_D12
21 DQ8 DQ12 22
1 DDR_B_D9 23 24 DDR_B_D13 7 DDR_B_MA[0..15] 1
DQ9 DQ13
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS1# DM1
29 DQS1 RESET# 30 SM_DRAMRST# 5,11
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
close to JDDRL.1 35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72

7 DDRB_CKE0 73 CKE0 CKE1 74 DDRB_CKE1 7

75 VDD VDD 76
2 77 78 DDR_B_MA15 2
NC A15 DDR_B_MA14
7 DDR_B_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
7 DDRB_CLK0 101 CK0 CK1 102 DDRB_CLK1 7
7 DDRB_CLK0# 103 CK0# CK1# 104 DDRB_CLK1# 7
105 VDD VDD 106
DDR_B_MA10 107 108
A10/AP BA1 DDR_B_BS1 7
7 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 7
111 VDD VDD 112
7 DDR_B_W E# 113 WE# S0# 114 DDRB_SCS0# 7
7 DDR_B_CAS# 115 CAS# ODT0 116 DDRB_ODT0 7
117 VDD VDD 118
DDR_B_MA13 119 120
A13 ODT1 DDRB_ODT1 7 +V_DDR3_DIMM_REF
7 DDRB_SCS1# 121 S1# NC 122
123 124 R97
VDD VDD +DDR_VREF_CA_DIMMB
125 TEST VREF_CA 126 1 2 0_0402_5% Layout Note: Layout Note: Place these 4 Caps near Layout Note:
127 VSS VSS 128
DDR_B_D32 129 130 DDR_B_D36 Place near JDDRL Command and Control signals of DIMMB Place near JDDRL.203 and 204
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

DQ33 DQ37
133 VSS VSS 134
3 DDR_B_DQS#4 DDR_B_DM4 +1.5V 3
135 DQS4# DM4 136 1 1
DDR_B_DQS4 137 138 @ +1.5V +0.75VS
DQS4 VSS DDR_B_D38 C189 1 2 330U_B2_2.5VM_R15M

+
139 VSS DQ38 140
C187

C188

DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 DQ34 DQ39 2 2 C190 1
143 DQ35 VSS 144 2 0.1U_0402_16V4Z C191 1 2 10U_0805_6.3V6M
145 146 DDR_B_D44 C192 1 2 10U_0805_6.3V6M
DDR_B_D40 VSS DQ44 DDR_B_D45 C193 1
147 DQ40 DQ45 148 2 0.1U_0402_16V4Z
DDR_B_D41 149 150 C194 1 2 10U_0805_6.3V6M C195 2 1 1U_0402_6.3V4Z
DQ41 VSS DDR_B_DQS#5 C196 1
151 VSS DQS5# 152 2 0.1U_0402_16V4Z
DDR_B_DM5 153 154 DDR_B_DQS5 C197 1 2 10U_0805_6.3V6M C198 2 1 1U_0402_6.3V4Z
DM5 DQS5 C199 1
155 VSS VSS 156 close to JDDRL.126 2 0.1U_0402_16V4Z
DDR_B_D42 157 158 DDR_B_D46 C200 1 2 10U_0805_6.3V6M C201 2 1 1U_0402_6.3V4Z
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 162 C202 1 2 10U_0805_6.3V6M C203 2 1 1U_0402_6.3V4Z
DDR_B_D48 VSS VSS DDR_B_D52
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53 C204 1 2 10U_0805_6.3V6M
DQ49 DQ53
167 VSS VSS 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
DDR_B_D50 VSS DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS DDR_B_D60
179 VSS DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS DQS7# DDR_B_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
4
DDR_B_D58 191 192 DDR_B_D62 4
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
R98 1 2 195 196
10K_0402_5% VSS VSS
197 SA0 EVENT# 198 PM_EXTTS# 5,11
+3VS 199 VDDSPD SDA 200 PM_SMBDATA 11,25,29,39
201 SA1 SCL 202 PM_SMBCLK 11,25,29,39
2.2U_0603_6.3V4Z 1 R99
1 1
10K_0402_5%
2 +0.75VS 203 VTT VTT 204 +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
205 GND1 BOSS1 206 Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title
C207 C208
2 2
207 GND2 BOSS2 208
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM1
0.1U_0402_16V4Z Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FOX_AS0A626-U2RN-7F_204P Custom 1.0
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 12 of 61
A B C D E
 5 4 3 2 1

UV1A
PCIE_GTX_C_CRX_P[0..15]
PCIE_CTX_C_GRX_P15 6 PCIE_GTX_C_CRX_P[0..15]
100NH_LQW18ANR10J00D_5%_0603 150mA , 10mil AP17 Part 1 of 7 K1
PCIE_CTX_C_GRX_N15 PEX_RX0 GPIO0
AN17 PEX_RX0_N GPIO1 K2
1 2 0.1U_0402_16V4Z +PLLVDD PCIE_CTX_C_GRX_P14 AN19 K3 VGA_PWM PCIE_GTX_C_CRX_N[0..15]
+1.05VS_DGPU PEX_RX1 GPIO2 6 PCIE_GTX_C_CRX_N[0..15]
LV1 PCIE_CTX_C_GRX_N14 AP19 H3 VGA_ENVDD
PCIE_CTX_C_GRX_P13 PEX_RX1_N GPIO3 VGA_ENBKL
1 1 1 1 AR19 PEX_RX2 GPIO4 H2
CV9 CV10 CV11 CV12 PCIE_CTX_C_GRX_N13 AR20 H1 GPU_VID0 PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_P12 PEX_RX2_N GPIO5 GPU_VID1 GPU_VID0 58 6 PCIE_CTX_C_GRX_P[0..15]
4.7U_0603_6.3V6K AP20 H4
PEX_RX3 GPIO6 GPU_VID1 58
PCIE_CTX_C_GRX_N12 AN20 H5
2 2 2 2 0.1U_0402_16V4Z PCIE_CTX_C_GRX_P11 PEX_RX3_N GPIO7 PCIE_CTX_C_GRX_N[0..15]
AN22 PEX_RX4 GPIO8 H6 6 PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_N11 AP22 J7 THERM#_VGA
PCIE_CTX_C_GRX_P10 PEX_RX4_N GPIO9 THERM#_VGA 14
1U_0402_6.3V4Z AR22 K4
PCIE_CTX_C_GRX_N10 PEX_RX5 GPIO10
AR23 K5
PCIE_CTX_C_GRX_P9 PEX_RX5_N GPIO11
AP23 H7

GPIO
D PCIE_CTX_C_GRX_N9 PEX_RX6 GPIO12 TV1 D
AN23 PEX_RX6_N GPIO13 J4 TV6
PCIE_CTX_C_GRX_P8 AN25 J6
100NH_LQW18ANR10J00D_5%_0603 PCIE_CTX_C_GRX_N8 PEX_RX7 GPIO14 VGA_HDMI_HPD
+SP_PLLVDD
150mA , 10mil PCIE_CTX_C_GRX_P7
AP25 PEX_RX7_N GPIO15 L1
VGA_ENVDD
+1.05VS_DGPU 1 2 AR25 L2 1 2
LV2 PCIE_CTX_C_GRX_N7 PEX_RX8 GPIO16 RV1 @ 10K_0402_5%
AR26 L4
PCIE_CTX_C_GRX_P6 PEX_RX8_N GPIO17 VGA_ENBKL
1 1 AP26 PEX_RX9 GPIO18 M4 2 1
CV7 CV8 PCIE_CTX_C_GRX_N6 AN26 L7 RV2 @ 10K_0402_5%
PCIE_CTX_C_GRX_P5 PEX_RX9_N GPIO19 VGA_PWM
AN28 PEX_RX10 GPIO20 L5 2 1
1U_0402_6.3V4Z 4.7U_0603_6.3V6K PCIE_CTX_C_GRX_N5 AP28 K6 RV3 @ 10K_0402_5%
2 2 PCIE_CTX_C_GRX_P4 PEX_RX10_N GPIO21 VGA_HDMI_HPD
AR28 L6 1 2
PCIE_CTX_C_GRX_N4 PEX_RX11 GPIO22 RV5 100K_0402_5%
AR29 M6
LANE Reversal PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
AP29
PEX_RX11_N
PEX_RX12
GPIO23
AN29 PEX_RX12_N
PCIE_CTX_C_GRX_P2 AN31 N1
PCIE_CTX_C_GRX_N2 PEX_RX13 MIOA_D0
AP31 P4
PCIE_CTX_C_GRX_P1 PEX_RX13_N MIOA_D1
AR31 P1
PCIE_CTX_C_GRX_N1 PEX_RX14 MIOA_D2
AR32 PEX_RX14_N MIOA_D3 P2
PCIE_CTX_C_GRX_P0 AR34 P3
PCIE_CTX_C_GRX_N0 PEX_RX15 MIOA_D4
AP34 PEX_RX15_N MIOA_D5 T3
T2
MIOA_D6
T1

PCI EXPRESS
PCIE_GTX_C_CRX_P15 CV13 0.1U_0402_10V7K PCIE_GTX_CRX_P15 MIOA_D7
1 2 AL17 U4
PCIE_GTX_C_CRX_N15 CV14 0.1U_0402_10V7K PCIE_GTX_CRX_N15 PEX_TX0 MIOA_D8
1 2 AM17 PEX_TX0_N MIOA_D9 U1
PCIE_GTX_C_CRX_P14 CV15 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_P14 AM18 U2 +3VS_DGPU
PCIE_GTX_C_CRX_N14 CV16 0.1U_0402_10V7K PCIE_GTX_CRX_N14 PEX_TX1 MIOA_D10
1 2 AM19 U3
PCIE_GTX_C_CRX_P13 CV17 0.1U_0402_10V7K PCIE_GTX_CRX_P13 PEX_TX1_N MIOA_D11
1 2 AL19 PEX_TX2 MIOA_D12 R6
PCIE_GTX_C_CRX_N13 CV18 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_N13 AK19 T6 VGA_EDID_CLK 1 2

DVO
PCIE_GTX_C_CRX_P12 CV19 0.1U_0402_10V7K PCIE_GTX_CRX_P12 PEX_TX2_N MIOA_D13 RV6 2.2K_0402_5%
1 2 AL20 N6
PCIE_GTX_C_CRX_N12 CV20 0.1U_0402_10V7K PCIE_GTX_CRX_N12 PEX_TX3 MIOA_D14 VGA_EDID_DATA
1 2 AM20 PEX_TX3_N 1 2
PCIE_GTX_C_CRX_P11 CV21 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_P11 AM21 Y1 RV7 2.2K_0402_5%
PCIE_GTX_C_CRX_N11 CV22 0.1U_0402_10V7K PCIE_GTX_CRX_N11 PEX_TX4 MIOB_D0
1 2 AM22 Y2
PCIE_GTX_C_CRX_P10 CV23 0.1U_0402_10V7K PCIE_GTX_CRX_P10 PEX_TX4_N MIOB_D1 SMB_CLK_GPU
1 2 AL22 Y3 1 2
C PCIE_GTX_C_CRX_N10 CV24 0.1U_0402_10V7K PCIE_GTX_CRX_N10 PEX_TX5 MIOB_D2 RV8 2.2K_0402_5% C
1 2 AK22 PEX_TX5_N MIOB_D3 AB3
PCIE_GTX_C_CRX_P9 CV25 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_P9 AL23 AB2 SMB_DATA_GPU 1 2
PCIE_GTX_C_CRX_N9 CV26 0.1U_0402_10V7K PCIE_GTX_CRX_N9 PEX_TX6 MIOB_D4 RV9 2.2K_0402_5%
1 2 AM23 AB1
PCIE_GTX_C_CRX_P8 CV27 0.1U_0402_10V7K PCIE_GTX_CRX_P8 PEX_TX6_N MIOB_D5
1 2 AM24 PEX_TX7 MIOB_D6 AC4
PCIE_GTX_C_CRX_N8 CV28 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_N8 AM25 AC1
PCIE_GTX_C_CRX_P7 CV29 0.1U_0402_10V7K PCIE_GTX_CRX_P7 PEX_TX7_N MIOB_D7 THERM#_VGA
1 2 AL25 AC2 1 2
PCIE_GTX_C_CRX_N7 CV30 0.1U_0402_10V7K PCIE_GTX_CRX_N7 PEX_TX8 MIOB_D8 RV10 100K_0402_5%
1 2 AK25 PEX_TX8_N MIOB_D9 AC3
PCIE_GTX_C_CRX_P6 CV31 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_P6 AL26 AE3
PCIE_GTX_C_CRX_N6 CV32 0.1U_0402_10V7K PCIE_GTX_CRX_N6 PEX_TX9 MIOBD_10
1 2 AM26 PEX_TX9_N MIOB_D11 AE2
PCIE_GTX_C_CRX_P5 CV33 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_P5 AM27 U6 HDCP_SCL 1 2
PCIE_GTX_C_CRX_N5 CV34 0.1U_0402_10V7K PCIE_GTX_CRX_N5 PEX_TX10 MIOB_D12 RV11 2.2K_0402_5%
1 2 AM28 PEX_TX10_N MIOB_D13 W6
PCIE_GTX_C_CRX_P4 CV35 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_P4 AL28 Y6 HDCP_SDA 1 2
PCIE_GTX_C_CRX_N4 CV36 0.1U_0402_10V7K PCIE_GTX_CRX_N4 PEX_TX11 MIOB_D14 RV12 2.2K_0402_5%
1 2 AK28 PEX_TX11_N
PCIE_GTX_C_CRX_P3 CV37 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_P3 AK29 N3
PCIE_GTX_C_CRX_N3 CV38 0.1U_0402_10V7K PCIE_GTX_CRX_N3 PEX_TX12 MIOA_HSYNC
1 2 AL29 L3
PCIE_GTX_C_CRX_P2 CV39 0.1U_0402_10V7K PCIE_GTX_CRX_P2 PEX_TX12_N MIOA_VSYNC VGA_CRT_DAT
1 2 AM29 1 2
PCIE_GTX_C_CRX_N2 CV40 0.1U_0402_10V7K PCIE_GTX_CRX_N2 PEX_TX13 RV13 2.2K_0402_5%
1 2 AM30 W1
PCIE_GTX_C_CRX_P1 CV41 0.1U_0402_10V7K PCIE_GTX_CRX_P1 PEX_TX13_N MIOB_HSYNC VGA_CRT_CLK
1 2 AM31 W2 1 2
PCIE_GTX_C_CRX_N1 CV42 0.1U_0402_10V7K PCIE_GTX_CRX_N1 PEX_TX14 MIOB_VSYNC RV14 2.2K_0402_5%
1 2 AM32
PCIE_GTX_C_CRX_P0 CV43 0.1U_0402_10V7K PCIE_GTX_CRX_P0 PEX_TX14_N
1 2 AN32 PEX_TX15 MIOA_DE N2
PCIE_GTX_C_CRX_N0 CV44 1 2 0.1U_0402_10V7K PCIE_GTX_CRX_N0 AP32 P5 I2CB_SCL 1 2
PEX_TX15_N MIOA_CTL3 RV121 2.2K_0402_5%
N5
MIOA_VREF I2CB_SDA 1 2
@ Y5 RV122 2.2K_0402_5%
CLK_PCIE_VGA MIOB_DE
1 2 29 CLK_PCIE_VGA AR16 W3
RV29 10M_0402_5% CLK_PCIE_VGA# PEX_REFCLK MIOB_CTL3
29 CLK_PCIE_VGA# AR17 AF1
CLKREQ_VGA# PEX_REFCLK_N MIOB_VREF
AR13 PEX_CLKREQ_N
YV1 N4 1 2
PEX_TSTCLK_OUT MIOA_CLKIN RV15 10K_0402_5%
1 2 AJ17 R4
XTALIN XTAL_OUT @ RV16 200_0402_1% PEX_TSTCLK_OUT# PEX_TSTCLK_OUT MIOA_CLKOUT
1 2
Differential signal AJ18
PEX_TSTCLK_OUT_N
AE1 1 2
27MHZ_16PF_X5H027000FG1H MIOB_CLKIN RV17 10K_0402_5%
V4
B @ PLTRST_VGA#_R MIOB_CLKOUT B
1 1 32 PLTRST_VGA# 1 2 AM16 PEX_RST_N
CV45 CV46 RV18 0_0402_5% AG21 T4
20P_0402_50V8J 20P_0402_50V8J PEX_TERMP MIOA_CLKOUT_N
1 2 W4
@ @ RV19 2.49K_0402_1% MIOB_CLKOUT_N
2 2
U5
+PLLVDD MIOACAL_PD_VDDQ
AE9 T5
PLLVDD MIOACAL_PU_GND
+SP_PLLVDD AF9 AA7
SP_PLLVDD MIOBCAL_PD_VDDQ
Reserve 27MHZ Crystal at Pre-MP MIOBCAL_PU_GND
AA6
AD9 VID_PLLVDD
CLK

RV103 1 2 0_0402_5% XTALIN B1

25 27M_CLK XTAL_IN
XTAL_OUT B2 AM15 VGA_CRT_R
XTAL_OUT DACA_RED VGA_CRT_G
33,47,58 DGPU_PWR_EN AM14
RV105 DACA_GREEN VGA_CRT_B
D1 XTAL_OUTBUFF DACA_BLUE AL14
2

+3VS_DGPU 1 2 XTALSSIN D2
25 27M_SSC XTAL_SSIN
RV124 RV26 0_0402_5% AM13 VGA_CRT_HSYNC Reserve vias for EVT debug
10K_0402_5% DACA_HSYNC VGA_CRT_VSYNC
10K_0402_5% AL13
DACA_VSYNC
Internal Thermal Sensor
2

SMB_CLK_GPU E2 AJ12 +DACA_VDD 2 1

14 SMB_CLK_GPU +3VS_DGPU
5 1

SMB_DATA_GPU E1 I2CS_SCL DACA_VDD +DACA_VREF RV32

RV118 14 SMB_DATA_GPU I2CS_SDA DACA_VREF
AK12 0_0402_5% Close to GPU
DACA_RSET
DACs

10K_0402_5% DACA_RSET AK13

VGA_EDID_CLK E3
I2CC_SCL

1
CLKREQ_VGA# VGA_EDID_DATA E4 VGA_CRT_R
29 CLKREQ_PEG# 3 4 LVDS AK4 1 1 2
1

I2CC_SDA DACB_RED RV27 CV47 RV20 75_0402_1%

AL4
I2CB_SCL DACB_GREEN 124_0402_1% VGA_CRT_G
G3 AJ4 1 2
QV2B I2CB_SDA I2CB_SCL DACB_BLUE
Another at page47 G2 0.1U_0402_16V4Z RV21 75_0402_1%
I2C

2N7002DW-T/R7_SOT363-6 I2CB_SDA 2 VGA_CRT_B

AM1 1 2

2
VGA_CRT_CLK DACB_HSYNC RV23 75_0402_1%
CRT VGA_CRT_DAT
G1
G4
I2CA_SCL DACB_VSYNC
AM2
I2CA_SDA
AG7 +DACB_VDD 2 1
HDCP_SCL DACB_VDD RV31 10K_0402_5%
F6 I2CH_SCL DACB_VREF AK6
A HDCP_SDA A
G6 AH7
XTALSSIN I2CH_SDA DACB_RSET
1 RV28 2
@ 10K_0402_5%
N11P-LP1-A3_BGA969 N11PR3@
Reserved for internal SSC

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIE/DAC/GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 13 of 61
5 4 3 2 1
 5 4 3 2 1

UV1D Internal Thermal Sensor

SMB_CLK_GPU 13
Part 4 of 7
AM11
AM12
IFPA_TXC
IFPA_TXC_N
NC_0
NC_1
A2
A7 External VGA Thermal Sensor SMB_DATA_GPU 13
AM8 B7
IFPA_TXD0 NC_2

1
AL8
AM10
IFPA_TXD0_N NC_3
C5
C7
Address: 0x9A H RV33 RV34
IFPA_TXD1 NC_4
AM9 IFPA_TXD1_N NC_5 D5 0_0402_5% 0_0402_5%
AK10 D6 @ @
IFPA_TXD2 NC_6
AL10 D7

2
IFPA_TXD2_N NC_7 +3VS_DGPU
AK11 E5
IFPA_TXD3 NC_8 UV2
D
AL11 IFPA_TXD3_N NC_9 E7 D
F4 2 1 1 8 VGA_THMCLK
NC_10 CV53 0.1U_0402_16V4Z VDD SCLK
G5
NC_11 THERM_D+ VGA_THMDATA
AP13 G11 2 7
IFPB_TXC NC_12 CV54 D+ SDATA
AN13 G12
IFPB_TXC_N NC_13 THERM#_VGA
AN8 IFPB_TXD4 NC_14 G14 1 2 3 D- ALERT# 6 THERM#_VGA 13
AP8 IFPB_TXD4_N NC_15 G15
AP10 G27 THERM_D- 2200P_0402_50V7K 4 5
IFPB_TXD5 NC_16 THERM# GND
AN10 G28
IFPB_TXD5_N NC_17
AR11 IFPB_TXD6 NC_18 G24
AR10 G25 ADM1032ARMZ-2REEL_MSOP8
IFPB_TXD6_N NC_19
AN11 IFPB_TXD7 NC_20 H32
AP11 IFPB_TXD7_N NC_21 J18
J19
NC_22

NC
NC_23 J25
AM7 J26
IFPC_L0 NC_24 +3VS_DGPU
AM6 L29
IFPC_L0_N NC_25
AL5 IFPC_L1 NC_26 M7
AM5 M29
IFPC_L1_N NC_27
AM3 P6 +3VS_DGPU 2 RV123 1 2.2K_0402_5%
IFPC_L2 NC_28
AM4 IFPC_L2_N NC_29 P29 2 RV117 1 2.2K_0402_5%

5
AP1 R29 QV1B
IFPC_L3 NC_30
AR2 IFPC_L3_N NC_31 U7
V6 VGA_THMDATA 4 3
NC_32 EC_SMB_DA2 29,38,44,45
Y4
NC_33

2
AR8 AA4 QV1A 2N7002DW-T/R7_SOT363-6
IFPD_L0 NC_34
AR7 AB4
IFPD_L0_N NC_35 VGA_THMCLK
AP7 AB7 1 6 EC_SMB_CK2 29,38,44,45
IFPD_L1 NC_36
AN7 AC5
IFPD_L1_N NC_37 2N7002DW-T/R7_SOT363-6

LVDS/TMDS
AN5 AD6
IFPD_L2 NC_38
C AP5 AD29 C
IFPD_L2_N NC_39
AR5 IFPD_L3 NC_40 AE29
AR4 AF6
IFPD_L3_N NC_41
NC_42 AG6
NC_43 AG20
AH6 IFPE_L0 NC_44 AG29
AH5 IFPE_L0_N NC_45 AH29
AH4 AJ5
IFPE_L1 NC_46
AG4 AK15
IFPE_L1_N NC_47
AF4 AL7
IFPE_L2 NC_48
AF5
IFPE_L2_N
AE6
IFPE_L3
AE5
IFPE_L3_N VGA_CORE Sense
VDD_SENSE_0 D35 VDD_SENSE 58
AL2 IFPF_L0 VDD_SENSE_1 P7
AL3 AD20
IFPF_L0_N VDD_SENSE_2
AJ3
IFPF_L1
AJ2
IFPF_L1_N
AJ1
IFPF_L2
AH1 IFPF_L2_N GND_SENSE_0 AD19
AH2 IFPF_L3 GND_SENSE_1 E35
AH3 R7
IFPF_L3_N GND_SENSE_2

AP2 IFPC_AUX_I2CW_SCL
AN3
IFPC_AUX_I2CW_SDA_N TEST
B B
AP4 AP35 TESTMODE
+3VS_DGPU IFPD_AUX_I2CX_SCL TESTMODE
AN4 AP14 TV2
IFPD_AUX_I2CX_SDA_N JTAG_TCK
AN14 TV3
JTAG_TDI

1
AN16 TV4
VGA_HDMI_CLK VGA_HDMI_CLK JTAG_TDO
1
RV119
2
4.7K_0402_5% HDMI VGA_HDMI_DATA
AE4
AD4
IFPE_AUX_I2CY_SCL JTAG_TMS
AR14
AP16 1 2
TV5 10K_0402_5%
VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N JTAG_TRST_N RV41 @ 10K_0402_5% RV47
1 2
RV120 4.7K_0402_5%

2
AF3 IFPF_AUX_I2CZ_SCL
AF2
IFPF_AUX_I2CZ_SDA_N SERIAL
C3
ROM_CS_N ROM_SI
ROM_SI D3 ROM_SI 24
C4 ROM_SO ROM_SO 24
ROM_SO ROM_SCLK
D4 ROM_SCLK 24
ROM_SCLK

GENERAL A5
NC/SPDIF
A4 BUFRST_N
N9 1 2
MULTI_STRAP_REF0_GND RV48 40.2K_0402_1%
+3VS_DGPU 1 2 AB5 CEC
RV49 10K_0402_5% M9 1 2
STRAP0 MULTI_STRAP_REF1_GND RV50 40.2K_0402_1%
24 STRAP0 W5
STRAP1 STRAP0 THERM_D+
24 STRAP1 W7 B5
STRAP2 STRAP1 THERMDP THERM_D-
24 STRAP2 V7 B4
STRAP2 THERMDN

A N11P-LP1-A3_BGA969 N11PR3@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/HDMI/DP/THM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 14 of 61
5 4 3 2 1
 5 4 3 2 1

D D

+VGA_CORE +VGA_CORE
UV1G +VGA_CORE

AB11 VDD_0 VDD_56 P21 SF000002Z00

AB13 Part 7 of 7 P23 SGA00002680 1 1
AB15
VDD_1 VDD_57
P25 H=4.5
VDD_2 VDD_58 CV58 + + CV57
AB17 VDD_3 VDD_59 R11
AB19 VDD_4 VDD_60 R12 330U_2.5V_M_R17
AB21 R13 330U_D2_2.5VM_R9M
VDD_5 VDD_61 2 2
AB23 VDD_6 VDD_62 R14
AB25 VDD_7 VDD_63 R15
AC11 VDD_8 VDD_64 R16
AC12 VDD_9 VDD_65 R17
AC13 R18 +VGA_CORE
VDD_10 VDD_66
AC14 VDD_11 VDD_67 R19
AC15 R20 4.7U_0603_6.3V6K 1U_0402_6.3V4Z 4700P_0402_25V7K
VDD_12 VDD_68
AC16 VDD_13 VDD_69 R21
AC17 VDD_14 VDD_70 R22
AC18 VDD_15 VDD_71 R23 1 1 1

1
AC19 R24 CV59 CV60 CV61 CV212 CV62 CV63 CV64
VDD_16 VDD_72 @
AC20 VDD_17 VDD_73 R25
AC21 T12 0.22U_0402_6.3V6K

2
VDD_18 VDD_74 2 2 2
C AC22 VDD_19 VDD_75 T14 C
AC23 VDD_20 VDD_76 T16

POWER
AC24 VDD_21 VDD_77 T18
AC25 T20 0.22U_0402_6.3V6K 4.7U_0603_6.3V6K 4700P_0402_25V7K
VDD_22 VDD_78
AD12 VDD_23 VDD_79 T22
AD14 VDD_24 VDD_80 T24
AD16 VDD_25 VDD_81 V11
AD18 VDD_26 VDD_82 V13
AD22 VDD_27 VDD_83 V15
AD24 V17 +VGA_CORE
VDD_28 VDD_84
L11 VDD_29 VDD_85 V19
L12 V21 0.047U_0402_25V6K 0.022U_0402_25V7K
VDD_30 VDD_86
L13 VDD_31 VDD_87 V23
L14 VDD_32 VDD_88 V25
L15 VDD_33 VDD_89 W11 1 1 1 1 1 1 1
L16 W12 CV66 CV67 CV68 CV69 CV70 CV71 CV65
VDD_34 VDD_90
L17 VDD_35 VDD_91 W13
L18 W14 0.047U_0402_25V6K 0.022U_0402_25V7K
VDD_36 VDD_92 2 2 2 2 2 2 2
L19 VDD_37 VDD_93 W15
L20 VDD_38 VDD_94 W16
L21 VDD_39 VDD_95 W17
L22 W18 0.047U_0402_25V6K 0.022U_0402_25V7K 0.022U_0402_25V7K
VDD_40 VDD_96
L23 VDD_41 VDD_97 W19
L24 VDD_42 VDD_98 W20
L25 VDD_43 VDD_99 W21
M12 VDD_44 VDD_100 W22
M14 W23 +VGA_CORE
VDD_45 VDD_101
B M16 VDD_46 VDD_102 W24 B
M18 W25 0.01U_0402_25V7K 0.01U_0402_25V7K
VDD_47 VDD_103
M20 VDD_48 VDD_104 Y12
M22 VDD_49 VDD_105 Y14
M24 VDD_50 VDD_106 Y16 1 1 1 1 1 1
P11 Y18 CV74 CV75 CV76 CV77 CV78 CV79
VDD_51 VDD_107 0.01U_0402_25V7K
P13 VDD_52 VDD_108 Y20
P15 VDD_53 VDD_109 Y22
2 2 2 2 2 2
P17 VDD_54 VDD_110 Y24
P19 VDD_55
0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K

N11P-LP1-A3_BGA969 N11PR3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 15 of 61
5 4 3 2 1
 5 4 3 2 1

UV1E Close to Pin

Part 5 of 7
+VRAM_1.5VS 4.7U_0603_6.3V6K 0.1U_0402_16V4Z J23
2000mA AG11 0.1U_0402_16V4Z 1U_0402_6.3V4Z +1.05VS_DGPU
FBVDDQ_0 PEX_IOVDDQ_0
J24 FBVDDQ_1 PEX_IOVDDQ_1 AG12
1 1 1 1 1 J29 FBVDDQ_2 PEX_IOVDDQ_2 AG13 1 1 1 1 1 1
CV82 CV83 N11P@ N11P@ AA27 AG15
N11P@ CV84 CV85 CV86 FBVDDQ_3 PEX_IOVDDQ_3 CV87 CV88 CV89 CV90 CV91 CV92
AA29 FBVDDQ_4 PEX_IOVDDQ_4 AG16
4.7U_0603_6.3V6K N11P@ AA31 AG17
2 2 2 2 2 0.1U_0402_16V4Z FBVDDQ_5 PEX_IOVDDQ_5 2 2 2 2 2 2 10U_0603_6.3V6M
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22
0.1U_0402_16V4Z AC27 AG23 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
FBVDDQ_8 PEX_IOVDDQ_8
D
AD27 FBVDDQ_9 PEX_IOVDDQ_9 AG24 D
AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25
AJ28 AG26 0.1U_0402_16V4Z 1U_0402_6.3V4Z +1.05VS_DGPU
FBVDDQ_11 PEX_IOVDDQ_11
B18 FBVDDQ_12 PEX_IOVDDQ_12 AJ14
+VRAM_1.5VS 0.047U_0402_25V6K 0.01U_0402_25V7K 0.01U_0402_25V7K E21 AJ15 1 1 1 1 1 1
FBVDDQ_13 PEX_IOVDDQ_13
G17 FBVDDQ_14 PEX_IOVDDQ_14 AJ19
G18 AJ21 CV93 CV94 CV95 CV96 CV97 CV98
1 1 1 1 1 1 1 FBVDDQ_15 PEX_IOVDDQ_15
CV99 CV100 CV101 CV102 CV103 CV104 CV218 G22 AJ22
N11P@ FBVDDQ_16 PEX_IOVDDQ_16 2 2 2 2 2 2 10U_0603_6.3V6M
G8 FBVDDQ_17 PEX_IOVDDQ_17 AJ24
0.047U_0402_25V6K G9 AJ25
2 2 2 2 2 2 2 FBVDDQ_18 PEX_IOVDDQ_18 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
H29 FBVDDQ_19 PEX_IOVDDQ_19 AJ27

POWER
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
0.047U_0402_25V6K 0.01U_0402_25V7K 0.01U_0402_25V7K J15 AK20
FBVDDQ_21 PEX_IOVDDQ_21
J16 FBVDDQ_22 PEX_IOVDDQ_22 AK23
J17
J20
FBVDDQ_23
FBVDDQ_24
PEX_IOVDDQ_23
PEX_IOVDDQ_24
AK26
AL16 Close to Pin
J21 100NH_LQW18ANR10J00D_5%_0603
FBVDDQ_25 0.1U_0402_16V4Z 1U_0402_6.3V4Z
J22 1 2
Close to Pin N27
P27
FBVDDQ_26
FBVDDQ_27 500mA AK16
LV4
+1.05VS_DGPU

FBVDDQ_28 PEX_IOVDD_0 1 1 1 1 1
R27 AK17 CV109
FBVDDQ_29 PEX_IOVDD_1 CV105 CV117 CV107 CV108
T27 FBVDDQ_30 PEX_IOVDD_2 AK21
U27 AK24 @ @ 4.7U_0603_6.3V6K
FBVDDQ_31 PEX_IOVDD_3 2 2 2 2 4.7U_0603_6.3V6K 2
U29 FBVDDQ_32 PEX_IOVDD_4 AK27
V27 FBVDDQ_33 1U_0402_6.3V4Z
V29 FBVDDQ_34 20 MIL
V34
W 27
FBVDDQ_35 110mA AG14 +PEX_PLLVDD
FBVDDQ_36 PEX_PLLVDD
Y27 FBVDDQ_37 +3VS_DGPU
C 220mA C
2 1 +IFPAB_PLLVDD AK9 IFPAB_PLLVDD PEX_SVDD_3V3_0 AG19
1 2 RV110 10K_0402_5% AJ11 IFPAB_RSET PEX_SVDD_3V3_1 F7
RV96 @ 1K_0402_1% 1 1
+3VS_DGPU CV111
2 110K_0402_5% +IFPA_IOVDD AG9 IFPA_IOVDD
150mA CV110
RV113 2 1 +IFPB_IOVDD AG10 150mA J10 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
RV114 10K_0402_5% IFPB_IOVDD VDD33_0 0.1U_0402_16V4Z 2 2
VDD33_1 J11
VDD33_2 J12 1 1 1 1 1
2 1 +IFPC_PLLVDD AJ9 IFPC_PLLVDD
220mA VDD33_3 J13 CV114
1 @ 2 RV107 10K_0402_5% AK7 J9 CV217 CV216 CV112 CV113
RV51 1K_0402_1% IFPC_RSET VDD33_4 4.7U_0603_6.3V6K
2 1 +IFPC_IOVDD AJ8 285mA 2 2 2 2 2
RV109 10K_0402_5% IFPC_IOVDD
P9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
MIOA_VDDQ_0
2 1 +IFPD_PLLVDD AC6 IFPD_PLLVDD
220mA MIOA_VDDQ_1 R9
1 @ 2 RV99 10K_0402_5% AB6 T9
RV52 1K_0402_1% IFPD_RSET MIOA_VDDQ_2
MIOA_VDDQ_3 U9
2 1 +IFPD_IOVDD AK8 IFPD_IOVDD
285mA
RV97 10K_0402_5%
MIOB_VDDQ_0 AA9
2 1 +IFPEF_PLLVDD AJ6 220mA AB9 +3VS_DGPU
IFPEF_PLLVDD MIOB_VDDQ_1
1 2 RV115 10K_0402_5% AL1 IFPEF_RSET MIOB_VDDQ_2 W9
RV53@ 1K_0402_1% Y9
RV1161 10K_0402_5% +IFPE_IOVDD MIOB_VDDQ_3
2 AE7 IFPE_IOVDD
285mA 1 1
2 1 +IFPF_IOVDD AD7 285mA CV115 CV116
RV101 10K_0402_5% IFPF_IOVDD
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
N11P-LP1-A3_BGA969 N11PR3@
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 16 of 61
5 4 3 2 1
 5 4 3 2 1

UV1F

B3 Part 6 of 7
GND_0
B6 GND_1 GND_97 V18
B9 GND_2 GND_98 V20
B12 GND_3 GND_99 V22
B15 GND_4 GND_100 V24
B21 GND_5 GND_101 V31
B24 GND_6 GND_102 Y11
B27 GND_7 GND_103 Y13
B30 GND_8 GND_104 Y15
B33 GND_9 GND_105 Y17
D
C2 GND_10 GND_106 Y19 D
C34 GND_11 GND_107 Y21
E6 GND_12 GND_108 Y23
E9 GND_13 GND_109 Y25
E12 GND_14 GND_110 AA2
E15 GND_15 GND_111 AA5
E18 GND_16 GND_112 AA11
E24 GND_17 GND_113 AA12
E27 GND_18 GND_114 AA13
E30 GND_19 GND_115 AA14
F2 GND_20 GND_116 AA15
F31 GND_21 GND_117 AA16
F34 GND_22 GND_118 AA17
F5 GND_23 GND_119 AA18
J2 GND_24 GND_120 AA19
J5 GND_25 GND_121 AA20
J31 GND_26 GND_122 AA21
J34 GND_27 GND_123 AA22
K9 GND_28 GND_124 AA23
L9 GND_29 GND_125 AA24
M2 GND_30 GND_126 AA25
M5 GND_31 GND_127 AA34
M11 GND_32 GND_128 AB12
M13 GND_33 GND_129 AB14
M15 GND_34 GND_130 AB16
M17 GND_35 GND_131 AB18
M19 GND_36 GND_132 AB20
M21 GND_37 GND_133 AB22
M23 GND_38 GND_134 AB24
M25 GND_39 GND_135 AC9
C M31 GND_40 GND_136 AD2 C
M34 GND_41 GND_137 AD5

GND
N11 GND_42 GND_138 AD11
N12 GND_43 GND_139 AD13
N13 GND_44 GND_140 AD15
N14 GND_45 GND_141 AD17
N15 GND_46 GND_142 AD21
N16 GND_47 GND_143 AD23
N17 GND_48 GND_144 AD25
N18 GND_49 GND_145 AD31
N19 GND_50 GND_146 AD34
N20 GND_51 GND_147 AE11
N21 GND_52 GND_148 AE12
N22 GND_53 GND_149 AE13
N23 GND_54 GND_150 AE14
N24 GND_55 GND_151 AE15
N25 GND_56 GND_152 AE16
P12 GND_57 GND_153 AE17
P14 GND_58 GND_154 AE18
P16 GND_59 GND_155 AE19
P18 GND_60 GND_156 AE20
P20 GND_61 GND_157 AE21
P22 GND_62 GND_158 AE22
P24 GND_63 GND_159 AE23
R2 GND_64 GND_160 AE24
R5 GND_65 GND_161 AE25
R31 GND_66 GND_162 AG2
R34 GND_67 GND_163 AG5
T11 GND_68 GND_164 AG31
B
T13 GND_69 GND_165 AG34 B
T15 GND_70 GND_166 AK2
T17 GND_71 GND_167 AK5
T19 GND_72 GND_168 AK14
T21 GND_73 GND_169 AK31
T23 GND_74 GND_170 AK34
T25 GND_75 GND_171 AL6
U11 GND_76 GND_172 AL9
U12 GND_77 GND_173 AL12
U13 GND_78 GND_174 AL15
U14 GND_79 GND_175 AL18
U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
U17 GND_82 GND_178 AL27
U18 GND_83 GND_179 AL30
U19 GND_84 GND_180 AN2
U20 GND_85 GND_181 AN34
U21 GND_86 GND_182 AP3
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
U24 GND_89 GND_185 AP12
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
V5 GND_92 GND_188 AP21
V9 GND_93 GND_189 AP24
V12 GND_94 GND_190 AP27
V14 GND_95 GND_191 AP30
V16 GND_96 GND_192 AP33

A A
N11P-LP1-A3_BGA969 N11PR3@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 17 of 61
5 4 3 2 1
 5 4 3 2 1

UV1B

D Part 2 of 7 V32 CMDA0 D

MDA[0..63] FBA_CMD0 CMDA0 20
MDA0 L32 W31 CMDA1
20,21 MDA[0..63] FBA_D0 FBA_CMD1 CMDA1 20,21
MDA1 CMDA2
MDA2
N33
L33
FBA_D1
FBA_D2
FBA_CMD2
FBA_CMD3
U31
Y32 CMDA3
CMDA2
CMDA3
20
20,21
Mode C - Mirror Mode Mapping
MDA3 N34 AB35 CMDA4
FBA_D3 FBA_CMD4 CMDA4 20,21
MDA4 N35 AB34 CMDA5 DATA Bus
FBA_D4 FBA_CMD5 CMDA5 20,21
MDA5 P35 W35 CMDA6
FBA_D5 FBA_CMD6 CMDA6 20,21
MDA6 P33 W33 CMDA7
CMDA7 20,21 Address 0..31 32..63
MDA7 FBA_D6 FBA_CMD7 CMDA8
P34 FBA_D7 FBA_CMD8 W30 CMDA8 20,21
MDA8 K35 T34 CMDA9 CMD0 CKE_L
FBA_D8 FBA_CMD9 CMDA9 20,21
MDA9 K33 T35 CMDA10
FBA_D9 FBA_CMD10 CMDA10 20,21
MDA10 K34 AB31 CMDA11 CMD1 A8 A8
FBA_D10 FBA_CMD11 CMDA11 21
MDA11 H33 Y30 CMDA12
FBA_D11 FBA_CMD12 CMDA12 20,21
MDA12 G34 Y34 CMDA13 CMD2 CS0#_L
FBA_D12 FBA_CMD13 CMDA13 20,21
MDA13 G33 W32 CMDA14
FBA_D13 FBA_CMD14 CMDA14 20,21
MDA14 E34 AA30 CMD3 A7 A6
MDA15 FBA_D14 FBA_CMD15 CMDA16
E33 FBA_D15 FBA_CMD16 AA32 CMDA16 20,21
MDA16 G31 Y33 CMDA17 CMD4 A2 A1
FBA_D16 FBA_CMD17 CMDA17 20,21
MDA17 F30 U32 CMDA18
FBA_D17 FBA_CMD18 CMDA18 20,21
MDA18 G30 Y31 CMDA19 CMD5 A11 A9
FBA_D18 FBA_CMD19 CMDA19 20,21
MDA19 G32 U34 CMDA20
FBA_D19 FBA_CMD20 CMDA20 20,21
MDA20 K30 Y35 CMDA21 CMD6 A5 A4
FBA_D20 FBA_CMD21 CMDA21 20,21
MDA21 K32 W34 CMDA22
FBA_D21 FBA_CMD22 CMDA22 20,21
MDA22 H30 V30 CMD7 A0 A12
MDA23 FBA_D22 FBA_CMD23 CMDA24
K31 FBA_D23 FBA_CMD24 U35 CMDA24 20,21
MDA24 L31 U30 CMDA25 CMD8 CAS# CAS#
FBA_D24 FBA_CMD25 CMDA25 20
MDA25 L30 U33 CMDA26
FBA_D25 FBA_CMD26 CMDA26 20,21

MEMORY INTERFACE
C MDA26 M32 AB30 CMDA27 CMD9 BA1 A3 C
FBA_D26 FBA_CMD27 CMDA27 20,21
MDA27 N30 AB33 CMDA28
FBA_D27 FBA_CMD28 CMDA28 20,21
MDA28 M30 T33 CMDA29 CMD10 A9 A11
FBA_D28 FBA_CMD29 CMDA29 20,21
MDA29 P31 W29 CMDA30
FBA_D29 FBA_CMD30 CMDA30 20,21
MDA30 R32 CMD11 CS0#_H
MDA31 FBA_D30
R30 FBA_D31
MDA32 AG30 CMD12 BA0 BA0
MDA33 FBA_D32 DQMA0
AG32 FBA_D33 FBA_DQM0 P32 DQMA[7..0] 20,21
MDA34 AH31 H34 DQMA1 CMD13 BA2 A15
MDA35 FBA_D34 FBA_DQM1 DQMA2
AF31 FBA_D35 FBA_DQM2 J30
MDA36 AF30 P30 DQMA3 CMD14 A3 BA1
MDA37 FBA_D36 FBA_DQM3 DQMA4
AE30 FBA_D37 FBA_DQM4 AF32
MDA38 AC32 AL32 DQMA5 CMD15 CS1#_H
MDA39 FBA_D38 FBA_DQM5 DQMA6
AD30 FBA_D39 FBA_DQM6 AL34
+VRAM_1.5VS MDA40 DQMA7
AN33 FBA_D40 FBA_DQM7 AF35 CMD16 ODT_H
MDA41 AL31 FBA_D41

A
MDA42 AM33 CMD17 A4 A5
FBA_D42
1

MDA43 AL33
RV55 MDA44 FBA_D43 DQSA#0
AK30 FBA_D44 FBA_DQS_RN0 L35 DQSA#[7..0] 20,21 CMD18 A13 A14
1.1K_0402_1% MDA45 AK32 G35 DQSA#1
@ MDA46 FBA_D45 FBA_DQS_RN1 DQSA#2
AJ30 FBA_D46 FBA_DQS_RN2 H31 CMD19 WE# A10
12mil MDA47 AH30 N32 DQSA#3
2

+FB_VREF MDA48 FBA_D47 FBA_DQS_RN3 DQSA#4

AH33 FBA_D48 FBA_DQS_RN4 AD32 CMD20 A1 A2
MDA49 AH35 AJ31 DQSA#5
FBA_D49 FBA_DQS_RN5
1

1 MDA50 AH34 AJ35 DQSA#6 CMD21 A10 WE#

RV56 CV146 MDA51 FBA_D50 FBA_DQS_RN6 DQSA#7
AH32 FBA_D51 FBA_DQS_RN7 AC34
1.1K_0402_1% 0.01U_0402_25V7K MDA52 AJ33 CMD22 A12 A0
@ @ MDA53 FBA_D52
B AL35 FBA_D53 B
2 MDA54 AM34 CMD23 CS1#_L
2

MDA55 FBA_D54 DQSA0

AM35 FBA_D55 FBA_DQS_WP0 L34 DQSA[7..0] 20,21
MDA56 AF33 H35 DQSA1 CMD24 RAS# RAS#
MDA57 FBA_D56 FBA_DQS_WP1 DQSA2
AE32 FBA_D57 FBA_DQS_WP2 J32
MDA58 AF34 N31 DQSA3 CMD25 ODT_L
MDA59 FBA_D58 FBA_DQS_WP3 DQSA4
AE35 FBA_D59 FBA_DQS_WP4 AE31
MDA60 AE34 AJ32 DQSA5 CMD26 A6 A7
MDA61 FBA_D60 FBA_DQS_WP5 DQSA6
AE33 FBA_D61 FBA_DQS_WP6 AJ34
MDA62 AB32 AC33 DQSA7 CMD27 CKE_H
MDA63 FBA_D62 FBA_DQS_WP7
AC35 FBA_D63
CMD28 RST RST
MMZ1608D301BT_0603 20 mil
+1.05VS_DGPU 1 2 1U_0402_6.3V4Z +FB_AVDD AG27 CMD29 A14 A13
LV11 FB_DLLAVDD CLKA0
AF27 FB_PLLAVDD FBA_CLK0 T32 CLKA0 20
1 1 1 1 T31 CLKA0# CMD30 A15 BA2
FBA_CLK0_N CLKA0# 20
CV147 CV148 CV149 CV150
@ +FB_VREF J27
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K FB_VREF CLKA1
FBA_CLK1 AC31 CLKA1 21
2 2 2 2 CLKA1#
+VRAM_1.5VS 2 1 T30 FBA_DEBUG FBA_CLK1_N AC30 CLKA1# 21
1U_0402_6.3V4Z RV57 10K_0402_5%

N11P-LP1-A3_BGA969 N11PR3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MEM Interface A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 18 of 61
5 4 3 2 1
 5 4 3 2 1

UV1C

Part 3 of 7
MDB[0..63] MDB0 B13 C17 CMDB0
22,23 MDB[0..63] FBC_D0 FBC_CMD0 CMDB0 22
MDB1 D13 B19 CMDB1
FBC_D1 FBC_CMD1 CMDB1 22,23
MDB2 CMDB2
MDB3
A13
A14
FBC_D2
FBC_D3
FBC_CMD2
FBC_CMD3
D18
F21 CMDB3
CMDB2
CMDB3
22
22,23
Mode C - Mirror Mode Mapping
MDB4 C16 A23 CMDB4
FBC_D4 FBC_CMD4 CMDB4 22,23
D MDB5 B16 D21 CMDB5 DATA Bus D
FBC_D5 FBC_CMD5 CMDB5 22,23
MDB6 A17 B23 CMDB6
FBC_D6 FBC_CMD6 CMDB6 22,23
MDB7 D16 E20 CMDB7
CMDB7 22,23 Address 0..31 32..63
MDB8 FBC_D7 FBC_CMD7 CMDB8
C13 FBC_D8 FBC_CMD8 G21 CMDB8 22,23
MDB9 B11 F20 CMDB9 CMD0 CKE_L
FBC_D9 FBC_CMD9 CMDB9 22,23
MDB10 C11 F19 CMDB10
FBC_D10 FBC_CMD10 CMDB10 22,23
MDB11 A11 F23 CMDB11 CMD1 A8 A8
FBC_D11 FBC_CMD11 CMDB11 23
MDB12 C10 A22 CMDB12
FBC_D12 FBC_CMD12 CMDB12 22,23
MDB13 C8 C22 CMDB13 CMD2 CS0#_L
FBC_D13 FBC_CMD13 CMDB13 22,23
MDB14 B8 B17 CMDB14
FBC_D14 FBC_CMD14 CMDB14 22,23
MDB15 A8 F24 CMD3 A7 A6
MDB16 FBC_D15 FBC_CMD15 CMDB16
E8 FBC_D16 FBC_CMD16 C25 CMDB16 22,23
MDB17 F8 E22 CMDB17 CMD4 A2 A1
FBC_D17 FBC_CMD17 CMDB17 22,23
MDB18 F10 C20 CMDB18
FBC_D18 FBC_CMD18 CMDB18 22,23
MDB19 F9 B22 CMDB19 CMD5 A11 A9
FBC_D19 FBC_CMD19 CMDB19 22,23
MDB20 F12 A19 CMDB20
FBC_D20 FBC_CMD20 CMDB20 22,23
MDB21 D8 D22 CMDB21 CMD6 A5 A4
FBC_D21 FBC_CMD21 CMDB21 22,23
MDB22 D11 D20 CMDB22
FBC_D22 FBC_CMD22 CMDB22 22,23
MDB23 E11 E19 CMD7 A0 A12
MDB24 FBC_D23 FBC_CMD23 CMDB24
D12 FBC_D24 FBC_CMD24 D19 CMDB24 22,23
MDB25 E13 F18 CMDB25 CMD8 CAS# CAS#
FBC_D25 FBC_CMD25 CMDB25 22
MDB26 F13 C19 CMDB26

MEMORY INTERFACE C
FBC_D26 FBC_CMD26 CMDB26 22,23
MDB27 F14 F22 CMDB27 CMD9 BA1 A3
FBC_D27 FBC_CMD27 CMDB27 22,23
MDB28 F15 C23 CMDB28
FBC_D28 FBC_CMD28 CMDB28 22,23
MDB29 E16 B20 CMDB29 CMD10 A9 A11
FBC_D29 FBC_CMD29 CMDB29 22,23
MDB30 F16 A20 CMDB30
FBC_D30 FBC_CMD30 CMDB30 22,23
MDB31 F17 CMD11 CS0#_H
MDB32 FBC_D31
C D29 FBC_D32 C
MDB33 F27 CMD12 BA0 BA0
MDB34 FBC_D33 DQMB0
F28 FBC_D34 FBC_DQM0 A16 DQMB[7..0] 22,23
MDB35 E28 D10 DQMB1 CMD13 BA2 A15
MDB36 FBC_D35 FBC_DQM1 DQMB2
D26 FBC_D36 FBC_DQM2 F11
MDB37 F25 D15 DQMB3 CMD14 A3 BA1
MDB38 FBC_D37 FBC_DQM3 DQMB4
D24 FBC_D38 FBC_DQM4 D27
MDB39 E25 D34 DQMB5 CMD15 CS1#_H
MDB40 FBC_D39 FBC_DQM5 DQMB6
E32 FBC_D40 FBC_DQM6 A34
MDB41 F32 D28 DQMB7 CMD16 ODT_H
MDB42 FBC_D41 FBC_DQM7
D33 FBC_D42
MDB43 E31 CMD17 A4 A5
MDB44 FBC_D43 DQSB#0
C33 FBC_D44 FBC_DQS_RN0 B14 DQSB#[7..0] 22,23
MDB45 F29 B10 DQSB#1 CMD18 A13 A14
MDB46 FBC_D45 FBC_DQS_RN1 DQSB#2
D30 FBC_D46 FBC_DQS_RN2 D9
MDB47 E29 E14 DQSB#3 CMD19 WE# A10
MDB48 FBC_D47 FBC_DQS_RN3 DQSB#4
B29 FBC_D48 FBC_DQS_RN4 F26
MDB49 C31 D31 DQSB#5 CMD20 A1 A2
MDB50 FBC_D49 FBC_DQS_RN5 DQSB#6
C29 FBC_D50 FBC_DQS_RN6 A31
MDB51 B31 A26 DQSB#7 CMD21 A10 WE#
MDB52 FBC_D51 FBC_DQS_RN7
C32 FBC_D52
MDB53 B32 CMD22 A12 A0
MDB54 FBC_D53
B35 FBC_D54
MDB55 B34 C14 DQSB0 CMD23 CS1#_L
FBC_D55 FBC_DQS_WP0 DQSB[7..0] 22,23
MDB56 A29 A10 DQSB1
MDB57 FBC_D56 FBC_DQS_WP1 DQSB2
B28 FBC_D57 FBC_DQS_WP2 E10 CMD24 RAS# RAS#
MDB58 A28 D14 DQSB3
MDB59 FBC_D58 FBC_DQS_WP3 DQSB4
B C28 FBC_D59 FBC_DQS_WP4 E26 CMD25 ODT_L B
MDB60 C26 D32 DQSB5
MDB61 FBC_D60 FBC_DQS_WP5 DQSB6
D25 FBC_D61 FBC_DQS_WP6 A32 CMD26 A6 A7
MDB62 B25 B26 DQSB7
MDB63 FBC_D62 FBC_DQS_WP7
A25 FBC_D63 CMD27 CKE_H
CMD28 RST RST
+VRAM_1.5VS 1 2 K27 E17 CLKB0
FBCAL_PD_VDDQ FBC_CLK0 CLKB0 22
RV58 40.2_0402_1% D17 CLKB0# CMD29 A14 A13
FBC_CLK0_N CLKB0# 22
1 2 L27 FBCAL_PU_GND
RV59 40.2_0402_1% D23 CLKB1 CMD30 A15 BA2
FBC_CLK1 CLKB1 23
1 N11P@ 2 M27 FBCAL_TERM_GND FBC_CLK1_N E23 CLKB1#
CLKB1# 23
RV60 40.2_0402_1%
FBC_DEBUG G19 1 2 +VRAM_1.5VS
10K_0402_5% RV61
RV60 N11M@
60.4_0402_1%
N11P-LP1-A3_BGA969 N11PR3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MEM Interface C
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 19 of 61
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits MDA[0..63]

CMDA[30..0]
18,21

18,21

DQMA[7..0] 18,21
UV5 UV6
DQSA[7..0] 18,21
+VRAM_1.5VS +FBA_VREF0 M8 E3 MDA1 +FBA_VREF0 M8 E3 MDA29
VREFCA DQL0 VREFCA DQL0 DQSA#[7..0] 18,21
H1 F7 MDA6 H1 F7 MDA26
VREFDQ DQL1 MDA0 VREFDQ DQL1 MDA30
DQL2 F2 DQL2 F2
1

D CMDA7 N3 F8 MDA3 CMDA7 N3 F8 MDA24 D

RV62 CMDA20 A0 DQL3 MDA4 CMDA20 A0 DQL3 MDA27
P7 A1 DQL4 H3 Group0 P7 A1 DQL4 H3 Group3
CMDA4 P3 H8 MDA7 CMDA4 P3 H8 MDA25
1.1K_0402_1% CMDA14 A2 DQL5 MDA2 CMDA14 A2 DQL5 MDA31
N2 A3 DQL6 G2 N2 A3 DQL6 G2
4PCS@ CMDA17 MDA5 CMDA17 MDA28
P8 H7 P8 H7
Mode C - Mirror
2

+FBA_VREF0 CMDA6 A4 DQL7 CMDA6 A4 DQL7

P2 A5 P2 A5
CMDA26 R8 CMDA26 R8
A6 A6
Mode Mapping
1

1 CMDA3 R2 D7 MDA22 CMDA3 R2 D7 MDA14

RV63 CV151 CMDA1 A7 DQU0 MDA18 CMDA1 A7 DQU0 MDA9
T8 A8 DQU1 C3 T8 A8 DQU1 C3
0.01U_0402_25V7K CMDA10 R3 C8 MDA23 CMDA10 R3 C8 MDA12
1.1K_0402_1% 4PCS@ CMDA21 A9 DQU2 MDA19 CMDA21 A9 DQU2 MDA11
2
L7 A10/AP DQU3 C2 Group2 L7 A10/AP DQU3 C2 DATA Bus
4PCS@ CMDA5 R7 A7 MDA20 CMDA5 R7 A7 MDA13 Group1
2

CMDA22 A11 DQU4 MDA17 CMDA22 A11 DQU4 MDA8 Address

N7 A12 DQU5 A2 N7 A12 DQU5 A2 0..31 32..63
CMDA18 T3 B8 MDA21 CMDA18 T3 B8 MDA15
CMDA29 A13 DQU6 MDA16 CMDA29 A13 DQU6 MDA10
T7 A14 DQU7 A3 T7 A14 DQU7 A3 CMD0 CKE_L
CMDA30 M7 CMDA30 M7
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD1 A8 A8
CMDA12 M2 B2 CMDA12 M2 B2 CMD2 CS0#_L
CMDA9 BA0 VDD CMDA9 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CLKA0 CMDA13 M3 G7 CMDA13 M3 G7 CMD3 A7 A6
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 CMD4 A2 A1
2

VDD N1 VDD N1
RV64 CLKA0 J7 N9 CLKA0 J7 N9 CMD5 A11 A9
18 CLKA0 CK VDD CK VDD
243_0402_1% CLKA0# K7 R1 CLKA0# K7 R1
18 CLKA0# CK VDD CK VDD
4PCS@ CMDA0 K9 R9 CMDA0 K9 R9 CMD6 A5 A4
CKE/CKE0 VDD CKE/CKE0 VDD
C C
1

CMD7 A0 A12
CLKA0# CMDA25 K1 A1 CMDA25 K1 A1 CMDA27
CMDA2 ODT/ODT0 VDDQ CMDA2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD8 CAS# CAS#
CMDA24 J3 C1 CMDA24 J3 C1 CMDA25
CMDA8 RAS VDDQ CMDA8 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD9 BA1 A3
CMDA19 L3 D2 CMDA19 L3 D2 CMDA16
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 CMD10 A9 A11
F1 F1 CMDA0
DQSA0 VDDQ DQSA3 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD11 CS0#_H
DQSA2 C7 H9 DQSA1 C7 H9
DQSU VDDQ DQSU VDDQ

2
CMD12 BA0 BA0
RV98 RV100 RV102 RV104
DQMA0 E7 A9 DQMA3 E7 A9 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% CMD13 BA2 A15
DQMA2 DML VSS DQMA1 DML VSS 4PCS@ 4PCS@ 4PCS@ 4PCS@
D3 DMU VSS B3 D3 DMU VSS B3
E1 E1 CMD14 A3 BA1

1
VSS VSS
VSS G8 VSS G8
DQSA#0 G3 J2 DQSA#3 G3 J2 CMD15 CS1#_H
DQSA#2 DQSL VSS DQSA#1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 CMD16 ODT_H
VSS M9 VSS M9
VSS P1 VSS P1 CMD17 A4 A5
CMDA28 T2 P9 CMDA28 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1 CMD18 A13 A14
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
CMD19 WE# A10
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 CMD20 A1 A2 B
1

RV65 RV66 L1 B9 RV67 L1 B9

NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 CMD21 A10 WE#
10K_0402_5% L9 D8 L9 D8
4PCS@ NCZQ1 VSSQ 4PCS@ NCZQ1 VSSQ
E2 E2 CMD22 A12 A0
2

2
4PCS@ VSSQ VSSQ
E8 E8
2

VSSQ VSSQ
VSSQ F9 VSSQ F9 CMD23 CS1#_L
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 CMD24 RAS# RAS#
96-BALL 96-BALL CMD25 ODT_L
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 CMD26 A6 A7
@ @
CMD27 CKE_H
+VRAM_1.5VS +VRAM_1.5VS CMD28 RST RST
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CMD29 A14 A13
1 1 1 1 1 1 1 1 1 1 1 1 1 1 CMD30 A15 BA2
CV152 CV153 CV154 CV155 CV156 CV157 CV158 CV159 CV160 CV161 CV162 CV163 CV164 CV165

4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM A Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 20 of 61
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits

MDA[0..63] 18,20

CMDA[30..0] 18,20
UV8 UV7
+VRAM_1.5VS
DQMA[7..0] 18,20
+FBA_VREF1 M8 E3 MDA38 +FBA_VREF1 M8 E3 MDA56
VREFCA DQL0 MDA33 VREFCA DQL0 MDA57
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSA[7..0] 18,20
1
F2 MDA39 F2 MDA58
RV68 CMDA22 DQL2 MDA32 CMDA22 DQL2 MDA59
D N3 A0 DQL3 F8 N3 A0 DQL3 F8 DQSA#[7..0] 18,20 D
CMDA4 P7 H3 MDA37 Group4 CMDA4 P7 H3 MDA60 Group7
1.1K_0402_1% CMDA20 A1 DQL4 MDA34 CMDA20 A1 DQL4 MDA61
P3 A2 DQL5 H8 P3 A2 DQL5 H8
4PCS@ CMDA9 N2 G2 MDA36 CMDA9 N2 G2 MDA62
2

+FBA_VREF1 CMDA6 A3 DQL6 MDA35 CMDA6 A3 DQL6 MDA63

P8 A4 DQL7 H7 P8 A4 DQL7 H7
CMDA17 P2 CMDA17 P2
A5 A5
1

1 CMDA3 R8 CMDA3 R8
RV69 CV166 CMDA26 A6 MDA41 CMDA26 A6 MDA51
0.01U_0402_25V7K CMDA1
R2
T8
A7
A8
DQU0
DQU1
D7
C3 MDA45 CMDA1
R2
T8
A7
A8
DQU0
DQU1
D7
C3 MDA52 Mode C - Mirror Mode Mapping
1.1K_0402_1% 4PCS@ CMDA5 R3 C8 MDA42 CMDA5 R3 C8 MDA48
4PCS@ 2 CMDA19 A9 DQU2 MDA44 CMDA19 A9 DQU2 MDA53
L7 C2 L7 C2 DATA Bus
2

CMDA10 A10/AP DQU3 MDA43 CMDA10 A10/AP DQU3 MDA49

R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group6
CMDA7 N7 A2 MDA46 CMDA7 N7 A2 MDA54 Address 0..31 32..63
CMDA29 A12 DQU5 MDA40 CMDA29 A12 DQU5 MDA50
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA18 T7 A3 MDA47 CMDA18 T7 A3 MDA55 CMD0 CKE_L
CMDA13 A14 DQU7 CMDA13 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+VRAM_1.5VS +VRAM_1.5VS
CMD1 A8 A8
CMDA12 M2 B2 CMDA12 M2 B2 CMD2 CS0#_L
CMDA14 BA0 VDD CMDA14 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CLKA1 CMDA30 M3 G7 CMDA30 M3 G7 CMD3 A7 A6
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 CMD4 A2 A1
2

VDD N1 VDD N1
RV70 CLKA1 J7 N9 CLKA1 J7 N9 CMD5 A11 A9
18 CLKA1 CK VDD CK VDD
243_0402_1% CLKA1# K7 R1 CLKA1# K7 R1
18 CLKA1# CK VDD CK VDD
4PCS@ CMDA27 K9 R9 CMDA27 K9 R9 CMD6 A5 A4
CKE/CKE0 VDD CKE/CKE0 VDD
C C
1

CMD7 A0 A12
CLKA1# CMDA16 K1 A1 CMDA16 K1 A1
CMDA11 ODT/ODT0 VDDQ CMDA11 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD8 CAS# CAS#
CMDA24 J3 C1 CMDA24 J3 C1
CMDA8 RAS VDDQ CMDA8 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD9 BA1 A3
CMDA21 L3 D2 CMDA21 L3 D2
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 CMD10 A9 A11
VDDQ F1 VDDQ F1
DQSA4 F3 H2 DQSA7 F3 H2 CMD11 CS0#_H
DQSA5 DQSL VDDQ DQSA6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
CMD12 BA0 BA0
DQMA4 E7 A9 DQMA7 E7 A9 CMD13 BA2 A15
DQMA5 DML VSS DQMA6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 CMD14 A3 BA1
VSS G8 VSS G8
DQSA#4 G3 J2 DQSA#7 G3 J2 CMD15 CS1#_H
DQSA#5 DQSL VSS DQSA#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 CMD16 ODT_H
VSS M9 VSS M9
VSS P1 VSS P1 CMD17 A4 A5
CMDA28 T2 P9 CMDA28 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1 CMD18 A13 A14
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
CMD19 WE# A10
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 CMD20 A1 A2 B
RV71 L1 B9 RV72 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 CMD21 A10 WE#
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
4PCS@ E2 4PCS@ E2 CMD22 A12 A0
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 CMD23 CS1#_L
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 CMD24 RAS# RAS#
96-BALL 96-BALL CMD25 ODT_L
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 CMD26 A6 A7
@ @
CMD27 CKE_H
+VRAM_1.5VS +VRAM_1.5VS
CMD28 RST RST
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
CMD29 A14 A13
1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV167 CV168 CV169 CV170 CV171 CV172 CV173 CV174 CV175 CV176 CV177 CV178 CV179 CV180 CMD30 A15 BA2
4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM A Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 21 of 61
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits MDB[0..63]

CMDB[30..0]
19,23

19,23

DQMB[7..0] 19,23

DQSB[7..0] 19,23
+VRAM_1.5VS UV9 UV10
DQSB#[7..0] 19,23
+FBB_VREF0 M8 E3 MDB24 +FBB_VREF0 M8 E3 MDB16
VREFCA DQL0 VREFCA DQL0
1
D H1 F7 MDB25 H1 F7 MDB17 D
RV73 VREFDQ DQL1 MDB26 VREFDQ DQL1 MDB18
DQL2 F2 DQL2 F2
CMDB7 N3 F8 MDB29 CMDB7 N3 F8 MDB19
1.1K_0402_1% CMDB20 A0 DQL3 MDB28 CMDB20 A0 DQL3 MDB20
P7 A1 DQL4 H3 Group3 P7 A1 DQL4 H3 Group2
8PCS@ CMDB4 MDB31 CMDB4 MDB21
P3 H8 P3 H8
Mode C - Mirror
2

+FBB_VREF0 CMDB14 A2 DQL5 MDB30 CMDB14 A2 DQL5 MDB22

N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDB17 P8 H7 MDB27 CMDB17 P8 H7 MDB23
A4 DQL7 A4 DQL7
Mode Mapping
1

1 CMDB6 P2 CMDB6 P2
RV74 CV181 CMDB26 A5 CMDB26 A5
R8 A6 R8 A6
0.01U_0402_25V7K CMDB3 R2 D7 MDB5 CMDB3 R2 D7 MDB13
1.1K_0402_1% 8PCS@ CMDB1 A7 DQU0 MDB1 CMDB1 A7 DQU0 MDB9
2
T8 A8 DQU1 C3 T8 A8 DQU1 C3 DATA Bus
8PCS@ CMDB10 R3 C8 MDB6 CMDB10 R3 C8 MDB14
2

CMDB21 A9 DQU2 MDB3 CMDB21 A9 DQU2 MDB11 Address

L7 A10/AP DQU3 C2 Group0 L7 A10/AP DQU3 C2 0..31 32..63
CMDB5 R7 A7 MDB4 CMDB5 R7 A7 MDB12 Group1
CMDB22 A11 DQU4 MDB2 CMDB22 A11 DQU4 MDB8
N7 A12 DQU5 A2 N7 A12 DQU5 A2 CMD0 CKE_L
CMDB18 T3 B8 MDB7 CMDB18 T3 B8 MDB15
CMDB29 A13 DQU6 MDB0 CMDB29 A13 DQU6 MDB10
T7 A14 DQU7 A3 T7 A14 DQU7 A3 CMD1 A8 A8
CMDB30 M7 CMDB30 M7
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS CMD2 CS0#_L
CMDB12 M2 B2 CMDB12 M2 B2 CMD3 A7 A6
CMDB9 BA0 VDD CMDB9 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CLKB0 CMDB13 M3 G7 CMDB13 M3 G7 CMD4 A2 A1
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 CMD5 A11 A9
2

VDD N1 VDD N1
RV75 CLKB0 J7 N9 CLKB0 J7 N9 CMD6 A5 A4
19 CLKB0 CK VDD CK VDD
C 243_0402_1% CLKB0# K7 R1 CLKB0# K7 R1 C
19 CLKB0# CK VDD CK VDD
8PCS@ CMDB0 K9 R9 CMDB0 K9 R9 CMD7 A0 A12
CKE/CKE0 VDD CKE/CKE0 VDD
1

CMD8 CAS# CAS#

CLKB0# CMDB25 K1 A1 CMDB25 K1 A1
CMDB2 ODT/ODT0 VDDQ CMDB2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD9 BA1 A3
CMDB24 J3 C1 CMDB24 J3 C1
CMDB8 RAS VDDQ CMDB8 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD10 A9 A11
CMDB19 L3 D2 CMDB19 L3 D2 CMDB27
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 CMD11 CS0#_H
F1 F1 CMDB25
DQSB3 VDDQ DQSB2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD12 BA0 BA0
DQSB0 C7 H9 DQSB1 C7 H9 CMDB16
DQSU VDDQ DQSU VDDQ
CMD13 BA2 A15
CMDB0
DQMB3 E7 A9 DQMB2 E7 A9 CMD14 A3 BA1
DQMB0 DML VSS DQMB1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 CMD15 CS1#_H

2
VSS G8 VSS G8
DQSB#3 G3 J2 DQSB#2 G3 J2 RV108 RV111 RV112 CMD16 ODT_H
DQSB#0 DQSL VSS DQSB#1 DQSL VSS RV106 10K_0402_5% 10K_0402_5% 10K_0402_5%
B7 DQSU VSS J8 B7 DQSU VSS J8
M1 M1 10K_0402_5% 8PCS@ 8PCS@ 8PCS@ CMD17 A4 A5
VSS VSS 8PCS@
M9 M9

1
VSS VSS
VSS P1 VSS P1 CMD18 A13 A14
CMDB28 T2 P9 CMDB28 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1 CMD19 WE# A10
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
B CMD20 A1 A2 B
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 CMD21 A10 WE#
1

RV76 RV77 L1 B9 RV78 L1 B9

NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 CMD22 A12 A0
10K_0402_5% L9 D8 L9 D8
8PCS@ NCZQ1 VSSQ 8PCS@ NCZQ1 VSSQ
E2 E2 CMD23 CS1#_L
2

2
8PCS@ VSSQ VSSQ
E8 E8
2

VSSQ VSSQ
VSSQ F9 VSSQ F9 CMD24 RAS# RAS#
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 CMD25 ODT_L
96-BALL 96-BALL CMD26 A6 A7
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 CMD27 CKE_H
@ @
CMD28 RST RST
+VRAM_1.5VS +VRAM_1.5VS CMD29 A14 A13
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CMD30 A15 BA2
1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV182 CV183 CV184 CV185 CV186 CV187 CV188 CV189 CV190 CV191 CV192 CV193 CV194 CV195

8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2
A 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 8PCS@ 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 8PCS@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM C Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 22 of 61
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits MDB[0..63] 19,22

CMDB[30..0] 19,22
UV11 UV12

+VRAM_1.5VS DQMB[7..0] 19,22

+FBB_VREF1 M8 E3 MDB39 +FBB_VREF1 M8 E3 MDB48
VREFCA DQL0 MDB35 VREFCA DQL0 MDB49
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSB[7..0] 19,22
D F2 MDB38 F2 MDB50 D
DQL2 DQL2
1
CMDB22 N3 F8 MDB33 CMDB22 N3 F8 MDB51
A0 DQL3 A0 DQL3 DQSB#[7..0] 19,22
RV79 CMDB4 P7 H3 MDB36 Group4 CMDB4 P7 H3 MDB52 Group6
CMDB20 A1 DQL4 MDB34 CMDB20 A1 DQL4 MDB53
P3 A2 DQL5 H8 P3 A2 DQL5 H8
1.1K_0402_1% CMDB9 N2 G2 MDB37 CMDB9 N2 G2 MDB54
8PCS@ CMDB6 A3 DQL6 MDB32 CMDB6 A3 DQL6 MDB55
P8 H7 P8 H7
2

+FBB_VREF1 CMDB17 A4 DQL7 CMDB17 A4 DQL7

P2 A5 P2 A5
CMDB3 CMDB3
R8 A6 R8 A6 Mode C - Mirror Mode Mapping
1

1 CMDB26 R2 D7 MDB41 CMDB26 R2 D7 MDB63

RV80 CV196 CMDB1 A7 DQU0 MDB47 CMDB1 A7 DQU0 MDB57
T8 A8 DQU1 C3 T8 A8 DQU1 C3
0.01U_0402_25V7K CMDB5 R3 C8 MDB44 CMDB5 R3 C8 MDB61 DATA Bus
1.1K_0402_1% 8PCS@ CMDB19 A9 DQU2 MDB46 CMDB19 A9 DQU2 MDB59
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
8PCS@ 2 CMDB10 MDB42 CMDB10 MDB60 Address
R7 A7 Group5 R7 A7 Group7 0..31 32..63
2

CMDB7 A11 DQU4 MDB45 CMDB7 A11 DQU4 MDB56

N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDB29 T3 B8 MDB40 CMDB29 T3 B8 MDB62 CMD0 CKE_L
CMDB18 A13 DQU6 MDB43 CMDB18 A13 DQU6 MDB58
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDB13 M7 CMDB13 M7 CMD1 A8 A8
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD2 CS0#_L
CMDB12 M2 B2 CMDB12 M2 B2
CMDB14 BA0 VDD CMDB14 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD3 A7 A6
CMDB30 M3 G7 CMDB30 M3 G7
CLKB1 BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD4 A2 A1
VDD K8 VDD K8
VDD N1 VDD N1 CMD5 A11 A9
2

CLKB1 J7 N9 CLKB1 J7 N9
19 CLKB1 CK VDD CK VDD
RV81 CLKB1# K7 R1 CLKB1# K7 R1 CMD6 A5 A4
19 CLKB1# CK VDD CK VDD
C 243_0402_1% CMDB27 K9 R9 CMDB27 K9 R9 C
CKE/CKE0 VDD CKE/CKE0 VDD
8PCS@ CMD7 A0 A12
1

CMDB16 K1 A1 CMDB16 K1 A1 CMD8 CAS# CAS#

CLKB1# CMDB11 ODT/ODT0 VDDQ CMDB11 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDB24 J3 C1 CMDB24 J3 C1 CMD9 BA1 A3
CMDB8 RAS VDDQ CMDB8 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDB21 L3 D2 CMDB21 L3 D2 CMD10 A9 A11
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD11 CS0#_H
DQSB4 F3 H2 DQSB6 F3 H2
DQSB5 DQSL VDDQ DQSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD12 BA0 BA0
CMD13 BA2 A15
DQMB4 E7 A9 DQMB6 E7 A9
DQMB5 DML VSS DQMB7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD14 A3 BA1
VSS E1 VSS E1
VSS G8 VSS G8 CMD15 CS1#_H
DQSB#4 G3 J2 DQSB#6 G3 J2
DQSB#5 DQSL VSS DQSB#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD16 ODT_H
VSS M1 VSS M1
VSS M9 VSS M9 CMD17 A4 A5
VSS P1 VSS P1
CMDB28 T2 P9 CMDB28 T2 P9 CMD18 A13 A14
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD19 WE# A10
B CMD20 A1 A2 B
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV82 L1 B9 RV83 L1 B9 CMD21 A10 WE#
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 CMD22 A12 A0
8PCS@ E2 8PCS@ E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD23 CS1#_L
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD24 RAS# RAS#
VSSQ G9 VSSQ G9
CMD25 ODT_L
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD26 A6 A7
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
@ @ CMD27 CKE_H
+VRAM_1.5VS CMD28 RST RST
+VRAM_1.5VS +VRAM_1.5VS
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CMD29 A14 A13
1 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+ CV122
1 1 1 1 1 1 1 CMD30 A15 BA2
1 1 1 1 1 1 1 CV205 CV206 CV207 CV208 CV209 CV210 CV211
330U_2.5V_M_R17 CV198 CV199 CV200 CV201 CV202 CV203 CV204
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z
2 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z 2 2 2 2 2 2 2
SF000002Z00 2 2 2 2 2 2 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 8PCS@
H=4.5 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 8PCS@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM C Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 23 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS_DGPU Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SO VDD33 XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
ROM_SCLK VDD33 PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLLEN_TERM

2
RV87 RV85 RV86 ROM_SI VDD33 RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
45.3K_0402_1% 34.8K_0402_1% 20K_0402_1%
N11P@ STRAP2 VDD33 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
D D

1
STRAP1 VDD33 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
14 STRAP0 STRAP0
14 STRAP1 STRAP1 STRAP0 VDD33 USER[3] USER[2] USER[1] USER[0]
14 STRAP2 STRAP2

2
RV84 RV88 RV89
45.3K_0402_1% 34.8K_0402_1% 15.4K_0402_1%
@ @ N11M@
Resistor Values Pull-up to +3VS Pull-down to Gnd
Device ID straps
1

1
5K 1000 0000
DeviceID PCI_DEVID[4..0] ROM_SCLK STRAP2 10K 1001 0001
15K 1010 0010
+3VS_DGPU
N11P-LP1 0xA2B [01011] Pull down 15K Pull up 20K
20K 1011 0011
N11M-GE1 0xA75 [10101] Pull up 15K Pull down 30K 25K 1100 0100
30K 1101 0101
2

2
N11M-OP1 0xA72 [10010] Pull up 15K Pull down 15K
RV90 RV91 RV92 35K 1110 0110
4.99K_0402_1% 4.99K_0402_1% 15.4K_0402_1%
C @ @ N11M@ 45K 1111 0111 C
1

14 ROM_SI ROM_SI
14 ROM_SO ROM_SO
14 ROM_SCLK ROM_SCLK
2

SUB_VENDOR XCLK_417
2

RV93
X76 15.4K_0402_1% RV94 RV95
@ 10K_0402_1% 15.4K_0402_1% 0 No VBIOS ROM (Default) 0 277MHz (Default)
N11P@
1

1 BIOS ROM is present 1 Reserved

FB_0_BAR_SIZE USER Straps

1110=EDID
0 256MB (Default) User[3:0]

VRAM RAMCFG[3..0] RV93 1 Reserved 1000-1100 Customer defined

B B

Hynix H5TQ1G63BFR-12C 512MB 0010 PD 15K SD034154280 3GIO_PADCFG PEX_PLL_EN_TERM

SA000032400 3GIO_PADCFG[3:0] 0
DDR3 1GB 0010 PD 15K SD034154280 Disable (Default)

64M16 Samsung K4W1G1646E-HC12 512MB 0011 PD 20K SD034200280 1110 Notebook Default 1 Enable
SA000035700
1GB 0011 PD 20K SD034200280 SLOT_CLOCK_CFG
0 GPU and MCH don't share a common reference clock

DDR3 Reserved for 128M16 1 GPU and MCH share a common reference clock (Default)

128M16 SMBUS_ALT_ADDR VGA_DEVICE

0 0x9E (Default) 0 3D Device

A 1 0x9C (Multi-GPU usage) 1 VGA Device (Default) A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MSIC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 24 of 61
5 4 3 2 1
 A B C D E F G H

Clock Generator For SED +3VS_CK505

For SED

1
FBMH1608HM601-T_0603 For SED
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CK505 R110
R100 1 1 1 1 For SED 10K_0402_5%

1
FBMH1608HM601-T_0603

2
C209 C210 C211 C212 C251 +1.05VS 1 2 10U_0805_10V4Z 0.1U_0402_16V4Z +1.05VS_CK505

2
R401 47P_0402_50V8J R101 1 1 1 1 CK_PW RGD

1
0_0603_5% @ 2 2 2 2 C252
10U_0805_10V4Z 0.1U_0402_16V4Z C219 C220 C221 C222 47P_0402_50V8J

6
1

2
2 2 2 2
1 1
FBMH1608HM601-T_0603 0.1U_0402_16V4Z 0.1U_0402_16V4Z Q6A
+1.5VS 1 2 0.1U_0402_16V4Z +1.5VS_CK505 2
R120 2N7002DW -T/R7_SOT363-6 CLK_ENABLE# 56
1 1 1 1 another at page 39

1
For SED
C267 C213 C214 C215
@
2 2 2 2
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CK505
Silego Have Internal Pull-Up
+1.05VS_CK505
H_STP_CPU# 10K_0402_5% 2 1 R105
+1.05VS_CK505 +3VS_CK505

+1.5VS_CK505
Low Power: SA00003HQ10
U5
+3VS_CK505
1 VDD_USB_48 SCL 32 PM_SMBCLK 11,12,29,39
2 VSS_48M SDA 31 PM_SMBDATA 11,12,29,39
3 30 CPU_SEL 1 2
29 CLK_DOT DOT_96 REF_0/CPU_SEL CLK_14M_PCH 29
4 29 33_0402_5% R102 10K_0402_5% 2 @ 1 R119 +1.05VS
29 CLK_DOT# DOT_96# VDD_REF
5 28 CLK_XTAL_IN
VDD_27 XTAL_IN
13 27M_CLK 1 R391 2 33_0402_5% 27M_CLK_R 6 27MHZ XTAL_OUT 27 CLK_XTAL_OUT
13 27M_SSC 1 R143 2 33_0402_5% 27M_SSC_R 7 27MHZ_SS VSS_REF 26
8 25 CK_PW RGD CPU_SEL 10K_0402_5% 2 1 R106
USB_48 CKPWRGD/PD#
9 VSS_27M VDD_CPU 24 IDT Have Internal Pull-Down
2 10 23 2
29 CLK_SATA SATA CPU_0 CLK_BCLK 29
29 CLK_SATA# 11 SATA# CPU_0# 22 CLK_BCLK# 29
12 VSS_SRC VSS_CPU 21
29 PCH_CLK_DMI 13 SRC_1 CPU_1 20 CPU_SEL CPU_0/0# CPU_1/1#
29 PCH_CLK_DMI# 14 SRC_1# CPU_1# 19
15 VDD_SRC_IO VDD_CPU_IO 18
H_STP_CPU# 16 CPU_STOP# VDD_SRC 17 +1.5VS_CK505 CLK_XTAL_OUT 0 (Default) 133MHz 133MHz
Routing the
33 Y1
TGND trace at
CLK_XTAL_IN 1 2 1 100MHz 100MHz
RTM890N-631-VB-GRT_QFN_32P _5X5 2 2
14.318MHZ_16PF_7A14300083
least 10mil
C223 C224
22P_0402_50V8J 22P_0402_50V8J
1 1

1.5A
LVDS / Int.Camera / TouchScreen / Int.MIC Conn +LCDVDD_R 2 L1
0_0805_5%
1 +LCD_VDD
+3VS_LVDS_CAM
1 1
+LCD_VDD +3VS 0.1U_0402_16V4Z D84 C226 C227
1 2 2 0.1U_0402_16V4Z 4.7U_0805_10V4Z
C225 2 2
1
1

3
3 R107 +3VS 0_0603_5% JLVDS @ 3
150_0603_5% R108 R388 1
W=20mils PACDN042Y3R_SOT23-3
W=60mils +3VS 2 1 1 2 2 LCD_EDID_CLK 31
100K_0402_5% USB20_P11_R 3 3 4 4 LCD_EDID_DATA 31 Reserve for EMI request
Camera USB20_N11_R 5 6 INT_MIC_CLK 42
6 2

5 6 R82 0_0402_5%
2 7 7 8 8 INT_MIC_DATA 42
C228 9 10 PCH_PW M_R 1 2 @
31 LCD_TXOUT0+ 9 10
0.1U_0402_16V7K
31 LCD_TXOUT0- 11 11 12 12 BKOFF#_R Int.MIC
3

S
Q1A
1 G 31 LCD_TXOUT1+ 13 13 14 14 L57 @ Touch Screen
2N7002DW -T/R7_SOT363-6 2 1 2 2 Q17
31 LCD_TXOUT1- 15 15 16 16 USB20_N12_R Touch Screen
R109 47K_0402_5% 1 AO3413_SOT23 17 18 USB20_P12_R USB20_N12_R 1 2 USB20_N12 32
31 LCD_TXOUT2+ 17 18 1 2
3

C229 D 19 20 +3VS
31 LCD_TXOUT2-
1

0.01U_0402_25V7K +LCD_VDD 19 20
31 LCD_TXCLK+ 21 21 22 22
23 24 +LCDVDD_R USB20_P12_R 4 3 USB20_P12 32
2 31 LCD_TXCLK- 23 24 4 3
31 UMA_ENVDD 5 25 25 26 26
Q1B 27 28 +LCD_INV W CM-2012-900T_0805
2N7002DW -T/R7_SOT363-6 BKOFF#_R 27 28
W=60mils 1 44 BKOFF# 1 2 29 30
4

29 30
2

33_0402_5% R137 R121 0_0402_5%

C233 31 1 2 @
GND1
1

R112 0.1U_0402_16V4Z To prevent EC pin from damage 32 +3VS

100K_0402_5% 2 R113 GND2 B+
10K_0402_5% ACES_88242-3001 Rated Current MAX:600mA
1

UMA PD 100K ohm L2 2 1 For EMI request

DIS PD 10K ohm FBMA-L11-201209-221LMA30T_0805 1 1
2

1 1 1
C236 C231 C232
Reserve for EMI request C234 C235 680P_0402_50V7K 680P_0402_50V7K
2 2
0.1U_0402_16V4Z
68P_0402_50V8J 0.1U_0402_25V6 @ @
R78 0_0402_5% @ 2 2 2
1 2 CAM@ 1 R195 2 0_0402_5%
4 44 INVT_PW M 4
31 PCH_PW M 1 R170 2 0_0402_5% PCH_PW M_R

W CM-2012-900T_0805
32 USB20_N11 4 3 USB20_N11_R
4 3
Camera Security Classification Compal Secret Data Compal Electronics, Inc.
32 USB20_P11 1 2 USB20_P11_R
1 2
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title
L55 @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator (CK505)/ LVDS CONN
R96 0_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
CAM@ Custom 1.0
1 2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 25 of 61
A B C D E F G H
 A B C D E

CRT CONNECTOR

1
+5VS 1
D6 +CRT_VCC_R +CRT_VCC
2 F1 30mil
1 1 2
3 RB491D_SOT23-3 1
1.1A_6V_MINISMDC110F-2
If=1A C237
@ 0.1U_0402_16V4Z

1
D3 D4 D5 2

+3VS
DAN217_SC59 DAN217_SC59 DAN217_SC59

3
@ @ @

JCRT
L3 6 6
31 UMA_CRT_R 1 2 11 11
NBQ100505T-800Y_0402 CRT_R_L 1 1
7 7
L4 CRT_DDC_DAT 12
CRT_G_L 12
31 UMA_CRT_G 1 2 2 2
NBQ100505T-800Y_0402 8
HSYNC 8
13 13
L5 CRT_B_L 3 3
31 UMA_CRT_B 1 2 +CRT_VCC 9 9
NBQ100505T-800Y_0402 VSYNC 14 16
2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
2 14 G 2
4 4 G 17
150_0402_1%

150_0402_1%

150_0402_1%

1 1 1 1 1 1 10 10
1

CRT_DDC_CLK 15
R138 R139 R140 C238 C239 C240 C241 C242 C243 15
5 5
2 2 2 2 2 2 ALLTO_C10532-11505-L_15P-T
@
2

+CRT_VCC

1 2 2 1
C244 0.1U_0402_16V4Z R141 10K_0402_5%
5
1OE#
P

2 4 D_CRT_HSYNC 1 2 +CRT_VCC +3VS

31 UMA_CRT_HSYNC A Y L6 10_0402_5%
G

U6
SN74AHCT1G125GW _SOT353-5 D_CRT_VSYNC 1 2
3

2
L7 10_0402_5%
R147 R146

10P_0402_50V8J

10P_0402_50V8J
+CRT_VCC 4.7K_0402_5% 4.7K_0402_5%
1 1

2
Q2A
3 C245 C246 3

1
5
1

@ @ CRT_DDC_DAT 6 1 UMA_CRT_DATA 31
2 2
OE#
P

5
2 4 2N7002DW -T/R7_SOT363-6 Q2B
31 UMA_CRT_VSYNC A Y
G

U7 CRT_DDC_CLK 3 4 UMA_CRT_CLK 31
SN74AHCT1G125GW _SOT353-5 1 1
3

2N7002DW -T/R7_SOT363-6 1 1
C250 C249
470P_0402_50V8J 470P_0402_50V8J C248 C247
@ 2 2 @ 33P_0402_50V8K 33P_0402_50V8K
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title
CRT\TV\LVDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 26 of 61
A B C D E
 5 4 3 2 1

HDMI CEC Controller U17

44,49 EC_SMB_CK1 1 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 11 CEC_INT# 44 +3VL

+3VL +3VL +3VL +3VL

+3VL 2 12 CEC_TEST 1 CEC@ 2

P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# R171 4.7K_0402_5%

1
R184
R193 D9 2 CEC@ 1CEC_RST# CEC_FSHUPD1 CEC@ 2 4.7K_0402_5% R185
10K_0402_5% CH751H-40PT_SOD323-2 R174 4.7K_0402_5%
3 RESET# SA000037Z70 P1_4/TXD0 13
R178 4.7K_0402_5% CEC@ 4.7K_0402_5%

2
CEC@ CEC_FSHUPD (Pin13) CEC@
CEC@ 2 CEC@ 1CEC_XOUT 4 Low= Force to update flash.

G
14
2

1 1

2
HDMI_CECIN R179 47K_0402_5% XOUT/P4_7 P1_3/KI3#/AN11/TZOUT
D D
+3VL HDMI_SCLK 1 3 HDMI_CLK

2
R581 5 15 CEC@ Q52
CEC@ 27K_0402_5% VSS/AVSS P1_2/KI2#/AN10/CMP0_2 Q47 BSH111_SOT23-3

G
D 1 2
1

CEC@ C848 1U_0402_6.3V4Z BSH111_SOT23-3 CEC@

Q49 2 2 CEC@ 1CEC_XIN 6
Address:0011010X 16 1 2 HDMI_SDATA CEC@ 1 3 HDMI_DATA
2
2N7002_SOT23-3 G HDMI_CEC R181 47K_0402_5% XIN/P4_6 P4_2/VREF C384 0.1U_0402_16V4Z
CEC@

S
S
3

7 17 HDMI_CLK
VCC/AVCC P1_1/KI1#/AN9/CMP0_1
D
1

HDMI_CECOUT 1 R194 2 2 Q50 2 CEC@ 1 8 18 HDMI_DATA

27K_0402_5% G 2N7002_SOT23-3 R176 4.7K_0402_5% MODE P1_0/KI0#/AN8/CMP0_0
CEC@ S C340 1
3
1

CEC@ 0.1U_0402_16V4Z HDMI_CECIN 9 19 HDMI_HPD_R 2 CEC@1 +3VL

R190 CEC@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 R177 10K_0402_5%
100K_0402_5%
CEC@ 2 HDMI_CECOUT 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA1 44,49
2

R5F211A4C33SP-W 4_LSSOP20
CEC@

+3VS
UMA_DVI_TXC- 1 2 R157 HDMI_R_CK-
@ 0_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
L8 +5VL
1 1 1 1 1 1 1 1
1 2 C256 C283 C257 C258 C302 C285 C284 C268
C 1 2 HDMI_HPD IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ C
2 1
2 R314 1K_0402_5% 10U_0805_10V4Z 0.1U_0402_16V4Z
C264 2 2 2 2 2 2 2 2
4 4 3 3 CEC@ 2

2
R186 C265 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
IHDMI@ OCE2012120YZF_0805 CEC@ U9 100K_0402_5% 0.1U_0402_16V4Z
UMA_DVI_TXC+ 1
1 2 R173 HDMI_R_CK+ IHDMI@

OE#
P
@ 0_0402_5% HDMI_HPD_R 1 IHDMI@
2 A Y 4
0.1U_0402_16V4Z U20

1
G +3VS
UMA_DVI_TXD0+ 1 2 R175 HDMI_R_D0+ CEC@ 25 OE# 2 @ 1
3

@ 0_0402_5% OE* R161 10K_0402_5% +HDMI_5V_OUT

L9 74AHCT1G125GW _SOT353-5 2 VCC3V HDMI_SCLK
1 1 2 2 11 VCC3V SCL_SINK 28 1 IHDMI@ 2
15 R153 2.2K_0402_5%
VCC3V HDMI_SDATA
21 VCC3V SDA_SINK 29 1 IHDMI@ 2
4 3 26 R130 2.2K_0402_5%
4 3 VCC3V
33 VCC3V
IHDMI@ OCE2012120YZF_0805 R169 40 30 HDMI_HPD
UMA_DVI_TXD0- VCC3V HPD_SINK
1 2 R180 HDMI_R_D0- +3VS 2 1 PCH_HDMI_HPD 46 VCC3V
@ 0_0402_5% @ 32 R168 2 1 4.7K_0402_5% +3VS
10K_0402_5% DDC_EN IHDMI@
2

UMA_DVI_TXD1- 1 2 R182 HDMI_R_D1-

@ 0_0402_5% R189 +3VS R167 1 2 @ 0_0402_5% 3 34 R162 2 1 0_0402_5% @
L10 100K_0402_5% R159 FUNCTION1 FUNCTION3
1 2 @ 0_0402_5% 4 FUCNTION2 FUNCTION4 35 R165 2 1 0_0402_5% @ +3VS
1 2 R163 1 2 @ 0_0402_5% R166 1 2 0_0402_5% IHDMI@
1 2 IHDMI@ R154 0_0402_5% R164 0_0402_5% @
1 2 1 2
1

2 R160 1 6 ANALOG1(REXT)
4 3 3.3K_0402_1% IHDMI@
4 3 PCH_HDMI_HPD
31,33 PCH_HDMI_HPD 7 HPD_SOURCE
B IHDMI@ OCE2012120YZF_0805 B
GND 31
UMA_DVI_TXD1+ 1 2 R183 HDMI_R_D1+ 8 27
31 UMA_HDMI_DATA SDA_SOURCE GND
@ 0_0402_5% 24
GND
31 UMA_HDMI_CLK 9 SCL_SOURCE GND 18
UMA_DVI_TXD2+ 1 2 R187 HDMI_R_D2+ +3VS 12
@ 0_0402_5% R689 @ GND
GND 5
L11 1 2 10 1
ANALOG2 GND
1

1 2 0_0402_5%
1 2 R1429 IHDMI@
10K_0402_5% UMA_DVI_TXC+ 13 48 HDMI_TXC+ C286 1 2 0.1U_0402_16V7K
OUT_D4+ IN_D4+ UMA_HDMI_TXC+ 31
4 3 IHDMI@ UMA_DVI_TXC- 14 47 HDMI_TXC- C312 1 2 0.1U_0402_16V7K
4 3 OUT_D4- IN_D4- UMA_HDMI_TXC- 31
IHDMI@ IHDMI@
2

IHDMI@ OCE2012120YZF_0805 OE# UMA_DVI_TXD2+ 16 45 HDMI_TX2+ C339 1 2 0.1U_0402_16V7K

OUT_D3+ IN_D3+ UMA_HDMI_TX2+ 31
UMA_DVI_TXD2- 1 2 R188 HDMI_R_D2- UMA_DVI_TXD2- 17 44 HDMI_TX2- C314 1 2 0.1U_0402_16V7K
OUT_D3- IN_D3- UMA_HDMI_TX2- 31
@ 0_0402_5% IHDMI@ IHDMI@
3

UMA_DVI_TXD1+ 19 42 HDMI_TX1+ C292 1 2 0.1U_0402_16V7K

OUT_D2+ IN_D2+ UMA_HDMI_TX1+ 31
Q161B UMA_DVI_TXD1- 20 41 HDMI_TX1- C317 1 2 0.1U_0402_16V7K
HDMI Connector 2N7002DW -T/R7_SOT363-6
5 HDMI_HPD UMA_DVI_TXD0+ 22
OUT_D2-

OUT_D1+
IN_D2-

IN_D1+ 39 HDMI_TX0+
IHDMI@
C319 1
IHDMI@
2 0.1U_0402_16V7K
UMA_HDMI_TX1- 31

UMA_HDMI_TX0+ 31
another at page 46 UMA_DVI_TXD0- 23 OUT_D1- IN_D1- 38 HDMI_TX0- C301 1 2 0.1U_0402_16V7K UMA_HDMI_TX0- 31
JHDMI IHDMI@
4

HDMI_HPD 19 +5VS_HDMI
HP_DET
+HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND 36 GND
HDMI_SDATA 16 37 49
HDMI_SCLK SDA PMEG2010AEH_SOD123 GND THERMAL_PAD IHDMI@
15 SCL 43 GND
14 +5VL 2 1 HDMI_TXC- 1 2
HDMI_CEC Reserved D54 CEC@ ASM1442 QFN_48P_7X7 R148 2.2K_0402_5%
13 CEC
A
HDMI_R_CK- 12 20 IHDMI@ A
CK- GND PMEG2010AEH_SOD123 IHDMI@ F2 IHDMI@
11 CK_shield GND 21 To solve display compatibility issue
HDMI_R_CK+ 10 22 +5VS 2 1 2 1 +HDMI_5V_OUT
HDMI_R_D0- CK+ GND D53 1.1A_6V_MINISMDC110F-2
9 D0- GND 23 1
8 C259
HDMI_R_D0+ D0_shield IHDMI@
7 D0+
HDMI_R_D1- 0.1U_0402_16V4Z
6
5
D1- 2 Security Classification Compal Secret Data Compal Electronics, Inc.
HDMI_R_D1+ D1_shield
4 D1+ Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title
HDMI_R_D2- 3
2
D2- HDMI Connector
HDMI_R_D2+ D2_shield THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
1 D2+ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
@ TYCO_1939864-1_19P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 27 of 61
5 4 3 2 1
 5 4 3 2 1

C287
CMOS Setting, near DDR Door 15P_0402_50V8J
JCMOS 2 1
+RTCVCC 1 2PCH_RTCRST# 1 2
R282 20K_0402_1% Y3

10M_0402_5%
1
1 2 3 NC OSC 4

R283
C288 1U_0402_6.3V4Z
+RTCBATT
iME Setting. J2
2 NC OSC 1 U11A
1 2PCH_SRTCRST# 1 2 32.768KHZ_12.5PF_Q13MC14610002

1
R284 20K_0402_1% PCH_RTCX1 B13 D33
RTCX1 FWH0 / LAD0 LPC_AD0 44,45
1 2 2 1 PCH_RTCX2 D13 B33
RTCX2 FWH1 / LAD1 LPC_AD1 44,45
C289 1U_0402_6.3V4Z C290 15P_0402_50V8J C32 D13
FWH2 / LAD2 LPC_AD2 44,45
D A32 +RTCVCC BAS40-04_SOT23-3 D
FWH3 / LAD3 LPC_AD3 44,45
PCH_RTCRST# C14 RTCRST#
C34 LPC_FRAME# 44,45

2
+RTCVCC PCH_SRTCRST# FWH4 / LFRAME#
D17 SRTCRST# 1 +CHGRTC
A34 1 2

RTC

LPC
LDRQ0# +3VS
Integrated SUS 1.05V VRM Enable 1 2 SM_INTRUDER# A16 F34 R286 10K_0402_5% C291
R285 1M_0402_5% INTRUDER# LDRQ1# / GPIO23 0.1U_0402_16V4Z
PCH_INTVRMEN SERIRQ 2
High - Enable Internal VRs 1 2 A14 INTVRMEN SERIRQ AB9 SERIRQ 44,45
PCH_INTVRMEN (must be always pulled high) R275 330K_0402_5%

AZ_BITCLK A30 HDA_BCLK

HDA_SYNC SATA0RXN AK7

AZ_SYNC D29 AK6
HDA_SYNC SATA0RXP
SATA0TXN AK11
This signal has a weak internal pull down. PCH_SPKR P1 AK9
31,42 PCH_SPKR SPKR SATA0TXP
H=>On Die PLL is supplied by 1.5V
AZ_RST#
*L=>On Die PLL is supplied by 1.8V C30 HDA_RST#
SATA1RXN AH6 SATA_PRX_C_DTX_N1 37

HDA_SDO SATA1RXP AH5 SATA_PRX_C_DTX_P1 37

42 AZ_SDIN0_HD G30 HDA_SDIN0 SATA1TXN AH9 SATA_PTX_DRX_N1 37 1ST HDD
SATA1TXP AH8 SATA_PTX_DRX_P1 37
This signal has a weak internal pull down. 38 AZ_SDIN1_MD F30 HDA_SDIN1
This signal can't PU SATA2RXN AF11
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6
Flash Descriptor Security Overide Desktop Only
SATA3RXN AH3
C
Low = Enabled AZ_SDOUT B29 AH1 C
HDA_SDO SATA3RXP
HDA_DOCK_EN# High = Disabled * SATA3TXN
SATA3TXP
AF3
AF1
44 PW RME_CTRL# H32

SATA
HDA_DOCK_EN# / GPIO33
2 SATA4RXN AD9 SATA_PRX_C_DTX_N4 37
41 CR_CPPE# J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8 SATA_PRX_C_DTX_P4 37
38 AZ_BITCLK_MD R287 1 MDC@ 2 33_0402_5% R118 AD6 SATA ODD
SATA4TXN SATA_PTX_DRX_N4 37
42 AZ_BITCLK_HD R288 1 2 33_0402_5% AZ_BITCLK 1K_0402_5% For JMB389C/385C AD5
SATA4TXP SATA_PTX_DRX_P4 37
@
38 AZ_SYNC_MD R289 1 MDC@ 2 33_0402_5% PCH_JTAG_TCK M3 AD3 SATA_PRX_C_DTX_N5 37
1

R290 1 JTAG_TCK SATA5RXN

42 AZ_SYNC_HD 2 33_0402_5% AZ_SYNC
SATA5RXP AD1 SATA_PRX_C_DTX_P5 37
PCH_JTAG_TMS K3 AB3 eSATA
JTAG_TMS SATA5TXN SATA_PTX_DRX_N5 37
38 AZ_RST_MD# R291 1 MDC@ 2 33_0402_5% AB1
SATA5TXP SATA_PTX_DRX_P5 37 +3VS
42 AZ_RST_HD# R292 1 2 33_0402_5% AZ_RST# PCH_JTAG_TDI K1 JTAG_TDI

JTAG
38 AZ_SDOUT_MD R293 1 MDC@ 2 33_0402_5% PCH_JTAG_TDO J2 AF16
R294 1 JTAG_TDO SATAICOMPO
42 AZ_SDOUT_HD 2 33_0402_5% AZ_SDOUT
PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2 SATA_LED# R301 2 1 10K_0402_5%
TRST# SATAICOMPI +1.05VS
R295 37.4_0402_1%
CR_W AKE# R303 1 2 10K_0402_5%

PCH_SPI_CLK BA2 VGA_PW ROK R306 1 2 10K_0402_5%

SPI_CLK @
for Optimus
PCH_SPI_CS0# AV3 SPI_CS0#
ITPM Enabled Internal: Pull down 20k AY3 T3 SATA_LED#
+3VS SPI_CS1# SATALED# SATA_LED# 46

High = Enabled
SPI_MOSI 2 @ 1PCH_SPI_MOSI AY1 Y9 CR_W AKE# For JMB389C/385C
B Low = Disabled (Default) SPI_MOSI SATA0GP / GPIO21 CR_W AKE# 41 B
R273 1K_0402_5%

SPI
PCH_SPI_MISO AV1 V1 VGA_PW ROK
SPI_MISO SATA1GP / GPIO19 VGA_PW ROK 32,47,58

IBEXPEAK-M QV20 A0_FCBGA1071

HM55R3@
+3VALW +3VALW +3VALW +3VALW
1

@ @ @ +3VS
R386 R363 @ R643
200_0402_5% 200_0402_5% R536 20K_0402_5% 4MB (SA000021A00)
200_0402_5%
1
2

PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_RST# U13

C293 8 VCC VSS 4 for EMI request
1

@ @ @ 0.1U_0402_16V4Z
R355 R535 @ R364 2 PCH_SPI_CLK
3 W
100_0402_5% 100_0402_5% R537 10K_0402_5%

1
100_0402_5% 7 HOLD R385
2

PCH_SPI_CS0# 1 10_0402_5% @
S
PCH_SPI_CLK 6

2
C
1
PCH_SPI_MOSI 5 2 PCH_SPI_MISO C86
D Q 33P_0402_50V8J @
1 2 PCH_JTAG_TCK MX25L3205DM2I-12G SO8
R156 51_0402_5% 2
A A
06/01 change R156 from 4.7K to 51 ohm Socket Footprint: WIESO_G6179-100000_8P
PCH JTAG Enable PCH JTAG Disable (Default)
PCH Pin RefDes ES1 ES2 ES1 ES2 Socket: SP07000F500 & SP07000H900
PCH_JTAG_TDO R358 No Install 200ohm No Install No Install
R535 No Install 100ohm No Install No Install
PCH_JTAG_TMS R355 200ohm 200ohm No Install No Install Security Classification Compal Secret Data Compal Electronics, Inc.
R354 100ohm 100ohm No Install No Install 2009/11/13 2010/01/23 Title
PCH_JTAG_TDI R536 200ohm 200ohm 20Kohm No Install Issued Date Deciphered Date
R537 100ohm 100ohm 10Kohm No Install
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-SPI/SATA/LPC/RTC/HDA
PCH_JTAG_TCK R156 51ohm 51ohm 51ohm 51ohm Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PCH_JTAG_RST# R643 20Kohm 20Kohm No Install No Install B 1.0
R353 10Kohm 10Kohm No Install No Install
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 28 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS
+3VALW 2 R229 1 2.2K_0402_5%
2 R230 1 2.2K_0402_5% R231 4.7K_0402_5%

5
Q3B R232 4.7K_0402_5%

PCH_SMBDATA 3 4 PM_SMBDATA 11,12,25,39

2
Q3A 2N7002DW -T/R7_SOT363-6

PCH_SMBCLK 6 1 PM_SMBCLK 11,12,25,39

2N7002DW -T/R7_SOT363-6

D U11B D

BG30 B9 EC_LID_OUT# EC_LID_OUT# 44

40 PCIE_PRX_C_LANTX_N1 PERN1 SMBALERT# / GPIO11
LAN 40 PCIE_PRX_C_LANTX_P1
C276 2
BJ30 PERP1
40 PCIE_PTX_C_LANRX_N1 1 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 BF29
PETN1 SMBCLK H14 PCH_SMBCLK
40 PCIE_PTX_C_LANRX_P1 C273 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_P1 BH29
PETP1 PCH_SMBDATA +3VS
SMBDATA C8
39 PCIE_PRX_W LANTX_N2 AW30 PERN2
WLAN 39 PCIE_PRX_W LANTX_P2
C274 2
BA30 PERP2
39 PCIE_PTX_C_W LANRX_N2 1 0.1U_0402_16V7K PCIE_PTX_W LANRX_N2 BC30
PETN2 SML0ALERT# / GPIO60 J14 PCH_GPIO60 +3VALW 2 R233 1 2.2K_0402_5%
39 PCIE_PTX_C_W LANRX_P2 C275 2 1 0.1U_0402_16V7K PCIE_PTX_W LANRX_P2 BD30 2 R234 1 2.2K_0402_5%
PETP2

5
C6 PCH_SMLCLK0 Q4B
SML0CLK
AU30

SMBus
39 PCIE_PRX_NEW TX_N3 PERN3
New Card AT30 G8 PCH_SMLDATA0 PCH_SMLDATA1 3 4
39 PCIE_PRX_NEW TX_P3 PERP3 SML0DATA EC_SMB_DA2 14,38,44,45
39 PCIE_PTX_C_NEW RX_N3 C269 2 1 0.1U_0402_16V7K PCIE_PTX_NEW RX_N3 AU32 PETN3

2
39 PCIE_PTX_C_NEW RX_P3 C270 2 1 0.1U_0402_16V7K PCIE_PTX_NEW RX_P3 AV32 Q4A 2N7002DW -T/R7_SOT363-6
PETP3 PCH_GPIO74
SML1ALERT# / GPIO74 M14
BA32 PCH_SMLCLK1 6 1
39 PCIE_PRX_JETTX_N4 PERN4 EC_SMB_CK2 14,38,44,45
JET BB32 E10 PCH_SMLCLK1
39 PCIE_PRX_JETTX_P4 PERP4 SML1CLK / GPIO58
39 PCIE_PTX_C_JETRX_N4 C282 2 1 0.1U_0402_16V7K PCIE_PTX_JETRX_N4 BD32 2N7002DW -T/R7_SOT363-6
C281 2 PETN4 +3VALW
39 PCIE_PTX_C_JETRX_P4 1 0.1U_0402_16V7K PCIE_PTX_JETRX_P4 BE32
PETP4 SML1DATA / GPIO75 G12 PCH_SMLDATA1

PCI-E*
BF33 PCH_SMLCLK0 2.2K_0402_5% 2 1 R237
41 PCIE_PRX_C_CRTX_N5 PERN5
Card Reader BH33 T13 PCH_SMLDATA0 2.2K_0402_5% 2 1 R238
41 PCIE_PRX_C_CRTX_P5 PERP5 CL_CLK1

Controller
41 PCIE_PTX_C_CRRX_N5 C280 2 1 0.1U_0402_16V7K PCIE_PTX_CRRX_N5 BG32 PCH_GPIO60 10K_0402_5% 2 1 R239
C279 2 PETN5
41 PCIE_PTX_C_CRRX_P5 1 0.1U_0402_16V7K PCIE_PTX_CRRX_P5 BJ32
PETP5 CL_DATA1 T11 PCH_GPIO74 10K_0402_5% 2 1 R240
EC_LID_OUT# 10K_0402_5% 2 1 R241

Link
BA34 PERN6 CL_RST1# T9
C AW34 1 2 C
PERP6 +3VALW
BC34 R260 10K_0402_5%
PETN6
BD34 PETP6
H1 CLKREQ_PEG# 1 2
PEG_A_CLKRQ# / GPIO47 R243@ 10K_0402_5%
AT34 PERN7
AU34 CLKREQ_PEG# CLKREQ_PEG# 13
PERP7
AU36 PETN7 CLKOUT_PEG_A_N AD43 CLK_PCIE_VGA# 13
AV36 PETP7 CLKOUT_PEG_A_P AD45 CLK_PCIE_VGA 13 VGA
NC BG34 AN4 CLK_PEG# 5
PERN8 CLKOUT_DMI_N

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_PEG 5
BG36 PETN8
BJ36 PETP8
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
40 CLK_LAN# AK48 CLKOUT_PCIE0N
LAN 40 CLK_LAN AK47 CLKOUT_PCIE0P

From CLK BUFFER

CLKIN_DMI_N AW24 PCH_CLK_DMI# 25
CLKREQ_LAN# P9 BA24 PCH_CLK_DMI 25
40 CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKIN_DMI_P

+3VS AM43 AP3

39 CLK_W LAN# CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BCLK# 25
CLKREQ_NEW #
WLAN 39 CLK_W LAN AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_BCLK 25 FROM CLK GEN FOR: 133/100/96/14.318 MHZ
1 2
10K_0402_5% R246 CLKREQ_W LAN# U4
39 CLKREQ_W LAN# PCIECLKRQ1# / GPIO18
CLKIN_DOT_96N F18 CLK_DOT# 25
1 2 CLKREQ_W LAN# E18 CLK_DOT 25
10K_0402_5% R248 CLKIN_DOT_96P
39 CLK_NEW # AM47 CLKOUT_PCIE2N
B
2 New Card 39 CLK_NEW AM48 CLKOUT_PCIE2P B
CLKIN_SATA_N / CKSSCD_N AH13 CLK_SATA# 25
C254 CLKREQ_NEW # N4 AH12 CLK_SATA 25 R247 1M_0402_5%
39 CLKREQ_NEW # PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P
2 1
680P_0402_50V7K 1 @ Y2
39 CLK_JET# AH42 P41 CLK_14M_PCH 25
CLKOUT_PCIE3N REFCLK14IN PCH_X1 PCH_X2
39 CLK_JET AH41 CLKOUT_PCIE3P 2 1
For EMI request JET CLKREQ_JET# A8 J42 1 25MHZ_20PF_7A25000012 1
39 CLKREQ_JET# PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCILOOP 32
C277 C278

AM51 AH51 PCH_X1 27P_0402_50V8J 27P_0402_50V8J

41 CLK_CR# CLKOUT_PCIE4N XTAL25_IN 2 2
AM53 AH53 PCH_X2
41 CLK_CR CLKOUT_PCIE4P XTAL25_OUT
Card Reader CLKREQ_CR# XCLK_RCOMP 1
M9 PCIECLKRQ4# / GPIO26 XCLK_RCOMP AF38 2 +1.05VS
R252 90.9_0402_1%

AJ50 CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64 T45

C277
Note: Stuff 0 ohm if
AJ52 CLKOUT_PCIE5P 0_0402_5% 25MHz crystal un-stuff
+3VALW PCH_GPIO44 H6 P43
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 @

1 2 CLKREQ_LAN#
10K_0402_5% R244 AK53 T42
CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
AK51 CLKOUT_PEG_B_P
1 2 PCH_GPIO44
10K_0402_5% R245 PCH_GPIO56 P13 N50
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
1 2 CLKREQ_CR#
A
10K_0402_5% R249 IBEXPEAK-M QV20 A0_FCBGA1071 @ A
HM55R3@ CLK_14M_PCH 1 @ 2 2 1
1 2 CLKREQ_JET# R70 100_0402_5%
10K_0402_5% R250 C206 100P_0402_50V8J

1 2 PCH_GPIO56
10K_0402_5% R251
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CLK/PCIE/SMBUS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 29 of 61
5 4 3 2 1
 5 4 3 2 1

D D

U11C
FDI_RXN0 BA18 FDI_CTX_PRX_N0 6
6 DMI_CTX_PRX_N0 BC24 DMI0RXN FDI_RXN1 BH17 FDI_CTX_PRX_N1 6
6 DMI_CTX_PRX_N1 BJ22 DMI1RXN FDI_RXN2 BD16 FDI_CTX_PRX_N2 6
6 DMI_CTX_PRX_N2 AW20 DMI2RXN FDI_RXN3 BJ16 FDI_CTX_PRX_N3 6
6 DMI_CTX_PRX_N3 BJ20 DMI3RXN FDI_RXN4 BA16 FDI_CTX_PRX_N4 6
FDI_RXN5 BE14 FDI_CTX_PRX_N5 6
6 DMI_CTX_PRX_P0 BD24 DMI0RXP FDI_RXN6 BA14 FDI_CTX_PRX_N6 6
6 DMI_CTX_PRX_P1 BG22 DMI1RXP FDI_RXN7 BC12 FDI_CTX_PRX_N7 6
6 DMI_CTX_PRX_P2 BA20 DMI2RXP
6 DMI_CTX_PRX_P3 BG20 DMI3RXP FDI_RXP0 BB18 FDI_CTX_PRX_P0 6
FDI_RXP1 BF17 FDI_CTX_PRX_P1 6
6 DMI_PTX_CRX_N0 BE22 DMI0TXN FDI_RXP2 BC16 FDI_CTX_PRX_P2 6
6 DMI_PTX_CRX_N1 BF21 DMI1TXN FDI_RXP3 BG16 FDI_CTX_PRX_P3 6
+3VALW BD20 AW16
6 DMI_PTX_CRX_N2 DMI2TXN FDI_RXP4 FDI_CTX_PRX_P4 6
6 DMI_PTX_CRX_N3 BE18 DMI3TXN FDI_RXP5 BD14 FDI_CTX_PRX_P5 6
FDI_RXP6 BB14 FDI_CTX_PRX_P6 6
1 2 PCH_SUSPW RDN 6 DMI_PTX_CRX_P0 BD22 DMI0TXP FDI_RXP7 BD12 FDI_CTX_PRX_P7 6
R316 10K_0402_5% BH21
6 DMI_PTX_CRX_P1 DMI1TXP
1 2 PCH_LOW _BAT# BC20
6 DMI_PTX_CRX_P2 DMI2TXP
R318 10K_0402_5% BD18 BJ14
6 DMI_PTX_CRX_P3 DMI3TXP FDI_INT FDI_INT 6
1 2 IBEX_RI#

DMI
FDI
R320 10K_0402_5% BF13
FDI_FSYNC0 FDI_FSYNC0 6
+1.05VS 1 2 DMI_COMP BH25
R311 49.9_0402_1% DMI_ZCOMP
FDI_FSYNC1 BH13 FDI_FSYNC1 6
2 1 PM_PW ROK BF25
R329 10K_0402_5% DMI_IRCOMP
C 2 1 PW ROK Close to PCH FDI_LSYNC0 BJ12 FDI_LSYNC0 6 C
R322 10K_0402_5% BG14
FDI_LSYNC1 FDI_LSYNC1 6
2 1 LAN_RST#
R323 10K_0402_5%

2 @ 1
0_0402_5% R256

+3VS XDP_DBRESET# T6 J12 EC_SW I# EC_SW I# 1 2

5 XDP_DBRESET# SYS_RESET# WAKE# EC_SW I# 39,40 +3VALW
0.1U_0402_16V4Z R313 10K_0402_5%
1 2
C230 VGATE M6 Y1 PM_CLKRUN# 2 1 +3VS
44,56 VGATE SYS_PWROK CLKRUN# / GPIO32
5

U12 R319 8.2K_0402_5%

2
P

44 PM_PW ROK B

System Power Management

4 PW ROK B17
VGATE Y PWROK
1 A
G

1 1 2 K5 P8 SUS_STAT# PADT38
PADT38
3

R321 0_0402_5% MEPWROK SUS_STAT# / GPIO61

C434 SN74AHC1G08DCKR_SC70-5
1000P_0402_50V7K LAN_RST# A10 F3 SUS_CLK PADT39
PADT39
2 LAN_RST# SUSCLK / GPIO62

to avoid noise D9 E4
5 DRAMPW ROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 44

PCH_RSMRST# C16 H7
RSMRST# SLP_S4# PM_SLP_S4# 44
B B
PCH_SUSPW RDN M1 P12
44 PCH_SUSPW RDN SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# 44

44 PBTN_OUT# P5 PWRBTN# SLP_M# K8

+3VALW 1 2 PCH_ACIN P7 N2
R324 330K_0402_5% ACPRESENT / GPIO31 TP23

D26 PCH_LOW _BAT# A6 BJ10

BATLOW# / GPIO72 PMSYNCH PMSYNCH 5
44,46,48 ACIN 1 2

CH751H-40PT_SOD323-2 IBEX_RI# F14 F6

RI# SLP_LAN# / GPIO29

IBEXPEAK-M QV20 A0_FCBGA1071

+3VALW HM55R3@

1 2
R691 1K_0402_5% 0_0402_5% @1 2 R325

3 Q26 1 PCH_RSMRST#
C

44 EC_RSMRST#
2 1
E

MMBT3906_SOT23-3 R326
10K_0402_5%
B
2

+3VALW 2 1
A
R327 A
1

4.7K_0402_5%
D15A D15B
BAV99DW -7_SOT363 BAV99DW -7_SOT363

Security Classification Compal Secret Data Compal Electronics, Inc.

6

1 2
RSMRST# circuit R328
2.2K_0402_5%
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-DMI/FDI/PWM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 30 of 61
5 4 3 2 1
 5 4 3 2 1

U11D
44 UMA_ENBKL T48 L_BKLTEN SDVO_TVCLKINN BJ46
1 2 UMA_ENBKL T47 BG46
25 UMA_ENVDD L_VDD_EN SDVO_TVCLKINP
R136 100K_0402_5%
25 PCH_PW M Y48 L_BKLTCTL SDVO_STALLN BJ48
SDVO_STALLP BG48
25 LCD_EDID_CLK AB48 L_DDC_CLK
25 LCD_EDID_DATA Y45 L_DDC_DATA SDVO_INTN BF45
SDVO_INTP BH45
1 2 LCTL_CLK AB46
+3VS L_CTRL_CLK
+3VS 1 R85 2 10K_0402_5% LCTL_DATA V48 L_CTRL_DATA
R84 10K_0402_5%
1 2 LVDS_IBG AP39 T51
LCD_EDID_CLK R127 2.37K_0402_1% LVD_IBG SDVO_CTRLCLK
D 2 1 AP41 LVD_VBG SDVO_CTRLDATA T53 To prevent PCH pending internal HPD D
R126 2.2K_0402_5% T15 PAD
AT43
interrupt function
LCD_EDID_DATA LVD_VREFH
2 1 AT42 LVD_VREFL DDPB_AUXN BG44
R125 2.2K_0402_5% BJ44 R133 100K_0402_5%
DDPB_AUXP
DDPB_HPD AU38 1 2

LVDS
25 LCD_TXCLK- AV53 LVDSA_CLK#
AV51 BD42 +3VS
25 LCD_TXCLK+ LVDSA_CLK DDPB_0N
DDPB_0P BC42
25 LCD_TXOUT0- BB47 LVDSA_DATA#0 DDPB_1N BJ42
BA52 BG42

Digital Display Interface

25 LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P

1
25 LCD_TXOUT2- AY48 LVDSA_DATA#2 DDPB_2N BB40
AV47 BA40 R128 R132
LVDSA_DATA#3 DDPB_2P 2.2K_0402_5% 2.2K_0402_5%
DDPB_3N AW38
BB48 BA38 IHDMI@ IHDMI@
25 LCD_TXOUT0+ LVDSA_DATA0 DDPB_3P
25 LCD_TXOUT1+ BA50

2
LVDSA_DATA1
25 LCD_TXOUT2+ AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49 UMA_HDMI_CLK 27
DDPC_CTRLDATA AB49 UMA_HDMI_DATA 27
AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
AY53 LVDSB_DATA#0 DDPC_HPD AV40 PCH_HDMI_HPD 27,33
AT49 LVDSB_DATA#1
+3VS AU52 BE40
LVDSB_DATA#2 DDPC_0N UMA_HDMI_TX2- 27
AT53 LVDSB_DATA#3 DDPC_0P BD40 UMA_HDMI_TX2+ 27
DDPC_1N BF41 UMA_HDMI_TX1- 27
UMA_CRT_CLK
C
2
R83
1
2.2K_0402_5%
AY51
AT48
LVDSB_DATA0
LVDSB_DATA1
DDPC_1P
DDPC_2N
BH41
BD38
UMA_HDMI_TX1+
UMA_HDMI_TX0-
27
27
HDMI C
AU50 LVDSB_DATA2 DDPC_2P BC38 UMA_HDMI_TX0+ 27
2 1 UMA_CRT_DATA AT51 BB36
LVDSB_DATA3 DDPC_3N UMA_HDMI_TXC- 27
R68 2.2K_0402_5% BA36
DDPC_3P UMA_HDMI_TXC+ 27

26 UMA_CRT_B AA52 CRT_BLUE DDPD_CTRLCLK U50

1 2 UMA_CRT_B AB53 U52
26 UMA_CRT_G CRT_GREEN DDPD_CTRLDATA
R94 150_0402_1% AD53
26 UMA_CRT_R CRT_RED
1 2 UMA_CRT_G
R95 150_0402_1% BC46
UMA_CRT_R DDPD_AUXN R135 100K_0402_5%
1 2 26 UMA_CRT_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
R124 150_0402_1% 26 UMA_CRT_DATA V53 AT38 1 2
CRT_DDC_DATA DDPD_HPD

DDPD_0N BJ40 To prevent PCH pending internal HPD

Y53 BG40
26 UMA_CRT_HSYNC
Y51
CRT_HSYNC DDPD_0P
BJ38
interrupt function
26 UMA_CRT_VSYNC CRT_VSYNC DDPD_1N
DDPD_1P BG38

CRT
DDPD_2N BF37
2 R266 1CRT_IREF AD48 DAC_IREF DDPD_2P BH37
AB51 CRT_IRTN DDPD_3N BE36
1K_0402_1% BD36
DDPD_3P

PCH Strap Pin IBEXPEAK-M QV20 A0_FCBGA1071

HM55R3@

Internal: Pull down 20k

+3VS
+1.8VS_PCH_NAND During Reset: Low Danbury Technology Enabled
Internal: Pull down 20k NO REBOOT Strap
B Initial: Low High = Enabled
B
During Reset: HZ
PCH_SPKR Low= Disable NV_ALE Low = Disabled (Default)
Initial: Low 2 @ 1 NV_ALE
@ PCH_SPKR
High= Enable R267 1K_0402_5%
NV_ALE 32
1 2 PCH_SPKR 28,42
R269 1K_0402_5%
Internal: Pull up 20k 2 @ 1 NV_CLE NV_CLE 32
Boot BIOS Strap R268 1K_0402_5% DMI Termination Voltage
During Reset: High
Initial: High PCI_GNT#1 PCI_GNT#0 Boot BIOS Loaction Internal: Pull down 20k Low= Set to Vss (Default)
During Reset: Low NV_CLE High= Set to Vcc
1K_0402_5% 2 @ 1 R270 PCI_GNT#0
PCI_GNT#0 32 0 0 LPC (Default) Initial: Low
1K_0402_5% 2 @ 1 R271 PCI_GNT#1
PCI_GNT#1 32 0 1 Reserved (NAND)
Internal: Pull up 20k 1 0 PCI
During Reset: High
Initial: High 1 1 SPI
2 @ 1 PCI_GNT#3
PCI_GNT#3 32
R272 1K_0402_5% A16 Swap Override Strap
Internal: Pull up 20k
During Reset: High Low= A16 swap override Enable
Initial: High
PCI_GNT#3 High= A16 swap override Disable

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-VGA/LVDS/TV
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 31 of 61
5 4 3 2 1
 5 4 3 2 1

2 @ 1
0_0402_5% R253

+3VS

5
U8
U11E PLT_RST# 1

P
IN1
H40 AD0 NV_CE#0 AY9 O 4 BUF_PLT_RST# 5
N34 AD1 NV_CE#1 BD1 2 IN2

G
2

1
D C44 AD2 NV_CE#2 AP15 D

1
A38 BD8 R53

3
AD3 NV_CE#3 R334 SN74AHC1G08DCKR_SC70-5 R129
C36 AD4
J34 AV9 100K_0402_5% 0_0402_5% 100K_0402_5%
AD5 NV_DQS0 @ @
A40 BG8

2
AD6 NV_DQS1
D45

2
AD7 +3VS
E36 AD8 NV_DQ0 / NV_IO0 AP7
H48 AD9 NV_DQ1 / NV_IO1 AP6
E40 AD10 NV_DQ2 / NV_IO2 AT6 1 2
C40 AT9 C477 0.1U_0402_16V4Z
AD11 NV_DQ3 / NV_IO3

5
M48 BB1 R336 0_0402_5% U23
AD12 NV_DQ4 / NV_IO4
M45 AV6 2 1 1

P
AD13 NV_DQ5 / NV_IO5 28,47,58 VGA_PW ROK IN1
F53 AD14 NV_DQ6 / NV_IO6 BB3 O 4 2 1 PLTRST_VGA# 13
M40 BA4 DGPU_RST# 2 R399 0_0402_5%
AD15 NV_DQ7 / NV_IO7 IN2

G
2
NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4

1
J36 BB6 SN74AHC1G08DCKR_SC70-5

3
AD17 NV_DQ9 / NV_IO9 R55
K48 AD18 NV_DQ10 / NV_IO10 BD6
F40 BB7 R405
+3VS AD19 NV_DQ11 / NV_IO11 1K_0402_5% 100K_0402_5%
C42 BC8

1
RP1 AD20 NV_DQ12 / NV_IO12
K46 BJ8

2
PCI_REQ#1 AD21 NV_DQ13 / NV_IO13
1 8 M51 AD22 NV_DQ14 / NV_IO14 BJ6
2 7 J52 AD23 NV_DQ15 / NV_IO15 BG6
3 6 PCI_PIRQD# K51 @
PCI_IRDY# AD24 NV_ALE PLT_RST# PLTRST_VGA#
4 5 L34 AD25 NV_ALE BD3 NV_ALE 31 2 1
F42 AY6 NV_CLE NV_CLE 31 R402 0_0402_5%
8.2K_0804_8P4R_5% AD26 NV_CLE
J40 AD27
RP2
G46
F44
AD28
AD29 NV_RCOMP AU2 1 @ 2 For Optimus
1 8 PCI_PIRQH# M47 R276 32.4_0402_1%
AD30

PCI
C 2 7 PCI_TRDY# H36 AV7 C
PCI_FRAME# AD31 NV_RB#
3 6
4 5 PCI_PIRQA# J50 AY8
C/BE0# NV_WR#0_RE#
G42 C/BE1# NV_WR#1_RE# AY5
8.2K_0804_8P4R_5% H47 C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
RP3 BF5
PCI_STOP# PCI_PIRQA# NV_WE#_CK1
1 8 G38 PIRQA#
2 7 PCI_PIRQE# PCI_PIRQB# H51
PCI_PIRQC# PCI_PIRQC# PIRQB#
3 6 B37 PIRQC# USBP0N H18 USB20_N0 37
4 5 PCI_PIRQG# PCI_PIRQD# A44 J18 USB-LEFT1
PIRQD# USBP0P USB20_P0 37
USBP1N A18 USB20_N1 37
8.2K_0804_8P4R_5% PCI_REQ#0 F51 C18 USB-LEFT2
REQ0# USBP1P USB20_P1 37
PCI_REQ#1 A46 N20
REQ1# / GPIO50 USBP2N
47 ODD_EN# B45 REQ2# / GPIO52 USBP2P P20
PCI_REQ#3 M53 J20
REQ3# / GPIO54 USBP3N USB20_N3 37
USBP3P L20 USB20_P3 37 eSATA-USB
31 PCI_GNT#0 F48 GNT0# USBP4N F20 USB20_N4 39
31 PCI_GNT#1
DGPU_RST#
K45 GNT1# / GPIO51 USBP4P G20 USB20_P4 39 NewCard
GNT2#/GPIO53: Not pull low, internal pull up 20K F36 GNT2# / GPIO53 USBP5N A20 USB20_N5 38
31 PCI_GNT#3 H53 GNT3# / GPIO55 USBP5P C20 USB20_P5 38 BT
USBP6N M22
PCI_PIRQE# B41 N22
PCI_PIRQF# PIRQE# / GPIO2 USBP6P
K53 PIRQF# / GPIO3 USBP7N B21
PCI_PIRQG# A36 D21
PCI_PIRQH# PIRQG# / GPIO4 USBP7P
A48 PIRQH# / GPIO5 USBP8N H22 USB20_N8 38
+3VS
USBP8P J22 USB20_P8 38 Finger Printer

USB
RP4 TP_PCI_RST# K6 E22
T37 PAD PCIRST# USBP9N
1 8 PCI_REQ#3 F22
B PCI_PIRQF# PCI_SERR# USBP9P B
2 7 E44 SERR# USBP10N A22 USB20_N10 39
3 6 PCI_PIRQB# PCI_PERR# E50 C22 3G
PERR# USBP10P USB20_P10 39
4 5 PCI_REQ#0 G24
USBP11N USB20_N11 25
8.2K_0804_8P4R_5% PCI_IRDY# USBP11P H24 USB20_P11 25 Int. Camera
A42 IRDY# USBP12N L24 USB20_N12 25 +3VALW
PCI_DEVSEL#
H44 PAR USBP12P M24 USB20_P12 25 Touch Screen
F46 DEVSEL# USBP13N A24 USB20_N13 39
PCI_FRAME# C46 C24 WiMax/WLAN
FRAME# USBP13P USB20_P13 39
+3VS RP8
PCI_PLOCK# D49
RP5 PLOCK# USB_OC#2
USBRBIAS# B25 4 5
1 8 PCI_DEVSEL# PCI_STOP# D41 USB_OC#3 3 6
PCI_PERR# PCI_TRDY# STOP# USBBIAS EXP_CPPE#
2 7
PCI_SERR#
C48 TRDY# USBRBIAS D25 2
R278
1
22.6_0402_1%
Within 500 mils USB_OC#1
2 7
3 6 1 8
4 5 PCI_PLOCK# M7 PME# USB_OC#0 10K_0804_8P4R_5%
OC0# / GPIO59 N16 USB_OC#0 37,44
8.2K_0804_8P4R_5% D5 J16 USB_OC#1
39,40,41,44,45 PLT_RST# PLTRST# OC1# / GPIO40 USB_OC#1 37,44 RP6
F16 USB_OC#2
OC2# / GPIO41 USB_OC#3 USB_OC#0
N52 CLKOUT_PCI0 OC3# / GPIO42 L16 4 5
P53 E14 USB_OC#4 SLP_CHG_M3 3 6
CLKOUT_PCI1 OC4# / GPIO43
2 1 CLK_SIO P46 CLKOUT_PCI2 OC5# / GPIO9 G16 SLP_CHG_M3
SLP_CHG_M3 37
SLP_CHG_M4 2 7
45 CLK_PCI_DDR 22_0402_5% R280
2 1 CLK_EC P51 CLKOUT_PCI3 OC6# / GPIO10 F12 SLP_CHG_M4
SLP_CHG_M4 37
USB_OC#4 1 8
44 CLK_PCI_EC 22_0402_5% R281
29 CLK_PCILOOP 2 1 CLK_PCH P48 CLKOUT_PCI4 OC7# / GPIO14 T15 EXP_CPPE#
EXP_CPPE# 39
22_0402_5% R279 10K_0804_8P4R_5%

IBEXPEAK-M QV20 A0_FCBGA1071

HM55R3@
Change to 47 ohm?
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH USB/PCI/NAND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 32 of 61
5 4 3 2 1
 5 4 3 2 1

U11F

27,31 PCH_HDMI_HPD Y3 BMBUSY# / GPIO0 CLKOUT_PCIE6N AH45

CLKOUT_PCIE6P AH46
D GPIO8 PCH_GPIO1 C38 D
TACH1 / GPIO1
Not pull down PCH_GPIO6 D37 TACH2 / GPIO6
Internal: Pull up 20k CLKOUT_PCIE7N AF48

MISC
EC_SCI# J32 AF47
During Reset: High 44 EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
Initial: High 44 EC_SMI# EC_SMI# F10 GPIO8
GPIO15 PCH_GPIO12 K9 U2
LAN_PHY_PWR_CTRL / GPIO12 A20GATE GATEA20 44
a Strong pull up may be needed
PCH_GPIO15 T7
for GPIO Functionality GPIO15
for Optimus
Internal: Pull down 20k 13,47,58 DGPU_PW R_EN DGPU_PW R_EN AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# 5
During Reset: Low RF_OFF#
39 RF_OFF# F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK 5
Initial: Low
BT_DET# Y7 BG10
38 BT_DET# SCLOCK / GPIO22 PECI PECI 5

GPIO
H10 T1 KB_RST#
GPIO24 RCIN# KB_RST# 44
On-Die PLL VR @ PCH_GPIO27
2 1 AB12 GPIO27 PROCPWRGD BE10 H_PW RGOOD 5

CPU
High = Enabled (Default) R274 1K_0402_5%
PCH_GPIO27 PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 1 2
Low = Disabled GPIO28 THRMTRIP# H_THERMTRIP# 5
R212 56_0402_1%
38,39 BT_PW R# M11 STP_PCI# / GPIO34

38 BT_RST# V6 SATACLKREQ# / GPIO35

1 2 +VTT
PROJECT_ID0 AB7 BA22 R210 56_0402_1%
C SATA2GP / GPIO36 TP1 C
+3VS PROJECT_ID1 AB13 AW22
SATA3GP / GPIO37 TP2
PCH_GPIO38 V3 BB22
SLOAD / GPIO38 TP3
1 2 PCH_GPIO1 CIR_EN# P3 SDATAOUT0 / GPIO39 TP4 AY45
10K_0402_5% R214
1 2 BT_DET# LVDS_SEL H3 AY46
8.2K_0402_5% R215 PCIECLKRQ6# / GPIO45 TP5
RST_GATE F1 AV43
5 RST_GATE PCIECLKRQ7# / GPIO46 TP6
1 2 PCH_GPIO6 PCH_GPIO48 AB6 SDATAOUT1 / GPIO48 TP7 AV45
10K_0402_5% R218
1 2 RF_OFF# 44 THM_ALT#
THM_ALT# AA4 SATA5GP / GPIO49 TP8 AF13 2 1 +3VS
10K_0402_5% R220 R228 10K_0402_5%
OPTIMUS_EN# F8 M18 PROJECT_ID0 2 1
GPIO57 TP9 R217 10K_0402_5%
TP10 N18 @
1 2 PCH_GPIO38 A4 VSS_NCTF_1 TP11 AJ24 PROJECT_ID[1..0]
10K_0402_5% R255 A49

NCTF
VSS_NCTF_2 00: NDU00 (Streamline-M/-S 11.6/13.3")

RSVD
1 2 THM_ALT# A5 AK41
VSS_NCTF_3 TP12
10K_0402_5% R259 A50 VSS_NCTF_4 01: NBQAA (Bordeuax 14" )
1 2 PCH_GPIO48 A52 AK42
10K_0402_5% R257 A53
VSS_NCTF_5 TP13 10: NWQAA (Marseille 16")
VSS_NCTF_6
1 2 CIR_EN# B2 VSS_NCTF_7 TP14 M32 11: NALAA (Hamburg 17.3")
10K_0402_5% R216 B4
EC_SCI# VSS_NCTF_8
1 2 B52 VSS_NCTF_9 TP15 N32
10K_0402_5% R224 B53 2 @ 1 +3VS
B VSS_NCTF_10 R254 10K_0402_5% B
BE1 VSS_NCTF_11 TP16 M30
BE53 PROJECT_ID1 2 1
VSS_NCTF_12 R235 10K_0402_5%
BF1 VSS_NCTF_13 TP17 N30
BF53 VSS_NCTF_14
+3VALW BH1 H12
VSS_NCTF_15 TP18
BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
1 2 EC_SMI# BH53
R225 10K_0402_5% VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
1 2 PCH_GPIO15 BJ49 VSS_NCTF_22
R227 1K_0402_5% BJ5 AB42
VSS_NCTF_23 NC_3
1 2 PCH_GPIO28 BJ50 VSS_NCTF_24
R242 10K_0402_5% LVDS_SEL: BJ52 AB41
VSS_NCTF_25 NC_4
1 2 LVDS_SEL Pull high for Single Channel BJ53 VSS_NCTF_26
R222 10K_0402_5% D1 T39
VSS_NCTF_27 NC_5
1 2 RST_GATE D2 VSS_NCTF_28 Not pull low
R223 10K_0402_5% D53 VSS_NCTF_29 internal pull up
1 2 PCH_GPIO12 E1 VSS_NCTF_30 INIT3_3V# P6
R219 10K_0402_5% E53 VSS_NCTF_31
TP24 C10 Internal: Pull up 20k
IBEXPEAK-M QV20 A0_FCBGA1071
During Reset: High
HM55R3@ Initial: High
DGPU_PW R_EN 1 2
R221 1K_0402_5%
OPTIMUS_EN# 2 1
A
10K_0402_5% R226 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH CPU/GPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 33 of 61
5 4 3 2 1
 5 4 3 2 1

+1.05VS +3VS
U11G POWER +3VS_VCCADAC
AB24 VCCCORE[1] VCCADAC[1] AE50 1 R339 2 1 L12 2
1 1 AB26 69mA 1 2 1 2.2_0603_1% 0_0603_5%
C295 C294 VCCCORE[2]
AB28 VCCCORE[3] VCCADAC[2] AE52
10U_0805_10V4Z 1U_0402_6.3V4Z AD26 VCCCORE[4]
C296 C297 C298 0311 To solve CRT issue

CRT
D AD28 AF53 0.01U_0402_25V7K 0.1U_0402_16V4Z 10U_0805_10V4Z D
2 2 VCCCORE[5] VSSA_DAC[1] 2 1 2
AF26 VCCCORE[6]

VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51
AF30 VCCCORE[8] close to AE50
AF31 VCCCORE[9]
AH26 VCCCORE[10]
AH28 VCCCORE[11]
AH30 VCCCORE[12]
AH31 VCCCORE[13] > 1mA VCCALVDS AH38 +3VS
AJ30 VCCCORE[14]
AJ31 VCCCORE[15] VSSA_LVDS AH39

+1.05VS 1432mA
VCCTX_LVDS[1] AP43 +1.8VS
59mA VCCTX_LVDS[2] AP45 1 1
AT46

LVDS
VCCTX_LVDS[3] C300 C299
AK24 VCCIO[24] VCCTX_LVDS[4] AT45
0.01U_0402_25V7K 0.01U_0402_25V7K
+3VS 2 2
BJ24 VCCAPLLEXP 40mA
VCC3_3[2] AB34

AN20 VCCIO[25] 375mA VCC3_3[3] AB35

AN22 2

HVCMOS
VCCIO[26] 0.1U_0402_16V4Z
AN23 VCCIO[27] VCC3_3[4] AD35
AN24 C303
VCCIO[28]
AN26 VCCIO[29] 1
AN28 VCCIO[30] close to AB34
BJ26 VCCIO[31]
C BJ28 C
VCCIO[32]
AT26 VCCIO[33]
AT28 VCCIO[34]
+1.05VS AU26 +PCH_VRM
VCCIO[35]
AU28 VCCIO[36]
1 2 AV26 VCCIO[37]
C304 10U_0805_10V4Z AV28 196mA AT24 1 2 +1.8VS
VCCIO[38] VCCVRM[2] R333 0_0402_5%
1 2 AW26 VCCIO[39]
C305 1U_0402_6.3V4Z AW28 3062mA
VCCIO[40] +VTT

DMI
1 2 BA26 VCCIO[41] VCCDMI[1] AT16
C306 1U_0402_6.3V4Z BA28 61mA
VCCIO[42] +PCH_VCCDMI
1 2 BB26 VCCIO[43] VCCDMI[2] AU16 1 2
C307 1U_0402_6.3V4Z BB28 1 R335 0_0603_5%
VCCIO[44] C309
1 2 BC26 VCCIO[45]

PCI E*
C308 1U_0402_6.3V4Z BC28 1U_0402_6.3V4Z
VCCIO[46]
BD26 VCCIO[47] 2
BD28 VCCIO[48] close to AT16
BE26 VCCIO[49] VCCPNAND[1] AM16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 AK19 +1.8VS_PCH_NAND +1.8VS
VCCIO[52] VCCPNAND[4]
BH27 VCCIO[53] VCCPNAND[5] AK15
156mA VCCPNAND[6] AK13 1
R338
2
0_0603_5%
AN30 VCCIO[54] VCCPNAND[7] AM12 2

NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
+3VS AM15 C311
VCCPNAND[9] 0.1U_0402_16V4Z
1
2 1 AN35 VCC3_3[1] 375mA close to Ak13
C310 0.1U_0402_16V4Z
B B

+PCH_VRM AT22 VCCVRM[1] +3VS

BJ18 VCCFDIPLL 37mA VCCME3_3[1] AM8
VCCME3_3[2] AM9
FDI

+1.05VS AM23 VCCIO[1] 85mA VCCME3_3[3] AP11 2

VCCME3_3[4] AP9
C313 0.1U_0402_16V4Z
1
close to AM8
IBEXPEAK-M QV20 A0_FCBGA1071
HM55R3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH POWER-1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 34 of 61
5 4 3 2 1
 5 4 3 2 1

U11J POWER +1.05VS

AP51 VCCACLK[1] VCCIO[5] V24

52mA VCCIO[6] V26 1
C316
AP53 VCCACLK[2] 3062mA VCCIO[7] Y24
VCCIO[8] Y26
1U_0402_6.3V4Z
AF23 V28 2
VCCLAN[1] VCCSUS3_3[1]
VCCSUS3_3[2] U28
VccLAN may be grounded if Intel LAN is disabled AF24 VCCLAN[2] 320mA VCCSUS3_3[3] U26
VCCSUS3_3[4] U24
D VCCSUS3_3[5] P28 D
2 1 +TP_PCH_VCCDSW Y20 P26 +3VALW
C320 0.1U_0402_16V4Z DCPSUSBYP VCCSUS3_3[6]
VCCSUS3_3[7] N28

+1.05VS
Near AD38 AD38
VCCSUS3_3[8] N26
M28
VCCME[1] VCCSUS3_3[9]
1 1 1 VCCSUS3_3[10] M26 2 2
AD39 L28 C321 C325

USB
C391 C322 C318 VCCME[2] VCCSUS3_3[11]
VCCSUS3_3[12] L26
If two VccME rails can be 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z AD41 J28 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 VCCME[3] VCCSUS3_3[13] 1 1
J26
combined, only total 2 x 22 µF and AF43
VCCSUS3_3[14]
H28
VCCME[4] VCCSUS3_3[15]
2 x 1 µF caps are necessary @ 163mA VCCSUS3_3[16] H26
AF41 VCCME[5] VCCSUS3_3[17] G28
1849mA VCCSUS3_3[18] G26
AF42 VCCME[6] VCCSUS3_3[19] F28
Near V39 V39
VCCSUS3_3[20] F26
E28 +3VALW +5VALW
VCCME[7] VCCSUS3_3[21]
1 1 1 E26

Clock and Miscellaneous

VCCSUS3_3[22]
V41 C28

CH751H-40PT_SOD323-2
C447 C323 C324 VCCME[8] VCCSUS3_3[23]
VCCSUS3_3[24] C26

1
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z V42 B27
2 2 2 VCCME[9] VCCSUS3_3[25] D16 R344
VCCSUS3_3[26] A28
Y39 VCCME[10] VCCSUS3_3[27] A26
@ 100_0402_1%
Y41 U23

2
VCCME[11] VCCSUS3_3[28] +3VS +5VS
Y42 VCCME[12] VCCIO[56] V23 +1.05VS

1
F24 +PCH_VCC5REFSUS 1 2
V5REF_SUS C326 1U_0402_6.3V4Z D17 R346
+VCCRTCEXT
> 1mA
C 1 2 V9 DCPRTC CH751H-40PT_SOD323-2 C
C327 0.1U_0402_16V4Z 100_0402_1%

2
+1.05VS L17 1 2 196mA > 1mA K49 +PCH_VCC5REF +PCH_VCC5REF
10UH_LB2012T100MR_20% V5REF
1 +PCH_VRM AU24

PCI/GPIO/LPC
VCCVRM[3]
1 1
1

C328 + C329 +3VS C330

220U_B2_2.5VM_R15 1U_0402_6.3V4Z R347 +1.05VS_PCHDPLL_A
68mA VCC3_3[8] J38
BB51 VCCADPLLA[1]
0_0603_5% BB53 L38 1U_0402_6.3V4Z
2 2 @ VCCADPLLA[2] VCC3_3[9] 2
2
69mA M36 C333
2

L18 1 +1.05VS_PCHDPLL_B VCC3_3[10] 0.1U_0402_16V4Z

2
10UH_LB2012T100MR_20%
BD51 VCCADPLLB[1] 375mA
1 BD53 VCCADPLLB[2] VCC3_3[11] N36
1
1
C331 + C332 1U_0402_6.3V4Z AH23 P36
+1.05VS VCCIO[21] VCC3_3[12]
220U_B2_2.5VM_R15 1U_0402_6.3V4Z 1 1 1 AJ35 VCCIO[22]
AH35 VCCIO[23] VCC3_3[13] U35
2 2 C334 C335 C336 +3VS
1U_0402_6.3V4Z AF34 3062mA
2 2 2 VCCIO[2]
VCC3_3[14] AD13 2 1
1U_0402_6.3V4Z AH34 C337 0.1U_0402_16V4Z
VCCIO[3]
AF32 VCCIO[4]
VCCSATAPLL[1] AK3
1 2 +VCCSST V12 31mA AK1
C338 0.1U_0402_16V4Z DCPSST VCCSATAPLL[2]

+1.05VS
1 2 +V1.1A_INT_VCCSUS Y22 DCPSUS
C341 0.1U_0402_16V4Z AH22
B VCCIO[9] B

+3VALW 163mA
P18 VCCSUS3_3[29] 196mA VCCVRM[4] AT20 +PCH_VRM

1 2 U19

SATA
C343 0.1U_0402_16V4Z VCCSUS3_3[30]

PCI/GPIO/LPC
VCCIO[10] AH19 +1.05VS
U20 VCCSUS3_3[31] 1
AD20 C342
VCCIO[11] 1U_0402_6.3V4Z
For HDA power rail U22 VCCSUS3_3[32]
AF22
+3VS VCCIO[12] 2
375mA VCCIO[13] AD19

U54
1
C344
2
0.1U_0402_16V4Z
V15 VCC3_3[5] 3062mA VCCIO[14] AF20
VCCIO[15] AF19
APL5508-25DC-TRL_SOT89-3 V16 AH20
VCC3_3[6] VCCIO[16]
+3VALW +VTT
2 IN OUT 3 +1.5VALW Y16 VCC3_3[7] VCCIO[17] AB19
VCCIO[18] AB20
1 2 VCCIO[19] AB22
GND C345 4.7U_0603_6.3V6K +1.05VS
> 1mA VCCIO[20] AD22
1

@ 1 2 AT18
C130 1 C131 C346 0.1U_0402_16V4Z V_CPU_IO[1]
AA34 +PCH_VCCME1 R351 1 2 0_0402_5%
CPU

1U_0603_10V6K 4.7U_0805_6.3V6K VCCME[13]

1 2 Y34 +PCH_VCCME2 R352 1 2 0_0402_5%
2

VCCME[14]
@ @ C347 0.1U_0402_16V4Z AU18 V_CPU_IO[2] 1849mA VCCME[15] Y35 +PCH_VCCME3 R353 1 2 0_0402_5%
VCCME[16] AA35 +PCH_VCCME4 R354 1 2 0_0402_5%
+RTCVCC
RTC

1 2 A12 2mA 6mA L30 R356 1 2 0_0402_5% +3VALW

VCCRTC VCCSUSHDA
HDA

C351 0.1U_0402_16V4Z VCCSUSHDA can be

A 1 A
IBEXPEAK-M QV20 A0_FCBGA1071
either 1.5V or 3.3V
1 2 C350 R357 1 2 0_0402_5% +1.5VALW
C348 1U_0402_6.3V4Z HM55R3@ @
1U_0402_6.3V4Z
2
1 2 For HDA power rail to +3.3V(default) /+1.5V
C349 0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH POWER-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 35 of 61
5 4 3 2 1
 5 4 3 2 1

U11I
AY7 VSS[159] VSS[259] H49
B11 H5 U11H
VSS[160] VSS[260]
B15 VSS[161] VSS[261] J24 AB16 VSS[0]
B19 VSS[162] VSS[262] K11
B23 VSS[163] VSS[263] K43 AA19 VSS[1] VSS[80] AK30
B31 VSS[164] VSS[264] K47 AA20 VSS[2] VSS[81] AK31
B35 VSS[165] VSS[265] K7 AA22 VSS[3] VSS[82] AK32
B39 VSS[166] VSS[266] L14 AM19 VSS[4] VSS[83] AK34
B43 VSS[167] VSS[267] L18 AA24 VSS[5] VSS[84] AK35
B47 VSS[168] VSS[268] L2 AA26 VSS[6] VSS[85] AK38
D B7 VSS[169] VSS[269] L22 AA28 VSS[7] VSS[86] AK43 D
BG12 VSS[170] VSS[270] L32 AA30 VSS[8] VSS[87] AK46
BB12 VSS[171] VSS[271] L36 AA31 VSS[9] VSS[88] AK49
BB16 VSS[172] VSS[272] L40 AA32 VSS[10] VSS[89] AK5
BB20 VSS[173] VSS[273] L52 AB11 VSS[11] VSS[90] AK8
BB24 VSS[174] VSS[274] M12 AB15 VSS[12] VSS[91] AL2
BB30 VSS[175] VSS[275] M16 AB23 VSS[13] VSS[92] AL52
BB34 VSS[176] VSS[276] M20 AB30 VSS[14] VSS[93] AM11
BB38 VSS[177] VSS[277] N38 AB31 VSS[15] VSS[94] BB44
BB42 VSS[178] VSS[278] M34 AB32 VSS[16] VSS[95] AD24
BB49 VSS[179] VSS[279] M38 AB39 VSS[17] VSS[96] AM20
BB5 VSS[180] VSS[280] M42 AB43 VSS[18] VSS[97] AM22
BC10 VSS[181] VSS[281] M46 AB47 VSS[19] VSS[98] AM24
BC14 VSS[182] VSS[282] M49 AB5 VSS[20] VSS[99] AM26
BC18 VSS[183] VSS[283] M5 AB8 VSS[21] VSS[100] AM28
BC2 VSS[184] VSS[284] M8 AC2 VSS[22] VSS[101] BA42
BC22 VSS[185] VSS[285] N24 AC52 VSS[23] VSS[102] AM30
BC32 VSS[186] VSS[286] P11 AD11 VSS[24] VSS[103] AM31
BC36 VSS[187] VSS[287] AD15 AD12 VSS[25] VSS[104] AM32
BC40 VSS[188] VSS[288] P22 AD16 VSS[26] VSS[105] AM34
BC44 VSS[189] VSS[289] P30 AD23 VSS[27] VSS[106] AM35
BC52 VSS[190] VSS[290] P32 AD30 VSS[28] VSS[107] AM38
BH9 VSS[191] VSS[291] P34 AD31 VSS[29] VSS[108] AM39
BD48 VSS[192] VSS[292] P42 AD32 VSS[30] VSS[109] AM42
BD49 VSS[193] VSS[293] P45 AD34 VSS[31] VSS[110] AU20
BD5 VSS[194] VSS[294] P47 AU22 VSS[32] VSS[111] AM46
BE12 VSS[195] VSS[295] R2 AD42 VSS[33] VSS[112] AV22
BE16 VSS[196] VSS[296] R52 AD46 VSS[34] VSS[113] AM49
BE20 VSS[197] VSS[297] T12 AD49 VSS[35] VSS[114] AM7
C BE24 T41 AD7 AA50 C
VSS[198] VSS[298] VSS[36] VSS[115]
BE30 VSS[199] VSS[299] T46 AE2 VSS[37] VSS[116] BB10
BE34 VSS[200] VSS[300] T49 AE4 VSS[38] VSS[117] AN32
BE38 VSS[201] VSS[301] T5 AF12 VSS[39] VSS[118] AN50
BE42 VSS[202] VSS[302] T8 Y13 VSS[40] VSS[119] AN52
BE46 VSS[203] VSS[303] U30 AH49 VSS[41] VSS[120] AP12
BE48 VSS[204] VSS[304] U31 AU4 VSS[42] VSS[121] AP42
BE50 VSS[205] VSS[305] U32 AF35 VSS[43] VSS[122] AP46
BE6 VSS[206] VSS[306] U34 AP13 VSS[44] VSS[123] AP49
BE8 VSS[207] VSS[307] P38 AN34 VSS[45] VSS[124] AP5
BF3 VSS[208] VSS[308] V11 AF45 VSS[46] VSS[125] AP8
BF49 VSS[209] VSS[309] P16 AF46 VSS[47] VSS[126] AR2
BF51 VSS[210] VSS[310] V19 AF49 VSS[48] VSS[127] AR52
BG18 VSS[211] VSS[311] V20 AF5 VSS[49] VSS[128] AT11
BG24 VSS[212] VSS[312] V22 AF8 VSS[50] VSS[129] BA12
BG4 VSS[213] VSS[313] V30 AG2 VSS[51] VSS[130] AH48
BG50 VSS[214] VSS[314] V31 AG52 VSS[52] VSS[131] AT32
BH11 VSS[215] VSS[315] V32 AH11 VSS[53] VSS[132] AT36
BH15 VSS[216] VSS[316] V34 AH15 VSS[54] VSS[133] AT41
BH19 VSS[217] VSS[317] V35 AH16 VSS[55] VSS[134] AT47
BH23 VSS[218] VSS[318] V38 AH24 VSS[56] VSS[135] AT7
BH31 VSS[219] VSS[319] V43 AH32 VSS[57] VSS[136] AV12
BH35 VSS[220] VSS[320] V45 AV18 VSS[58] VSS[137] AV16
BH39 VSS[221] VSS[321] V46 AH43 VSS[59] VSS[138] AV20
BH43 VSS[222] VSS[322] V47 AH47 VSS[60] VSS[139] AV24
BH47 VSS[223] VSS[323] V49 AH7 VSS[61] VSS[140] AV30
BH7 VSS[224] VSS[324] V5 AJ19 VSS[62] VSS[141] AV34
C12 VSS[225] VSS[325] V7 AJ2 VSS[63] VSS[142] AV38
C50 VSS[226] VSS[326] V8 AJ20 VSS[64] VSS[143] AV42
B B
D51 VSS[227] VSS[327] W2 AJ22 VSS[65] VSS[144] AV46
E12 VSS[228] VSS[328] W52 AJ23 VSS[66] VSS[145] AV49
E16 VSS[229] VSS[329] Y11 AJ26 VSS[67] VSS[146] AV5
E20 VSS[230] VSS[330] Y12 AJ28 VSS[68] VSS[147] AV8
E24 VSS[231] VSS[331] Y15 AJ32 VSS[69] VSS[148] AW14
E30 VSS[232] VSS[332] Y19 AJ34 VSS[70] VSS[149] AW18
E34 VSS[233] VSS[333] Y23 AT5 VSS[71] VSS[150] AW2
E38 VSS[234] VSS[334] Y28 AJ4 VSS[72] VSS[151] BF9
E42 VSS[235] VSS[335] Y30 AK12 VSS[73] VSS[152] AW32
E46 VSS[236] VSS[336] Y31 AM41 VSS[74] VSS[153] AW36
E48 VSS[237] VSS[337] Y32 AN19 VSS[75] VSS[154] AW40
E6 VSS[238] VSS[338] Y38 AK26 VSS[76] VSS[155] AW52
E8 VSS[239] VSS[339] Y43 AK22 VSS[77] VSS[156] AY11
F49 VSS[240] VSS[340] Y46 AK23 VSS[78] VSS[157] AY43
F5 VSS[241] VSS[341] P49 AK28 VSS[79] VSS[158] AY47
G10 VSS[242] VSS[342] Y5
G14 Y6 IBEXPEAK-M QV20 A0_FCBGA1071
VSS[243] VSS[343] HM55R3@
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
A H30 VSS[255] VSS[355] AK45 A
H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

Security Classification Compal Secret Data Compal Electronics, Inc.

IBEXPEAK-M QV20 A0_FCBGA1071 2009/11/13 2010/01/23 Title
Issued Date Deciphered Date
HM55R3@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 36 of 61
5 4 3 2 1
 5 4 3 2 1

SATA HDD Conn. SATA ODD Conn

+5VS
Place closely JHDD SATA CONN.
1.2A
JODD0
1
C356
1
C357
1
C358
1
C359 1
Slot ODD conn
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z GND SATA_PTX_C_DRX_P4 C378 1
A+ 2 2 ODD0@ 0.01U_0402_25V7K SATA_PTX_DRX_P4 28
3 SATA_PTX_C_DRX_N4 C377 1 2 ODD0@ 0.01U_0402_25V7K
2 2 2 2 A- SATA_PTX_DRX_N4 28
4 JODD1
GND SATA_PRX_DTX_N4 C376 1
B- 5 2 ODD0@ 0.01U_0402_25V7K SATA_PRX_C_DTX_N4 28 +5VS_ODD 1 1
6 SATA_PRX_DTX_P4 C375 1 2 ODD0@ 0.01U_0402_25V7K 2
B+ SATA_PRX_C_DTX_P4 28 2
D
GND 7 3 3 D
SSD HDD need 400mA for 3V(PHISON) 4 4
+3VS 0.01U_0402_25V7K ODD1@ 2 1 C374 SATA_PRX_DTX_P4_ODD 5
0.01U_0402_25V7K ODD1@ 2 5
+3VS rail reserve for SSD DP 8 1 C373 SATA_PRX_DTX_N4_ODD 6 6
+5V 9 +5VS_ODD 7 7
1 1 1 10 0.01U_0402_25V7K ODD1@ 2 1 C372 SATA_PTX_C_DRX_N4_ODD 8
C363 C364 +5V 8
1 C365 C366
MD 11 0.01U_0402_25V7K ODD1@ 2 1 C371 SATA_PTX_C_DRX_P4_ODD 9 9
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 15 12 10
@ @ @ @ GND GND +5VS_ODD 10
14 GND GND 13 11 GND
2 2 2 1.1A
2 Place components closely ODD CONN. 12 GND
Check SSD spec SANTA_206401-1_RV 1 1 1 1 1 ACES_85201-1005N
@ C352 C353 C354 @
@ C355 C360
10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2
JHDD
GND 1
2 SATA_PTX_C_DRX_P1 C3691 2 0.01U_0402_25V7K
RX+ SATA_PTX_DRX_P1 28
3 SATA_PTX_C_DRX_N1 C3671 2 0.01U_0402_25V7K
RX- SATA_PTX_DRX_N1 28 +USB_VCCA +USB_VCCA
4 W=60mils
GND
TX-
TX+
5
6
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
C3681
C3701
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_C_DTX_N1 28
SATA_PRX_C_DTX_P1 28
USB conn C263 220U_6.3V_M_R15
C260

+
7 2 1 SF000001500 2 1
GND H=5.7
0.1U_0402_16V4Z C261
8 +5VALW C266 2 1
3.3V +3VS
3.3V 9 2 1
10 For EMI request 0.1U_0402_16V4Z
C 3.3V C389 1 1000P_0402_50V7K C262 C
GND 11 2 W=60mils
12 2 1
GND
GND 13 0.1U_0402_16V4Z
U14
2A +USB_VCCA
For EMI request
JUSB0 @
1000P_0402_50V7K JUSB1 @
5V 14 +5VS 1 VCC GND 5
15 1 8 2 1 USB20_N0_R 2 6 1 5
5V GND VOUT C361 1000P_0402_50V7K USB20_P0_R D- GND USB20_N1_R VCC GND
5V 16 2 VIN VOUT 7 3 D+ GND 7 2 D- GND 6
17 3 6 4 8 USB20_P1_R 3 7
GND VIN VOUT GND GND D+ GND

2
Rsv 18 44 USB_EN# 4 EN FLG 5 USB_OC#0 32,44 4 GND GND 8

2
19 1 D8 P-TW O_CU304G-A0G1G-P D7
GND RT9715BGS_SO8 P-TW O_CU304G-A0G1G-P
24 GND 12V 20
21 C362 PJDLC05_SOT23-3
12V 4.7U_0805_10V4Z
23 GND 12V 22
2

@
SANTA_194002-1 PJDLC05_SOT23-3

1
@ @

1
+USB_VCCB

2A W=60mils
eSATA/USB combo +5VALW
U15
+USB_VCCB
W=60mils 1000P_0402_50V7K
1 GND VOUT 8
2 VIN VOUT 7 1 1 1
SLP_CHG_M3 SLP_CHG_M4 3 VIN VOUT 6 SF000002Y00 +
Reserve for EMI request
44 USB_CHG_EN# 4 5 C379
B EN FLG USB_OC#1 32,44 H=4.5 C380 C381 @ R73 0_0402_5% B
2 2
Mode 3 HIGH LOW RT9715BGS_SO8 1 220U_6.3V_M_R17
2
1 2
C383 L53
+3VALW 4.7U_0805_10V4Z 0.1U_0402_16V4Z 32 USB20_P0 1 1 2 USB20_P0_R
2
Mode 4 LOW HIGH U52
2
@ D18 @ PJDLC05_SOT23-3
C403 0.1U_0402_16V4Z 2
USB20_P3_S 1 1D+ VCC 10 1 2 1
3
eSATA/USB Conn 32 USB20_N0 4 4 3 3 USB20_N0_R

USB20_N3_S SLP_CHG# JESATA W CM-2012-900T_0805

SLP_CHG FUNCTION 2 1D- S 9 SLP_CHG# 44
1 USB 1 2
USB20_P3 USB20_P3_R USB20_N3_RL VBUS @ R87 0_0402_5%
32 USB20_P3 3 2D+ D+ 8 2 D-
USB20_P3_RL
LOW D=1D USB20_N3 4 7 USB20_N3_R
3
4
D+ @ R77 0_0402_5%
32 USB20_N3 2D- D- GND
1 2
USB_CHG_EN# L54
HIGH D=2D 5 GND OE# 6
C385 1 2 0.01U_0402_25V7K SATA_PTX_C_DRX_P5
5
6
GND
32 USB20_N1 1 1 2 USB20_N1_R
28 SATA_PTX_DRX_P5 A+ ESATA 2
C386 1 2 0.01U_0402_25V7K SATA_PTX_C_DRX_N5 7
28 SATA_PTX_DRX_N5 A-
8 GND SHIELD 12
TS3USB221RSER_QFN10_2x1P5~D C387 1 2 0.01U_0402_25V7K SATA_PRX_DTX_N5 9 13 32 USB20_P1 4 3 USB20_P1_R
28 SATA_PRX_C_DTX_N5 B- SHIELD 4 3
Place close to PCH within 30mm 28 SATA_PRX_C_DTX_P5
C388 1 2 0.01U_0402_25V7K SATA_PRX_DTX_P5 10 B+ SHIELD 14
11 15 W CM-2012-900T_0805
GND SHIELD
1 2
+USB_VCCB 2 R191 @1 0_0402_5% FOX_3Q318111 @ R88 0_0402_5%
@
U53 W CM2012F2SF-900T04_0805
1 USB20_P3_R 3 4 USB20_P3_RL
32 SLP_CHG_M3 1OE# 3 4
1

4 2OE#
10 R949 R952
32 SLP_CHG_M4 3OE#
A 13 75K_0402_1% 43K_0402_1% USB20_N3_R 2 1 USB20_N3_RL A
4OE# 2 1
USB20_P3_S 2 3 USB20_P3_S_O L16
2

USB20_N3_S 1A 1B USB20_N3_S_O
5 2A 2B 6
9 3A 3B 8 R131 1 2 USB20_P3_S_O 2 R192 @1 0_0402_5%
12 4A 4B 11 100_0402_1% USB20_N3_S_O
Security Classification Compal Secret Data Compal Electronics, Inc.
1

+USB_VCCB 14 VCC GND 7

2 R951 R950 2009/11/13 2010/01/23 Title
Issued Date Deciphered Date
SN74CBT3125PW RG4_TSSOP14 51K_0402_1% 51K_0402_1%
C382
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA-HDD/ODD/USB/E-SATA
0.1U_0402_16V4Z Size Document Number Rev
2

1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 37 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS

BlueTooth Interface Cap Sensor / Light Sensor Conn

2
2
R361 C396
100K_0402_5% 0.1U_0402_16V7K
BT@

3
1 S

1
G
33,39 BT_PW R# 1 2 2
R362 47K_0402_5% 1 JCS
BT@ C390 D Q28 BT@ +5VALW 1

1
0.01U_0402_25V7K AO3413_SOT23 1
+3VL 2 2
D BT@ +3VS 3 D
2 FBMA-11-100505-301T_0402 L13 1 ESB_DAZ 3
+BT_VCC 44 ESB_DAT 2 4 4
Cap Sensor 44 ESB_CK
FBMA-11-100505-301T_0402 L14 1 2 ESB_CKZ 5 5
44 CAP_INT# 6 6
CAP_RST# 7
(MAX=200mA) 44 CAP_RST# 7
+BT_VCC Bluetooth Connector 14,29,44,45 EC_SMB_CK2 8 8
1 Light Sensor 14,29,44,45 EC_SMB_DA2 9 9
JBT 10
BT@ C398 C399 BT@ 10
1 1 11 GND
4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 12
2 2 GND
32 USB20_P5 3 3
4 P-TW O_161021-10021
32 USB20_N5 4
33 BT_RST# 1 2 BT_RESET# 5 J3 @
R366 BT@ 5 CAP_RST#
0_0402_5%
33 BT_DET# 6 6 Reserve J3 for debug 2 1

C397 7
0.1U_0402_16V4Z BT@ GND
8 GND ESB_DAZ 1 2 1 2 ESB_CKZ 1 2 1 2
ACES_87213-0600G_6P
@ @ R428 @ C271 @ R427 @ C272
100_0402_5% 100P_0402_50V8J 100_0402_5% 100P_0402_50V8J

C C

TP LED Conn JTPL

TP/B LED/B FP/B Conn
+5VS 1 1
2 2
43,44 KSI6 3 3
43,44 KSO0 4 4
TP_LED# 5 7
5 G7 +3VS_FP JTOUCH
6 6 G8 8
+5VS 1 1
P-TW O_161021-06021_6P-T +3VS 1 R134 2 2
@ 0_0603_5% 1 2
3 3
6

C480 4
44 TP_CLK 4
44 TP_DATA 5 5
0.1U_0402_16V4Z LOGO_LED# 6
2 D19 6
2 7 7
44 TP_LED 2 USB20_N8 8
32 USB20_N8 8
Q163A 1 USB20_P8 9
32 USB20_P8
1

2N7002DW -T/R7_SOT363-6 9
3 10 10
Fringer Printer 11 GND
PACDN042Y3R_SOT23-3 12 GND
P-TW O_161021-10021
@

3
2N7002DW -T/R7_SOT363-6
Q163B
B MDC 1.5 Conn 5 LOGO_LED 44
B

D82

4
+3VS_FP 4 2 USB20_N8
+MDC_VCC VIN IO1
R61 USB20_P8 3 1
IO2 GND
+3VALW 1 2
MDC@ 0_0603_5% 1 1 1 1 CM1293A-02SR SOT143-4

1 R56 2 C394 C395 C400 C430 For EMI request

+1.5VALW
@ 0_0603_5% 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 MDC@ 2 MDC@ 2 MDC@ 2 MDC@

For HDA power rail to +3.3V(default) /+1.5V

JMDC @

1 GND1 RES0 2 +MDC_VCC

28 AZ_SDOUT_MD 3 IAC_SDATA_OUT RES1 4
5 GND2 3.3V 6 +3VALW
28 AZ_SYNC_MD 7 IAC_SYNC GND3 8
AZ_SDIN1_MD_R 9 10
IAC_SDATA_IN GND4
28 AZ_RST_MD# 11 IAC_RESET# IAC_BITCLK 12 AZ_BITCLK_MD 28
2

R368
GND
GND
GND
GND
GND
GND

10_0402_5%
@
28 AZ_SDIN1_MD 2 MDC@ 1 AZ_SDIN1_MD_R ACES_88018-124G
13
14
15
16
17
18

A A
R369 33_0402_5% 1
C401
Connector for MDC Rev1.5 10P_0402_50V8J
@
2

For EMI
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/BT/FP/MDC/TP/CAP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 38 of 61
5 4 3 2 1
 PCIe Mini Card-WLAN/WiMax PCIe Mini Card-3G/JET 500mA+1.5VS +3VS
2.75A
PJ27 +3V_W LAN +3VS
For SED J3G For SED
+3VALW 2 1 +3V_W LAN 1 2
120 MIL
2 1 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z
3 3 4 4
DEFAULT @ 1 1 1 5 6 1 1 1
JUMP_43X79 5 6

1
29 CLKREQ_JET# 7 7 8 8 +UIM_PWCM4
R CM5 CM6 CM12
CM1 CM2 CM3 CM10 UIM_DATA 47P_0402_50V8J
Short PJ27 for Wimax 47P_0402_50V8J 29 CLK_JET#
9
11
9 10 10
12 UIM_CLK 3GJET@ 3GJET@ 3GJET@ 3GJET@
PJ26

2
2 2 2 11 12 UIM_RESET 2 2 2
+3VS 2 1
Short PJ26 for WLAN 0.01U_0402_25V4Z 4.7U_0805_10V4Z
29 CLK_JET 13
15
13 14 14
16 UIM_VPP 0.01U_0402_25V7K 4.7U_0805_10V4Z
2 1 15 16
17 17 18 18
@ 19 20
JUMP_43X79 19 20 RF_OFF# 33
21 22 PLT_RST#
+1.5VS 21 22
+3V_W LAN
For SED 29 PCIE_PRX_JETTX_N4 23 23 24 24
29 PCIE_PRX_JETTX_P4 25 25 26 26
0.1U_0402_16V4Z 27 28
+1.5VS 27 28 PM_SMBCLK
1 1 1 29 29 30 30

1
31 32 PM_SMBDATA
29 PCIE_PTX_C_JETRX_N4 31 32
JW LAN CM7 CM8 CM9 CM11 33 34
29 PCIE_PTX_C_JETRX_P4 33 34
1 2 47P_0402_50V8J 35 36 USB20_N10 32

2
1 2 2 2 2 35 36
BT_CTRL
3 3 4 4
0.01U_0402_25V4Z 4.7U_0805_10V4Z
PCIE--JET 37 37 38 38 USB20_P10 32 3G
5 5 6 6 +3VS 39 39 40 40
7 8 41 42 LED_W IMAX#
29 CLKREQ_W LAN# 7 8 41 42
9 9 10 10 43 43 44 44
29 CLK_W LAN# 11 11 12 12 45 45 46 46
29 CLK_W LAN 13 13 14 14 BT on Combo module 47 47 48 48
15 15 16 16 49 49 50 50
17 18 51 52 +UIM_PW R
17 18 51 52
19 19 20 20 W L_OFF# 44 Enable Disable
21 22 PLT_RST# 53 54
21 22 PLT_RST# 32,40,41,44,45 GND1 GND2
29 PCIE_PRX_W LANTX_N2 23 23 24 24

1
29 PCIE_PRX_W LANTX_P2 25 25 26 26 BT_CRTL HIGH LOW RM2
27 28 FOX_AS0B226-S40N-7F 4.7K_0402_5%
27 28 @ @
29 29 30 30 PM_SMBCLK 11,12,25,29
29 PCIE_PTX_C_W LANRX_N2 31 31 32 32 PM_SMBDATA 11,12,25,29 BT_PWR# LOW HIGH J3GSIM
29 PCIE_PTX_C_W LANRX_P2 33 34

2
33 34 +UIM_PW R
35 35 36 36 USB20_N13 32 +UIM_PW R 1 VCC GND 4
WLAN/ WiFi 37 38 USB20_P13 32 WiMax/BT UIM_RESET 2 5 UIM_VPP
37 38 RST VPP

1
+3V_W LAN 39 40 1 UIM_CLK 3 6 UIM_DATA
39 40 LED_W IMAX# DM1 CLK I/O
41 41 42 42 LED_W IMAX# 46
43 44 CM13 RLZ20A_LL34 7 8 1
43 44 0.1U_0402_16V4Z NC NC
45 45 46 46 1 2 +3VS 3G@ 1 1
2
47 48 RM6 100K_0402_5% **If +3V_WLAN is +3VS, please 3G@ MOLEX_47273-0001~D CM14

2
47 48 W IMAX@ CM15 CM16 22P_0402_50V8J
44 E51_TXD 1 2 49 49 50 50 remove D22 @
2 @
44 E51_RXD 1R16 0_0402_5%
2 51 51 52 52 10P_0402_50V8J 10P_0402_50V8J
R17 0_0402_5% DM2 3G@ 2 2 3G@
53 54 SUSP# 1 2 BT_CTRL
GND1 GND2
Debug card using
CH751H-40PT_SOD323-2
2

3
FOX_AS0B226-S40N-7F
R342 @
Q14B
100K_0402_5% 5 2N7002DW -T/R7_SOT363-6
33,38 BT_PW R#
1

4
+3VALW _CARD +3VS_CARD +1.5VS_CARD JEXP
Imax = 0.275A Imax = 1.35A Imax = 0.75A
1 GND
1 1 1 1 1 1 USB20_N4_R 2
CN1 CN2 CN3 CN4 CN5 CN6 USB20_P4_R USB_D-
3 USB_D+
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z CP_USB# 4 CPUSB#
5 RSV
2 2 2 2 2 2
6 RSV
PM_SMBCLK 7
PM_SMBDATA SMB_CLK
8 SMB_DATA
+3VALW UN1 60mils 9
+1.5VS_CARD +1.5V
+1.5VS 12 1.5Vin 1.5Vout 11 +1.5VS_CARD 10 +1.5V
1 2 CP_USB# 14 1.5Vin 1.5Vout 13 30,40 EC_SW I# 11 WAKE#
RN4 100K_0402_5% +3VALW _CARD 12 +3.3VAUX
40mils PERST# 13 PERST#
+3VS 2 3.3Vin 3.3Vout 3 +3VS_CARD +3VS_CARD 14 +3.3V
4 3.3Vin 3.3Vout 5 15 +3.3V
40mils CLKREQ# 16 CLKREQ#
+3VALW 17 15 +3VALW _CARD EXP_CPPE# 17
AUX_IN AUX_OUT 32 EXP_CPPE# CPPE#
29 CLK_NEW # 18 REFCLK-
PLT_RST# 6 19 19
SYSRST# OC# 29 CLK_NEW REFCLK+
20 GND GND 31
20 8 PERST# 21 32
44,54 SYSON SHDN# PERST# 29 PCIE_PRX_NEW TX_N3 PERn0 GND
29 PCIE_PRX_NEW TX_P3 22 PERp0
+3VS +3VS
44,47,50,53,58 SUSP# 1 STBY# NC 16 Reserve for EMI request 23 GND GND 29
29 PCIE_PTX_C_NEW RX_N3 24 PETn0 GND 30
+3VS EXP_CPPE# 10 7 RN25 0_0402_5% 29 PCIE_PTX_C_NEW RX_P3 25
CPPE# GND PETp0
1

RN6 1 1 2 26
10K_0402_5% CN7 CP_USB# @ GND
9 CPUSB# Thermal_Pad 21
1

@ 0.1U_0402_16V4Z 27
RN7 UN2 @ RCLKEN W CM-2012-900T_0805 GND
18 RCLKEN 28 GND
5

10K_0402_5% @ 2 USB20_P4_R
32 USB20_P4 4 3
2

@ CLKREQ# TPS2231MRGPR-2 QFN 4 3 SANTA_130861-2_26P_RT-T

2
G Vcc

B CLKREQ_NEW # @
4 CLKREQ_NEW # 29
2

Y USB20_N4_R
1 A 32 USB20_N4 1 1 2 2
3

NC7SZ32P5X_NL_SC70-5 LN1
3

Q6B
2N7002DW -T/R7_SOT363-6 RN24 0_0402_5%
RCLKEN 5 another at page46 1 2
@
4

CLKREQ# 1 2 CLKREQ_NEW #
RN8 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-WLAN/3G/JET/NEW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 39 of 61
 5 4 3 2 1

+3V_LAN

2 EC_SW I# +3V_LAN
1
+LAN_VDD10
Close to Pin 27,39,12,47,48
RL3 @ 100K_0402_5% UL1
LL1
29 PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 31 +LAN_REGOUT 1 2 21
HSOP LED3/EEDO LAN_SK_LINK# 2.2UH +-5% NLC252018T-2R2J-N 0.1U_0402_16V4Z CL10
LED1/EESK 37
29 PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 40 LAN_ACTIVITY# 21
HSON LED0 0.1U_0402_16V4Z CL4
1 2
17 30 RL2 2 1 10K_0402_5% Layout Note: LL1 must be 1 2
29 PCIE_PTX_C_LANRX_P1 HSIP EECS/SCL
18 32 RL1 2 1 10K_0402_5% within 200mil to Pin36, CL13 CL9 0.1U_0402_16V4Z CL5
29 PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 1 2
200mil to LL1 2 1 0.1U_0402_16V4Z CL6
D D
RL19 0_0402_5% 16 1 LAN_MDI0+ +LAN_REGOUT: Width =60mil 1 2
+3VS 29 CLKREQ_LAN# CLKREQB MDIP0
2 LAN_MDI0- 0.1U_0402_16V4Z CL7
MDIN0 LAN_MDI1+ CL7 close to pin12
32,39,41,44,45 PLT_RST# 25 PERSTB MDIP1 4
5 LAN_MDI1-
MDIN1
1

19 7 LAN_MDI2+
29 CLK_LAN REFCLK_P NC/MDIP2
RL6 20 8 LAN_MDI2-
29 CLK_LAN# REFCLK_N NC/MDIN2
1K_0402_1% 10 LAN_MDI3+
NC/MDIP3 LAN_MDI3-
NC/MDIN3 11
LAN_X1 +LAN_VDD10 +LAN_EVDD10
43 Close to Pin 3,6,9,13,29,41,45
2

ISOLATEB CKXTAL1
LAN_X2 44 13 2 1 +LAN_VDD10
CKXTAL2 DVDD10 +LAN_VDD10
29 0_0603_5% LL2 1 2
DVDD10
41 1 2
RL7 EC_SW I# DVDD10 CL18 CL17 0.1U_0402_16V4Z CL19
30,39 EC_SW I# 28
15K_0402_5% LANWAKEB 1U_0402_6.3V4Z 0.1U_0402_16V4Z 1 2
ISOLATEB 26 27 2 1 0.1U_0402_16V4Z CL20
ISOLATEB DVDD33 +3V_LAN
39 1 2
DVDD33 0.1U_0402_16V4Z CL21
Close to Pin 21
14 12 +3V_LAN 1 2
8111E@ 2 RL21 NC/SMBCLK AVDD33
1 10K_0402_5% 15 NC/SMBDATA AVDD33 42 +3V_AVDDXTAL 0.1U_0402_16V4Z CL22
+3V_LAN 1 RL22 2 1K_0402_5% 38 47 1 2
GPO/SMBALERT AVDD33 0.1U_0402_16V4Z CL23
AVDD33 48
RTL8105E RTL8111E 1 2
ENSW REG 33 0.1U_0402_16V4Z CL24
ENSWREG
Pin14 NC NC EVDD10
21 +LAN_EVDD10 1 2
34 +3V_LAN +LAN_VDDREG 0.1U_0402_16V4Z CL25 8111E@
+LAN_VDDREG VDDREG
Pin15 NC 10K ohm PD 35
VDDREG AVDD10
3 +LAN_VDD10
6 2 1 CL23,CL24,CL25 close to pin6,9,41, respectively
AVDD10
C Pin38 1K ohm Pull-high AVDD10
9 0_0603_5% LL3 1 2 C
1 2 46 45
RL5 2.49K_0402_1% RSET AVDD10 CL28 CL29
24 36 +LAN_REGOUT 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
GND REGOUT 2 1
49 PGND +3V_AVDDXTAL RL8 +3V_LAN
0_0402_5%
RTL8111E-VB-GR_QFN48_6X6
8111E@ RL9 +LAN_VDD10
YL1
@ 0_0402_5%
+3VALW TO +3V_LAN LAN_X1 2 1LAN_X2 Reserved For 1.05V Crystal
1
+3VALW 25MHZ_20PF_7A25000012 +3V_LAN
+3VALW CL11
1 1
CL11 close to pin42 0.1U_0402_16V4Z
2

Vgs=-4.5V,Id=3A,Rds<97mohm CL26 CL27 2

RL24 27P_0402_50V8J 27P_0402_50V8J RL4
100K_0402_5% 2 2
2 0_0402_5%
CL12
1

0.1U_0402_16V7K QL1 For EMI's request

1

S
PJ28 ENSW REG
LAN Conn.
1

1 2 1 2
G
CL30 68P_0402_50V8J
44 W OL_EN# JUMP_43X39
RL16 47K_0402_5% @ UL4 2 1
2

1
D RL23
1

CL14 AO3413_SOT23 LAN_MDI0+ 1 16 RJ45_MIDI0+ 0_0402_5% JLAN

2

0.01U_0402_25V7K +3V_LAN LAN_MDI0- TD+ TX+ RJ45_MIDI0- LAN_ACTIVITY# RL10 1 LAN_ACTIVITY#_R

2 15 @ 2 12
TD- TX- 150_0402_5% Yellow LED-
3 CT CT 14
2
4 NC NC 13 +3V_LAN 2 1 11 Yellow LED+
5 12 RL17 150_0402_5%
B NC NC RJ45_MIDI3- B
1 1 6 11 8
LAN_MDI1+ CT CT RJ45_MIDI1+ PR4-
7 10
CL15 CL8 1U_0402_6.3V4Z LAN_MDI1- RD+ RX+ RJ45_MIDI1- RJ45_MIDI3+
8 9 7
4.7U_0805_10V4Z RD- RX- PR4+
@ 2 2 RJ45_MIDI1- 6
NS681680 PR2-
8105E@ RJ45_MIDI2- 5 PR3-
RJ45_MIDI2+ 4 PR3+
UL3 For EMI's request RJ45_MIDI1+ 3
CL39 1000P_0402_50V7K PR2+
1 TCT1 MCT1 24 2 1 1 8111E@ 2 CL31 68P_0402_50V8J RJ45_MIDI0- 2 PR1-
LAN_MDI3- 2 23 8111E@ RL11 75_0402_1% RJ45_MIDI3- 2 1 14
LAN_MDI3+ TD1+ MX1+ RJ45_MIDI3+ RJ45_MIDI0+ SHLD2
3 22 1
TD1- MX1- CL40 1000P_0402_50V7K PR1+
13
LAN_SK_LINK# LAN_SK_LINK#_R SHLD1
4 TCT2 MCT2 21 2 1 1 8111E@ 2 2 RL14 1 10 Green LED-
LAN_MDI2- 5 20 8111E@ RL12 75_0402_1% RJ45_MIDI2- 150_0402_5%
LAN_MDI2+ TD2+ MX2+ RJ45_MIDI2+
6 19 +3V_LAN 2 1 9
TD2- MX2- CL41 1000P_0402_50V7K Green LED+
7 18 2 1 1 2 RL18 150_0402_5% SUYIN_100073FR012G101ZL
LAN_MDI1- TCT3 MCT3 RL13 75_0402_1% RJ45_MIDI1- @
8 TD3+ MX3+ 17
LAN_MDI1+ 9 16 RJ45_MIDI1+
TD3- MX3- CL42 1000P_0402_50V7K
10 TCT4 MCT4 15 2 1 1 2
LAN_MDI0- 11 14 RL15 75_0402_1% RJ45_MIDI0- RJ45_GND 1 2 1000P_1808_3KV7K LANGND
LAN_MDI0+ TD4+ MX4+ RJ45_MIDI0+ CL36
12 13 1 1
TD4- MX4- CL37 CL38
For P/N and footprint
A Please place them to ISPD page RJ45_GND 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
A
1
UL1 SUPERW ORLD_SW G150401 2 2
CL34 8111E@
Place CL34 colse 0.1U_0402_25V4K
to LAN chip 2

RTL8105E-VB-GR
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
8105E@
Issued Date 2009/11/13 Deciphered Date 2010/02/02
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8105E/RTL8111E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 40 of 61
5 4 3 2 1
 A B C D

+1.8VS_OUT

place close to pin 5

20mil
D3E mode

1000P_0402_50V7K
10U_0805_10V4Z

0.1U_0402_16V4Z
0.22U_0402_6.3V4K
1 1 1 1
+3VALW
CC1 CC2 CC3 CC4 (Intel only)
CC4 close to pin 10

1
2 2 2 2 Intel can use PCIe root port
RC4
10K_0402_5%
JMB389C / JMB385C PCH GPIO13

2
1 1
+3VS PU HDA SUS RC5 0_0402_5%
UC1 28 CR_CPPE# 1 2 CPPE#
+TVA33 place near pin 19,20 and 44 +TVA33
CLK_CR# 3 5 JMB389@ 1 2 RC14 0_0402_5%
29 CLK_CR# CLK_CR APCLKN APVDD RC19 0_0402_5% CC5 0.1U_0402_16V4Z SD_CD#
29 CLK_CR 4 APCLKP APV18 10 2 28 CR_W AKE# 1 2
36 1 2 1 2 JMB389@
PCIE_PTX_C_CRRX_N5 NC/TAV33
29 PCIE_PTX_C_CRRX_N5 9 APRXN
CC6 0.1U_0402_16V4Z CC12 PCH GPIO21
PCIE_PTX_C_CRRX_P5 8 19 40mil 1 2 0.1U_0402_16V4Z
29 PCIE_PTX_C_CRRX_P5 APRXP DV33 CC7 0.1U_0402_16V4Z 1
DV33 20
29 PCIE_PRX_C_CRTX_N5 CC8 1 2 0.1U_0402_16V7K PCIE_PRX_CRTX_N5 11 44
CC9 0.1U_0402_16V7K PCIE_PRX_CRTX_P5 APTXN DV33 +1.8VS_OUT
29 PCIE_PRX_C_CRTX_P5 1 2 12 APTXP DV18 18 CC12 close to pin 36
DV18 37 20mil
2 1 APREXT 7
RC2 APREXT XD_SD_MS_D0
12mil MDIO0 48 2 1
12K_0402_1% 47 XD_SD_MS_D1 CC11 10U_0805_10V4Z
RC2 JMB389@ +SEL43 MDIO1 XD_SD_MS_D2
43 SDDV/MDIO4 MDIO2 46
9.1K_0402_1% 39 45 XD_SD_MS_D3 CC11 close to pin18 Power On Strapping setting
JMB385@ TXIN/NC MDIO3 SEL41 1 2
MDIO6/4 41 For intenal LDO's usage
42 SDCLK_MSCLK_XDCE# Description
MDIO5 SEL24
JMB389 G/MDIO6 24 Pin name
40 XD_CLE CC10 High low
SA00003Z400 MDIO7
★
JMB389@ 100_0402_5% 29 XD_SD_D4 0.22U_0402_6.3V4K
MDIO8 XD_SD_D5
32,39,40,44,45 PLT_RST# 1 2 1 XRSTN MDIO9 28 CC10 close to pin37
RC3 1 2 27 XD_SD_D6 MDIO7 on-board add-in card
CC13 XTEST MDIO10 XD_SD_D7
MDIO11 26
0.1U_0402_16V4Z JMB389@ 25 XD_RE#

★
CPPE# MDIO12 XD_RB#
2
13 CPPE_N MDIO13 23 CR_LED CR_LED
XD_CD# 14 22 XD_ALE MDIO14
RC3 CR1_CD2N MDIO14 high active low active
0_0402_5% 30
JMB385@ MS_CD# NC/SPI_SCK SEL33
15 CR1_CD1N NC/SPI_CSN 33
2
SD_CD# 16 34 +3VS 2

CR1_CD0N NC/SPI_SO
NC/SPI_SI 35
40 mils
+3VS 17 XD_CLE 1 2
+VCC_OUT CR1_PCTLN
APGND 6 MDIO7 RC28 10K_0402_5%
JMB385@ 31
SD_CD# CR_LED NC/GND UC1
1 2 21 CR1_LEDN NC/GND 32
RC27 4.7K_0402_5% 38 JMB385-QGAZ0C QFN 48P
MS_CD# NC/GND XD_ALE
1 JMB385@2 JMB385@ 1 2
RC29 4.7K_0402_5% MDIO14 RC26 @ 10K_0402_5%

GND
1 2 XD_CD# SA00003G010
RC32 4.7K_0402_5% 1 2
JMB385@ JMB389-QGAZ0C_QFN48_7X7 RC25 200K_0402_5%

49
JMB389@ place 6 GND vias on T-pad

+VCC_OUT

JMB385@ RC15 CC22 JMB385@

XDW P#_SDW P# 1 2 RC11 SD_CLK 1 2 1 2
RC7 10K_0402_5% SDCLK_MSCLK_XDCE# 2 1 SD_CLK FBMA-10-100505-121T_0402
XD_RB# 2 1 RC11 JMB389@ 22_0402_5% JMB385@ 100_0402_5% 100P_0402_50V8J
RC9 1K_0402_5% 2 1 MS_CLK RC12
SDCMD_MSBS_XDW E# 1 2 RC12 JMB389@ 22_0402_5% FBMA-10-100505-121T_0402 JMB385@ RC16 CC23 JMB385@
RC30 10K_0402_5% 2 1 XD_CE# JMB385@ MS_CLK 1 2 1 2
JMB385@ RC13 JMB389@ 22_0402_5% RC13
FBMA-10-100505-121T_0402 100_0402_5% 100P_0402_50V8J
JMB385@
JMB385@RC24
JMB385@RC24 CC24 JMB385@
Reserved for EMI,close to UC1.42 XD_CE# 1 2 1 2 RC18 0_0402_5%
SD_CD# XD_CD# SEL33 1 2
3
100_0402_5% 100P_0402_50V8J JMB385@ 3
0.1U_0402_16V4Z

0.1U_0402_16V4Z

@ CC20
1
CC21
1
@
NBQAA 4 in 1 Card Reader Reserved for EMI,close to JREAD SEL24
RC1 0_0402_5%
1 2
JREAD JMB385@
2 2 +VCC_OUT

MS-VCC 10 +VCC_OUT
40 mils 34 12 MS_CLK RC21 0_0402_5%
XD_CD# XD-VCC MS-SCLK MS_CD# XDW P#_SDW P#
1 XD-CD-SW MS-INS 16 1 2
1 1 XD_RB# 2 23 SDCMD_MSBS_XDW E# JMB389@
CC18 XD_RE# XD-R/B MS-BS XD_SD_MS_D0
3 XD-RE MS-DATA0 19
CC17 XD_CE# 4 21 XD_SD_MS_D1 RC22 0_0402_5%
10U_0805_10V4Z 0.1U_0402_16V4Z XD_CLE XD-CE MS-DATA1 XD_SD_MS_D2 SEL41
5 XD-CLE MS-DATA2 18 1 2
2 2 XD_ALE XD_SD_MS_D3 JMB385@
6 XD-ALE MS-DATA3 14
SDCMD_MSBS_XDW E# 7
+5VS XDW P#_SDW P# XD-WE RC23 0_0402_5%
8 XD-WP SD-VCC 20 +VCC_OUT
22 SD_CLK 1 2 SDCMD_MSBS_XDW E#
XD_SD_MS_D0 SD-CLK SDCMD_MSBS_XDW E# JMB389@
9 XD-D0 SD-CMD 15
2

XD_SD_MS_D1 24 30 XD_SD_MS_D0
RC6 XD_SD_MS_D2 XD-D1 SD-DAT0 XD_SD_MS_D1 RC20 0_0402_5%
25 XD-D2 SD-DAT1 32
390_0402_5% XD_SD_MS_D3 27 11 XD_SD_MS_D2 +SEL43 1 2
XD_SD_D4 XD-D3 SD-DAT2 XD_SD_MS_D3 JMB385@
28 XD-D4 SD-DAT3 13
XD_SD_D5 29 35 XDW P#_SDW P#
2 1

XD_SD_D6 XD-D5 SD-WP-SW SD_CD#

31 XD-D6 SD-CD-SW 36
XD_SD_D7 33 JMB389@
DC1 XD-D7 CC16 2.2U_0603_6.3V6K
HT-F196BP5_W HITE 4in1-GND 17 1 2
4in1-GND 26
4in1-GND 37 CC16 close to pin43
RC8 38 For internal LDO in SD3.0
1

4in1-GND
2 1 0_0402_5%
4 4
1

QC1 D TAITW _R015-300-LM_RV @

2 CR_LED
2N7002_SOT23-3 G
2

@S JMB can sink 16mA

3

RC10
4.7K_0402_5%
@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/10/08 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader-JMB389C/385C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NBQAA LA6071P M/B 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 41 of 61
A B C D
 5 4 3 2 1

place close to chip placement near Audio Codec

RA2 LA16
+5VALW 1 2 0.1U_0402_16V4Z +PVDD1 600 mA 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z SPKL+ 2 1 SPK_L1
+3VS +5VALW SPK_L1 43
RA19 0_0603_5% 1 2 0_0603_5% 1 1 0_0603_1% 2
EC setting: H/L 2 1 CA57 CA44 CA28
@ CA1 CA56 CA43 @

2
RA43 +1.5VS 1 2 CA2 10U_0603_6.3V6M 10U_0603_6.3V6M 2
@ RA20 0_0603_5% +3VS_DVDD JA1 2 1 2 2 1 CA30
100K_0402_5%

2
1 2 JUMP_43X39 10U_0805_10V4Z 1U_0402_6.3V4Z
2
10U_0603_6.3V6M CA33 @
1

1
EC_MUTE# 0.1U_0402_16V4Z @ place close to chip @
2

D 1 2 35 mA LA15 10U_0603_6.3V6M D
+3VS

1
RA45 RA1 0_0603_5% SPKL- 1 SPK_L2
2 1 2 1 SPK_L2 43
4.7K_0402_5% RA11 0_0603_1%
CA8 CA7 +PVDD2 1 2 0.1U_0402_16V4Z +5VALW LA17
02/04 To solve noise issue 1 2 0_0603_5% 1 2 SPKR+ 2 1 SPK_R1
SPK_R1 43
1

1 2 0.1U_0402_16V4Z CA60 @ CA59 CA58 0_0603_1% 2

10U_0603_6.3V6M CA61 @ @ @ CA32
+AVDD 10U_0603_6.3V6M 10U_0603_6.3V6M @
2 1 2 1 10U_0603_6.3V6M
1 2
CA31
RA3 2 1U_0402_6.3V4Z
Add CA34~CA37 for GPRS noise 68 mA 10U_0603_6.3V6M 0.1U_0402_16V4Z 1 2 CA29 @
+5VALW 1
0_0603_5% @
RA36 RA35 CA34 LA14 10U_0603_6.3V6M
MIC1_LINE1_R_L 1
2 10P_0402_50V8J SPKR- SPK_R2

39

46

25

38
1 2 2 1 1 2 1 SPK_R2 43

9
UA1 CA3 CA4 CA5 CA6 0_0603_1%
0_0402_5% 0_0402_5% RA30 CA9 1U_0402_6.3V4Z

PVDD1

PVDD2

AVDD1

AVDD2
DVDD_IO
DVDD
Ext. Mic/LINE IN 0_0402_5% 2 1
1 1 2 2
@ place close to chip
21 10U_0603_6.3V6M 0.1U_0402_16V4Z
Change CA9 and CA10 CA10
1U_0402_6.3V4Z 2
to 1U at pre-MP 23 40 SPKL+
LINE1_L SPK_OUT_L+
RA39 RA38 1 2 24 41 SPKL- Add CA38,CA39 for GPRS noise CA40 3.3P_0402_50V8
MIC1_LINE1_R_R CA35 10P_0402_50V8J LINE1_R SPK_OUT_L- EC Beep
14 LINE2_L SPK_OUT_R+ 45 SPKR+ CA38 3.3P_0402_50V8
44 EC_BEEP#
1
1
RA7
2 Beep sound
0_0402_5% 0_0402_5% 1 2 15 44 SPKR- 2 1 47K_0402_5%
RA37 CA36 10P_0402_50V8J LINE2_R SPK_OUT_R- Add CA40,CA51
10/9 Add RA30,RA35~RA39 0_0402_5% MIC1_LINE1_R_L 21 32 RA4 75_0402_1% for GPRS noise
MIC1_L HP_OUT_L HP_L 43
@ 4.7U_0603_6.3V6K CA21 22 33
C for AMP gain Test MIC1_LINE1_R_R MIC1_R HP_OUT_R RA5 75_0402_1%
HP_R 43
PCI Beep RA8
CA13 C
4.7U_0603_6.3V6K CA22 16 CA39 1 2 1 2 MONO_IN
MIC2_L 3.3P_0402_50V8 28,31 PCH_SPKR
1 2 17 MIC2_R 2 1 2 47K_0402_5%
CA37 10P_0402_50V8J 10 0.1U_0402_16V4Z
SYNC AZ_SYNC_HD 28
For EMI 3.3P_0402_50V8 CA51
25 INT_MIC_DATA 2 GPIO0/DMIC_DATA BCLK 6 AZ_BITCLK_HD 28
RA41 1
INT_MIC_CLK_R 3
25 INT_MIC_CLK GPIO1/DMIC_CLK

1
SDATA_OUT 5 AZ_SDOUT_HD 28 1
KC FBMA-10-100505-301T_0402
4 8 AZ_SDIN0_HD_R 2 1 RA12 CA18
44 EC_MUTE# PD# SDATA_IN AZ_SDIN0_HD 28
RA6 33_0402_5% 10K_0402_5% 0.1U_0402_16V4Z
2

2
28 AZ_RST_HD# 11 RESET# EAPD 47

SPDIFO 48
2

1 2 MONO_IN 12
RA17 CA12 100P_0402_50V8J PCBEEP
MONO_OUT 20
100K_0402_5% @
SENSE_A 13 SENSE A
29 Ext.MIC/LINE IN JACK
1

MIC2_VREFO
18 SENSE B
MIC1_VREFO_R 30 +MIC1_VREFO_R CA23
1 2 36 28 2 1 RA33 2 1 +MIC1_VREFO_R
CA15 CBP LDO_CAP 1K_0402_5% RA31 2.2K_0402_5%
2.2U_0603_6.3V4Z 35 27 AC_VREF 10U_0603_6.3V6M MIC1_LINE1_R_R 2 1
CBN VREF MIC1_R 43
CA47 1 2 0.1U_0603_50V7K +MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1%
MIC1_VREFO_L JDREF MIC1_LINE1_R_L
1 2 2 1 MIC1_L 43
B CA48 1 B
2 0.1U_0603_50V7K 43 PVSS2 CPVEE 34 1 2 @ 1K_0402_5%
42 CA14 2.2U_0603_6.3V4Z CA17 CA16 RA32 2 1 +MIC1_VREFO_L
CA49 1 PVSS1
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26 RA29 2.2K_0402_5%
2 1
10U_0603_6.3V6M
7 DVSS1 AVSS2 37
CA50 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z
ALC269Q-VB5-GR_QFN48_7X7
1 2 place close to chip
RA18 0_0603_5%
DGND AGND
MIC_SENSE

6
QA1A
RA28 100K_0402_5%
2N7002DW -T/R7_SOT363-6 2

Sense Pin Impedance Codec Signals Function

1
RA34 100K_0402_5%
39.2K PORT-I (PIN 32, 33) Headphone out place close to chip +3VL

20K PORT-B (PIN 21, 22) Ext. MIC MIC_SENSE 2 1 SENSE_A EC44 SM_SENSE#

3
SENSE A RA10 20K_0402_1%
QA1B
10K PORT-C (PIN 23, 24)
5 BACK_SENSE 43
2N7002DW -T/R7_SOT363-6
5.1K (PIN 48) 43 NBA_PLUG

4
A A
RA21 39.2K_0402_1%

39.2K PORT-E (PIN 14, 15)

SENSE B 20K PORT-F (PIN 16, 17) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title
10K PORT-H (PIN 20) HDA CODEC ALC269
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 42 of 61
5 4 3 2 1
 HeadPhone/LINE Out JACK Keyboard LED
JLINE
5 Q38 KBL@
4 +5VS AO3413_SOT23-3
42 NBA_PLUG
@ JKBL

D
LA6 1 2 HP_R_L 3 3 1 +5VS_LED 6 4 +5VS_LED
42 HP_R GND 4
KC FBM-L11-160808-121LMT 0603 6 1 5 3
GND 3

1
LA7 1 2 HP_L_L 2 2
42 HP_L 2
KC FBM-L11-160808-121LMT 0603 JGND 1 R587 C836 KBL@ 1

G
2
10K_0402_5% 0.1U_0402_16V4Z 1
FOX_JA6333L-B3T0-7F KBL@ 2 ACES_85201-04051
1
3 @

2
1 CA45 CA46 CA11 @
2 100P_0402_50V8J 100P_0402_50V8J
D

1
2
DA6 @ 0.1U_0402_16V4Z 2 Q51
44 KB_LED
PJDLC05_SOT23-3 G 2N7002_SOT23-3
For EMI S KBL@

3
please close to JKB

CURS_LED# 1 2
JGND C402 100P_0402_50V8J

2
KSO2 1 2
RA22 RA23 C404 100P_0402_50V8J
Ext.MIC/LINE IN JACK 0_0603_5% 0_0603_5% KEYBOARD CONN. KSO1 1
C405
2
100P_0402_50V8J
+5VL KSO0 1 2

1
C406 100P_0402_50V8J
KSO4 1 2
C407 100P_0402_50V8J
RA40 KSI[0..7] KSO3 1 2
KSI[0..7] 38,44
4.7K_0402_5% C408 100P_0402_50V8J
KSO[0..15] KSO5 1 2
KSO[0..15] 38,44
C409 100P_0402_50V8J
JEXMIC KSO14 1 2
5 C410 100P_0402_50V8J
JKB KSO6 1 2
4 JKB34 1 2 +3VS C411 100P_0402_50V8J
42 BACK_SENSE 34 R372 300_0402_5% KSO7 1 2
LA8 1 33
42 MIC1_R 2 MIC1_L_R 3 32
C412 100P_0402_50V8J
KC FBM-L11-160808-121LMT 0603 6 KSO13 1 2
LA9 1 31
42 MIC1_L 2 MIC1_L_L 2 30
C413 100P_0402_50V8J
KC FBM-L11-160808-121LMT 0603 JGND 1 JKB29 1 2 +3VS KSO8 1 2
29 KSO2 R373 300_0402_5% C415 100P_0402_50V8J
FOX_JA6333L-B3T0-7F 28 KSO1 KSO9
27 1 2
3 1 @ KSO0 C416 100P_0402_50V8J
26 KSO4 KSO10
1 25 1 2
2 CA41 CA42 CA19 @ KSO3 C417 100P_0402_50V8J
100P_0402_50V8J 100P_0402_50V8J 24 KSO5 KSO11
23 1 2
DA7 @ 2 KSO14 C418 100P_0402_50V8J
PJDLC05_SOT23-3 0.1U_0402_16V4Z 22 KSO6 KSO12
21 1 2
KSO7 C419 100P_0402_50V8J
20 KSO13 KSO15
For EMI 19 1 2
KSO8 C420 100P_0402_50V8J
18 KSO9 KSI7
17 1 2
KSO10 C421 100P_0402_50V8J
16 KSO11 KSI2
15 1 2
KSO12 C422 100P_0402_50V8J
14 KSO15 KSI3
13 1 2
KSI7 C423 100P_0402_50V8J
12 KSI2 KSI4
11 1 2
KSI3 C424 100P_0402_50V8J
10 KSI4 KSI0
9 1 2
KSI0 C425 100P_0402_50V8J
8 KSI5 KSI5 1 2
Speaker Connector @
7
6
KSI6
KSI1 KSI6
C427
1
100P_0402_50V8J
2
DA8 PJDLC05_SOT23-3 5 JKB4 C429 100P_0402_50V8J
4 2 1 +3VS
3 CAPS_LED# R376 300_0402_5% KSI1 1 2
3 CAPS_LED# 44
1 CURS_LED# C431 100P_0402_50V8J
2 CURS_LED# 44
2 NUM_LED# CAPS_LED# 1 2
1 NUM_LED# 44
C433 100P_0402_50V8J
JSPKL ACES_88170-3400 NUM_LED# 1 2
1 3 @ C435 100P_0402_50V8J
42 SPK_L1 1 NC1
42 SPK_L2 2 2 NC2 4
Check KB spec
ACES_85204-0200N
@
JSPKR
42 SPK_R1 1 1 NC1 3
42 SPK_R2 2 2 NC2 4

PJDLC05_SOT23-3 ACES_85204-0200N
3 @
1
2

DA11 @

Need to update symbol

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO/KB CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 43 of 61
 5 4 3 2 1

+3VL
+3VL
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 2 2 C442
C436 1 2 +5VALW
C437 C438 C439 C440 C441
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z USB_EN# 2 1
2 2 2 2 1 1 R103 @ 10K_0402_5%

111
125
0.1U_0402_16V4Z 1000P_0402_50V7K

22
33
96

67
9
for EMI request U19

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
CLK_PCI_EC BATT_TEMPA 1 2
C445 100P_0402_50V8J

1
D ACIN_D 1 2 D
R377 1 21 C446 100P_0402_50V8J
33 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F KB_LED 43
@ 10_0402_5% KB_RST# 2 23
33 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP# 42
28,45 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 SM_SENSE# 42
28,45 LPC_FRAME# 4 27 ACOFF 50
2

LFRAME# ACOFF/FANPWM2/GPIO13
1 28,45 LPC_AD3 5 LAD3
28,45 LPC_AD2 7 LAD2 PWM Output
C443 8 63 BATT_TEMPA
28,45 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA 49 To avoid folating
@ 22P_0402_50V8J VR_ON
2 28,45 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
R69
2 1
10K_0402_5% when EC is on initial
ADP_I/AD2/GPIO3A 65 ADP_I 50
CLK_PCI_EC 12 AD Input 66
32 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V 50
PLT_RST# 13 75
32,39,40,41,45 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
ECRST# 37 76
+3VL R378 ECRST# SELIO2#/AD5/GPIO43 HDPACT 45
33 EC_SCI# 20 SCI#/GPIO0E
47K_0402_5% 38
46 W L_BT_LED# CLKRUN#/GPIO1D
2 1 ECRST# 68
DAC_BRIG/DA0/GPIO3C VTTP_EN 52 +3VL
EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 6
2 1 DA Output IREF/DA2/GPIO3E 71 IREF 50
C444 0.1U_0402_16V4Z KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CHGVADJ 50
KSI1 56 CEC_INT# 2 1
KSI2 KSI1/GPIO31 100K_0402_5% R63
57 KSI2/GPIO32
KSI3 58 83
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# 42
KSI4 59 84 USB_EN# CAP_INT# 1 2
+3VL KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 37
KSI5 60 85 @ R172 4.7K_0402_5%
KSI5/GPIO35 PSCLK2/GPIO4C USB_CHG_EN# 37
KSI6 61 PS2 Interface 86 +5VS
KSI6/GPIO36 PSDAT2/GPIO4D HDPINT 45
1 2 KSO1 KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 38
R380 47K_0402_5% KSO0 39 88 TP_DATA TP_CLK 1 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 38
1 2 KSO2 KSO1 40 4.7K_0402_5% R379
R382 47K_0402_5% KSO2 KSO1/GPIO21 TP_DATA
41 KSO2/GPIO22 1 2
C KSO3 42 97 4.7K_0402_5% R381 C
KSO3/GPIO23 SDICS#/GPXOA00 VGATE 30,56 +3VALW
Avoid EC entering ENE test mode KSO4 43 KSO4/GPIO24 SDICLK/GPXOA01 98 W OL_EN# 40
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW #
PW RME_CTRL# 28
LID_SW #
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # 45 2 1
KSO7 46 SPI Device Interface 47K_0402_5% R383
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119
KSI[0..7] KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 45
KSO10 49 120 SYSON 1 2
38,43 KSI[0..7] KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 45
KSO11 50 SPI Flash ROM 126 R5 4.7K_0402_5%
KSO[0..15] KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 45
KSO12 51 128
38,43 KSO[0..15] KSO12/GPIO2C SPICS# SPI_CS# 45
KSO13 52
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
KSO15 54 73
KSO15/GPIO2F CIR_RX/GPIO40 CAP_RST# 38
RP7 81 74 CAP_INT#
KSO16/GPIO48 CIR_RLC_TX/GPIO41 CAP_INT# 38
+3VL 1 8 EC_SMB_CK1 82 89 R341 330K_0402_5%
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 50
2 7 EC_SMB_DA1 90 +3VALW 1 2
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# 46
+3VS 3 6 EC_SMB_CK2 91 D21
CAPS_LED#/GPIO53 CAPS_LED# 43
4 5 EC_SMB_DA2 EC_SMB_CK1 77 GPIO 92 ACIN_D 2 1
27,49 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW _LED# 46 ACIN 30,46,48
EC_SMB_DA1 78 93
27,49 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PW R_ON_LED# 46
2.2K_0804_8P4R_5% EC_SMB_CK2 79 SM Bus 95 SYSON CH751H-40PT_SOD323-2
14,29,38,45 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 39,54
EC_SMB_DA2 80 121 VR_ON
14,29,38,45 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 56
127 ACIN_D
AC_IN/GPIO59

+3VALW 6 100
30 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 30
C818 SLP_S5# 14 101
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 29
1 2 EC_SMI# 15 102
33 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 46 +3VALW
0.1U_0402_16V4Z 16 103
33 THM_ALT# LID_SW#/GPIO0A EC_SWI#/GPXO06 TP_LED 38
5

38 ESB_CK 17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 PM_PW ROK 30

B B
2 18 GPO 105
P

30 PM_SLP_S5# B 38 ESB_DAT PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 25

4 SLP_S5# 19 GPIO 106
Y 30 PCH_SUSPW RDN EC_PME#/GPIO0D WL_OFF#/GPXO09 W L_OFF# 39

2
30 PM_SLP_S4# 1 A 25 INVT_PW M 25 EC_THERM#/GPIO11 GPXO10 107 CURS_LED# 43
G

28 108 LOGO_LED R343

6 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 LOGO_LED 38
U44
45 HDPLOCK 29 @ 100K_0402_5% LOGO_LED EC Version
3

SN74AHC1G08DCKR_SC70-5 FANFB2/GPIO15
39 E51_TXD 30 EC_TX/GPIO16
31 110 CEC_INT#
39 E51_RXD CEC_INT# 27

1
EC_RX/GPIO17 PM_SLP_S4#/GPXID1
46 ON/OFFBTN# 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 UMA_ENBKL 31
LOGO_LED HIGH KB926D3
46 PW R_SUSP_LED# 34 PWR_LED#/GPIO19 GPXID3 114 USB_OC#1 32,37

2
36 GPI 115 SLP_CHG#
43 NUM_LED# NUMLED#/GPIO1A GPXID4 SLP_CHG# 37
GPXID5 116 SUSP# 39,47,50,53,58
R345 LOW KB926E0
117 100K_0402_5%
GPXID6 PBTN_OUT# 30
GPXID7 118 USB_OC#0 32,37
CRY1 122

1
CRY2 XCLK1 +EC_V18R
123 XCLK0 V18R 124
AGND

R389
GND
GND
GND
GND
GND

R337 100K_0402_5% CRY1 1 2CRY2 C448

1 2 VTTP_EN 4.7U_0805_10V4Z
@ 10M_0402_5% KB926QFE0_LQFP128_14X14
11
24
35
94
113

69

1 1
1

C449 C450
Y4 +3VALW
18P_0402_50V8J

OSC

OSC

18P_0402_50V8J

2 2
A
SLP_CHG# 2 1 A
R72 10K_0402_5%
2 KB_RST#
NC

NC

1
C474 @ 100P_0402_50V8J
1 2 PLT_RST#
2

C456 @ 100P_0402_50V8J
1 2 EC_SMI#
C455 @ 100P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
Reserved for EMI 32.768KHZ_12.5PF_Q13MC14610002
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title
ENE-KB926 RevD3/E0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 44 of 61
5 4 3 2 1
 SPI Flash (256KB) Lid SW LPC Debug Port
Socket: SP07000F500 & SP07000H900 Please place the PAD under DDR DIMM.

+3VL H99
+3VS

20mils +3VALW 6 5
1
C451 U22
8 4 U21
0.1U_0402_16V4Z VCC VSS APX9132ATI-TRL_SOT23-3
28,44 SERIRQ 7 4 PLT_RST# 32,39,40,41,44
2
3 W
2 3

GND
VDD VOUT LID_SW # 44
7 HOLD 28,44 LPC_AD3 8 3 LPC_AD2 28,44

44 SPI_CS# 1 1 1

1
S
28,44 LPC_AD1 9 2 LPC_AD0 28,44
6 C453 C452
44 SPI_CLK C 0.1U_0402_16V4Z 10P_0402_50V8J
2 2
44 EC_SO_SPI_SI 5 D Q 2 EC_SI_SPI_SO 44 28,44 LPC_FRAME# 10 1 CLK_PCI_DDR 32
MX25L2005CMI-12G SO8

2
@ DEBUG_PAD R393
22_0402_5%

SPI_CLK 1 R394 2 1 2

1
10_0402_5% C454 10P_0402_50V8J 2
@ @
reserve for EMI, close to U22 C457
22P_0402_50V8J
1

reserve for EMI

G-Sensor +3VS_HDP 2
UG1
3 VOUTXCG1 1 2 0.033U_0402_16V7K
Vdd1 Voutx VOUTYCG2 0.033U_0402_16V7K
12 Vdd2 Vouty 5 1 2
7 VOUTZCG3 1 2 0.033U_0402_16V7K +3VS_HDP
Voutz CG9 UG4
SELF_TEST 4 10 0.1U_0402_16V4Z 2 1VOUTX 2 6
ST NC1 CG10 @ XOUT VDD
6 PD NC2 11
8 14 0.1U_0402_16V4Z 2 1VOUTY 3
RG2 @ FS NC3 CG11 @ YOUT
NC4 15 NC 1
+3VS 2 1 +3VS_HDP 16 0.1U_0402_16V4Z 2 1VOUTZ 4 8
NC5 @ ZOUT NC
NC 11
0_0603_5% +3VS_HDP 9 1 9 12
+5VS +3VS_HDP Rev GND1 0G-DET NC
GND2 13 NC 14
DG1 CH751H-40PT_SOD323-2 +3VS_HDP 7
TSH35TR_LGA16 SLEEP#
1 2 10 G-SELECT
2 2 SELF_TEST 13 5
CG12 UG3 ST VSS
1U_0402_6.3V4Z CG13 MMA7360LR2_LGA14
1 5 1U_0402_6.3V4Z @ Reserved for 2nd source
1 VIN VOUT 1 SA00003A600 Supports ODD unexpected tray eject prevention
2 GND CG14 UG2
3 SHDN# BP 4 2 1
@ 1 11 HDPACT 44
14,29,38,44 EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01

2
G9191-330T1U_SOT23-5 0.22U_0402_10V4Z
SELF_TEST2 12 RG9
P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11#
47K_0402_5%

+3VS_HDP RG3 2 1 3 13

1
4.7K_0402_5% RESET# P1_4/TXD0

RG4 2 1GXOUT 4 14
XOUT/P4_7 P1_3/KI3#/AN11/TZOUT HDPLOCK 44
4.7K_0402_5%
RG10 47K_0402_5%
5 15 VOUTZ 2 1
VSS/AVSS P1_2/KI2#/AN10/CMP0_2

RG5 2 1GXIN 6 16 +3VS_HDP

4.7K_0402_5% XIN/P4_6 P4_2/VREF
1
7 17 VOUTX CG6
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_16V4Z

RG6 VOUTY 2
2 1 8 MODE P1_0/KI0#/AN8/CMP0_0 18

4.7K_0402_5%
HDPINT RG7 2 1 9 19
44 HDPINT P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
1K_0402_5%
1 1 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA2 14,29,38,44
CG8
CG7
0.1U_0402_16V4Z R5F211B4D34SP_LSSOP20
2 2
0.1U_0402_16V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPI ROM/G-SENSOR/Debug
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 45 of 61
 5 4 3 2 1

Power Button
+3VL
PWR/B Conn
ISPD

2
R395 ZZZ UV1 UV1 UV1

100K_0402_5%
SW 2
PCB DAZ0CL00200 GPU SA00003SC10 SA00003SC00 SA00003RA00

1
1 3 ON/OFFBTN# 44 For EMI request
TOP side JPOW ER @
2 4 POW ER_ON_LED PCB DIS LA-6072P REV1 N11M-OP1-B-A3 N11M-OP1-B-A3 N11P-LP1-A3
D 1
C458 1 1 1
C476
2
0.1U_0402_16V4Z N11MR3@ N11MR1@ N11PR1@
D

@ SMT1-05-A_4P 0.1U_0402_25V6 2 2 ON/OFFBTN#

6 3 3
5 @
51_ON# 48 4 4
PJP1
2 N11PR3@: SA00003RA10
G1 5

2
SW 3
1 3
G2 6 D83
DC-IN DC301009V00
HM55R3@: SA00003N790
HM55: BD82HM55 SLGZS B3

6
ACES_85201-0405N PJSOT05C_SOT23-3 HM57: BD82HM57 SLGZR B3
BTM side 2 4 For EMI request Q13A @
2N7002DW -T/R7_SOT363-6 PJP1
@ SMT1-05-A_4P 2 another at page 35 45@
6
5

1
44 EC_ON

1
R396 U11 U11 U11 U11 U11
debug phase using 10K_0402_5%

PCH SA00003NI60 SA00003NI30 SA00003N750 SA00003G8G0 SA00003G8A0

1
PCH PCH PCH PCH PCH
HM57R3@ HM57R1@ HM55R1@ PM55R3@ PM55R1@

DC-IN LED WL/BT LED

Screw Hole
ACIN 30,44,48
2

C R58 D12 D25 H14 H15 H16 H17 H18 H19 H20 H21 C
1 2 2 1 +5VALW
+5VS W L_BT_LED# 44
+5VALW 1 2 2 1 6 1 R400 510_0402_5%
HT-191UD5_AMBER_0603 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 2

1
390_0402_5% HT-F196BP5_W HITE Q161A 2N7002DW -T/R7_SOT363-6 @ @ @ @ @ @ @ @
another at page 27 C392
0.1U_0402_16V4Z
1
H22 H23 H24 H25 H26
For EMI's request
Close to H21
H_3P0 H_2P7N H_3P0 H_2P7X3P7N H_2P7N
BATT CHARGE/FULL LED WiMAX/3G LED

1
W IMAX_LED_GND 1 R506 2 @ @ @ @ @
LED_W IMAX# 39
0_0402_5%

2
@ +3VS
W IMAX@ W IMAX@
D14 +5VS 2 R819 1 6 1 H30
R60 10K_0402_5% 2

5
1 2 2 1 Q8A
BATT_FULL_LED# 44
390_0402_5% D75 2N7002DW -T/R7_SOT363-6 H_3P8 C393

1
+5VALW HT-F196BP5_W HITE +5VS 1 2 2 1W IMAX_LED_GND 3 4 @ 0.1U_0402_16V4Z
R59 D23 R778 390_0402_5% 1
1 2 2 1 W IMAX@ HT-F194NB5_BLUE_0603 Q8B 2N7002DW -T/R7_SOT363-6
BATT_CHG_LOW _LED# 44 For EMI's request
510_0402_5% W IMAX@ W IMAX@
HT-191UD5_AMBER_0603
H1 H2 H3 H4
CPU
H_4P2 H_4P3 H_4P3X5P3 H_4P3X5P3

1
B @ @ @ @ B

H31 H32
POWER/SUSPEND LED HDD LED H5 H6 H7
VGA MDC
H_1P2 H_1P2

1
+5VALW H_2P9 H_3P0 H_3P0X4P0 @ @

1
+5VS +5VS @ @ @
3

47K WLAN H8 H9 3G H10 H11 JET H12 H13

1

Q42
2

R51
10K 2 390_0402_5% R404 H_1P2 H_1P2 H_1P2 H_1P2 H_1P2 H_1P2
PW R_ON_LED# 44

1
10K_0402_5% @ @ @ @ @ @
SATA_LED# 28
2 2

PDTA114YT PNP SOT23-3 D11

D10
1

1 2 2 1 HT-F196BP5_W HITE 6 1
R516 390_0402_5%
5

HT-F196BP5_W HITE Q7A

1 2 POW ER_ON_LED 2N7002DW -T/R7_SOT363-6
PCB Fedical Mark PAD
1

R544 390_0402_5% HDD_LED# 3 4

Q7B 2N7002DW -T/R7_SOT363-6

FD1 FD2 FD3 FD4

A
@ @ @ @ A
D20

1
R770
+5VALW 1 2 2 1 PW R_SUSP_LED# 44
510_0402_5%
HT-191UD5_AMBER_0603
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Comm. SW/ Sub Conn./LEDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 46 of 61
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS

+3VALW +3VS Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW +5VS
4.7U_0805_10V4Z
+1.5V +1.5VS
1 1 1 1 Vgs=-0V,Id=9A,Rds=18.5mohm
Q29 C459 C460 4.7U_0805_10V4Z Q30 C461 C462

470_0805_5%

470_0805_5%
8 D S 1 8 D S 1 1 1

2
7 2 7 2 Q31 C463 C464
D S 2 2 R406 D S 2 2 R407

470_0805_5%
6 D S 3 6 D S 3 8 D S 1

2
1 5 4 5 4 7 2 4.7U_0805_10V4Z 1
D G 1U_0402_6.3V4Z D G 1U_0402_6.3V4Z D S 2 2 R408
6 D S 3
SI4800BDY_SO8 1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB 5 4

3 1

3 1
47K_0402_5% 47K_0402_5% D G 1U_0402_6.3V4Z
1 1 1 1

0.01U_0402_25V7K
4.7U_0805_10V4Z

0.022U_0402_25V7K

4.7U_0805_10V4Z
1

6
C466 SI4800BDY_SO8 1 R411 2 +VSB

3 1
C465 R412 Q10A C467 C468 R413 Q11A 1 1 220K_0402_5%

4.7U_0805_10V4Z

6
330K_0402_5% Q10B 200K_0402_5% Q11B

0.1U_0402_25V6
2 2 2 2

C470
2 SUSP 5 @ 2 SUSP 5 C469 R414 Q12A
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 820K_0402_5% Q12B

2
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 2 2 SUSP
2 5

4
2N7002DW -T/R7_SOT363-6

2
2N7002DW -T/R7_SOT363-6

4
+5VS TO +5VS_ODD
+5VS +1.5V to +VRAM_1.5VS +1.05VS to +1.05VS_DGPU
+5VS_ODD (11A,440mils ,Via NO.= 22)
+5VS (2.87A,120mils ,Via NO.= 6)

2
+1.5V +VRAM_1.5VS
2

2 R433
R398 C471 Vgs=-4.5V,Id=3A,Rds<97mohm 470_0805_5% Vgs=10V,Id=14.5A,Rds=6mohm +1.05VS +5VALW
100K_0402_5% 0.1U_0402_16V7K
1 1

1
2

2
2 1 C478 2
1

S
Q45 PJ32 Q43 C475 R416

470_0805_5%
2

2
G
ODD_EN# 1 R122 2 2 JUMP_43X39 8 1 4.7U_0805_10V4Z 220K_0402_5%
32 ODD_EN# D S

2
47K_0402_5% 2 2 R429
@ 7 D S 2 D

1
+5VS_ODD
1

2 AO3413_SOT23 Q9B 6 3 PJ34 Q56

D

2
1

1
ODD_EN# D S 1U_0402_6.3V4Z
5 5 4 JUMP_43X79 2
1

D G
C217 1 R431 2 +VSB @ G Another at page13

3 1

1
0.01U_0402_25V7K 2N7002DW -T/R7_SOT363-6 1 FDS6676AS_SO8 1 220K_0402_5% S AO3416_SOT23-3

4.7U_0805_10V4Z
4

3
1

6
1
1

0.1U_0402_25V6

1
C481
1 C473 R430 Q164A 1 QV2A
C680 820K_0402_5% Q164B C479
C679 1U_0402_6.3V4Z 2 2
2 VGA_PW ROK# 5 2N7002DW -T/R7_SOT363-6 +1.05VS_DGPU 1 2 DGPU_PW R_EN#
4.7U_0805_10V4Z 2 2N7002DW -T/R7_SOT363-6 0.1U_0402_25V6

2
@ 2 C686 2 2N7002DW -T/R7_SOT363-6

1
1U_0402_6.3V4Z
2

+3VS to +3VS_DGPU (780mA,40mils ,Via NO.= 2) +5VALW +0.75VS

2
+3VS

2
+3VALW R422
100K_0402_5% R421 R421
470_0805_5% 47_0805_5%
@

1
2

3 SUSP 3
2 9,55 SUSP

1
R434 C491

3
100K_0402_5% Vgs=-4.5V,Id=3A,Rds<97mohm
0.1U_0402_16V7K

6
Q5B Q5A
2

1 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6

1

S
R432 Q54 PJ33 5
2

G 39,44,50,53,58 SUSP# +3VALW

DGPU_PW R_EN# 1 2 2 JUMP_43X39 2 SUSP
2

@ +3VS_DGPU 4
1

47K_0402_5% AO3413_SOT23
For S3 Power Reduction
D
2
1

1
6

R423
1

2
Q165A C492 10K_0402_5%
0.01U_0402_25V7K R425
1

1 +5VALW 100K_0402_5%
13,33,58 DGPU_PW R_EN 2 1
2N7002DW -T/R7_SOT363-6 1
C684
0.75VR_EN# 55
1

1
C683 1U_0402_6.3V4Z
2

4.7U_0805_10V4Z 2

3
@ 2 R426 Q44B
100K_0402_5% 2N7002DW -T/R7_SOT363-6

5,52 VTTPW ROK 1 2 0.75VR_EN 5

1

VGA_PW ROK# R158 100K_0402_5%

4
3

6
+1.05VS_DGPU Q44A
+3VS_DGPU +VGA_CORE Q13B 2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
2

5 SUSP 2
28,32,58 VGA_PW ROK
R458 R459 R460 another at page 46
470_0805_5% 470_0805_5% 470_0805_5%
4

1
4 4
3 1

6 1

6 1

Q165B Q9A Q14A

2N7002DW -T/R7_SOT363-6 5 DGPU_PW R_EN# 2 DGPU_PW R_EN# 2 Security Classification Compal Secret Data Compal Electronics, Inc.
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 2009/11/13 2010/01/23 Title
Issued Date Deciphered Date
DC-DC INTERFACE
4

Another at page41 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 47 of 61
A B C D E
 A B C D

VS
VIN PR1
PL1 VIN 1M_0402_1%
PF1 SMB3025500YA_2P
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
1 2

1
1
PJP1 N1 PR3
10A_125V_451010MRL PR2 5.6K_0402_5% PR4

680P_0402_50V7K
1000P_0402_50V7K

1000P_0402_50V7K
+ 1
84.5K_0402_1% 10K_0402_1%

680P_0402_50V7K

100P_0402_50V8J

100P_0402_50V8J
1

1
1 1

PC5
2 1 2 ACIN 30,44,46

2
+

1
PC1

PC2

PC3

PC4

PC6
PR5

8
3 22K_0402_1% PU1A

2
-
@ 1 2 3

P
2
@ + PACIN
- 4 O 1 PACIN 50
2 -

G
1
@ SINGA_2DW -0005-B03

1
PR6 LM393DG_SO8

4
PC7 20K_0402_1% PC8 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%

2
2

2
2 1 +CHGRTC
PR8
VIN 10K_0402_1%
3.3V Vin Detector

2
PD2
High 18.384 17.901 17.430
RLS4148_LL34-2 Low 17.728 17.257 16.976

1
BATT+ 2 1

1
PD3 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR11

2
200_0603_5%
2
CHGRTCP 1 2 N1 3 1 VS 1 2 2
0.22U_0603_25V7K

PR12
1

1K_1206_5%
1

1
PC10 PD4
PC9

PR13 0.1U_0603_25V7K 2 1 N3 1 2
100K_0402_1% VIN B+
2

2
RLS4148_LL34-2 PR14
2

1K_1206_5%
46 51_ON# 1 2
PR15 1 2
22K_0402_1%
RTC Battery PR16
1K_1206_5%

1
1

PR19 PR20
PR17
200_0603_5%
- PBJ1 + PR21
560_0603_5%
PR22
560_0603_5%
VL
100K_0402_1%
1 2
2.2M_0402_5%
2 1
PR18
499K_0402_1%
PU2 G920AT24U_SOT89-3 2 1 1 2 1 2
3.3V +RTCBATT

2
2

3 2 N2
+CHGRTC OUT IN PD5

8
@ MAXEL_ML1220T10 RB715F_SOT323-3 PU1B
1

GND
2 5

P
51 EN0 +
PC11 PC12 1 7
10U_0805_10V4Z 1 O
50 ACON 3 6 2 1 +CHGRTC
2

1
1U_0805_25V4Z
SP093MX0000 LM393DG_SO8 PR23 PR24

1
10K_0402_1% 499K_0402_1% PC14

1
PR26 1000P_0402_50V7K
PC13 @ PR25 191K_0402_1%

2
3 3

1000P_0402_50V7K 66.5K_0402_1%

2
1

2
PJ1 PJ2 PJ3 PC15
+3VALW P 2 1 +3VALW 2 1 +1.8VSP 2 1 +1.8VS 1000P_0402_50V7K

2
2 1 2 1 2 1
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X79
(5A,200mils ,Via NO.= 10) (2A,80mils ,Via NO.= 4) PR27

1
PJ4 D 47K_0402_1%
OCP=8.6A 2 1
OCP=4.2A PQ2 2 2 1 PACIN
+1.5VP 2 1 +1.5V PJ6
PJ5 SSM3K7002FU_SC70-3 G
+5VALW P 2 1 +5VALW @ JUMP_43X118 VL 2 1 +5VL S

3
2 1 2 1
@ JUMP_43X118 (15A,600mils ,Via NO.= 30) @ JUMP_43X39

1
(5A,200mils ,Via NO.= 10) OCP=21.73A (100mA,40mils ,Via NO.= 2)
OCP=7.9A
PJ7
PJ8
PJ9
+VSBP 2 1 +VSB 2 1 +GFX_CORE 2
2 1 2 1 +5VALW P
+GFX_COREP +3VLP 2 1 +3VL
@ JUMP_43X39 @ JUMP_43X118 2 1
@ JUMP_43X39 PQ3
(120mA,40mils ,Via NO.= 1) PJ10 (100mA,40mils ,Via NO.= 2) Precharge detector DTC115EUA_SC70-3

3
2 2 1 1
PJ12
15.97V/14.84V FOR
2
PJ11
1
@ JUMP_43X118 2 2 1 1 ADAPTOR
2 1
(22A,880mils ,Via NO.=44) @ JUMP_43X118
@ JUMP_43X118
OCP=26A
PJ13 PJ15
+VTTP 2 1 +VTT PJ17 +VGA_COREP 2 1 +VGA_CORE
4 2 1 2 1 4
+0.75VSP 2 2 1 1 +0.75VS
@ JUMP_43X118 @ JUMP_43X118
(18A,720mils ,Via NO.=36) @ JUMP_43X79
OCP=29.73A (1.5A,60mils ,Via NO.= 4) (26A,1040mils ,Via NO.=52)
OCP=28.65A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN / DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA DIS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 48 of 61
A B C D
 A B C D

1 1
VMB
PF2 PL2
PH1 under CPU botten side :
PJP2 15A_65V_451015MRL SMB3025500YA_2P
1 BATT_S1 1 2 1 2
CPU thermal protection at 95 degree C
1 BATT+
2 2
3 BATT_P3 1 2 1 2
Recovery at 56 degree C
3 +3VLP

1
BATT_P4 PR28 PR29

1000P_0402_50V7K
4 4

1
BATT_P5 1K_0402_1% 47K_0402_1% PC17
5 5 PH2 near main Battery CONN :

1
0.01U_0402_25V7K

PC16
10 6 EC_SMDA @ PC73

2
GND 6 EC_SMCA @ PC18 0.1U_0402_25V6K
11 7 BAT. thermal protection at 95 degree C

2
GND 7

1
12 8 0.1U_0402_25V6K

2
GND 8 PR30
13 GND 9 9
1K_0402_1%
Recovery at 48 degree C
@ SUYIN_200045MR009G171ZR

2
VL

PD7
1

PJSOT24C_SOT23-3

1
PD6 2

1
PJSOT24C_SOT23-3 1 PR31
3 PC19 19.6K_0402_1%
PR32 0.1U_0603_25V7K

2
6.49K_0402_1% PR33
2

2
2 1 19.6K_0402_1%
+3VLP

2
PR34

1
1

8.66K_0402_1%
PR35 PU4
2
1K_0402_1% 1 8 2

1
VCC TMSNS1

1
2 7
2

GND RHYST1
2

PR36 PR37 3 6 PH1

BATT_TEMPA 44 OT1 TMSNS2
100_0402_1% 100_0402_1% 100K_0402_1%_NCP15W F104F03RC

1
4 5

2
OT2 RHYST2 PR40
1

51 VS_ON G718TM1U_SOT23-8 7.87K_0402_1%

EC_SMB_DA1 27,44

2
EC_SMB_CK1 27,44

1
PH2
100K_0402_1%_NCP15W F104F03RC

2
PQ4
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
3 3
100K_0402_1%

0.1U_0603_25V7K
0.22U_0603_25V7K
1

1
PR41

PC20

PC21

@ @
2

2
2

VL PR42
22K_0402_1%
1 2
2

PR43
100K_0402_1%

PR44
1

0_0402_5% D
1 2 2 PQ5
51 POK
G SSM3K7002FU_SC70-3
.1U_0402_16V7K

S
3
1

@ PC22
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 49 of 61
A B C D
 A B C D

B+

10U_1206_25V6M

10U_1206_25V6M
PQ6
AO4407A_SO8

1
PC194
1 8

PC193
2 7
B+ 3 6

2
PQ7 P2 PQ8 P3 PR45 0.02_2512_1% CHG_B+ 5
AO4407A_SO8 AO4407A_SO8 PJ18
VIN 8 1 1 8 1 4 2 1

4
2 1
7 2 2 7
@ JUMP_43X118 CSIN

0.1U_0402_25V6K
6 3 3 6 2 3

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5 5 @ PQ9 AO4407A_SO8
1 8
CSIP 2 7

4
1
1 1

3 6

1
PQ11 TP0610K-T1-E3_SOT23-3 5

3
PQ10 PR46 PR47 10_0603_5%

5600P_0402_25V7K
2
DTA144EUA_SC70-3 200K_0402_1% DCIN

0.1U_0603_25V7K
3 1 1 2
P3

4
PC28
2
1

PC23

PC24

PC25

PC26
2 PR49

<BOM Structure>
1
PC27
PR50 PQ12 47K_0402_1%

1
PR48 100K_0402_1% DTC115EUA_SC70-3 1 2

2
47K_0402_1% @ VIN

2
PR51 PD8
2

2
100K_0402_1% 2 FSTCHG PR52 PD9
1

2
1

PD10 2 1 2 1 10K_0402_1% 1 2 ACOFF

1SS355_SOD323-2 3
1 2 6251VDD SUSP# 39,44,47,53,58 1SS355_SOD323-2

1
RB715F_SOT323-3 PR54

2.2U_0603_6.3V6K
PC29
2 PR53 200K_0402_1%

3
1

1
PQ13 10K_0402_1% 1 2 VIN
DTC115EUA_SC70-3 2 1 PU5 PC31
44 FSTCHG 0.1U_0603_25V7K

2
DCIN PQ15 PD11

100K_0402_1%
1 2 1 24 2 1
3

VDD DCIN
1

1
DTC115EUA_SC70-3 2 1 2

PR56
PC30
PR55 .1U_0402_16V7K 2 23 1SS355_SOD323-2
ACSET ACPRN
1

D 150K_0402_1% PR57
2 PQ14 20_0603_5%
2

1
G SSM3K7002FU_SC70-3 6251_EN CSON D
3 EN CSON 22 1 2

1
S PC32 PC33 2 PACIN
3

5
6
7
8
0.047U_0603_16V7K 0.1U_0603_25V7K G
CSOP

AO4466_SO8
4 21 1 2 PQ16
SSM3K7002FU_SC70-3

3
CELLS CSOP PR58 SSM3K7002FU_SC70-3
PC35 6800P_0402_25V7K 20_0603_5%

PQ17
2 2
1 2 5 ICOMP CSIN 20 2 1
1

2
D PR59 4
PQ18

2 PC36 PR60 6.81K_0402_1% PC37 20_0603_5%

G 1 2 1 2 6 19 0.1U_0603_25V7K1 2

1
VCOMP CSIP PL3 PR63
S
3

0.01U_0402_25V7K 1 2 PR62 47K_0402_1% PR61 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1% BATT+

3
2
1
PR64 1 2 7 18 LX_CHG 2.2_0603_1% 1 2 CHG 1 4
ICM PHASE

1
22K_0402_5% @ PC38 100P_0402_50V8J

4.7_1206_5%
5
6
7
8

PR65
PACIN 1 2 1 2 2 3
48 PACIN
PC39 6251VREF DH_CHG

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
8 VREF UGATE 17
PR66 .1U_0402_16V7K PR67 PC40
48 ACON 44
154K_0402_1% ADP_I 0_0603_5% 0.1U_0603_25V7K

AO4466_SO8

1
PC41

PC42

PC192
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1
44 IREF CHLIM BOOT
1

1
PR68 4

1
24K_0402_1% PD12

680P_0603_50V8J
0.01U_0402_25V7K

2
PQ19

PC43
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1

2
1

1
PC44

ACOFF 2 PQ20 PR69 1 26251VDD

44 ACOFF

3
2
1
DTC115EUA_SC70-3 120K_0402_1% PR70 11 14 DL_CHG
VADJ LGATE

2
20K_0402_1% PR71
2

4.7_0603_5%
2

12 13 PC45
3

1
GND PGND 4.7U_0805_6.3V6K

ISL6251AHAZ-T_QSOP24

PR72
15.4K_0402_1%
1 2
44 CHGVADJ
1

3
PR73 3

31.6K_0402_1%
VIN
2

CP mode

1
Iada=0~4.737A(90W) CP= 92%*Iada; CP=4.36A
PR74
Vaclim=0.736V(90W) PR70=53.6k PR49=0.015 309K_0402_1%

PR75

2
10K_0402_1%
1 2
CC=0.25A~3A CHGVADJ=(Vcell-4)/0.10627 ADP_V 44

1
IREF=1.016*Icharge Vcell CHGVADJ

1
PR76
47K_0402_1% PC46
IREF=0.254V~3.048V 4V 0V .1U_0402_16V7K

2
VCHLIM need over 95mV 4.2V 1.882V 2

4.35V 3.2935V

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 50 of 61
A B C D
 5 4 3 2 1

2VREF_51125

1U_0603_10V6K
D D

1
PC47

2
PR77 PR78
13K_0402_1% 30K_0402_1%
1 2 1 2

PR79 PR80
B++
20K_0402_1% 19.1K_0402_1%
1 2 1 2 B++
@ PJ19

ENTRIP2

ENTRIP1
B+ 2 2 1 1 +3VLP
PR81 PR82
JUMP_43X118 165K_0402_1% 150K_0402_1%
1 2 1 2
10U_1206_25V6M

10U_1206_25V6M
0.1U_0603_25V7K

1
PC48

PC49
1
PC188

4.7U_0805_10V6K
2

1
PU6

5
6
7
8
PC50

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
2

8
7
6
5

1
C C
25 PQ22
PQ21 P PAD AO4466_SO8

2
AO4466_SO8
7 VO2 VO1 24 POK 49 4
4
8 23 PC52
PR83 VREG3 PGOOD PR84 .1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
2.2_0603_5% BOOT2 BOOT1 2.2_0603_5%
1
2
3

PL4 PC51 UG_3V 10 21 UG_5V PL5

4.7UH_FMJ-0630T-4R7 HF_5.5A_20% .1U_0402_16V7K UGATE2 UGATE1 4.7UH_FMJ-0630T-4R7 HF_5.5A_20% +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
1

8
7
6
5

5
6
7
8

1
LG_3V LG_5V
4.7_1206_5%

12 19

4.7_1206_5%
LGATE2 LGATE1
PR85

PR86
SKIPSEL
PQ23 PQ24

VREG5
1 AO4712_SO8 AO4712_SO8 @ 1

GND
150U_V_6.3VM_R18

150U_V_6.3VM_R18
VIN
48 EN0 RT8205EGQW _W QFN24_4X4

NC
EN
2

2
1

1
+ +
PC53

PC54
4 <BOM Structure> 4
@ PC74 PR87 @ PC75

13

14

15

16

17

18
1

1
.1U_0402_16V7K 499K_0402_1% .1U_0402_16V7K
680P_0603_50V8J

680P_0603_50V8J
2

2
2 2
PC55

PC56
1 2
B+
2

1
2
3

3
2
1

2
1
Ipeak=5A @

100K_0402_5%
1
1U_0402_6.3V6K
Imax=3.5A

PR88
1 2
VL
PC57

F=305KHz 2

1
@ PR89

PC58
4.7U_0805_10V6K
2
B Total Capacitor 150uF, 0_0402_5% B

ESR 15mohm Ipeak=5A

2
ENTRIP1 ENTRIP2 B++
Imax=3.5A
F=245KHz

1
Total Capacitor 700uF,

0.1U_0603_25V7K
ESR 5.2mohm

2
PC59
D D
1

2VREF_51125
PQ25 2 2 PQ26
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3

2 1
VL
PR90
100K_0402_1%
1

PQ27
DTC115EUA_SC70-3
49 VS_ON
VS 1 2 2

PR91
42.2K_0402_1%

0.01U_0402_16V7K
1

100K_0402_1%
1
PR92

PC60

A A

@
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 51 of 61
5 4 3 2 1
 A B C D

B+ PL6
HCB4532KF-800T90_1812
1 1

2 1+VTTP_B+
+5VS
0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
VTTPW ROK 5,47

3.4K_0402_1%
1

1
PC189

PR93
5 VTTPW ROK_CPU
2

1 PR272 PR94 2.2_0603_1%

PC61

PC62

PC63
PC186

2
2

2
1 2 1 2

2
0_0402_5%

BST_+VTTP
PR95 PC64

DH_+VTTP
LX_+VTTP
1 2 1 2 0.1U_0603_25V7K
+5VALW
PR273 2.43K_0402_1% 4.53K_0402_1%

DH_+VTTP

5
PR96
0_0402_5% PR97 PQ28

16

15
8

1
PU7 4.7_0603_5% Ipeak=27.97A
1 2 TPCA8030-H_SOP-ADV8-5

UG
GND

PGOOD

PHASE

BOOT
+VTTP_VCC

2
Imax=19.58A
4 F=231KHz
3 VIN PVCC 14 1 2 PC65
2.2U_0603_6.3V6K Total Capacitor 1430uF,
+VTTP_VCC ESR 3.15mohm

3
2
1
4 13 DL_+VTTP PL7
VCC LG 1.0UH_PCMC104T-1R0MN_20A_20%
+1.05V
1

PC66 1 2
2

2.2U_0603_6.3V6K
+VTTP 2

APW 7138NITRL_SSOP16
12
2

PGND

4.7_1206_5%

390U_2.5V_M
1

1
TPCA8028-H_SOP-ADVANCE8-5
+

PQ29

PR99

PC67
1 2 5 11 SE_+VTTP 1 2
44 VTTP_EN EN ISEN PR98
PR100 2

FSET
6.98K_0402_1%
0_0402_5%

2
VO
NC
4

FB

680P_0603_50V8J
.1U_0402_16V7K

1
6

10
1

PC69
3
2
1

2
+VTTP
PC68

FB_+VTTP
2

@ Material Note:
33.2K_0402_1%

0.01U_0402_16V7K
1

1
330uF/ 6mohm, number are 3,
1
PR101

57.6K_0402_1%

power x1, HW x2
PR102

@ PC70
2
1

@
2

2
2200P_0603_50V7K

@ PC71
33P_0402_50V8J
2

1
PC72
2

3 @ 3

1 2 1 2+VTTP
PR103 PR104
3.32K_0402_1% 0_0402_5%
1

PR106 1 2
4.42K_0402_1% PR108 VTT_SENSE 8 PJ20
10_0402_5% +VTTP +1.05VS
2 1 Arrandale -- mount,
2

2 1
1
PR110
2
VSS_SENSE_VTT 8
@ JUMP_43X79 Clarksfield --non mount @
(7.0A,280mils ,Via NO.=14)
10_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VTTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 52 of 61
A B C D
 A B C D

1 1

PL9

4
PJ25 PU9 2.2UH_FMJ-0630T-2R2 HF_8A_20%
2 1 10 2 LX_SY8033B 1 2

PG
+5VALW 2 1 PVIN LX +1.8VSP

1
@ JUMP_43X79 9 3
PC85 PVIN LX PR126
22U_0805_6.3V6M 4.7_1206_5%

22U_0805_6.3V6M

22U_0805_6.3V6M
8

2
SVIN

1
6 FB_SY8033B @ PC86

1 2
FB

1
PC88

PC89
1 2 EN_SY8033B 5 PR124 22P_0402_50V8J
39,44,47,50,58 SUSP# EN

NC

NC
PC90 51.1K_0402_1%

TP

2
PR122 680P_0603_50V8J

2
1
0_0402_5%

11

2
1
PR125 @ PC83 SY8033BDBC_DFN10_3X3
499K_0402_1% .1U_0402_16V7K

2
2

1
PR123
25.5K_0402_1%

2
2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 53 of 61
A B C D
 5 4 3 2 1

PJ22
1.5V_B+ 2 1 B+
2 1
@ JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC91

PC92

PC187
D D

TPCA8030-H_SOP-ADV8-5
5

2
PQ34
PR127
255K_0402_1% 4
1 2
PR128
0_0402_5%
1 2 BST_1.5V 1 2
39,44 SYSON

3
2
1
PR129

1
2.2_0603_1% PC94 PL10

15

14
1
@PC93
@ PC93 PU10 0.1U_0603_25V7K 1.0UH_PCMC104T-1R0MN_20A_20%
.1U_0402_16V7K 1 2 1 2

EN/DEM

NC

BOOT
+1.5VP

2
2 13 DH_1.5V

4.7_1206_5%
TON UGATE

1
TPCA8028-H_SOP-ADVANCE8-5
PR131 LX_1.5V
Ipeak=20.15A

PR130
3 12 1

220U_D2_4VY_R15M
VOUT PHASE Imax=14.11A

5
100_0603_1%
+

PQ35
+5VALW

PC95
+5VALW 1 2 4 VDD CS 11 1 2 F=313KHz
PR132

2
5 FB VDDP 10 7.5K_0402_1% Total Capacitor 1210uF,
2
ESR 3.3mohm
1

1
6 9 DL_1.5V 4

680P_0603_50V8J
PGOOD LGATE

PGND
PC96

PC97
GND
4.7U_0603_6.3V6K
2

2
1
C C
RT8209BGQW _W QFN14_3P5X3P5 PC98

3
2
1
4.7U_0805_10V6K

2
PR133
10K_0402_1%
1 2
10K_0402_1%
1
PR134

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/10/21 Title
2009/11/13 Deciphered Date
+1.5VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 54 of 61
5 4 3 2 1
 A B C D

1 1

+1.5V

1
PJ23

1
@ JUMP_43X79

2 2
PU11
1 VIN VCNTL 6 +5VALW

4.7U_0805_6.3V6K
2 GND NC 5

1
3 VREF NC 7

1
PC100

1K_0402_1%
PR135
@ PR136 4 8 PC99

2
0_0402_5% VOUT NC 1U_0603_10V6K

2
1 2 9
9,47 SUSP

2
TP
G2992F1U_SO8

PR137

0.1U_0402_10V7K
D +0.75VSP

1
0_0402_5%

1K_0402_1%
SSM3K7002FU_SC70-3
PQ36

PR138

PC102
1 2 2
47 0.75VR_EN# G

1
2 S 2

3
1
PC103

2
PC101 10U_0805_6.3V6M

2
.1U_0402_16V7K

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.75VSP/
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B 1.0
Date: Monday, March 22, 2010 Sheet 55 of 61
A B C D
 8 7 6 5 4 3 2 1

CPU_VID0 2 1 PR142 1K_0402_1% CPU_VID0 2 1 @ PR143 1K_0402_1% +CPU_B+

VR_ON 1 2 PL11
PC195 1000P_0402_50V7K CPU_VID1 2 1 PR144 1K_0402_1% CPU_VID1 2 1 @ PR145 1K_0402_1% HCB4532KF-800T90_1812
1 2 B+
CPU_VID2 2 1 PR146 1K_0402_1% CPU_VID2 2 1 @ PR147 1K_0402_1%

PR150 0_0402_5% reserve to avoid noise CPU_VID3 2 1@ PR148 1K_0402_1% CPU_VID3 2 1 PR149 1K_0402_1%

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
470P_0603_50V8J

0.1U_0603_25V7K
1 2

220U_25V_M
H 8 CPU_VID0 1 1 H
PR153 0_0402_5% CPU_VID4 2 1@ PR151 1K_0402_1% CPU_VID4 2 1 PR152 1K_0402_1%

100U_25V_M
1

1
+ +

PC198

PC112

PC116

PC113

PC114

PC111

PC115
8 CPU_VID1 1 2
PR156 0_0402_5% CPU_VID5 1 PR154 1K_0402_1% CPU_VID5 1 @ PR155 1K_0402_1%

PC110
2 2
8 CPU_VID2 1 2

2
5
PR159 0_0402_5% CPU_VID6 2 1@ PR157 1K_0402_1% CPU_VID6 2 1 PR158 1K_0402_1% 2 @ 2
1 2 PQ37
8 CPU_VID3
PR162 0_0402_5% H_DPRSLPVR 2 1 PR160 1K_0402_1% H_DPRSLPVR 2 1 @ PR161 1K_0402_1%
1 2 TPCA8030-H_SOP-ADV8-5
8 CPU_VID4
PR164 0_0402_5% H_PSI# 2 1 PR163 1K_0402_1%
8 CPU_VID5 1 2 4
PR165 0_0402_5%
1 2 +VTT
8 CPU_VID6
PC117

3
2
1
PR166 2.2_0603_1% 0.22U_0603_25V7K
PR167 0_0402_5% BOOT2 1 2 BOOT2_2 1 2
1 2 PL12
44 VR_ON
UGATE2 0.36UH_PCMC104T-R36MN1R17_30A_20%
G PR168 0_0402_5% G
1 2 PHASE2 4 1 +CPU_CORE
8 H_DPRSLPVR
3 2 V2N
25 CLK_ENABLE#

5
PQ38

PR169
4.7_1206_5%

10K_0402_5%
1

1
TPCA8028-H_SOP-ADVANCE8-5
PQ39

3.65K_0805_1%
+3VS PR172 TPCA8028-H_SOP-ADVANCE8-5 PR171
1.91K_0402_1% @ 1_0402_5%

PR170

PR173
1 2 CLK_ENABLE# @ PR175
LGATE2 4 4 0_0402_5%

2
2

1 2 V1N
PR174
1.91K_0402_1%
PR177 VSUM+

3
2
1

3
2
1

1
0_0402_5%

680P_0603_50V8J
30,44 VGATE
1

VSUM-

PC118
1 2

2
@ PR178 1K_0402_1%
F
1 2 ISEN2 F
+VTT
PR179 0_0402_5%
8 H_PSI# 1 2
PR180
1 2 ISL62883HRZ-T_QFN40_5X5~D
147K_0402_1%
PC119 +5VALW
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

PU13 1 2
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

2
30 PR183
BOOT2
29 0_0402_5%
UGATE2
1 28
PGOOD PHASE2
2 27

1
PSI# VSSP2
3 26
RBIAS LGATE2
4 25
VR_TT# VCCP
E 5 24 E
NTC PWM3
6 23
VW LGATE1
7 22
COMP VSSP1
8 21
FB PHASE1
9
ISEN3
UGATE1

1 2 10 PR186 0_0402_5%
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN

IMON

1 2
249K_0402_1%

8.06K_0402_1%

1U_0603_10V6K
VDD
1000P_0402_50V7K

RTN

VIN

PC126 41
AGND
1

22P_0402_50V8J
PC127

PC128
PR189

PR188

11
12
13
14
15
16
17
18
19
20

PR194
2

562_0402_1% PC130
@ 1 2 1 2
2

390P_0402_50V7K
PR196 PR195 0_0402_5%
2.55K_0402_1% 1 2
1 2 1 2 8 IMVP_IMON
PC131 PR198 0_0402_5%
D 10P_0402_50V8J 1 2 +CPU_B+ D
0.22U_0603_25V7K

1 2 1 2
PR201 1_0402_5%
PC132 PR199 1 2 +5VALW +CPU_B+
150P_0402_50V8J 412K_0402_1% ISEN2 1 2
1

1
PC133

PC134

PC135
1U_0603_10V6K

0.22U_0603_25V7K

PR202 0_0402_5%
PC137 0.22U_0402_6.3V6K

PC138 0.22U_0402_6.3V6K

ISEN1 1 2 PR204
2

9.09K_0402_1%
BOOT1

470P_0603_50V8J
5
Layout Note: PR203 0_0402_5%

10U_1206_25V6M

10U_1206_25V6M
2

PQ43
PH3 place near
1

1
VSSSENSE

PC139
Phase1 L-MOS TPCA8030-H_SOP-ADV8-5

PC140

PC141
2

2
VSUM+ UGATE1 4

+CPU_CORE 1 2
PC143
1

C @ PR205 10_0402_5% PR207 2.2_0603_1% 0.22U_0603_25V7K C

3
2
1
0.047U_0402_16V7K

1
VSUM-

1 2 BOOT1_1 1 2
2.61K_0402_1%
0.22U_0603_10V7K

PL14
PR208

PR206 0.36UH_PCMC104T-R36MN1R17_30A_20%
1

82.5_0402_1%
PC144

PC145

8 VCCSENSE 1 2
2

PHASE1 4 1 +CPU_CORE
2

PR209 0_0402_5%
2

2
1

3 2 V1N
1

5
TPCA8028-H_SOP-ADVANCE8-5
PC146
10K_0402_1%_ERTJ0EG103FA

TPCA8028-H_SOP-ADVANCE8-5
PQ44

@ PQ45
330P_0402_50V7K

4.7_1206_5%
2

1
PC147

PR210

10K_0402_5%
3.65K_0805_1%
2

1
0.01U_0402_25V7K PR213
1_0402_5%
LGATE1

PR212
4 4
330P_0402_50V7K

@ PR216

PR211
11K_0402_1%

2
1

PC148 0_0402_5%
PH4
PC149

PR215

2
1000P_0402_50V7K 1 2 1 2 V2N
PR217 0_0402_5%
2

3
2
1

3
2
1

1
1 2 PR214 VSUM-

680P_0603_50V8J
8 VSSSENSE
2

B 1.2K_0402_1% B

PC150
2
@ PR219 10_0402_5%
1 2 1 2 1 2 VSUM- VSUM+
@ PC185 @ PR274 ISEN1
Layout Note:
1200P_0402_50V7K 100_0402_1%
Place near Phase1 Choke
.1U_0402_16V7K
1

PC151
2

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 56 of 61
8 7 6 5 4 3 2 1
 A B C D E F G H

1 1

9
GFXVR_VID_0

GFXVR_VID_1

GFXVR_VID_2

GFXVR_VID_3

GFXVR_VID_4

GFXVR_VID_5

GFXVR_VID_6
9
GFXVR_EN
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
+5VS

+GFX_B+ PL15
HCB4532KF-800T90_1812

2
+1.05VS

PR221

PR222

PR223

PR224

PR225

PR226

PR227

PR231
2 1 B+
1

PR228
@ PR229 10_0603_1%
300K_0402_5%

10U_1206_25V6M

10U_1206_25V6M
1

1
PC152

PC153
GFX_EN
2

2
9 GFXVR_IMON GFX_IMON

5
GFX_VCC
+3VS PC154
1

TPCA8030-H_SOP-ADV8-5
1U_0805_25V6K

PQ46
32

31

30

29

28

27

26

25

2
0.056U_0402_16V7K
1

PR232
PC155

6.98K_0402_1%

VID0

VID1

VID2

VID3

VID4

VID5

VID6
EN
1
2

24 PR234 PC157 4
2

PR233 VCC 0_0603_5% 0.22U_0603_25V7K

1
10K_0402_1% PWRGD
23 GFX_BOOST 1 2GFX_BOOST-1
1 2
BST
1

GFX_IMON 2
2

PC156 IMON GFX_DRVH PL16

22

3
2
1
1000P_0402_50V7K DRVH 0.36UH_PCMC104T-R36MN1R105_30A_20%
2 3 2
2

VSS_AXG_SENSE CLKEN# GFX_SW

21 1 2
4
SW +GFX_COREP
FBRTN ADP3211AMNR2G_QFN32_5X5 20 +5VS
PVCC

1
TPCA8028-H_SOP-ADVANCE8-5
GFX_FB

PQ47
1 2 5
FB PU15 GFX_DRVL
19 2 1 Ipeak=22A

330U_2.5V_M
DRVL 1
PC158 PC160 1 GFX_COMP 6
COMP
@ PR235
220P_0402_50V7K 47P_0402_50V8J PC159 4.7_1206_5% + Imax=15.4A

PC161
18
GFX_VCC 7 PGND 2.2U_0603_10V6K F=350KHz
2

12
GPU
1 2 1 2GFX_COMP-1
1 2 17 4
GFX_ILIM 8 AGND @ PC163 2 Total Capacitor 660uF,

CSCOMP
PR236 PC162 PR237 ILIM 680P_0603_50V7K
33 ESR5.88mohm

CSREF

2
AGND

RAMP

LLINE

CSFB
1K_0402_1% 470P_0402_50V8J 20K_0402_1%

IREF

RPM

RT

3
2
1
9

10

11

12

13

14

15

16
2

PR238
10.7K_0402_1%
GFX_IREF

GFX_RAMP

GFX_CSCOMP

GFX_CSFB

GFX_CSCOMP
GFX_RT
2 GFX_RPM
PH5
GFX_CSCOMP 1

220K_0402_5%_ERTJ0EV224J~D

1 2
80.6K_0402_1%

237K_0402_1%

340K_0402_1%
2

Avoid high dV/dt

PR239

Place RTH1 close to inductor

PR240

PR241

PR242
71.5K_0402_1% on the same layer
1

2 1
422K_0402_1%
1

1
2

PR245

1
PR243 PR244

1
0_0402_5% 0_0402_5% PC165
560P_0402_50V7K PR246
2

PC164 165K_0402_1%
1

2
1000P_0402_50V7K

2
PR248 2 1
1K_0402_1%
3 3
+GFX_B+ 2 1 GFX_RAMP-1 PR247
47.5K_0603_1%
9

Connect to input caps

VSS_AXG_SENSE

VCC_AXG_SENSE

PC166 PC167
1000P_0402_50V7K 1000P_0402_50V7K
2

Shortest the
Switchable -- mount
net trace Non Swithchable--non mount @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+GFX_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 57 of 61
A B C D E F G H
 5 4 3 2 1

B+ 1 2 B+_core
6268_VCC
PL17 LX_VCORE

1
HCB4532KF-800T90_1812 PR249
1K_0402_1%

10U_1206_25VAK

4.7U_0805_25V6-K
DH_VCORE

10U_1206_25VAK

1
PR250 2.2_0603_1%

PC170
PC168

PC169
2 1 1 2 1 2

2
BST_VCORE

2
28,32,47 VGA_PW ROK PR270 PC171
0_0402_5% 0.1U_0603_25V7K

D 2 1 D
+5VALW
PR275

1
3K_0402_1%

TPCA8030-H_SOP-ADV8-5
5
PR251
0_0603_5%

PQ48
Ipeak=24.10A
26268_VCC

16

15
1

2
Imax=16.87A

1
PU16
PR252 4 F=213KHz

UG
GND

PGOOD

PHASE

BOOT
4.7_0603_5%
Total Capacitor 990uF,
3 VIN PVCC 14 1 2 PC172 ESR 5.7mohm

3
2
1
6268_VCC 2.2U_0603_6.3V6K
2.2U_0603_6.3V6K

PL18
PC173

4 13 DL_VCORE +VGA_COREP
VCC LG
1

0.56U_PCMC104T-R56MN_25A_20%
1 2
APW 7138NITRL_SSOP16
2

1
PGND 12

TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
PR254

330U_D2_2.5VY_R15M
@ 4.7_1206_5%

10U_1206_25VAK

10U_1206_25VAK
PR253 1

PQ50

PC174

1
1 2 5 11 ISEN_VCORE 1 2 +

1 2
EN ISEN

2
39,44,47,50,53 SUSP#

PQ49

PC176

PC177
4 4

FSET
0_0402_5% PR255

0_0402_5%
680P_0603_50V8J

2
1

7.15K_0402_1% @ 2

VO
NC

PC175

PR256
FB
.1U_0402_16V7K

@
PC178

2
C C
2

10

3
2
1

3
2
1

1
PR271
1 2
13,33,47 DGPU_PW R_EN PR257
10K_0402_5% 10_0402_5%
1 2

57.6K_0402_1%
1

VDD_SENSE 14

1
1

1
PC179 @ PR258

2
22P_0402_50V8J
@ 49.9K_0402_1% @PC180
@ PC180

PR259
0.01U_0402_25V7K

1000P_0402_50V7K
2

2
PR260

2
4.75K_0402_1%
1

1
@ PC182
1
@ PC181
2200P_0402_25V7K
2

2
+3VS_DGPU
FSW=1/(75E-12*57.6K)=231.48KHz

2
PR261

1
56.2K_0402_1%

29.4K_0402_1%
2
N11P N11M

1
PR262
PR264

PR263

1
Imax=16.87A Imax=12.73A 14K_0402_1% 10K_0402_1%

2
B B

SSM3K7002FU_SC70-3
Ipeak=24.10A Ipeak=18.19A

1
PR265

2
D

1
Iocp=28.65A Iocp=20.48A 0_0402_5%

PQ51
2 1 2
G GPU_VID0 13
PR255=7.15K PR255=5.36K S

3
PQ49=unpop PQ49=unpop

22K_0402_1%
.1U_0402_16V7K
PC183

@ PR266
+3VS_DGPU

1
1
VFB(0.6)=Vout*Rbottom/(Rtop+Rbottom) PR267
10K_0402_1%

SSM3K7002FU_SC70-3
PR268

2
D

1
GPU_VID0 GPU_VID1 N11M-OP1 N11P 0_0402_5%

PQ52
2 1 2
G GPU_VID1 13
0 0 0.80V S

22K_0402_1%
.1U_0402_16V7K
PC184

@ PR269
1 0 0.85V 0.85V

2
0 1

1
A A

1 1 1.03V

PR260= 4.75K PR260= 4.75K

PR262 =14K PR262 =14K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/10/21 Title
PR261 =56.2K PR261 =56.2K 2009/11/13 Deciphered Date
+VGA_COREP
PR263=16.2K PR263=29.4K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 58 of 61
5 4 3 2 1
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------
2009/12/06 P48-59 Release
2009/12/18 P49 PR31,PR33,PR34,PR40 PH1,PH2 setting point change
2009/12/18 P52 PR98 VTT adjust OCP
2009/12/18 P55 Remove PR136,Add PR137,PC101 0.75VSP Enable signal (EVT added by memo)
2009/12/18 P58 Add PR254,PC175 VGA add snubber (EVT added by memo)
2009/12/18 P58 PC174 VGA output cap change to lower
2009/12/28 P51,P52 Add PC188,PC189,PC115 Add EMC,EMI solution.
2009/12/28 P51 change PR83,PR84,Add PR85,PC55 For EMI,EMC solution
2010/01/06 P51 PR81,PR132,PR255 OCP setting.
2010/01/06 P58 change PR249,PR271,PC178 HW request
2010/02/05 P53 change PU9 solution change 1.8V Solution
2010/02/05 P51 change PL4,PL5 Change to lower height to solve ME request
2010/01/28 P43 PC197 Reserve 10uF at B+ shape for ripple improvement.
2010/02/08 P50 Add PD6,PD7 ESD solution.
2010/02/08 P57 Change PR247 GFX load-line
2010/02/08 P50 Add PC192,PC193,PC194 ISN issue
2010/03/16 P50 Change PR45,PR68 CP setting
2010/03/16 P50 Change PL3 ME issue
2010/03/16 P51 Change PC53,PC54 ME issue
2010/03/16 P53 PR122,PC83 unmount 1.8V enable signal adjust
2010/03/16 P56 Add PC195 VR_ON prevent noise,same as UMA
2010/03/16 P58 Change PC174 ME issue
2010/03/16 P58 Change PR264,PR265,PR267,PR268,PR263,PC184,PQ52 GPU voltage adjust
2010/03/18 P57 Add PC198 High frequency noise
2010/03/22 P58 Add PR275 Adjust VGA POK voltage level for HW request

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/10/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBQAA LA6072P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 22, 2010 Sheet 59 of 61
 5 4 3 2 1

PIR (Product Improve Record)

NBQAA LA-6072P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2

NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------------------------------------
D 1. 12/22 25 Change JLVDS routing To prevent workmanship and burn issue D

2. 12/22 09 Change Q33 routing For common design

3. 12/22 47 Change Q43 routing For common design
4. 12/22 39 Change JEXP footprint to SANTA_130861-2_26P_RT-T Modify footprint
5. 12/22 38 Change JTPL footprint to P-TWO_161021-06021_6P-T For ME's request
6. 12/22 43 Change JKBL footprint to ACES_85201-04051_4P-T For ME's request
7. 12/22 13 Delete DV2, Add RV124, QV2 for CLKREQ_VGA# CLKREQ_VGA# circuit for NV's Optimus
8. 12/23 38 Change JCS footprint to P-TWO_161021-10021_10P-T For ME's request
9. 12/23 38 Change JTOUCH footprint to P-TWO_161021-10021_10P-T For ME's request
10. 12/23 33 Change PCH's GPIO57 netname to OPTIMUS_EN# and pull down to GND For BIOS recognizing Optimus
11. 12/23 33 Change PCH's GPIO45 netname to LVDS_SEL For Common design
12. 12/23 33 Change PCH's GPIO39 netname to CIR_EN# For Common design
13. 12/24 39 Add DM2, QM1, BT_CTRL on JWLAN.5 For WLAN/BT combo module
14. 12/24 42 Add RA43 on EC_MUTE# For Audio issue
15. 12/24 43 Detele JEXMIC.5 from GND For Audio issue
16. 12/24 44 Change PWRME_CTRL to PWRME_CTRL# Active low signal
C 17. 12/24 33 Delete GND guide pins of JTOUCH, JCS, JTPL, JODD1 For common design C

18. 12/29 29 Add C254 on CLKREQ_WLAN# For EMI's Request

19. 12/29 43 Exchange JKBL pin1 and pin4 To meet correct footprint
20. 12/29 37 Add C389 on U14 For EMI's Request
21. 12/29 46 Add C392 on H21 for +5VALW For EMI's Request
22. 12/29 40 Stuff CL7, CL23, CL24 For EMI's Request
23. 12/29 46 Add C393, close to C7 for +3VS For EMI's Request
24. 12/29 32 Add R55 on DGPU_RST# For common design
25. 12/29 27 Add R314 on HDMI_HPD and U9 To prevent ESD damage to U9
26. 01/03 47 change +1.05VS_DGPU routing To turn on/off normally

REVISION CHANGE: 0.2 TO 0.3

NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------------------------------------
1. 02/01 31 Change RA40 to pull up +5VL Support S/M function in battery mode
2. 02/01 30 Change RA34 to pull up +3VL Support S/M function in battery mode
B B

3. 02/01 44 Add R103 to USB_EN# and pull up +5VALW For common code with NWQAA
4. 02/01 44 Add R69 to VR_ON and pull low to GND To avoid folating when EC is on initial
5. 02/01 30 Add C434 to VGATE Reserve to avoid noise
6. 02/01 05 Add C482 to H_PWRGOOD Reserve to avoid noise
7. 02/01 40 Add UL4 for 10/100/1000 transformer co-layout
8. 02/01 38 Add MDC circuits For A51's request, Add MDC in DIS SKU
9. 02/01 35 Reserve U54 for +1.5VALW LDO and change VCCSUSHDA power rail For MDC design change
10. 02/01 28 Add R287, R289, R291, R293 for Azalia bus to MDC For MDC design change
11. 02/02 46 Add H31, H32 For MDC design change
12. 02/02 44 Add CAP_RST# on EC pin73 and link to JCS For Cap sensor design change
13. 02/04 31 Stuff R133, R135 to 100Kohm PD GND To prevent PCH pending internal HPD
14. 02/04 14 Reserve UV4,RV54,CV56,RV44 Reserved for VBIOS
15. 02/04 42 Add RA45, un-stuff RA43 To solve audio issue
16. 02/06 32 Exchange USB port 4&8 Design change, for A51's request
17. 02/08 08 Change C117,C118,C119,C120,C127,C128,C129 To improve ESD
A 18. 02/08 40 Change LL1, CL13 For design change A

19. 02/09 41 Change RC7, RC8, RC9, RC12, RC13, RC14 from 0 ohm to 22 ohm For EMI's request

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR-1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Monday, March 22, 2010 Sheet 60 of 61
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

NBQAA LA-6072P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.3 TO 1.0

NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------------------------------------
D 1. 03/11 27 Add R148 To solve display compatibility issue D

3. 03/11 15 Change CV58 from OSCON to POLY type Due to the keyboard stress test is fail
4. 03/11 09 Change C216 from OSCON to POLY type Due to the keyboard stress test is fail
5. 03/11 11 Change C163 from OSCON to POLY type Due to the keyboard stress test is fail
6. 03/11 14 Delete UV4,RV54,CV56,RV44 Design change, no need extra BIOS ROM
7. 03/11 25 Stuff D84,D82,D19,D83 For ESD's request
8. 03/11 34 Change L12 from bead to R389 2.2 ohm+- 1% For CRT issue
9. 03/14 13 Reserve YV1,RV29,CV45,CV46 Reserved for design change
10. 03/14 33 Change R221 to 1K ohm For NV's Optimus sequence
11. 03/14 32 Change R55 to 1K ohm For NV's Optimus sequence
12. 03/14 32 Reserve R334, add R336 For NV's Optimus sequence
13. 03/14 39 Change QM1 to Q14B For cost down
14. 03/15 42 Un-mount CA16 For audio noise issue
15. 03/15 46 Un-mound SW2,SW3 Power button is no need after pre-MP
16. 03/16 42 Change CA12.1, RA12.2, CA18.2 from GND to AGND For audio noise issue
17. 03/16 42 Change CA9 and CA10 to from 4700pF tp 1uF For audio noise issue
C 18. 03/16 42 Add CA34~CA40 and CA51 For audio noise issue C

19. 03/18 41 Change Card reader solution from O2 to JMB389C/385C For design change
20. 03/19 27 Add D54 For HDMI CEC
21. 03/19 34 Add L12 that reserved 0 ohm for EMI For CRT issue
22. 03/19 46 H22 from 6.0 to 3.0 For ME's request
23. 03/20 20 Change BIOS ROM footprint to M25P80-VMW6TP_SO8 No need the debug connector in MP phase
24. 03/22 13 Stuff RV28, un-stuff RV105 Reserved for 27M_SSC from clock gen
25. 03/22 43 Add RA22,RA23 Reserved to solve GPRS noise
26. 03/22 05 Stuff C482 To avoid noise
27. 03/22 30 Stuff C434 To avoid noise

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR-1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBQAA LA6072P M/B
Date: Tuesday, March 23, 2010 Sheet 61 of 61
5 4 3 2 1
www.s-manuals.com