EEL525

Processor Applications in
Power Electronics
TMS320f28335
ePWM
Siba Kumar Patro
ePWM
• What is PWM and its use?
• ePWM: Enhanced PWM. These are of two types: standard 16 bit mode
and 24-bit high resolution PWM mode (HRPWM)

ePWm can generate two PWMs (EPWMxA and EPWMxB, x=1, 2, …6)
related to each other or independent from each other. It can be single
ended signal or a pair of output signals.
ePWM Block Diagram
CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
TBCLK Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0 EPWMxB
PCCTL . 10 - 0
TZy
TZSEL . 15 - 0
ePWM
1. Register TBPRD defines the length of a period of an output signal, in
multiples of the time-period of the input signal.
2. Another unique feature of the F2833x is its “shadow” functionality of
operating registers, in the case of ePWM units available for compare
register A, B and period register.
3. For some applications it is necessary to modify the values inside a compare
or period register, every period. The advantage of the background registers
is that we can prepare the values for the next period in the current one.
Without a background function we would have to wait for the end of the
current period, and then trigger a high prioritized interrupt. Sometimes this
form of scheduling will miss its deadline…
ePWM Phase Synchronisation
1. Two hardware signals "SYNCI" (synch in) and "SYNCO" (synch out) can
be used to synchronize ePWM units to each other.
2. For example, we could define one ePWM unit as a "master" to generate an
output signal "SYNCO" each time the counter equals period.
3. Two more ePWM units could be initialized to recognize this signal as
"SYNCI" and start immediately counting, each time they receive this
signal.
4. In such way we have established a synchronous set of 3 ePWM channels.
But we can do even better. By using another register called "TBPHS" we
can introduce a phase shift between master, slave 1 and slave 2, an
absolute necessity for three-phase control systems.

5
ePWM Phase Synchronization
Ext. SyncIn
(optional)

Phase
=0°
En
o o 
SyncIn
EPWM1A
o
CTR=zero o
CTR=CMPB o o EPWM1B
X o
SyncOut
To eCAP1
SyncIn
Phase
=120°
En
o o 
SyncIn
EPWM2A =120°
o
CTR=zero o
CTR=CMPB o o EPWM2B
X o
SyncOut

Phase
=240°
En
o o 
SyncIn
EPWM3A
=120°

o
CTR=zero o
CTR=CMPB o o EPWM3B
X o
SyncOut =240°
1. Register TBCNT of ePWM2 and ePWM3 are preloaded with
a start value that corresponds to 120° and 240° respectively.
2. In this example ePWM1 has been initialized as master to
generate SYNCO each time the counter register equals zero.
3. With the enabled phase input feature for ePWM2 and ePWM3
the two channels operate as slave 1 and slave 2 and will load
their counter registers TBCNT with numbers stored in the
corresponding phase registers TBPHS.
Example:
• ePWM1 counts from 0 to 6000. TBPRD = 6000
• ePWM2 register TBPHS = 2000
• ePWM3 register TBPHS = 4000
ePWM Time-Base Count Modes
TBCTR

TBPRD
Asymmetrical
Waveform

Count Up Mode
TBCTR

TBPRD
Asymmetrical
Waveform

Count Down Mode

TBCTR

TBPRD

Symmetrical
Waveform

Count Up and Down Mode

ePWM Time-Base Module Registers
Name Description Structure
TBCTL Time-Base Control EPwmxRegs.TBCTL.all =
TBSTS Time-Base Status EPwmxRegs.TBSTS.all =
TBPHS Time-Base Phase EPwmxRegs.TBPHS =
TBCTR Time-Base Counter EPwmxRegs.TBCTR =
TBPRD Time-Base Period EPwmxRegs.TBPRD =

TBCTL :
EPwm1Regs.TBCTL.all = 0x1234;
A bit field access to fields "CLKDIV" only would look like:
EPwm1Regs.TBCTL.bit.CLKDIV = 7;
ePWM Register TBCTL
Lower Register:
Counter Mode
00 = count up
Software Force Sync Pulse 01 = count down
0 = no action 10 = count up and down
1 = force one-time sync 11 = stop – freeze (default)

6 5-4 3 2 1-0
SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE

Sync Output Select Period Shadow Load Phase Reg. Enable

(source of EPWMxSYNC0 signal) 0 = load on CTR = 0 0 = disable
00 = EPWMxSYNCI 1 = load immediately 1 = CTR = TBPHS on
01 = CTR = 0 EPWMxSYNCI signal
10 = CTR = CMPB
11 = disable SyncOut
ePWM Register TBCTL
PHSDIR:
• specifies if this ePWM unit starts counting up or down after a SYNCIN pulse has
Upper Register: been seen.
• In case of a single ePWM setup with a disabled sync in feature, this bit is a "don't
care"
Phase Direction
0 = count down after sync
1 = count up after sync TBCLK = SYSCLKOUT / (HSPCLKDIV * CLKDIV)

15 - 14 13 12 - 10 9-7
FREE_SOFT PHSDIR CLKDIV HSPCLKDIV

Emulation Halt Behavior TB Clock Prescale High Speed TB A clock prescaler

00 = stop after next CTR inc/dec 000 = /1 (default) Clock Prescale (register TBCTL, bits 12
01 = stop when: 001 = /2 000 = /1
Up Mode; CTR = PRD 010 = /4 001 = /2 (default) to 7) can be used to
Down Mode; CTR = 0 011 = /8 010 = /4 reduce the input counting
Up/Down Mode; CTR = 0 100 = /16 011 = /6 frequency by a selectable
1x = free run (do not stop) 101 = /32 100 = /8
110 = /64 101 = /10 factor between 1 and
111 = /128 110 = /12 1792.
111 = /14
ePWM Register TBSTS

Counter Max Latched Counter Direction

0 = max value not reached 0 = CTR counting down
1 = CTR = 0xFFFF (write 1 to clear) 1 = CTR counting up

15 - 3 2 1 0
reserved CTRMAX SYNCI CTRDIR

External Input Sync Latched

0 = no sync event occurred
1 = sync has occurred (write 1 to clear)
Generate a 1 KHz Signal at ePWM1A
Objective:
• Generate a 1 KHz square wave signal at ePWM1A with a
duty cycle of 50 %
• Measure it with an oscilloscope or
• Connect the signal to an external buzzer or loudspeaker

• Registers involved:
• TBPRD: define signal frequency
• TBCTL: setup operating mode and time prescale
• AQCTLA: define signal shape for ePWM1A

1 TPWM
TBPRD  
2 TSYSCLKOUT  CLKDIV  HSPCLKDIV
 GPIO - A Multiplex Register GPAMUX1
GPAMUX1 - Bits 00 01 10 11
1,0 GPIO0 EPWM1A - -
3,2 GPIO1 EPWM1B ECAP6 MFSRB
5,4 GPIO2 EPWM2A - -
7,6 GPIO3 EPWM2B ECAP5 MCLKRB
9,8 GPIO4 EPWM3A - -
11,10 GPIO5 EPWM3B MFSRA ECAP1
13,12 GPIO6 EPWM4A EPWMSYNCI EPWMSYNC0
15,14 GPIO7 EPWM4B MCLKRA ECAP2
17,16 GPIO8 EPWM5A CANTXB /ADCSOCA0
19,18 GPIO9 EPWM5B SCITXDB ECAP3
21,20 GPIO10 EPWM6A CANRXB /ADCSOCB0
23,22 GPIO11 EPWM6B SCIRXDB ECAP4
25,24 GPIO12 /TZ1 CANTXB SPISIMOB
27,26 GPIO13 /TZ2 CANRXB SPISOMIB
29,28 GPIO14 /TZ3_/XHOLD SCITXDB SPICLKB
31,30 GPIO15 /TZ4_/XHOLDA SCIRXDB /SPISTEB

GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // ePWM1A active or GpioCtrlRegs.GPAMUX1.all = 0x00000001;

Generate a 1 KHz Signal at ePWM1A
Objective:
• Generate a 1 KHz square wave signal at ePWM1A with a
duty cycle of 50 %
• Measure it with an oscilloscope or
• Connect the signal to an external buzzer or loudspeaker

• Registers involved:
• TBPRD: define signal frequency
• TBCTL: setup operating mode and time prescale
• AQCTLA: define signal shape for ePWM1A

1 TPWM 1 103
TBPRD    
2 TSYSCLKOUT  CLKDIV  HSPCLKDIV 2 150  106 1  1  2
up down
mod e
Action Qualifier Control Register
EPwmxRegs.AQCTLy (y = A or B)

Action when Action when

CTR = CMPB CTR = CMPA Action when
on UP Count on UP Count CTR = 0

15 - 12 11 - 10 9-8 7-6 5-4 3-2 1-0

reserved CBD CBU CAD CAU PRD ZRO

Action when Action when Action when

CTR = CMPB CTR = CMPA CTR = PRD
on DOWN Count on DOWN Count

00 = do nothing (action disabled)

01 = clear (low)
10 = set (high)
11 = toggle (low  high; high  low)
Things to observe:- 1 KHz square wave signal at ePWM1A (GPIO 00) with a duty cycle of 50 %
1) State 1 corresponds to 3.3 V
17
Objective-2:
Generate a 3 identical 1 kHz - signals with zero
phase-shift between the 3 ePWM lines and with 50%
duty ratio
• Registers involved:
• TBPRD: define signal frequency
• TBCTL: setup operating mode and time prescale
• AQCTLA: define signal shape for ePWM1A, 2A and 3A

1 TPWM
TBPRD  
2 TSYSCLKOUT  CLKDIV  HSPCLKDIV
Objective-3:
Generate a 3 phase system
• Generate three 1 KHz square wave signals at ePWM1A, 2A
and 3A with duty cycles of 50 % and a phase shift of 120°
and 240° between the signals
• Measure all three signals with an oscilloscope

• Registers involved:
• TBPRD: define signal frequency
• TBCTL: setup operating mode and time prescale
• AQCTLA: define signal shape for ePWM1A
• TBPHS: definition of the phase shift for 2A and 3A
1 TPWM
TBPRD  
2 TSYSCLKOUT  CLKDIV  HSPCLKDIV
Objective-3:
• define ePWM1A as the master phase to generate a SYNCOUT pulse each time its
counter register TBCNT equals zero.
• For ePWM2, enable a SYNCIN - pulse and also define SYNCIN as SYNCOUT to drive
it into ePWM3 unit.
• for ePWM2 and ePWM3, a phase shift of 1/3rd and 2/3rd of that value preloaded in
register TBPHS.
• Step 1
EPwm1Regs.TBCTL: Sync Out Select: generate a signal if CTR = 0

EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // generate a syncout if CTR = 0

ePWM Register TBCTL
Lower Register:
Counter Mode
00 = count up
Software Force Sync Pulse 01 = count down
0 = no action 10 = count up and down
1 = force one-time sync 11 = stop – freeze (default)

6 5-4 3 2 1-0
SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE

Sync Output Select Period Shadow Load Phase Reg. Enable

(source of EPWMxSYNC0 signal) 0 = load on CTR = 0 0 = disable
00 = EPWMxSYNCI 1 = load immediately 1 = CTR = TBPHS on
01 = CTR = 0 EPWMxSYNCI signal
10 = CTR = CMPB
11 = disable SyncOut
Objective-3:
• Step 1
EPwm1Regs.TBCTL: Sync Out Select: generate a signal if CTR = 0
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // generate a syncout if CTR = 0
• Step 2
EPwm2Regs.TBCTL:
• Set phase enable
• Sync Out Select: SYNCIN = SYNCOUT
EPwm2Regs.TBPHS:
• Load it with 1/3rd of TBPRD
• Since TBPHS is a union type, a valid access is made like this:

EPwm2Regs.TBCTL.bit.PHSEN = 1; // enable phase shift for ePWM2

EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; // syncin = syncout
EPwm2Regs.TBPHS.half.TBPHS = 12500; // 1/3 phase shift
Objective-3:
• Step 2
EPwm2Regs.TBCTL:
• Set phase enable
• Sync Out Select: SYNCIN = SYNCOUT

EPwm2Regs.TBCTL.bit.PHSEN = 1; // enable phase shift for ePWM2

EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; // syncin = syncout
EPwm2Regs.TBPHS.half.TBPHS = 12500; // 1/3 phase shift
Step 3
Epwm3Regs.TBCTL:
• Set phase enable
EPwm3Regs.TBPHS:
• Load TBPHS with 2/3 of TBPRD
rd

EPwm3Regs.TBCTL.bit.PHSEN = 1; // enable phase shift for ePWM3

EPwm3Regs.TBPHS.half.TBPHS = 25000; // 2/3 phase shift
Objective-3:
Generate a 3 phase system
• Generate three 1 KHz square wave signals at ePWM1A, 2A
and 3A with duty cycles of 50 % and a phase shift of 60°
and 120° between the signals
• Measure all three signals with an oscilloscope

• Registers involved:
• TBPRD: define signal frequency
• TBCTL: setup operating mode and time prescale
• AQCTLA: define signal shape for ePWM1A
• TBPHS: definition of the phase shift for 2A and 3A
1 TPWM
TBPRD  
2 TSYSCLKOUT  CLKDIV  HSPCLKDIV
What is Pulse Width Modulation?
• PWM is a scheme to represent a signal as a sequence of pulses

• fixed carrier frequency

• fixed pulse amplitude
• pulse width proportional to instantaneous signal amplitude
• PWM energy ≈ original signal energy/area over a sampling period

Solution:- modulation is based on another set of control registers of a unit called “Compare Module”.

t t
T
Original Signal PWM representation
 Why use PWM with Power Switching Devices?

• Desired output currents or voltages are known

• Power switching devices are transistors
• Difficult to control in proportional region
• Easy to control in saturated region

• PWM is a digital signal  easy for DSP to output

DC Supply DC Supply

? PWM
Desired PWM approx.
signal to of desired
system signal
Unknown Base Signal Base Signal known with PWM
ePWM Compare Module
CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
TBCLK Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCI
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0 EPWMxB
PCCTL . 10 - 0
TZy
TZSEL . 15 - 0
 ePWM Compare Event Waveforms
TBCTR  = compare events are fed to the Action Qualifier Module

Depending on the
TBPRD
CMPA
CMPB       Asymmetrical
Waveform
pre-selected
operating mode of the
ePWM unit, it is Count Up Mode
possible to define 2 TBCTR

  
or 4 events within a
period of the PWM - TBPRD
frequency, by CMPA Asymmetrical
choosing the CMPB Waveform
appropriate values in
CMPA and/or CMPB. Count Down Mode
TBCTR

TBPRD
CMPA
CMPB    
   Symmetrical
Waveform

Count Up and Down Mode

 ePWM Compare Module Registers
Name Description Structure
CMPCTL Compare Control EPwmxRegs.CMPCTL.all =
CMPA Compare A EPwmxRegs.CMPA =
CMPB Compare B EPwmxRegs.CMPB =

By changing this set-point between 0 and 100% of the period, we can adjust the duty
cycle of the output signal.
With a PWM signal we can represent any analogue output signal as a series of digital
pulses! All we need to do with this pulse series is to integrate it (with a simple low
pass filter) to imitate the desired signal. This way we can build a sine wave shaped
output signal. The more pulses we use for one period of the desired signal, the more
precisely we can imitate it. We speak very often of two different frequencies, the
PWM-frequency (or sometimes “carrier frequency”) and the desired signal
frequency.
A lot of practical applications have an internal integrator. For example the windings
of an electrical motor are perfectly suited to behave as a low-pass filter.
Shadows or Background registers can be used to prepare a new value for the next coming period while the current period
is still running and may still rely on the value in the foreground.
ePWM Compare Control Register
EPwmxRegs.CMPCTL CMPA and CMPB Shadow Full Flag
(bit automatically clears on load)
0 = shadow not full
1 = shadow full

15 - 10 9 8 7
reserved SHDWBFULL SHDWAFULL reserved

6 5 4 3-2 1-0
SHDWBMODE reserved SHDWAMODE LOADBMODE LOADAMODE

CMPA and CMPB Operating Mode CMPA and CMPB Shadow Load Mode
0 = shadow mode; 00 = load on CTR = 0
double buffer w/ shadow register 01 = load on CTR = PRD
1 = immediate mode; 10 = load on CTR = 0 or PRD
shadow register not used 11 = freeze (no load possible)
LOADxMODE:
• define the hardware event, which will copy a value from background into the active foreground register

SHDWxMODE:
• enable (0) or disable (1) the background update mode. If disabled, all write instructions will immediately change the value
in register CMPA or CMPB

SHDWxFULL:
• read only status field. If shadow is full (1) and the hardware copies the value into foreground, the bit is cleared
automatically

For most applications it is highly recommended to use this shadow feature, since it eases the urgency of accesses to the
CMP registers, when we change these values on a cycle-by-cycle base, sometimes called “on the fly”.

After a hardware reset, or by default, shadow mode is enabled and LOADxMODE is set to “load on CTR=0”; If we don’t
initialize CMPCTL at all, the default mode will be active.
Thank You

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