EEL525

Processor Applications in
Power Electronics
Fixed Point Processors and
Floating Point Processors
Siba Kumar Patro
 Multiplication:
The multiplication of two Q-15 numbers results in a Q-30 number.
Consider two decimal fractions x and y. Their multiplication z’ is
Z’ = (x * 215) (y * 215) = xy * 230;
which is the Q-30 representation of the desired fractional result z = xy.
To get the Q-15 representation of the result, it is necessary to multiply z’ as follows.
z * 215 = z’ * 2-15
That is, z’ needs to be shifted right by 15 bits. Equivalently, we may shift z’ left by one
bit, and take the most significant 16 bits of the resulting number to be the Q-15
representation of the result z; this is the preferred method.
Formula: Multiply two Q-15 numbers, shift the 32-bit result left by one bit and take the
most significant 16 bits to get the Q-15 result
Example:
0x4000 * 0x6000 = 0x18000000 0x30000000  0x3000
(0.5 * 0.75 = 0.375)
Multiply 0.6 * 0.7 in Q15 Signed decimal fraction
Fractional Representation in IQ Format or
Binary Fraction Format
31 0
S IIIIIIII fffffffffffffffffffffff
32 bit

.
-2I + 2I-1 + … + 21 + 20 2-1 + 2-2 + … + 2-Q

“IQ” – Format
“I”  INTEGER “Q”  QUOTIENT
It is implemented by IQ-Math
Advantage  Precision same for all numbers in an IQ format
Disadvantage  Limited dynamic range compared to Floating-Point
I1Q3 – Format:
3 0

S fff

Most negative decimal number: -1.0 = 1.000 B

Most positive decimal number: + 0.875 = 0.111 B

Smallest negative decimal number: -1*2-3 (-0.125) = 1.111 B

Smallest positive decimal number: 2-3 (+0.125) = 0.001 B

Range: -1.0 …. 0.875 ( + 1.0)

Resolution: 2-3
I3Q1 – Format:
3 0
SII f

Most negative decimal number: -4.0 = 100.0 B

Most positive decimal number: + 3.5 = 011.1 B

Smallest negative decimal number: -1 * 2-1 (- 0.5) = 111.1 B

Smallest positive decimal number: 2-1 (+0.5) = 000.1 B

Range: -4.0 …. +3.5 ( + 4.0)

Resolution: 2-1
I8Q24 – Format:
0
31
S III IIII ffff ffff ffff ffff ffff
Most negative decimal number: -128
1000 0000. 0000 0000 0000 0000 0000 0000 B

Most positive decimal number:  + 128

0111 1111. 1111 1111 1111 1111 1111 1111 B

Smallest negative decimal number: -1*2-24

1111 1111. 1111 1111 1111 1111 1111 1111 B

Smallest positive decimal number: 2-24

0000 0000. 0000 0000 0000 0000 0000 0001 B

Range: -128 …. (+128)

Resolution: 2-24
 Floating Point Number Representation

e: 8-bit exponent field, contains signed 2’s complement integer (2y or 2-y)
s: Sign bit (+x or -x)
f: Fractional part of the mantissa (signed 2’s complement form)
x: Floating point number
Example: +1.7 * 101
+17 s = 0
+17 = 1.0625 * 16=1.0625 * 24
e = 4 and f = 00010000000000000000000
x = 0000 0100 0000 1000 0000 0000 0000 0000
= 0x04080000
1) +32, +18.5 2) Convert Floating Point Number to decimal point number
0x81000000, 0x7f7fffff, 0x7f800000, 0x81ffffff
 Floating Point Number Representation

1) 0x81000000
-7f=2-127
000000=(1+0)=1
1*2-127= +5.8774717*10-39

2) 0x7f800000
7f= 2127
800000= -(1+20)=-2
-2*2127=-2128 =-3.4028236*1038
 Floating Point Number Representation

e: 8-bit exponent field, contains signed 2’s complement integer (2y or 2-y)
s: Sign bit (+x or -x)
f: Fractional part of the mantissa (signed 2’s complement form)
x: Floating point number
Example: +1.7 * 101
+17 s = 0
+17 = 1.0625 * 16=1.0625 * 24
e = 4 and f = 00010000000000000000000
x = 0000 0100 0000 1000 0000 0000 0000 0000
= 0x04080000
1) +32, +18.5 2) Convert Floating Point Number to decimal point number
0x81000000+5.8774717*10-39, 0x7f7fffff  +3.4028234*1038, 0x7f800000  -
3.4028236*1038, 0x81ffffff  -5.8774724*10-39
 Floating Point Number Representation

32-bit Floating Point Number Range

Most positive number:
0x7f7fffff = +3.4028234*1038
Least positive number:
0x81000000 = +5.8774717*10-39
Most negative number:
0x7f800000 = -3.4028236*1038
Least negative number:
0x81ffffff = -5.8774724*10-39
TMS320f28335

Daughter Board Station

Docking Station with DSP
 Program Bus
ePWM

Boot DMA eCAP

Sectored RAM ROM 6 Ch.
A(19-0) XINTF Flash eQEP

DMA Bus 12-bit ADC

D(31-0)
Watchdog

PIE
32-bit R-M-W Interrupt CAN 2.0B
32x32 bit
Auxiliary Atomic FPU Manager
Multiplier I2C
Registers ALU
3
SCI
Real-Time 32-bit
JTAG Register Bus Timers SPI
Emulation
CPU
McBSP
Data Bus
GPIO
Courtesy: TI Modules
The Peripheral Frames
All peripheral registers are grouped together into what are known as “Peripheral
Frames”-PF0, PF1, PF2 and PF3. These frames are mapped in data memory only.

The detailed mapping of peripherals into data memory is as follows:

PF0: includes register sets to control the internal speed of the FLASH memory (non-
volatile memory, code memory), as well as the timing setup for external memory
devices, direct memory access (DMA) unit registers, core CPU timer registers and the
code security module control block (This is a feature to prevent reverse engineering).
PIE: PIE Interrupt Enable and Control Registers plus PIE Vector Table
Flash: Flash Wait state Registers
XINTF: External Interface Registers
DMA: DMA Registers
Timers:CPU-Timers 0, 1, 2 Registers
CSM: Code Security Module KEY Registers
ADC: ADC Result registers
The Peripheral Frames
All peripheral registers are grouped together into what are known as “Peripheral
Frames”-PF0, PF1, PF2 and PF3. These frames are mapped in data memory only.

The detailed mapping of peripherals into data memory is as follows:

PF1: contains most of the peripheral unit control registers, such as ePWM, eCAP, Digital
Input/Output control and the CAN-“Controller Area Network” register block.
eCAN: eCAN Mailbox and Control Registers
GPIO: “general purpose input output” MUX Configuration and Control
Registers
ePWM:Enhanced Pulse Width Modulator Module and Registers (dual mapped)
eCAP: Enhanced Capture Module and Registers
eQEP: Enhanced Quadrature Encoder Pulse Module and Registers
The Peripheral Frames

PF2: SYS: System Control Registers

SCI: Serial Communications Interface (SCI) Control and RX/TX Registers
SPI: Serial Port Interface (SPI) Control and RX/TX Registers
ADC: ADC Status, Control, and Result Register
I2C: Inter-Integrated Circuit Module and Registers
XINT: External Interrupt Registers
PF3: McBSP: Multichannel Buffered Serial Port Registers
ePWM: Enhanced Pulse Width Modulator Module and Registers
Digital I/O Unit
All digital I/O’s are grouped together into “Ports”, called GPIO-A (00-31), B (32-63), and
C (64-87). The F2833x features a total of 88 I/O-pins, called GPIO0 to GPIO87.
The device comes with so many additional internal units, that not all features could be
connected to dedicated pins of the device package at any one time. The solution is:
multiplex. This means, one single physical pin of the device can be used for up to 4
different functions and it is up to the programmer to decide which function is selected.
F2833x GPIO Pin Block Diagram
I/O DIR Bit Peripheral Peripheral Peripheral
GPxSET 0 = Input 1 2 3
GPxCLEAR 1 = Output
GPxTOGGLE
GPxDIR
GPxDAT • • 10
01
GPxMUX2
00• •11
Out
GPxMUX1
I/O DAT
Bit (R/W) In MUX Control Bits *
00 = GPIO
01 = Peripheral 1
10 = Peripheral 2
X= A, B and C Input 11 = Peripheral 3
• Qualification
(GPIO 0-63 only)
GPxQSEL1
GPxPUD
GPxQSEL2
Internal Pull-Up GPxCTRL
0 = enable (default GPIO 12-31)
1 = disable (default GPIO 0-11)
Pin
F2833x GPIO Pin Block Diagram
I/O DIR Bit Peripheral Peripheral Peripheral
GPxSET 0 = Input 1 2 3
GPxCLEAR 1 = Output
GPxTOGGLE
GPxDIR
GPxDAT • • 10
01
GPxMUX2
00• •11
Out
GPxMUX1
I/O DAT
Bit (R/W) In MUX Control Bits *
00 = GPIO
01 = Peripheral 1
10 = Peripheral 2
X= A, B and C Input 11 = Peripheral 3
• Qualification
(GPIO 0-63 only)
GPxQSEL1
GPxPUD
GPxQSEL2
Internal Pull-Up GPxCTRL
0 = enable (default GPIO 12-31)
1 = disable (default GPIO 0-11)
Pin
Register Group “GPxPUD” GPIO 0-31 can be used to disable internal pull-up resistors
to leave the voltage level floating or high-impedance.

When a digital I/O function is selected, then register group GPxDIR defines the
direction of the Input or Output.
Clearing a bit position to zero configures the line as an input, setting the bit position to
1 configures the line as an output.

A data read from an input line is performed with a set of GPxDAT registers.
A data write to an output line can also be performed with registers GPxDAT.

Additionally, there are 3 more groups of registers:

• GPxSET To set a bit
• GPxCLEAR To reset a bit
• GPxTOGGLE To toggle a bit
GpioDataRegs.GPACLEAR.bit.GPIO5 = 1; to clear pin 5
 GPIO Port A Mux1
Input

GPIO Port A
Register (GPAMUX1) GPIO Port A
[GPIO 0 to 15] Qual
Direction Register
(GPADIR)
GPIO Port A Mux2
[GPIO 0 to 31]
Register (GPAMUX2)
[GPIO 16 to 31]

GPIO Port B Mux1

Input
Internal Bus

GPIO Port B
Register (GPBMUX1) GPIO Port B
[GPIO 32 to 47]
Qual
Direction Register
GPIO Port B Mux2 (GPBDIR)
Register (GPBMUX2) [GPIO 32 to 63]
[GPIO 48 to 63]

GPIO Port C Mux1

GPIO Port C
Register (GPCMUX1) GPIO Port C
[GPIO 64 to 79] Direction Register
GPIO Port C Mux2 (GPCDIR)
Register (GPCMUX2) [GPIO 64 to 87]
[GPIO 80 to 87]
Thank You

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