JOURNAL OF LATEX CLASS FILES, VOL. 18, NO.

9, JUNE 2023 1

A Survey of Spiking Neural Network Accelerator

on FPGA
Murat Isik

Abstract— Gate Arrays (FPGAs) become a potential hardware platform

Due to the ability to implement customized topology, FPGA is for SNN acceleration, based on its features of logic recon-
increasingly used to deploy SNNs in both embedded and high- figurability, high power efficiency, and support of computing
performance applications. In this paper, we survey state-of-the-
art SNN implementations and their applications on FPGA. We parallelization and bit-level operations.
arXiv:2307.03910v1 [cs.AR] 8 Jul 2023

collect the recent widely-used spiking neuron models, network Recent research has deployed SNNs on different platforms,
structures, and signal encoding formats, followed by the enu- such as Central Processing Units (CPUs), Graphics Process-
meration of related hardware design schemes for FPGA-based ing Units (GPUs) and Application-Specific Integrated Circuits
SNN implementations. Compared with the previous surveys, this (ASICs). However, due to the restricted memory bandwidth,
manuscript enumerates the application instances that applied the
above-mentioned technical schemes in recent research. Based on SNNs on CPU/GPU consume high power overhead with lim-
that, we discuss the actual acceleration potential of implementing ited throughput [1], [2]. To achieve the best performance and
SNN on FPGA. According to our above discussion, the upcoming energy efficiency, many researchers have focused on building
trends are discussed in this paper and give a guideline for further custom ASICs for accelerating network inference workloads.
advancement in related subjects. Despite being an attractive solution, ASICs cannot offer suffi-
Index Terms—Neural Networks, Spiking Neural Network, cient flexibility to accommodate the rapid evolution of Neural
FPGA Implementation, Hardware Accelerator, Survey. Network (NN) models. The emergence of new types of layers
within NN, including branching, elementwise addition, and
I. I NTRODUCTION batch normalization layers, has been seen in more recent
PIKING Neural Network (SNN) has been one of the most models that require flexibility. Further, the high Non-Recurring
S extensive research subjects in recent decades. Researchers
successfully deployed the related instances in various applica-
Engineering (NRE) cost and time for design, verification, and
fabrication of a large ASIC chip make it difficult to keep pace
tion scenarios, such as speech recognition, biomedical analy- with the rapid model improvements in this space [3]. Con-
sis, and self-driving cars. SNNs are inspired by the biological sequently, FPGAs serve as configurable tools, facilitating the
neural system with the understanding of brain functionalities. creation of unique logic, which may mitigate the limitations on
The related works are more biologically plausible in both the execution of neural networks. As an outcome, due to the
information transmission across neurons and internal neuron apparent benefits of the SNN on hardware implementation,
signal processing. Therefore, this technique causes a paradigm one of the current research hotspots is the development of
shift in the field of neural network research. The goal of SNNs hardware systems supporting SNN inference based on FPGA
is to develop a computational system modeling the behavior of to achieve high throughput and power efficiency [4].
real neurons. However, the complexities of the network model
and corresponding computation requirements in SNN infer- A. Contributions of Our Survey
ence are rapidly increasing. The trade-off between hardware In this manuscript, we survey the upcoming techniques of
and power consumption and acceleration performance has FPGA-based SNN accelerators and its application instance in
become a research topic of importance. This leads to an actual various scenarios. The major contributions of our survey are
requirement for customized hardware accelerators to achieve as follows:
higher computing/power efficiency, especially for embedded
• We categorize the widely-used spiking neuron models,
and lightweight applications. Recent research shows that SNNs
have the following excellent hardware implementation fea- spiking signal format, currently explored SNNs, SNN
tures: SNNs communicate across neurons using spikes, which training tools, etc.
• Based on the above-mentioned background, we survey
are equivalent to a single bit in terms of logic resources and
decrease the logic occupation. Therefore, Field Programmable the feasible techniques for hardware design of SNN
accelerator on FPGA and analyze the difficulties in the
Manuscript created June 2023; This work was developed by the IEEE implementation, including accelerator architectures, opti-
Publication Technology Department. This work is distributed under the LATEX mization, and upcoming solutions.
Project Public License (LPPL) ( http://www.latex-project.org/ ) version 1.3. A
copy of the LPPL, version 1.3, is included in the base LATEX documentation of • We enumerated the related application-based SNN accel-
all distributions of LATEX released 2003/12/01 or later. The opinions expressed eration on FPGA.
here are entirely that of the author. No warranty is expressed or implied. User • We examine the research trends and optimization direc-
assumes all risk.
Murat Isik is with Stanford University, 94305 Stanford, CA, United States tions in developing FPGA-based SNN accelerators based
of America [email protected] on the above works.
JOURNAL OF LATEX CLASS FILES, VOL. 18, NO. 9, JUNE 2023 2

B. Organization transmission encoding method as shown in Figure 1d.

This manuscript is structured as following Section II in- This method encodes the input value as the number of
troduces the technology background of Spiking Neural Net- spikes and the inter-spike interval (ISI) in the burst. More
works. Section III discusses the popular implementations and intensive spikes in burst represent a larger input.
solutions for SNN accelerators on FPGA in recent works. • Rank Order Coding Format: Figure 1d shows the
Section IV briefly emulates the previous FPGA applications scheme of Rank Order Coding [10]. Instead of apply-
in different scenarios based on SNN. Section V analyzes the ing the spikes latency in stimulus to encode the inputs
trend of further work and upcoming research for the SNN like Time-to-first Spiking Coding scheme, this encoding
accelerator on FPGA. Section VI concludes the survey. method encodes the input information as the spikes fire
order ignoring the fire latency. Therefore, for N pre-
II. BACKGROUND neurons, their outputs can be encoded as 2N different
A. Coding Formats of Spiking Signals data.
In recent artificial intelligence research, spiking neural net-
works have become a state-of-the-art topic for further mod-
eling the working principle of bio-neural systems. Therefore, B. Spiking Neuron Modelling and the Differences with Classic
the input data need to be encoded into a spiking signal format. ANN Neuron
For instance, Figure 1 shows five most popular spiking coding 1) Spiking Neuron Modelling: A bio-inspired artificial in-
formats in recent research [5], [6]: telligence technology called SNN has become a state-of-the-
art technology in recent years. Therefore, the implementa-
Values: A>B>C>B tions of spiking neurons also mimic the actual natural neural
stimulus
cells. Based on the cell structure modelling, there are three
𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐴 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐴 widely-explored spiking neuron models on FPGA acceler-
𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐵 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐵
𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐶 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐶
ator implementations: i) Hodgkin-Huxley (HH) Model [11],
ΔtD
𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐷 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐷 ΔtC
ΔtB ΔtA
ii) Izhikevich Model [12], iii) Leaky Integrate-and-Fire Model
a) Rate Coding Format b) Time-to-first Spiking Coding (LIF) [13][14].
Format
Assume A=11010010B, B=10110100B, C=01011010B,
D=00101101B

𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐴 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐴 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐴

• Hodgkin-Huxley (HH) Model: This model simplified
𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐵 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐵 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐵 the neural cell structure as a RC circuit model as shown
𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐶 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐶 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐶
in Figure 2.
𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐷 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐷 𝑆𝑝𝑖𝑘𝑖𝑛𝑔𝐷

c) Phase Coding Format d) Burst Coding Format e) Rank Order Coding

Format

Fig. 1. Five popular spiking coding formats I

• Rate Coding Format: Rate coding is the most widely- Capacity of Cell
Membrane
used format in related works. This format converts the
C RLeaky RK RNa
input value to a Poisson spiking train with the correspond- U
ing fire rate. As shown in Figure 1a, larger input can be
represented as the spiking train with a higher fire rate.
• Time-to-first Spiking Coding Format: Time-to-first ELeaky EK ENa
Spiking Coding is a kind of temporal coding method.
Instead of using fire rate to represent different inputs
value, Time-to-first coding applies the fire latency in a
stimulus duration to convert data as a spike. As shown Fig. 2. RC Circuit Modelling of Hodgkin-Huxley Spiking Neuron Model
in Figure 1b, the spike of larger input will be fired
earlier. Compared with the rate coding format, time-to- In this model, C represents the capacity of the cell mem-
first coding only requires a single spike, data information brane. RK and RN a mimic the sodium and potassium ion
will be encoded in the temporal latency. channels in neurons. RLeaky simulates the leaky channel
• Phase Coding Format: Above two coding methods need to lose the charge in the membrane. Therefore, Equation 1
a conversion between data value and fire rate/latency.
Different conversion solutions will influence the encoded
spike trains. As shown in Figure 1c, work [7] explored I (t) = IC (t) + IK (t) + IN a (t) + ILeaky (t)
another spiking encoding method that directly converts dU (1)
the binary format of input value as the spike train. The ⇒C = I (t) − IK (t) − IN a (t) − ILeaky (t)
dt
weight spike in this work will represent the significance
of each input bit. Because the conductance of ion channels in this model is
• Burst Coding Format: To reduce the transmission simulated as the function of time and voltage, Equation 1
duration of spiking signal, work [8][9] explored a burst will be rewritten as:
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dU V − Vrest
dU C = I (t) − (4)
4 dt R
I (t) = C + gK n (t, U ) · (U − UK )
dt 2) Brief introduction of SNN Neurons hardware implemen-
3
+ gN a m (t, U ) h (t, U ) · (U − UN a ) tation: Figure 4 shows the structure of neuron processing
+ gLeaky (t) · (U − UK ) elements in SNNs hardware implementation. For SNN, when

dn (t, U ) networks apply different neuron models and signal encoding

 = αn (U ) · (1 − n (t, U )) − βn (U ) · n (t, U ) schemes, the structures of neuron processing elements will

 dt
dm (t, U ) be different. For instance, in the implementations based on

= αm (U ) · (1 − m (t, U )) − βm (U ) · m (t, U )LIF model and rate coding schemes, the neurons can consist
 dt
 dh (t, U ) = α (U ) · (1 − h (t, U )) − β (U ) · h (t, U ) of the following submodules: 1) Multiplier, 2) Accumulator,



h h
 dt 3) Thresholds, and 4) Spiking Encoder:
αi (U ) = p∞ (U ) /τp
βi (U ) = (1 − p∞ (U ))/τp
(2) W eigh ts Spiking Tspiking
h e outputofsom e
neuron is not

Enc oding
a spike butth e spike
In Equation 2, n, m, and h are the conductance parame- Date
Integer, F l
F orm at:
oating- points,
train, wh ich needs to
be encoded before
F ixed- points, etc. firing.
ters for sodium and potassium ion channels, p represent
the steady state values for activation.
• Izhikevich Model: Considering the parameters and com-
Inputs M UL A CCU T H R ES EN C O DE
plex computing in Equation 2, work [12] simplified the Date F orm at:
HH model based on bifurcation methodologies as Equa- Spiking signal
latency code,
s-

rate code, etc.

tion 3 to reduce the number of parameters.
B ias T h resh ol
d
′ 2 F or som e SN N P aram eters
v = 0.04v + 5v + 140 − u + I m odel
wil
s, bias
lbe ignored. th resh ol
ds, l
eakage, reset, etc.

u′ = a(bv − u)
 (3)
v←c Fig. 4. Neuron Structure of Spiking Neural Networks
if v ≥ 30mV, then
u←u+d
• Multiplier and Accumulator compute the product sum
In Equation 3, v implies the membrane potential (input). of weighted spikes based on different data formats.
u means recover parameter. a means how fast the mem- However, storing network weights consumes a large
brane potential recovers, the typical value is 0.02. b means number of on-chip memory resource on FPGA. Consid-
the responsibility between u and input v, typical value is ering the limitation of hardware resources, in addition
0.2. c means the reset potential after spiking, the typical to the common floating-point and fixed-point formats,
value is −65mV . d means the increase value of u after some low-precision data formats are widely explored in
reset, typical value is 2mV [15]. recent research, such as i) Quantization, ii) Binarization,
• Leaky Integrate-and-Fire Model: iii) Approximation Computation, and iv) Posit-floating
Computation:
The authors of Q-SpiNN [16] and work [17] implemented
I a Quantized Spiking Neural Network (QSNN) framework
Input to reduce the memory consumption of network weights
R based on the low-precision integer scheme. Moreover,
O utput work BS4NN [18] and work [19] further reduced the
L eaky weight precision to the Binarized Spiking Neural Network
C V R est
(BSNN). Work AxSNN [20] explored the application of
T h resh ol
d
approximation computation on SNN. The authors of [21]
V rest
researched the possibility of applying Posit-floating com-
putation [22], [23] on FPGA-based SNN accelerators.
R efractory T ime • Thresholds and Spiking Encoding: As shown in Fig-
ure 4, the parameters of thresholds will be the leaky
rate, refractory time, fire thresholds, etc. For some coding
Fig. 3. RC Circuit Modelling of Leaky Integrate-and-Fire Spiking Neuron
Model schemes, such as Phase Coding, the encoding module
will be necessary. More technique details about the spik-
To further simplify the spiking neuron model, authors ing neuron implementation will be discussed in Section
in [13], [14] discussed the simplification of the HH model III.
as Leaky Integrate-and-Fire (LIF) model, which has been
the most widely-used model in recent research. As shown C. SNN Model Training and Conversion Tools
in Figure 3, LIF further simplified the HH model, the RC The simulation and evaluation of SNN accelerator im-
modeling formula is Equation 4: plementations on FPGA require trained models. However,
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because of the difference between SNN and classic ANN, The spatial and temporal properties of the SNN can be pre-
SNN training is still a challenge in recent research and limits served to a greater extent with the use of recurrent convolution
the application of SNNs. Some upcoming toolkits support the SNN. A sampling window in recurrent architecture captures
SNN model generation-based conversion from trained ANN the temporal correlations in event-based sequences. In [35],
models or directly SNN training. Xing et al. use a supervised Spike Layer Error Reassignment
1) ANN Model Conversion: Because of the difficulties in (SLAYER) training mechanism for ANN-SNN conversion.
synaptic weight learning on SNN training, some works ex- The SCRNN architecture is a combination of single SCRNN
plored the solution that converts an ANN model to SNN. Spik- cells that process input sequences separately to maintain the
ing Neural Network Conversion Toolbox [24] implemented one temporal dimension. The spatial complexity is handled with
python-based conversion tool from ANN to SNN supporting decomposed input processed in cells at every time step. Each
various ANN training libraries, such as Keras, PyTorch, Caffe, SCRNN cell accepts an input feature map, a fused feature map
etc. It also supports the SNN model export for evaluation of previous states, and an output feature map of the current
based on SNN simulation tools, like pyNN [25], Brain2 [26], input. Thus, the network was made recurrent and evaluated on
sPyNNaker [27], etc. the Dynamic Vision Sensor (DVS) gesture dataset, achieving
2) SNN Model Training: Compared with the ANN conver- an accuracy of 96.59% for a 10-class gesture recognition task.
sion, direct training of SNN can achieve higher accuracy. Some The elimination of all matrix multiplications in SNN makes
researchers explored the related SNN training algorithms [28], them more energy-efficient than CNN. In [36], Wu et al.
[29], [30]. Based on previous works, snnTorch [31] imple- develop a unified framework that supports weight normal-
mented a PyTorch-based SNN training acceleration library. ization, threshold balancing and an Explicit Current Control
This library supports the training of Spiking Convolution (ECC) method that controls the number of spikes passed to
Neural Network (SCNN) and Spiking Long-Short Term Mem- the SNN and reduces the residual membrane potential. The
ory Network (SLSTM) based on the LIF neuron model and residual current in the neurons causes accuracy loss for shorter
rate/latency coding. The training based on this work can inference. The ECC also enables the conversion of Batch
also be accelerated by applying the GPU platform through Normalization (BN) layer that many of the recent works fail to
PyTorch. include. The role of the BN layer is to normalize the previous
layer’s output, which accelerates the CNN’s convergence. This
III. T ECHNIQUES is implemented in the conversion by a numerical constant
A. Topology Conversion dependent on the training platform that updates the weight
Spiking neural networks are biologically inspired Artificial and bias to a normalized version of the same.
Neural Networks (ANN), which are more power-efficient, but
the discrete nature of the spikes makes it difficult to train an B. Neuron models on FPGA
SNN. Thus, much work has been done to convert the topology A biological neuron can be implemented in either of the
of a trained network from ANN or CNN to SNN while neuron models as discussed in section II. In [37], Juneeth et
copying the trained weights and adjusting the spiking threshold al. develop a spiking neuron model of Hodgkin-Huxley on
potential in SNN. In one such work [32], Deng et al. analyze an FPGA. The hardware architecture is based on a series
the ANN to SNN conversion error and propose a method of adder and multiplier blocks to implement the first-order
to transfer weights with no loss of accuracy. The authors differential equations in Verilog on Xilinx Virtex-5. Each of
modify the ReLU function on the source ANN by thresholding the neuron parameters is represented in a fixed point with
the maximum activation and reducing the simulation time chosen bit lengths. However, the physical justification for the
to 1/10th of a typical SNN simulation time. Followed by a bit optimization strategies is inconsistent. The use of multiplier
shifting operation to balance the output frequency is termed blocks increases the number of LUTs and eventually, power
as the threshold balancing mechanism [33]. consumption.
The ANN-SNN conversion techniques have managed to On the contrary, in [38], Farzin et al. propose a multiplier-
achieve deeper architectures but most of these techniques less Hodgkin-Huxley model. The model approximates hy-
are based on the assumption that spike patterns of SNN a perbolic functions as piece-wise linear terms implement all
time-sampled ANN. Thus, the temporal properties of SNN multiply operations as logical shifts and adds. This is made
are ignored. Some training algorithms like Backpropagation possible with equations modified to power-2-based functions.
Through Time (BPPT) could solve this by training through Considering the high accuracy of a HH neuron, a multiplier-
time but it introduces vanishing gradients. Samadzadeh et al. less design furthermore reduces the operational cost and
in [34] instead initialize the weights with non-spiking training increases the frequency.
data. For the first few epochs, the SNN is trained like an Two simplified two-dimensional versions of the HH neuron
ANN where the output activation function is changed to leaky model are the FitzHugh-Nagumo and Morris-Lecar neuron
ReLU. After which the activation function is modeled as a step models [39]. In [40], Nouri et al. investigate the FitzHugh-
function with the LIF neuron. By utilizing the skip connec- Nagumo neuron model in terms of its digital implementation
tions in ResNet architecture a Spiking ResNet (STS-ResNet) feasibility and computation overhead. The model is a cubical
architecture is proposed for testing the conversion accuracy approximation with no auxiliary reset equations. The area and
and temporal feature extraction on CIFAR10-DVS, NMNIST power numbers of the proposed design with Euler discritiza-
and DVS-Gesture. tion are lower than a HH model apparatus. In [41], Mellal et
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al. study the behavior of the Morris-Lecar neuronal model on Fang focuses their work to retain the temporal information in a
a Xilinx Zynq UltraScale+ board. The simulated and hardware sequence of spikes in the architecture. The leaky integrate and
results of the original and discrete implementations have a high fire neuron-based hardware avails a series of Infinite Impulse
correlation. Response (IIR) filters to represent SNN. The time-encoded
One of the basic building blocks of the human body is spikes provide the time information to interpret neurons as
the Central Nervous System comprised of neurons, synapses, filters. Further, the suggested model incorporates synapse
and glial cells. In [42], Abdulaziz et al. evaluate a model dynamics adding flexibility to the system. Each layer has a
based on its complexity and hardware resources required to processing element that updates the neuron and synapse state
realize it on an FPGA. The two-neuron coupled Izhikevich variables. An optimized framework of end-to-end neuromor-
model while satisfying the above parameters regenerates all phic systems is described with reduced inference latency. The
the different dynamics of the human brain. The authors use results compared to a CPU has better performance metrics.
a LUT-based approach to the quadratic equations instead of Additionally, the LIF model has been holistically modified
an approximation technique to replace the non-linear terms. to several other forms. In [48], Heidarpour et al present
As the size of the LUT increases to 1000 points the model a CORDIC implementation of an Adaptive exponential in-
becomes closer to the mathematical equations. tegrate and fire (AdEx) neuron model. The primary difference
Another unique technique involving the Izhikevich neuron to Equation 4 is that the potential difference integrates expo-
model is discussed in [43]. According to the authors, the nentially in the current equation. In a biological neuron, the
Izhikevich neuron is practically more suitable for electrical increase in action potential with an input spike is non-linear.
realization due to its chaotic behavior. A modified version Thus, non-linear LIF neuron models depict the biological
of the model is compared with the original coupled neuron behavior rather closely although the implementation cost of
dynamics through numerical simulations and FPGA device non-linear behavior on hardware is always higher. The authors
demonstration. The modified model has a longer processing in [48] discretized the differential equations explicitly with
time (2 clock cycles) but with no multiplier usage. This design the Euler method and implement it on a Xilinx Spartan 6
characteristic has significantly reduced the utilization number using simple add and shift operations only. Similarly, in [49],
while maintaining the accuracy of the model. Along with the Basham et al demonstrate a quadratic integrate and fire
spinal network these neuron models have been altered for (QIF) neuron model where the current equation integrates the
use. In [44], Niu et al. the motoneurons in the motor nervous square of potential difference. The design utilizes a fixed-point
system are emulated with the Izhikevich model on an FPGA multiplier to evaluate the square of the voltage.
to analyze pediatric neurological diseases. Lastly, in [50], Nallathambi et al instrument a probabilistic
In [45], Panchapakesan et al. proposed a novel synchronous integrate and fire neuron model. In a deterministic approach
SNN execution divided into layers for each input, hidden, when a neuron i spikes, the applied weight of the postsynaptic
and output layers. The input is executed layer-by-layer as neuron is wij .For a set of Ni spikes with a probability of
shown in Figure 5 synchronously to avoid frequent off- pij the new weight updates to Ni × pij × wij .In stochastic
chip memory communication. Further, the internal parameters processing, the number of memory fetches can be reduced
like membrane potential can be immediately used, reducing significantly. By sorting the synaptic weights the authors report
the on-chip resources utilized. Each layer is composed of a reduction of 90% off-chip memory accesses.
modules that implement the functionality of integrating and
fire neuron structure as discussed in section II. Such layer
network depiction can also be observed in [46]. Khodamoradi C. Optimization techniques
et al. propose a streaming SNN accelerator architecture that Spiking Neural Networks can be divided in two different
utilizes the concept of layer modules for generating output categories of optimization strategies. One, to make more
spikes. However, this architecture is made more specific to biologically plausible neural models with better plasticity
edge devices with sparse input data. Highly sparse events can and second, to devise tuning algorithms that can transcend
still utilize significant memory to store null information. This performance. More plasticity is accomplished with a train-
is mitigated with the use of binary tensors as input buffers. able spiking network. Backpropagation is one such learning
mechanism that has shown significant accuracy in ANN but
it is not realizable for a biological spiking network. Thus,
much work has been done to create the equivalent spiking
backpropagation.
1) Training SNN: Training deep spiking Neural networks
have shown a great requirement for optimized gradient-based
approaches. One of the reasons for facing difficulty in achiev-
ing deeper DNN is its complex Spatio-Temporal Dynamics.
Converting ANN to SNN and Backpropagation with Surrogate
Gradient are two ways to get deep SNN. Converted SNNs
Fig. 5. Layer-by-layer architecture with LIF neuron in Processing Unit (PU). need a longer training time for similar precision as ANN.
Most popularly, Backpropagation Through Time (BPTT) is
The hardware layer network is also observed in [47] where implemented by unfolding the gradient over a simulation time.
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In [51], Fang et al propose Spike-Element-wise (SEW) ResNet implementation with LUTs and series expansion techniques.
to resolve exploding gradient with identity mapping. In Spiking Moreover, the LIF neuron model is discretized to surpass
ResNet, the adaptation of residual learning from ResNet, the differential equations. Compared to baseline LSM the current
ReLU activation block is replaced by spiking neurons which model has outperformed by 8% for speech recognition TIMIT
is incapable to replicate the identity mapping for all neuron dataset. Although a hardware resource utilization trade-off
models. However, in SEW ResNet element-wise function ”g” with extra energy overhead could be observed.
facilitates identity mapping. When ”g” is chosen to be an ADD 2) Tuning SNN: Since SNN architectures are resource-
function it avoids the infinite outputs problem by restricting constrained, compression methods like pruning are an es-
the output. sential optimization to tune the performance. Nonetheless,
Apart from a purely algorithmic perspective of improvement most of the pruning approaches are ANN-specific and not
in spiking realizable Backpropagation, some work has been compatible with SNN. This factor lingers the performance
done by Shrestha et al to develop a biologically plausible of a pruned SNN. In [56], Chen et al formulate a learning
algorithm that can fit the constraints of neuromorphic hard- algorithm of connectivity and weight that defines gradient
ware. In [52], the authors have shown in-hardware supervised as a different parameter called Gradient Rewiring (Grad R).
learning demonstrated on Intel’s Loihi chip. The supervised The combined learning and pruning algorithm change the
learning is based on Error modulated Spike-Timing Depnedent synaptic connections based on the synaptic gradient parameter
Plasticity (EMSTDP) with Direct Feedback Alignment (DFA) introduced. The algorithm is evaluated on MNIST and CIFAR-
that reduces the number of neuron updates in the feedback 10 datasets with a maximum of 73% connectivity. Although
path. The hardware realization of the algorithm is designed by the techniques discussed in this section are the new frontiers
creating two replicas of the same neuron with each of them of SNN optimization innovation, most of them have not made
functional in feed-forward and feedback paths respectively. their way to a physical hardware implementation.
Further in [53], Heidarpur et al propose on-FPGA online
STDP. Based on CORDIC an iterative algorithm all hyperbolic
D. Technique Discussion
and exponential functions can be implemented with shift
and addition operations. A Izhikevich neuron behaviour was The design and implementation of deep learning algorithms,
replicated with qualitative error analysis between the CORDIC particularly SNN hardware implementation, has been a hot
model compared to the original model of operation to achieve topic during the previous decade [57]. SNN is hungry for
maximum precision.The proposed algorithm is tested for a computing power. Because of the rapid improvements in
two-layer network of 21 neurons with one output neuron.To integrated circuit technology, it is now feasible to build high-
demonstrate STDP learning on Xilinx Spartan-6 FPGA, all the performance chips at a low cost and with efficient energy
exponential terms were approximated with a negative power consumption. This allowed for the deployment of inference
of 2 terms which can be synthesized in fast and low-cost at the edge. Along with, SNN can be executed on any device
hardware. with adequate capability. There are some examples: i) CPUs,
In STDP the weight update depends on the timing difference ii) GPUs, iii) FPGAs, iv) ASICs. Diverse technologies have
between the presynaptic and postsynaptic neuron pair. On the a different throughput, performance, design flexibility, and
other hand, Triplet STDP (TSTDP) considers three consecutive power efficiency.
spikes, one presynaptic and two post synaptic spikes for Firstly, we partially consider traditional computing plat-
potentiation and depression respectively. In [54], Gomar et al forms to provide a comparison overview of the latest SNN
could reproduce the learning curve by approximating the two accelerators targeting low-power and high-performance. As
variable TSTDP equations to one variable piecewise linear depicted in Table I, after developing circuits for edge comput-
term where exponentials are converted to base-2 functions. ing, energy and performance efficiency are the most important
The discrete values of the lines are stored in LUT memory criteria to consider. CPUs [47][58] are the most adaptable
whose size is optimized as per the design. The design is driven gadgets, and as such, have the lowest performance and energy
through a Finite State Machine (FSM) of 4 states with 2 states efficiency.
representing the Learning unit of the system. Compared to the Furthermore, ASICs [59], [60], [61], [62], [63] provide the
LUT model this model is less accurate but consumes less than highest performance and energy efficiency, but with very little
1% on-chip resources. flexibility attainable primarily by additional hardware logic.
So far we have discussed Hebbian learning applications, It has reached a peak performance of 100Kimg/sec and
however, in [55], Liu et al explored non-Hebbian on-chip 7.89T OP S/W mean that are very energy efficient. ASIC
learning IP on recurrent SNN. The Liquid State Machine circuits are specifically built for neural networks to improve
(LSM) based recurrent SNN consists of a reservoir which performance and power efficiency.
maps the input pattern to a multi-dimensional response in Modern GPUs incorporate single-precision computation
the reservoir. The output of the reservoir is then passed modules capable of performing several half-precision floating-
to the readout layer. The focus of this work is to develop point calculations. Thus, they seem to be the perfect basis for
learning rules with SpiKL-IP algorithm based on neural plas- both learning and prediction. However, due to their multi-core
ticity. SpiKL is a Intrinsic Plasticity (IP) rule whose key idea structure, GPUs present a challenge with high power usage.
is to maximize the input to output information transfer. The Studies [47], [58] have shown power consumption figures
algorithm is modified to reduce the complexity of hardware markedly higher than those for FPGAs.
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TABLE I
SNN ON DIFFERENT HETEROGENEOUS DEVICES

Work Platform Operation Frequency Power Technology Throughput Scaled Efficiency

Park et al. [59] ASIC LP CMOS 20M Hz 23.6mW 65nm 100Kimg/sec 7.89T OP S/W
Buhler et al. [60] ASIC CMOS 250M Hz 87mW 40nm 1778M pixel/sec 3.43T OP S/W
Kim et al. [61] ASIC CMOS 40M Hz 3.65mW 65nm 640M pixel/sec 0.175T OP S/W
Chen et al. [62] ASIC FinFET CMOS 110M Hz 46.6W 10nm - 0.110T OP S/W
Cho et al. [63] ASIC CMOS 105M Hz 94mW 40nm 440M pixel/sec 0.083T OP S/W
Yang et al. [64] FPGA Stratix-III 100M Hz 10.5W 65nm - -
Pani et al. [65] FPGA Zynq-7 100M Hz 8.5W 40nm - 0.290GOP S/W
Han et al. [66] FPGA Zynq-7 200M Hz 0.40W 28nm 161f rame/sec 16.80GOP S/W
Liu et al. [67] FPGA Kintex-7 200M Hz 0.53W 28nm 208f rame/sec 27.85GOP S/W
Ma et al. [68] FPGA Spartan-6 75M Hz 6.3mW 45nm 208f rame/sec 27.85GOP S/W
Li et al. [69] FPGA Virtex-7 100M Hz 0.50W 28nm 317image/sec 2.08GOP S/W
Carpegna et al. [70] FPGA Artix-7 100M Hz - 28nm 465image/sec -
FPGA ZCU-102 150M Hz 4.6W 16nm 164f rame/sec 4.66GOP S/W
Ju et al. [58] CPU İ7-6700k 4.0GHz 54W 14nm 4f rame/sec 1.03GOP S/W
GPU GTX 1080 1.6GHz 100W 16nm 162f rame/sec 0.061GOP S/W
FPGA ZCU-102 125M Hz 4.5W 16nm 2124image/sec 6.92GOP S/W
Fang et al. [47] CPU i9-9900K 3.7GHz 58.1W 14nm 100f rame/sec 2.18GOP S/W
GPU AGX Xavier 1.3GHz 14W 12nm 211f rame/sec 1.67GOP S/W

FPGAs combine hardware and software (processing) in a In this section, key ideas for SNN implementation in
single device, where software ensures programmability and equipment are shown, along with a comparison to different
hardware is utilized to implement specialized accelerators. techniques in Table II. The table combines the most important
GPUs have the higher performance among programmable or information received from the available sources from among
configurable devices and are less expensive than FPGAs. the numerous structures specified from now on. Without being
Researchers have demonstrated that FPGAs may efficiently exhaustive, this chart allows for a quick representation of the
implement Spiking Neural Networks (SNN) in both hardware show status of the advanced systems.
and software/hardware contexts [64], [65], [66], [67], [58], This work [76], the usage of the NeuroFlow which FPGA
[47], [68], [69], [70]. They showed that their FPGA-based architecture for SNN that was suggested approach aims for a
design had the highest performance of 2124 frame/sec and real-time execution time of 0.1ms. NeuroFlow may be further
the lowest power of 0.40W . This corresponds to an energy reduced by adjusting the size of the arrangement or guessing
efficiency of 16.80mOP s/W . The same platform may then on the network within this architecture. Moreover, the huge
be upgraded with an SNN without any board modifications quantity of simulated neurons made available by NeuroFlow
just by reconfiguring the device. may be achieved using six FPGAs in a toroidal network
design. The configuration restricts the number of synapses to
a range of 1,000–10,000, where the chance of connection is
based on a Gaussian probability of synaptic disconnection,
with a standard deviation varying from 32 to 512. In this
spectrum, a direct comparison might be challenging and
potentially unfair to other SNN models. Another approach
in this direction has been implemented by Han [66], which
highlights crossover upgrade algorithms that integrate the
points of interest of current algorithms to improve equipment
planning and execution. Thus, this design, capacitively sup-
ports 16 384 neurons and 16.8 million synapses but uses fewer
hardware resources and has a very low power consumption
(0.477W) and the performance for processing neuron activa-
tion events is 6.72ms. For a modest to large scale SNNs on
sophisticated equipment should be computationally simple and
simultaneously capable of communicating to the large range
of termination patterns displayed by various organic neurons.
Fig. 6. SNN on Different Heterogeneous Devices For this reason, several designs employ simpler custom neural
models [71], and much more with the LIF model [73], [72].
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TABLE II
D IFFERENT SNN MODELS ON FPGA

Resources
Work Model Time Resolution Neurons / Core Synapses / Neurons
(FF, LUTs)
Upegui et al. [71] Custom 1.0ms 30 30 100, 100
Pearson et al. [72] LIF 0.5ms 1120 ≈912/112 - -
Cassidy et al. [73] LIF 320.0 ns 51 128 146, 230
Han et al. [66] LIF 6.7ms 16.384 ≈1.025x103 5381, 7309
Thomas et al. [74] IZ 10.0 µs 1024 1024 39, 19
Ambroise et al. [75] IZ 1.0ms 117 117 8, 17
Cheung et al. [76] IZ 1.0ms 98.000 1.000 - 10.000 - -
Pani et al. [65] IZ 0.1ms 1440 1.440 37, 39
Gupta et al. [77] Simplified LIF 1.0ms 800 12.544 29, 70
Li et al [69] LIF - 1094 162 - -
Asgari et al [78] LIF 45.6 µs 16 7 5090, 34648
Fang H et al [79] LIF 1.0ms 984 1.59 -, 57600
Ma et al. [68] LIF 160s 1794 360 4705, 11489
Carpegna et al [70] LIF 21.5ms 1384 226 26853 , 29145
Liu et al. [67] LIF 7.5ms 16.384 ≈1.025x103 30417, 46371

Spikes collection is performed at 32bits to maintain as much established an embedded auxiliary processor to hasten the
accuracy as conceivable. In [75], the authors demonstrate inference mechanism of SNNs. By time-sharing the physical
a comparable technique capable of simulating up to 167 neuron components, and developing a reconfigurable memory
neurons. In comparison to the one suggested, due to increased subsystem, the design realizes high hardware efficiency, fitting
information exactness and synaptic current preparation which for resource-limited embedded applications. It also permits
is more sophisticated to a certain degree such a task employs a customizable quantity of neurons, synapses, and synaptic
a greater number of assets. The FPGA architectures by [74] delays, yielding significant flexibility.
and [65] simulate a fully-connected network of 1024 neurons, Moreover, work by Fang H et al [79], Asgari et al [78], and
1440 neurons, based on the biologically plausible Izhikevich Li et al [69] proposed to utilize their design on the identical
spiking model. The reported time resolutions are 10.0 µs and neuron model (LIF) and targeting the same dataset (MNIST).
0.1ms. These implementations have low latency, despite the Recently, Carpegna et al [70] presented Spiker, which employs
fact that simplified resource utilization is employed for it. An a clock-driven neuron design wherein the membrane potential
alternate notable design is that by Gupta et al. [77], which is modified at each clock cycle absent any spikes. Neverthe-
offers a simulation of a simpler and more computationally less, inputs are only processed when there’s at least one spike
efficient model using FPGA infrastructure. This was engi- present at the input of a layer. This approach uses more power
neered to leverage the sparsity of the network and generate than purely event-driven designs but allows for the utilization
each time unit corresponding to network activities. A network of fewer hardware resources. The FPGA usage is of 1384
comprising 784 input and 16 output neurons, along with neurons and 313600 synapses are around 55% for the LUTs,
12,544 synapses, was realized on hardware, thereby facilitating and 25% for the FFs. Considering the number of instantiated
the creation of a hardware accelerator with minimal resource neurons, this is a major finding.
consumption.
In another study by Liu et al. [67], a neuron comput- IV. A PPLICATIONS
ing module was used, designed to replicate both LIF and
Izhikevich neurons using the concurrent spike caching and A. Image and Audio Processing
scheduling strategy while simulating 16,384 neurons and 16.8 In [80], authors presented an application of animal behavior
million synapses. They structured two distinct three-layer recognition using an SNN-based sound recognition system
SNN networks applied for recognition tasks on the suggested associated with animal movements. The spiking neural net-
platform. The employment of Slice LUTs, Slice Registers, and work was built on an FPGA device, and the neuromorphic
DSP of the SNN acceleration unit stands at 6.0%, 2.5%, and auditory system employed in this study creates a representation
7.6% respectively. similar to the spike outputs of the biological cochlea. Even
It is noteworthy that their design exhibits the highest when the sound was accompanied by the white noise of the
occupancy ratio in BRAM. As a consequence, the param- same strength, the detection system based on SNN achieved
eters of the LIF and IZH neurons, along with the event an accuracy of over 91%.
buffer and synaptic delays, are produced using the on-chip In [81], the authors proposed a continuous voice recogni-
storage resource BRAM. Hence, the BRAM is significantly tion system that employs a Delta Recurrent Neural Network
employed, leading to increased power usage. Ma et al. [68] (DeltaRNN) on a Xilinx Zynq-7100 FPGA to provide low
JOURNAL OF LATEX CLASS FILES, VOL. 18, NO. 9, JUNE 2023 9

trained the MNIST dataset for digital categorization on a

Stratix-3 FPGA processor with 93% precision. As a result,
the cost-effective network demonstrated great efficiency and
can readily be scaled to a larger size.

B. Biomedical Applications
The manuscript [89] presents a freely available FPGA-
centric emulation environment for delving into the neuromor-
phic computation. The authors implemented the MNIST [90]
dataset andVector-Matrix Multiplication (VMM), comparing
their accuracy with analogous architectures generated by
IBM’s Compass simulation infrastructure. Considering the
substantial computational intricacy of spiking neural networks,
it’s arduous to actualize them on hardware necessitating profi-
ciency. Thus, QingXiang Wu [91] unveiled a straightforward,
Fig. 7. System architecture of microphone effective, and swift strategy to instantiate SNN employing
a customized toolkit. Thus, participants in this investigation
seamlessly engineered and modeled various spiking neural
latency Recurrent Neural Network (RNN) processing. This networks on FPGA, enhancing the execution speed.
system is suitable for Internet of Thing (IoT) applications since In a different study, Junxiu Liu [92] proposed a novel
FPGA uses just 70mW and can process each feature frame biologically-derived gas identification technique with minimal
in microseconds. hardware footprints. This method utilized spiking neural path-
Edge detection is a prominent machine learning job that ways and neurons to recognize the abnormal frequency of the
necessitates the use of a large number of neurons as well input spike generation by adjusting the discharge likelihood of
as software simulations. As a result, scalability suffers, and the inhibitory neural linkage under diverse input situations.
computational time increases. This research [82] proposed a
scalable FPGA implementation strategy with several innova-
tions to shorten calculation times. Within this scenario, given
spatial constraints, the time-division multiplexing structure
proposes a balance between acceleration performance and
the dimensions of SNN simulations. Furthermore, a study by
Louis-Charles Caron et al. [83] accomplished image seg-
mentation and monophonic audio source separation utilizing
Oscillatory Dynamic Link Matcher (ODLM) protocols for
motif recognition.
Fig. 8. Block diagram of the neuromorphic platform (a) and Functional
The authors in [84] developed a character identification magnetic resonance imaging (fMRI) brain image (b)
model for multicore architectures relying on two SNN models.
The selection of the Izhikevich and Hodgkin-Huxley neuron In [93], a neuromorphic system on a Virtex-2 pro FPGA
models over the integrate and fire models were motivated by was shown how neuronal elements from this construction kit
their biological accuracy. All 48 visuals in the learning datasets can be deployed in parallel. The neuromorphic system mir-
were accurately distinguished within 14ms and 3.75ms, re- roring the known architecture of the early olfactory pathway
spectively. Moreover, the authors of [85] employed SNN for when coupled spontaneously produces rhythmic, limit-cycle
image clustering using FPGA. The Gaussian Receptive Field dynamics resembling biology. Thus, The findings of this work
(GRF) is the most commonly used method for encoding data, show how these attractors may be read from the network to
with Hebbian learning being used for neural models. Not only recognize previously experienced learned fragrances without
did [85] use the Receptive Field (RF) for data encoding, confusion.
but [86] also applied the T.Iakymchuk model. To examine The authors [94] present a neuromorphic system that com-
an image in its spatial domain form, the authors also utilized bines a neural recording headstage with an SNN processing
the Gabor filter, a bandpass filter. core on the same die for processing iElectroencephalography
A biologically driven, rotationally invariant visual identi- (iEEG), and demonstrate how it can reliably detect High-
fication system, executed using a pixel camera on FPGA, Frequency Oscillations (HFO), achieving state-of-the-art ac-
was deployed in [87]. The structure merged the Ripple Pond curacy, sensitivity, and specificity. This is the first feasibility
Network (RPN), a neural network proficient in fundamental research aimed at finding significant characteristics in iEEG
2D to 1D image conversion, rotationally invariant Temporal in real-time utilizing mixed-signal neuromorphic computing
Patterns (TPs), and the Synaptic Kernel Adaptation Network Technologies on a custom board XEM7360 FPGA.
(SKAN). By using the event-driven Spike-timing dependent In [95], The researchers wanted to construct an artificial
plasticity (STDP) rule, Zaibo Kuang and Jiang Wang [88] intelligence signal identification system in a PYNQ-Z2 FPGA
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TABLE III
A PPLICATIONS OF C ONTROL S YSTEMS

Work Task Platform Neuron Model Power Frequency Resources

Jimenez et al. [96] spike-based PID Spartan-3 LIF 65 mW 145 MHz 167 slice registers
Jalilian et al. [97] PWM Spartan-6 Izhikevich 14 mW 57 MHz 499 slice registers
Kotlyarevskaya et al. [98] Myoelectric Control Virtex-6 LIF - - -
Linares et al. [99] spike-based PID Spartan-6 Custom 12 W 140 MHz -

board that can detect patterns of bio-signals such as Electro-

cardiography (ECG) in battery-powered edge devices. Despite
the increase in classification accuracy, deep learning models
need expensive processing resources and power. Therefore, it
makes deep neural network mapping a time-consuming pro-
cess and deployment on wearable devices difficult to achieve.
SNNs have been used to overcome these constraints. Fig. 9. Overview of ELAS

C. Control Systems
In [96], proposed a procedure that permits the usage shown in Figure 9 calculation is reformulated as a standard
of analog-like spike-based Proportional–Integral–Derivative design with a back focus introduction for hardware execution.
(PID) controllers on low-cost Virtex-3 FPGA. Spike-based PID Within the examination at [101] the bound-together com-
controllers have been logically analyzed and characterized, pute bottleneck of different localization frameworks is dis-
demonstrating that they are exceptionally near to nonstop tinguished. Therefore, an Oriented-Fast and Rotated-BRIEF
controller models unless they are actualized in a totally com- (ORB) based visual frontend design is displayed for real-time
puterized gadget as FPGAs. and energy-efficient localization and assessed on the FPGA
In [97], biological neuron model-generated spiking wave- platform.
forms were utilized as substitutes for sawtooth waveforms Authors illustrated [102] an end-to-end usage on a genuine,
to effectuate Pulse-Width Modulation (PWM), a modulation high-Degrees of Freedom (DOF) mechanical arm, and the
strategy that produces variable-width pulses to symbolize the quickening agent was able to unravel energetic pick-and-place
amplitude of an analog input signal. This study proposes a scenarios with a high rate of success. This sub-millisecond
signal generator on the FPGA platform, grounded in the Izhike- speed is adequate with a few limitations to empower already
vich neuron model, prized for its simplicity and precision. the infeasible automated applications, such as real-time arrang-
An innovative stride in the realm of prosthetics is the bio- ing in energetic situations.
electric upper limb prosthesis serving as an actuator’s control.
The authors of [98] adopted the Izhikevich neuron model and E. Robotics
an FPGA-oriented LIF to mimic the behavior of biological Due to their handy and beneficial assistance, robots are
neurons. Moreover, PWM has surged in its acceptance as a increasingly being integrated into our society. The authors
governing technique in both analog and digital circuits. of [103] aimed to leverage FPGA to create a cerebellum
In [99], a spike-oriented proportional-integral-derivative en- model capable of learning and adjusting conversational robot
gine speed controller was modified to govern the position timing. The Central Pattern Generator (CPG), a locomotion
of the 4 joints of a lightweight and safe physical human- mechanism for multi-legged robots, is an SNN application as
robot interaction (pHRI) robotic arm, referred to as event- well.
driven BioRob (ED-BioRob). These spiking PID (sPID) con- The research conducted in [104] applied advanced hip-
trollers were deployed on two Spartan-3 FPGA platforms, pocampal pyramidal neuron models to construct hardware-
that is, the address-event representation Robot (AER-Robot). spiking neural networks for navigation purposes. J.Parker
The robot furnishes address-event-representation interfacing Mitchell [105] utilized a Dynamic Adaptive Neural Network
for spiking systems and is capable of driving DC motors Array (DANNA) framework for Autonomous Robotic Naviga-
with Pulse Frequency Modulation signals, reflecting the motor tion. The DANNA framework comprises a grid of adaptable
neurons of mammals. neuromorphic computing components, each capable of behav-
ing like a neuron and connected to its adjacent counterpart in
D. Autonomous Systems the grid.
FPGAs are gaining popularity because of their reconfigura- A modular hardware execution of a spiking neural network
bility and hardware efficiency, and have been proposed for with real-time adjustable connections is presented in [106],
robotic vision. The publication [100] introduced the Efficient framed within an autonomous robot impediment evasion
Large-scale Stereo (ELAS) based stereo vision system that is schema. The structure is situated in a conventional 2D matrix
completely implemented on FPGA and is intended for real- of cells, each operating as a spiking neuron with unique
time and energy-efficient applications. The ELAS which is functions. Another study [107] likewise tackled the robot
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TABLE IV
DATA T RANSMISSION S CHEME C OMPARISION

Platform Technology Routing Method Router Frequency Router Latency Peak Spike Throughput
SpiNNaker [112] ASIC(130nm) Multicast 180M Hz 280ns 189M spike/s
Loihi [113] ASIC(14nm) Unicast 1.67GHz 6.5ns 160M spike/s
Ding et al. [111] FPGA(28nm) Multicast/Unicast 200M Hz 25ns 200M spike/s

obstacle avoidance dilemma. Inspired by the robustness and In Table IV displays the comparison of data transmission
adaptability of biological systems, this research offered a exists similar works. The proposed routers separate them-
uniquely flexible neural network model. The network observed selves from prior efforts by supporting both source-driven and
a reduction of up to 75% of the initial synaptic inputs to a cell. destination-driven packet representations. The FPGA imple-
In [108], a neuromorphic framework was established on mented method has a spike processing rate of 200M spikes/s.
a Spartan-6 FPGA to enable locomotion for three types of The research found that their algorithm, routing strategies,
robots: bipedal, quadrupedal, and hexapods. In this explo- and router design improved communication efficiency in the
ration, the researcher conceived a fast, compact, and con- specified multichip network.
figurable FPGA architecture that hinged on the CPG, the
movement mechanism for multi-legged robots. V. T REND
Based on the above surveyed related works, we can con-
F. Event vision sensors clude the following four potential topics in further FPGA-
A fault injection experiment and fault resilience analysis for based SNN accelerator research:
an SNN hardware accelerator were given in the study at [109]. • Approximation Computing in SNN: Considering the
They created a fault injection framework that builds and maps hardware resource limitation on FPGA platforms, further
SNN faulty instances into the hardware. The framework is compressing the memory consumption of weights and pa-
allowing the researchers to expedite fault injection and analyze rameters in SNN models is necessary. The approximation
fault criticality on ZCU104 FPGA development board. computing methods and Posit computing methods applied
in work [114][115] are the upcoming techniques that can
be applied in SNN accelerators on FPGA. Besides, the
application of quantization and binarization techniques on
SNN accelerators can also be potential.
• Implementation Toolchain/Framework for SNN
on FPGA: Considering the complexity of FPGA
development, as the python-based hardware generation
framework shown in HLS4ML [116][117][118]
and FINN [119][120][121], an automatic hardware
design generation framework/library/toolchain, will
Fig. 10. System flow diagram of the neuromorphic vision sensor highly benefit the implementation and deployment
of SNN acceleration on FPGA platforms. These
This research described [110] one of the first end-to-
frameworks/libraries/toolchains should be able to
end neuromorphic frameworks for real-time object tracking
cooperate with the training/accelerating software
and categorization shown utilizing a low-power hardware
libraries and convert the trained SNN model to the
implementation on Trenz TE0720 FPGA. To take use of the
suitable hardware design for targeting platforms.
low latency and asynchronous nature of Neuromorphic Vision
• Automatic Network Generation of SNN on FPGA: The
Sensors (NVS) as an optional paradigm. The framework’s
automatic network model generation techniques, such
integral operation includes gathering occurrences from the
as Network Architecture Search (NAS) are the upcoming
camera, handling these occurrences to isolate surveilled en-
topic in recent research. Work [122] explored the applica-
tities, forwarding these observed coordinates to the neuromor-
tion of NAS on FPGA, which could also be one potential
phic chip for sorting, and the entity detection illustration, as
research and application idea for SNN acceleration on
demonstrated in Figure 10.
FPGA.
• Upcoming Network Models of SNN on FPGA: Recent
G. Communication work of FPGA-based SNN acceleration focus on the
The authors of the work [111] describe a hybrid-mode classic MLP, CNN, and LSTM models. Some state-
router architecture for large-scale neuromorphic simulation by of-the-art works, such as [123][124][125], explored the
merging two types of router schemes. These router schemes application of SNN on Transformer and Graph Neural
are proposed to allow chip-to-chip transmission of spike and Networks (GNNs). The implementation of FPGA-based
non-spike data. This work is being tested on a neuromorphic accelerators for the above networks can extend the appli-
platform constructed using an chip Artix-7 FPGA. cation scenarios of related research.
JOURNAL OF LATEX CLASS FILES, VOL. 18, NO. 9, JUNE 2023 12

VI. C ONCLUSIONS [19] M.-L. Wei, M. Yayla, S.-Y. Ho, J.-J. Chen, C.-L. Yang, and H. Am-
rouch, “Binarized snns: Efficient and error-resilient spiking neural
We have provided a survey on the hardware implementation networks through binarization,” in 2021 IEEE/ACM International Con-
ference On Computer Aided Design (ICCAD). IEEE, 2021, pp. 1–9.
of SNN that, in particular, covers recent trends in deploying [20] S. Sen, S. Venkataramani, and A. Raghunathan, “Approximate com-
FPGAs in different applications. The field of FPGA has proven puting for spiking neural networks,” in Design, Automation & Test in
that, despite the already apparent exceptional results, various Europe Conference & Exhibition (DATE), 2017. IEEE, 2017, pp.
193–198.
researchers have illustrated the advantages of reconfigurable [21] V. H. Silva, J. F. Chaves, R. M. Gomes, and B. A. Santos, “Posit-based
hardware implementations over other heterogeneous devices. spiking neuron in an fpga.”
In addition, we explained how different neural networks per- [22] J. L. Gustafson, “Posit arithmetic,” Mathematica Notebook describing
the posit number system, vol. 30, 2017.
form on FPGAs. With this survey, we proposed to summa- [23] Gustafson and Yonemoto, “Beating floating point at its own game: Posit
rize state-of-the-art work and highlight critical directions of arithmetic,” Supercomput. Front. Innov.: Int. J., vol. 4, no. 2, p. 71–86,
inquiry about that such as image/audio processing, robotics, Jun. 2017. [Online]. Available: https://doi.org/10.14529/jsfi170206
[24] B. Rueckauer, I.-A. Lungu, Y. Hu, M. Pfeiffer, and S.-C. Liu,
autonomous systems, event vision sensor, and biomedical “Conversion of continuous-valued deep networks to efficient event-
applications. driven networks for image classification,” Frontiers in Neuroscience,
vol. 11, 2017. [Online]. Available: https://www.frontiersin.org/article/
10.3389/fnins.2017.00682
R EFERENCES [25] A. Davison, D. Brüderle, J. Eppler, J. Kremkow, E. Muller,
D. Pecevski, L. Perrinet, and P. Yger, “Pynn: a common interface for
[1] P. K. Huynh, M. L. Varshika, A. Paul, M. Isik, A. Balaji, and A. Das, neuronal network simulators,” Frontiers in Neuroinformatics, vol. 2,
“Implementing spiking neural networks on neuromorphic architectures: 2009. [Online]. Available: https://www.frontiersin.org/article/10.3389/
A review,” arXiv preprint arXiv:2202.08897, 2022. neuro.11.011.2008
[2] M. Isik, K. Inadagbo, and H. Aktas, “Design optimization for high- [26] M. Stimberg, R. Brette, and D. F. Goodman, “Brian 2, an intuitive
performance computing using fpga,” arXiv preprint arXiv:2304.12474, and efficient neural simulator,” eLife, vol. 8, p. e47314, aug 2019.
2023. [Online]. Available: https://doi.org/10.7554/eLife.47314
[3] A. Boutros, S. Yazdanshenas, and V. Betz, “You cannot improve what [27] O. Rhodes, P. A. Bogdan, C. Brenninkmeijer, S. Davidson,
you do not measure: Fpga vs. asic efficiency gaps for convolutional D. Fellows, A. Gait, D. R. Lester, M. Mikaitis, L. A. Plana,
neural network inference,” ACM Transactions on Reconfigurable Tech- A. G. D. Rowley, A. B. Stokes, and S. B. Furber, “spynnaker:
nology and Systems (TRETS), vol. 11, no. 3, pp. 1–23, 2018. A software package for running pynn simulations on spinnaker,”
[4] M. Isik, A. Paul, M. L. Varshika, and A. Das, “A design methodol- Frontiers in Neuroscience, vol. 12, 2018. [Online]. Available:
ogy for fault-tolerant computing using astrocyte neural networks,” in https://www.frontiersin.org/article/10.3389/fnins.2018.00816
Proceedings of the 19th ACM International Conference on Computing [28] J. H. Lee, T. Delbruck, and M. Pfeiffer, “Training deep spiking neural
Frontiers, 2022, pp. 169–172. networks using backpropagation,” Frontiers in neuroscience, vol. 10,
p. 508, 2016.
[5] W. Guo, M. E. Fouda, A. M. Eltawil, and K. N. Salama, “Neural
[29] J. J. Wade, L. J. McDaid, J. A. Santos, and H. M. Sayers, “Swat: a
coding in spiking neural networks: A comparative study for robust
spiking neural network training algorithm for classification problems,”
neuromorphic systems,” Frontiers in Neuroscience, vol. 15, p. 212,
IEEE Transactions on Neural Networks, vol. 21, no. 11, pp. 1817–1830,
2021.
2010.
[6] J. von Kügelgen, “On artificial spiking neural networks: Principles,
[30] Y. Wu, L. Deng, G. Li, J. Zhu, Y. Xie, and L. Shi, “Direct training for
limitations and potential,” June, vol. 18, p. 2017, 2017.
spiking neural networks: Faster, larger, better,” in Proceedings of the
[7] J. Kim, H. Kim, S. Huh, J. Lee, and K. Choi, “Deep neural networks AAAI Conference on Artificial Intelligence, vol. 33, no. 01, 2019, pp.
with weighted spikes,” Neurocomputing, vol. 311, pp. 373–386, 2018. 1311–1318.
[8] E. M. Izhikevich, N. S. Desai, E. C. Walcott, and F. C. Hoppensteadt, [31] J. K. Eshraghian, M. Ward, E. Neftci, X. Wang, G. Lenz, G. Dwivedi,
“Bursts as a unit of neural information: selective communication via M. Bennamoun, D. S. Jeong, and W. D. Lu, “Training spiking
resonance,” Trends in neurosciences, vol. 26, no. 3, pp. 161–167, 2003. neural networks using lessons from deep learning,” arXiv preprint
[9] H. G. Eyherabide, A. Rokem, A. V. Herz, and I. Samengo, “Bursts gen- arXiv:2109.12894, 2021.
erate a non-reducible spike-pattern code,” Frontiers in Neuroscience, [32] S. Deng and S. Gu, “Optimal conversion of conventional artifi-
vol. 3, p. 2, 2009. cial neural networks to spiking neural networks,” arXiv preprint
[10] S. Thorpe and J. Gautrais, “Rank order coding,” in Computational arXiv:2103.00476, 2021.
neuroscience. Springer, 1998, pp. 113–118. [33] A. Sengupta, Y. Ye, R. Wang, C. Liu, and K. Roy, “Going deeper in
[11] A. L. Hodgkin and A. F. Huxley, “A quantitative description of spiking neural networks: Vgg and residual architectures,” Frontiers in
membrane current and its application to conduction and excitation in neuroscience, vol. 13, p. 95, 2019.
nerve,” The Journal of physiology, vol. 117, no. 4, p. 500, 1952. [34] A. Samadzadeh, F. S. T. Far, A. Javadi, A. Nickabadi, and M. H.
[12] E. M. Izhikevich, “Simple model of spiking neurons,” IEEE Transac- Chehreghani, “Convolutional spiking neural networks for spatio-
tions on neural networks, vol. 14, no. 6, pp. 1569–1572, 2003. temporal feature extraction,” arXiv preprint arXiv:2003.12346, 2020.
[13] L. F. Abbott, “Lapicque’s introduction of the integrate-and-fire model [35] Y. Xing, G. Di Caterina, and J. Soraghan, “A new spiking convolutional
neuron (1907),” Brain Research Bulletin, vol. 50, pp. 303–304, 1999. recurrent neural network (scrnn) with applications to event-based hand
[14] A. M. Andrew, “Spiking neuron models: Single neurons, populations, gesture recognition,” Frontiers in neuroscience, vol. 14, p. 1143, 2020.
plasticity,” Kybernetes, 2003. [36] D. Wu, X. Yi, and X. Huang, “A little energy goes a long way: Build
[15] X. Fang, S. Duan, and L. Wang, “Memristive izhikevich spiking an energy-efficient, accurate spiking neural network from convolutional
neuron model and its application in oscillatory associative memory,” neural network,” Frontiers in Neuroscience, vol. 16, 05 2022.
Frontiers in Neuroscience, vol. 16, 2022. [Online]. Available: [37] J. Kumar, J. Kumar, R. Bhakthavatchalu et al., “Design and imple-
https://www.frontiersin.org/article/10.3389/fnins.2022.885322 mentation of hodgkin and huxley spiking neuron model on fpga,” in
[16] R. V. W. Putra and M. Shafique, “Q-spinn: A framework for quantizing 2016 IEEE International Conference on Recent Trends in Electronics,
spiking neural networks,” in 2021 International Joint Conference on Information & Communication Technology (RTEICT). IEEE, 2016,
Neural Networks (IJCNN). IEEE, 2021, pp. 1–8. pp. 1483–1487.
[17] C. J. Schaefer and S. Joshi, “Quantizing spiking neural networks [38] F. Shama, S. Haghiri, and M. A. Imani, “Fpga realization of hodgkin-
with integers,” in International Conference on Neuromorphic Systems huxley neuronal model,” IEEE Transactions on Neural Systems and
2020, ser. ICONS 2020. New York, NY, USA: Association for Rehabilitation Engineering, vol. 28, no. 5, pp. 1059–1068, 2020.
Computing Machinery, 2020. [Online]. Available: https://doi.org/10. [39] W. Gerstner and W. M. Kistler, Spiking neuron models: Single neurons,
1145/3407197.3407203 populations, plasticity. Cambridge university press, 2002.
[18] S. R. Kheradpisheh, M. Mirsadeghi, and T. Masquelier, “Bs4nn: [40] M. Nouri, G. R. Karimi, A. Ahmadi, and D. Abbott, “Digital mul-
Binarized spiking neural networks with temporal coding and learning,” tiplierless implementation of the biological fitzhugh–nagumo model,”
Neural Processing Letters, pp. 1–19, 2021. Neurocomputing, vol. 165, pp. 468–476, 2015.
JOURNAL OF LATEX CLASS FILES, VOL. 18, NO. 9, JUNE 2023 13

[41] I. Mellal, D. Crompton, M. Popovic, and M. Lankarany, “A flexible chip learning,” in 2015 Symposium on VLSI Circuits (VLSI Circuits).
fpga implementation of morris-lecar neuron for reproducing different IEEE, 2015, pp. C50–C51.
neuronal behaviors,” in International Conference on Neuromorphic [62] G. K. Chen, R. Kumar, H. E. Sumbul, P. C. Knag, and R. K.
Systems 2021, 2021, pp. 1–5. Krishnamurthy, “A 4096-neuron 1m-synapse 3.8-pj/sop spiking neural
[42] A. S. Alkabaa, O. Taylan, M. T. Yilmaz, E. Nazemi, and E. M. network with on-chip stdp learning and sparse weights in 10-nm finfet
Kalmoun, “An investigation on spiking neural networks based on cmos,” IEEE Journal of Solid-State Circuits, vol. 54, no. 4, pp. 992–
the izhikevich neuronal model: Spiking processing and hardware ap- 1002, 2018.
proach,” Mathematics, vol. 10, no. 4, p. 612, 2022. [63] S.-G. Cho, E. Beigné, and Z. Zhang, “A 2048-neuron spiking neural
[43] Z. Karaca, N. Korkmaz, Y. Altuncu, and R. Kılıç, “An extensive fpga- network accelerator with neuro-inspired pruning and asynchronous
based realization study about the izhikevich neurons and their bio- network on chip in 40nm cmos,” in 2019 IEEE Custom Integrated
inspired applications,” Nonlinear Dynamics, vol. 105, no. 4, pp. 3529– Circuits Conference (CICC). IEEE, 2019, pp. 1–4.
3549, 2021. [64] S. Yang, J. Wang, B. Deng, C. Liu, H. Li, C. Fietkiewicz, and K. A.
[44] C. Niu, S. Nandyala, W. Sohn, and T. Sanger, “Multi-scale hyper-time Loparo, “Real-time neuromorphic system for large-scale conductance-
hardware emulation of human motor nervous system based on spiking based spiking neural networks,” IEEE transactions on cybernetics,
neurons using fpga,” Advances in Neural Information Processing vol. 49, no. 7, pp. 2490–2503, 2018.
Systems, vol. 25, 2012. [65] D. Pani, P. Meloni, G. Tuveri, F. Palumbo, P. Massobrio, and L. Raffo,
[45] S. Panchapakesan, Z. Fang, and J. Li, “Syncnn: Evaluating and accel- “An fpga platform for real-time simulation of spiking neuronal net-
erating spiking neural networks on fpgas,” in 2021 31st International works,” Frontiers in neuroscience, vol. 11, p. 90, 2017.
Conference on Field-Programmable Logic and Applications (FPL). [66] J. Han, Z. Li, W. Zheng, and Y. Zhang, “Hardware implementation of
IEEE, 2021, pp. 286–293. spiking neural networks on fpga,” Tsinghua Science and Technology,
[46] A. Khodamoradi, K. Denolf, and R. Kastner, “S2n2: A fpga accelerator vol. 25, no. 4, pp. 479–486, 2020.
for streaming spiking neural networks,” in The 2021 ACM/SIGDA [67] Y. Liu, Y. Chen, W. Ye, and Y. Gui, “Fpga-nhap: A general fpga-based
International Symposium on Field-Programmable Gate Arrays, 2021, neuromorphic hardware acceleration platform with high speed and low
pp. 194–205. power,” IEEE Transactions on Circuits and Systems I: Regular Papers,
[47] H. Fang, Z. Mei, A. Shrestha, Z. Zhao, Y. Li, and Q. Qiu, “Encoding, 2022.
model, and architecture: Systematic optimization for spiking neural [68] D. Ma, J. Shen, Z. Gu, M. Zhang, X. Zhu, X. Xu, Q. Xu, Y. Shen,
network in fpgas,” in 2020 IEEE/ACM International Conference On and G. Pan, “Darwin: A neuromorphic hardware co-processor based
Computer Aided Design (ICCAD). IEEE, 2020, pp. 1–9. on spiking neural networks,” Journal of Systems Architecture, vol. 77,
[48] M. Heidarpour, A. Ahmadi, and R. Rashidzadeh, “A cordic based pp. 43–51, 2017.
digital hardware for adaptive exponential integrate and fire neuron,” [69] S. Li, Z. Zhang, R. Mao, J. Xiao, L. Chang, and J. Zhou, “A fast and
IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, energy-efficient snn processor with adaptive clock/event-driven com-
no. 11, pp. 1986–1996, 2016. putation scheme and online learning,” IEEE Transactions on Circuits
[49] E. J. Basham and D. W. Parent, “Compact digital implementation of and Systems I: Regular Papers, vol. 68, no. 4, pp. 1543–1552, 2021.
a quadratic integrate-and-fire neuron,” in 2012 Annual International [70] A. Carpegna, A. Savino, and S. Di Carlo, “Fpga-optimized hard-
Conference of the IEEE Engineering in Medicine and Biology Society. ware acceleration for spiking neural networks,” arXiv preprint
IEEE, 2012, pp. 3543–3548. arXiv:2201.06993, 2022.
[50] A. Nallathambi and N. Chandrachoodan, “Probabilistic spike prop- [71] A. Upegui, C. A. Pena-Reyes, and E. Sanchez, “An fpga platform for
agation for fpga implementation of spiking neural networks,” arXiv on-line topology exploration of spiking neural networks,” Micropro-
preprint arXiv:2001.09725, 2020. cessors and microsystems, vol. 29, no. 5, pp. 211–223, 2005.
[51] W. Fang, Z. Yu, Y. Chen, T. Huang, T. Masquelier, and Y. Tian, “Deep [72] M. J. Pearson, A. G. Pipe, B. Mitchinson, K. Gurney, C. Melhuish,
residual learning in spiking neural networks,” Advances in Neural I. Gilhespy, and M. Nibouche, “Implementing spiking neural networks
Information Processing Systems, vol. 34, 2021. for real-time signal-processing and control applications: A model-
[52] A. Shrestha, H. Fang, D. P. Rider, Z. Mei, and Q. Qiu, “In-hardware validated fpga approach,” IEEE Transactions on Neural Networks,
learning of multilayer spiking neural networks on a neuromorphic vol. 18, no. 5, pp. 1472–1487, 2007.
processor,” in 2021 58th ACM/IEEE Design Automation Conference [73] A. Cassidy, S. Denham, P. Kanold, and A. Andreou, “Fpga based
(DAC). IEEE, 2021, pp. 367–372. silicon spiking neural array,” in 2007 IEEE Biomedical Circuits and
[53] M. Heidarpur, A. Ahmadi, M. Ahmadi, and M. R. Azghadi, “Cordic- Systems Conference. IEEE, 2007, pp. 75–78.
snn: On-fpga stdp learning with izhikevich neurons,” IEEE Transac- [74] D. Thomas and W. Luk, “Fpga accelerated simulation of biologically
tions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. plausible spiking neural networks,” in 2009 17th IEEE symposium on
2651–2661, 2019. field programmable custom computing machines. IEEE, 2009, pp.
[54] S. Gomar and M. Ahmadi, “Digital realization of pstdp and tstdp 45–52.
learning,” in 2018 International Joint Conference on Neural Networks [75] M. Ambroise, T. Levi, S. Joucla, B. Yvert, and S. Saı̈ghi, “Real-
(IJCNN). IEEE, 2018, pp. 1–5. time biomimetic central pattern generators in an fpga for hybrid
[55] Y. Liu, W. Zhang, and P. Li, “Enabling non-hebbian learning in experiments,” Frontiers in neuroscience, vol. 7, p. 215, 2013.
recurrent spiking neural processors with hardware-friendly on-chip [76] K. Cheung, S. R. Schultz, and W. Luk, “Neuroflow: a general pur-
intrinsic plasticity,” IEEE Journal on Emerging and Selected Topics pose spiking neural network simulation platform using customizable
in Circuits and Systems, vol. 9, no. 3, pp. 465–474, 2019. processors,” Frontiers in neuroscience, vol. 9, p. 516, 2016.
[56] Y. Chen, Z. Yu, W. Fang, T. Huang, and Y. Tian, “Pruning of deep [77] S. Gupta, A. Vyas, and G. Trivedi, “Fpga implementation of simplified
spiking neural networks through gradient rewiring,” arXiv preprint spiking neural network,” in 2020 27th IEEE International Conference
arXiv:2105.04916, 2021. on Electronics, Circuits and Systems (ICECS). IEEE, 2020, pp. 1–4.
[57] S. Mittal, “A survey of fpga-based accelerators for convolutional neural [78] H. Asgari, B. M.-N. Maybodi, M. Payvand, and M. R. Azghadi, “Low-
networks,” Neural computing and applications, vol. 32, no. 4, pp. energy and fast spiking neural network for context-dependent learning
1109–1139, 2020. on fpga,” IEEE Transactions on Circuits and Systems II: Express Briefs,
[58] X. Ju, B. Fang, R. Yan, X. Xu, and H. Tang, “An fpga implementation vol. 67, no. 11, pp. 2697–2701, 2020.
of deep spiking neural networks for low-power and fast classification,” [79] H. Fang, A. Shrestha, D. Ma, and Q. Qiu, “Scalable noc-based
Neural computation, vol. 32, no. 1, pp. 182–204, 2020. neuromorphic hardware learning and inference,” in 2018 International
[59] J. Park, J. Lee, and D. Jeon, “7.6 a 65nm 236.5 nj/classification joint conference on neural networks (IJCNN). IEEE, 2018, pp. 1–8.
neuromorphic processor with 7.5% energy overhead on-chip learning [80] E. Cerezuela-Escudero, A. Jimenez-Fernandez, R. Paz-Vicente, J. P.
using direct spike-only feedback,” in 2019 IEEE International Solid- Dominguez-Morales, M. J. Dominguez-Morales, and A. Linares-
State Circuits Conference-(ISSCC). IEEE, 2019, pp. 140–142. Barranco, “Sound recognition system using spiking and mlp neural
[60] F. N. Buhler, P. Brown, J. Li, T. Chen, Z. Zhang, and M. P. Flynn, “A networks,” in International Conference on Artificial Neural Networks.
3.43tops/w 48.9pj/pixel 50.1nj/classification 512 analog neuron sparse Springer, 2016, pp. 363–371.
coding neural network with on-chip learning and classification in 40nm [81] C. Gao, S. Braun, I. Kiselev, J. Anumula, T. Delbruck, and S.-C. Liu,
cmos,” in 2017 Symposium on VLSI Circuits, 2017, pp. C30–C31. “Real-time speech recognition for iot purpose using a delta recurrent
[61] J. K. Kim, P. Knag, T. Chen, and Z. Zhang, “A 640m pixel/s 3.65 mw neural network accelerator,” in 2019 IEEE International Symposium on
sparse event-driven neuromorphic object recognition processor with on- Circuits and Systems (ISCAS). IEEE, 2019, pp. 1–5.
JOURNAL OF LATEX CLASS FILES, VOL. 18, NO. 9, JUNE 2023 14

[82] B. Glackin, J. Harkin, T. M. McGinnity, L. P. Maguire, and Q. Wu, [101] Z. Wan, Y. Zhang, A. Raychowdhury, B. Yu, Y. Zhang, and S. Liu, “An
“Emulating spiking neural networks for edge detection on fpga hard- energy-efficient quad-camera visual system for autonomous machines
ware,” in 2009 International Conference on Field Programmable Logic on fpga platform,” in 2021 IEEE 3rd International Conference on
and Applications. IEEE, 2009, pp. 670–673. Artificial Intelligence Circuits and Systems (AICAS). IEEE, 2021,
[83] L.-C. Caron, F. Mailhot, and J. Rouat, “Fpga implementation of a spik- pp. 1–4.
ing neural network for pattern matching,” in 2011 IEEE International [102] S. Murray, W. Floyd-Jones, Y. Qi, G. Konidaris, and D. J. Sorin, “The
Symposium of Circuits and Systems (ISCAS). IEEE, 2011, pp. 649– microarchitecture of a real-time robot motion planning accelerator,” in
652. 2016 49th Annual IEEE/ACM International Symposium on Microar-
[84] M. A. Bhuiyan, R. Jalasutram, and T. M. Taha, “Character recognition chitecture (MICRO). IEEE, 2016, pp. 1–12.
with two spiking neural network models on multicore architectures,” in [103] T. V. Nhu and H. Sawada, “Cerebellum-like neural network for
2009 IEEE Symposium on Computational Intelligence for Multimedia short-range timing function of a robotic speaking system,” in 2017
Signal and Vision Processing. IEEE, 2009, pp. 29–34. 3rd International Conference on Control, Automation and Robotics
[85] M. A. Nuno-Maganda, M. Arias-Estrada, C. Torres-Huitzil, H. H. (ICCAR). IEEE, 2017, pp. 184–187.
Avilés-Arriaga, Y. Hern’ndez-Mier, and M. Morales-Sandoval, “A hard- [104] M. Mokhtar, D. M. Halliday, and A. M. Tyrrell, “Autonomous naviga-
ware architecture for image clustering using spiking neural networks,” tional controller inspired by the hippocampus,” in 2007 International
in 2012 IEEE Computer Society Annual Symposium on VLSI. IEEE, Joint Conference on Neural Networks. IEEE, 2007, pp. 813–818.
2012, pp. 261–266. [105] J. P. Mitchell, G. Bruer, M. E. Dean, J. S. Plank, G. S. Rose, and
[86] T. Iakymchuk, A. Rosado-Munoz, M. Bataller-Mompean, J. Guerrero- C. D. Schuman, “Neon: Neuromorphic control for autonomous robotic
Martı́nez, J. Francés-Villora, M. Wegrzyn, and M. Adamski, navigation,” in 2017 IEEE International Symposium on Robotics and
“Hardware-accelerated spike train generation for neuromorphic image Intelligent Sensors (IRIS). IEEE, 2017, pp. 136–142.
and video processing,” in 2014 IX Southern Conference on Pro- [106] D. Roggen, S. Hofmann, Y. Thoma, and D. Floreano, “Hardware
grammable Logic (SPL). IEEE, 2014, pp. 1–6. spiking neural network with run-time reconfigurable connectivity in an
[87] R. J. Sofatzis, S. Afshar, and T. J. Hamilton, “Rotationally invariant autonomous robot,” in NASA/DoD Conference on Evolvable Hardware,
vision recognition with neuromorphic transformation and learning 2003. Proceedings. IEEE, 2003, pp. 189–198.
networks,” in 2014 IEEE International Symposium on Circuits and [107] A. P. Johnson, J. Liu, A. G. Millard, S. Karim, A. M. Tyrrell, J. Harkin,
Systems (ISCAS). IEEE, 2014, pp. 469–472. J. Timmis, L. J. McDaid, and D. M. Halliday, “Homeostatic fault
[88] Z. Kuang, J. Wang, S. Yang, G. Yi, B. Deng, and X. Wei, “Digital tolerance in spiking neural networks: a dynamic hardware perspective,”
implementation of the spiking neural network and its digit recognition,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65,
in 2019 Chinese Control And Decision Conference (CCDC). IEEE, no. 2, pp. 687–699, 2017.
2019, pp. 3621–3625. [108] E. I. Guerra-Hernandez, A. Espinal, P. Batres-Mendoza, C. H. Garcia-
[89] L. Lu and Y. Liang, “Spwa: An efficient sparse winograd convolutional Capulin, R. D. J. Romero-Troncoso, and H. Rostro-Gonzalez, “A fpga-
neural networks accelerator on fpgas,” in Proceedings of the 55th based neuromorphic locomotion system for multi-legged robots,” IEEE
Annual Design Automation Conference, 2018, pp. 1–6. Access, vol. 5, pp. 8301–8312, 2017.
[90] Y. LeCun, “The mnist database of handwritten digits,” http://yann. [109] T. Spyrou, S. El-Sayed, E. Afacan, L. Camuñas-Mesa, B. Linares-
lecun. com/exdb/mnist/, 1998. Barranco, and H.-G. Stratigopoulos, “Reliability analysis of a spiking
[91] Q. X. Wu, X. Liao, X. Huang, R. Cai, J. Cai, and J. Liu, “Development neural network hardware accelerator,” in Design, Automation and Test
of fpga toolbox for implementation of spiking neural networks,” in in Europe Conference (DATE), 2022.
2015 Fifth International Conference on Communication Systems and [110] A. Ussa, C. S. Rajen, D. Singla, J. Acharya, G. F. Chuanrong,
Network Technologies. IEEE, 2015, pp. 806–810. A. Basu, and B. Ramesh, “A hybrid neuromorphic object tracking
[92] J. Liu, J. Harkin, L. McDaid, S. Karim, A. G. Millard, J. Hilder, and classification framework for real-time systems,” arXiv preprint
S. Hickinbotham, A. P. Johnson, J. Timmis, D. M. Halliday et al., “Bio- arXiv:2007.11404, 2020.
inspired anomaly detection for low-cost gas sensors,” in 2018 IEEE [111] C. Ding, Y. Huan, H. Jia, Y. Yan, F. Yang, L. Liu, M. Shen, Z. Zou, and
18th International Conference on Nanotechnology (IEEE-NANO). L. Zheng, “A hybrid-mode on-chip router for the large-scale fpga-based
IEEE, 2018, pp. 1–4. neuromorphic platform,” IEEE Transactions on Circuits and Systems
[93] R. Guerrero-Rivera and T. C. Pearce, “Attractor-based pattern classifi- I: Regular Papers, 2022.
cation in a spiking fpga implementation of the olfactory bulb,” in 2007 [112] X. Lagorce, E. Stromatias, F. Galluppi, L. A. Plana, S.-C. Liu, S. B.
3rd International IEEE/EMBS Conference on Neural Engineering. Furber, and R. B. Benosman, “Breaking the millisecond barrier on
IEEE, 2007, pp. 593–599. spinnaker: implementing asynchronous event-based plastic models with
[94] M. Sharifshazileh, K. Burelo, J. Sarnthein, and G. Indiveri, “An elec- microsecond resolution,” Frontiers in neuroscience, vol. 9, p. 206,
tronic neuromorphic system for real-time detection of high frequency 2015.
oscillations (hfo) in intracranial eeg,” Nature communications, vol. 12, [113] M. Davies, N. Srinivasa, T.-H. Lin, G. Chinya, Y. Cao, S. H. Choday,
no. 1, pp. 1–14, 2021. G. Dimou, P. Joshi, N. Imam, S. Jain et al., “Loihi: A neuromorphic
[95] A. Rana and K. K. Kim, “Fpga implementation of an artificial in- manycore processor with on-chip learning,” Ieee Micro, vol. 38, no. 1,
telligence signal recognition system,” Journal of Sensor Science and pp. 82–99, 2018.
Technology, vol. 31, no. 1, pp. 16–23, 2022. [114] S. Ullah, S. Rehman, M. Shafique, and A. Kumar, “High-performance
[96] A. Jimenez-Fernandez, G. Jimenez-Moreno, A. Linares-Barranco, M. J. accurate and approximate multipliers for fpga-based hardware accel-
Dominguez-Morales, R. Paz-Vicente, and A. Civit-Balcells, “A neuro- erators,” IEEE Transactions on Computer-Aided Design of Integrated
inspired spike-based pid motor controller for multi-motor robots with Circuits and Systems, pp. 1–1, 2021.
low cost fpgas,” Sensors, vol. 12, no. 4, pp. 3831–3856, 2012. [115] S. Nambi, S. Ullah, S. S. Sahoo, A. Lohana, F. Merchant, and
[97] M. Jalilian, M. Nouri, A. Ahmadi, and N. Kandalaft, “Pulse width mod- A. Kumar, “¡italic¿expan(n)d¡/italic¿: Exploring posits for efficient
ulation (pwm) signals using spiking neuronal networks,” in 2017 IEEE artificial neural network design in fpga-based systems,” IEEE Access,
International Conference on Signal and Image Processing Applications vol. 9, pp. 103 691–103 708, 2021.
(ICSIPA). IEEE, 2017, pp. 180–184. [116] F. Fahim, B. Hawks, C. Herwig, J. Hirschauer, S. Jindariani,
[98] M. V. Kotlyarevskaya, A. A. Zhilenkov, and L. O. Slepova, “Control of N. Tran, L. P. Carloni, G. D. Guglielmo, P. C. Harris, J. D. Krupa,
an actuator in the motion prosthetics device by signals of biological ner- D. S. Rankin, M. B. Valentin, J. D. Hester, Y. Luo, J. Mamish,
vous system,” in 2018 IEEE Conference of Russian Young Researchers S. Orgrenci-Memik, T. Aarrestad, H. Javed, V. Loncar, M. Pierini,
in Electrical and Electronic Engineering (EIConRus). IEEE, 2018, A. A. Pol, S. Summers, J. M. Duarte, S. Hauck, S. Hsu, J. Ngadiuba,
pp. 894–897. M. Liu, D. Hoang, E. Kreinar, and Z. Wu, “hls4ml: An open-source
[99] A. Linares-Barranco, F. Perez-Peña, A. Jimenez-Fernandez, and codesign workflow to empower scientific low-power machine learning
E. Chicca, “Ed-biorob: a neuromorphic robotic arm with fpga-based devices,” CoRR, vol. abs/2103.05579, 2021. [Online]. Available:
infrastructure for bio-inspired spiking motor controllers,” Frontiers in https://arxiv.org/abs/2103.05579
neurorobotics, p. 96, 2020. [117] G. D. Guglielmo, J. M. Duarte, P. C. Harris, D. Hoang, S. Jindariani,
[100] T. Gao, Z. Wan, Y. Zhang, B. Yu, Y. Zhang, S. Liu, and A. Raychowd- E. Kreinar, M. Liu, V. Loncar, J. Ngadiuba, K. Pedro, M. Pierini, D. S.
hury, “Ielas: An elas-based energy-efficient accelerator for real-time Rankin, S. Sagear, S. Summers, N. Tran, and Z. Wu, “Compressing
stereo matching on fpga platform,” in 2021 IEEE 3rd International deep neural networks on fpgas to binary and ternary precision with
Conference on Artificial Intelligence Circuits and Systems (AICAS). HLS4ML,” CoRR, vol. abs/2003.06308, 2020. [Online]. Available:
IEEE, 2021, pp. 1–4. https://arxiv.org/abs/2003.06308
JOURNAL OF LATEX CLASS FILES, VOL. 18, NO. 9, JUNE 2023 15

[118] F. Fahim, B. Hawks, C. Herwig, J. Hirschauer, S. Jindariani, N. Tran,

L. Carloni, G. D. Guglielmo, P. Harris, J. Krupa, D. Rankin, M. B.
Valentin, J. Hester, Y. Luo, J. Mamish, S. Memik, T. Aarrestad,
H. Javed, V. Loncar, M. Pierini, A. A. Pol, S. Summers, J. Duarte,
S. Hauck, S.-C. Hsu, J. Ngadiuba, M. Liu, D. Hoang, E. Kreinar,
and Z. Wu, “hls4ml: An open-source co-design workflow to
empower scientific low-power machine learning devices,” in Research
Symposium on Tiny Machine Learning, 2021. [Online]. Available:
https://openreview.net/forum?id=YBFqldo30vG
[119] Y. Umuroglu, N. J. Fraser, G. Gambardella, M. Blott, P. Leong,
M. Jahre, and K. Vissers, “Finn: A framework for fast, scalable
binarized neural network inference,” in Proceedings of the 2017
ACM/SIGDA international symposium on field-programmable gate
arrays, 2017, pp. 65–74.
[120] M. Blott, T. B. Preußer, N. J. Fraser, G. Gambardella, K. O’brien,
Y. Umuroglu, M. Leeser, and K. Vissers, “Finn-r: An end-to-end
deep-learning framework for fast exploration of quantized neural net-
works,” ACM Transactions on Reconfigurable Technology and Systems
(TRETS), vol. 11, no. 3, pp. 1–23, 2018.
[121] V. Rybalkin, A. Pappalardo, M. M. Ghaffar, G. Gambardella, N. Wehn,
and M. Blott, “Finn-l: Library extensions and design trade-off analysis
for variable precision lstm networks on fpgas,” in 2018 28th interna-
tional conference on field programmable logic and applications (FPL).
IEEE, 2018, pp. 89–897.
[122] Y. Kim, Y. Li, H. Park, Y. Venkatesha, and P. Panda, “Neural
architecture search for spiking neural networks,” CoRR, vol.
abs/2201.10355, 2022. [Online]. Available: https://arxiv.org/abs/2201.
10355
[123] E. Mueller, V. Studenyak, D. Auge, and A. Knoll, “Spiking transformer
networks: A rate coded approach for processing sequential data,” in
2021 7th International Conference on Systems and Informatics (ICSAI),
2021, pp. 1–5.
[124] Z. Zhu, J. Peng, J. Li, L. Chen, Q. Yu, and Z. Zheng,
“Spiking graph convolutional networks,” 2022. [Online]. Available:
https://openreview.net/forum?id=Ul3o26VB6KZ
[125] M. Xu, Y. Wu, L. Deng, F. Liu, G. Li, and J. Pei, “Exploiting
spiking dynamics with spatial-temporal feature normalization in graph
learning,” CoRR, vol. abs/2107.06865, 2021. [Online]. Available:
https://arxiv.org/abs/2107.06865