Computer Organization

Computer Function and

Interconnection
Dr. Khalil Al-Shqeerat
QU/CS

1
Introduction
Buses 4531
The Control Unit (an instruction interpreter) and
the Arithmetic and Logic Unit constitute the
Central Processing Unit
Data and instructions need to get into the system
and results out
Input/output
Revie out inp É
Input module: contains basic components for
2
I
accepting data and instructions in some form and
converting them into an internal form of signals usable
by the system.
y on s y 6AMA E I W Ba fro's
input output 2
Cont.
W
An input device will bring instructions and data
in sequentially. But a program is not invariably
executed sequentially.
Operations on data may require access to more
than just one element at a time in a
predetermined sequence. E WI W IN yo
There must be a place to store temporarily both
instruction, data and results.
Main memory (to distinguish it from external storage).
ta
3
Registers
G B's Cpu my
Use two internal registers to exchange data
between CPU and memory: O d
N W H
MAR: which specifies the address in memory for the
next read or write. J o I K E N d
Ifl
MBR: which contains the data to be written into
memory or receives from memory.
Use two internal registers to exchange data
between CPU and I/O modules:
adores
I/O AR: which specifies a particular I/O device. g
go
I/O BR: used to exchange data
twain
I 4
Memory and I/O Modules

A memory module consists of a set of locations,

defined by sequentially numbered addresses.
Each location contains binary number that can be
interpreted as either an instruction or data.
An I/O module transfers data from external
devices to CPU and memory, and vice versa. twist
It contains internal buffers for temporarily holding this
data until it can be sent on.

5
Top-Level View

pointer

o est III
tax

artnimatic

go
6
Computer Function

The basic function performed by a computer is

execution of a program, which consists of a
set of instructions stored in memory.
can bet timing
The processor does the actual work by executing
instructions specified in the program.
Instruction processing consists of two steps:
The processor reads (fetches) instructions from
memory one at a time, (fetch cycle),
and executes each instruction, (execute cycle).
9
7
Instruction Cycle

Program execution consists of repeated process of

instruction fetch and instruction execution.
The instruction execution may involve several operations
and depends on the nature of the instruction.

Basic Instruction Cycle

8
Fetch Cycle

Program Counter (PC) holds address of next

instruction to fetch.
Processor fetches an instruction from memory
location where the PC is pointing.
Increment PC: The processor increment the PC after
each instruction fetch.
Instruction loaded into Instruction Register (IR)
The instruction contains bits that specify the action
which the processor is to take.
Processor interprets instruction and performs
required actions.
9
General actions:

Processor-memory
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processing Tx e o g É
Perform some arithmetic yor logical operation on data
Control
Alteration of sequence of operations, e.g. jump
Combination of above
10
The Fetch-Execute Cycle

11
 É É
Interrupts

Mechanism by which other modules (e.g. I/O)

may interrupt normal sequence of processing.
It improves processing efficiency. 241881 is
It allows the processor to execute other
instructions while an I/O operation is in progress.
A suspension of a process caused by an event
external to that process and performed in such a
way that the process can be resumed.

12
Classes of interrupts
fo 25 E g p ti ie
Program: Generated by some condition that occurs as a
result of an instruction execution, e.g. overflow, division
by zero, execute illegal instruction..
Timer: Generated by internal processor timer.
- Allows the OS to perform certain functions. 82km1
03
- Used in pre-emptive multi-tasking.
I/O: By I/O controller, to signal normal completion of an
operation, or to signal a variety of error conditions.
Hardware failure: e.g. power failure.
in D 51.3
is 26 13
Program Flow Control Type of interrap
I

14
Program Timing:

Short I/O Wait Long I/O Wait

15
Interrupt Cycle
Added to instruction cycle
Processor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context
Set PC to start address of interrupt handler routine
Process interrupt
Restore context and continue interrupted program
16
 Instruction Cycle with Interrupts

tax mil
Fet in
Ex cut

interred in

17
Interrupt Handler th'd

A program that determines nature of the

interrupt and performs whatever actions are
needed.
Control is transferred to this program.
The interrupt handler program is generally part
of the operating system.
When the interrupt service routine (interrupt
handler) is completed, the processor can
resume execution of the user program at the
point of interruption.
18
Multiple Interrupts

Disable interrupts
Processor will ignore further interrupts whilst
processing one interrupt oxW65Ut1
Interrupts remain pending and are checked after first

imwW
interrupt has been processed
Interrupts handled in sequence as they occur
Define priorities a did Mia
Low priority interrupts can be interrupted by higher
priority interrupts
When higher priority interrupt has been processed,
processor returns to previous interrupt 19
 type of multipl interrupt

Multiple Interrupts - Sequential

20
Multiple Interrupts - Nested

21
Time Sequence of Multiple Int.

22
Interconnection structures

A computer consists of a set of components

(Memory, Input/Output, CPU) that communicate
with each other.
There must be paths for connecting these modules.
The collection of paths connecting the various
modules is called Interconnection structures.
The design of this structure will depend on the
exchanges that must be made between modules.

23
 Memory Connection
w MJ
A memory module consists of N words of equal
length.
Each word is assigned a unique numerical address.
A word of data can be read from or written into the
0 memory.
25
The nature of the operation is indicated by read
and write control signals.
The location for the operation is specified by an
address. I 3
i i
035 Z
3
g 24
Input/Output Connection
w ik
Similar to memory from computer’s viewpoint
There are two operations: read and write.
An I/O module may control more than one
external device.
We can refer to each of the interfaces to an external
device as a port and give each a unique address.
There external data paths for the input and output of
data with an external device.
An I/O module may be able to send interrupt
signals to the processor.

25
CPU Connection

Reads instruction and data

Writes out data (after processing)
Sends control signals to other units (to control the
overall operation of the system).
Receives (& acts on) interrupts

26
 Computer modules

gotta
t

go I
wid E's

27
Interconnection structures

The interconnection structure must support the

following types of transfers:
Memory to processor: the processor reads an
instruction or a unit of data from memory.
processor to Memory: the processor writes a unit of
data to memory.
I/O to processor: the processor reads data from an
I/O device.
processor to I/O: the processor sends data to it.
I/O to or from memory: an I/O module is allowed to
exchange data directly with memory using DMA.

28
What is a Bus?

A communication pathway connecting two or

more devices
It is a shared transmission medium.
Usually broadcast
Multiple devices connect to the Bus, and a signal
transmitted by any one device is available for
reception by all other devices attached to the bus.
Only one device at a time can successfully transmit.
Often grouped (number of channels in one bus).
A bus consists of multiple communication pathways.
29
Bus interconnection
I Bite
Each line is capable of transmitting signals
representing binary number (1,0).
Several lines of a bus can be used to transmit binary
digits in parallel. e.g. 32 bit data bus is 32 separate
single bit channels.
Computer systems contain a number of different buses
that provide pathways between components at various
levels of computer system hierarchy.
A bus that connects major computer components
(CPU, Memory, I/O) is called a system bus.
System bus consists of from 50-100 separate lines.
Each line is assigned a function.
30
Bus Structure

There are many different bus designs.

On any bus the lines can be classified into three
functional groups: Data, Address, Control lines.
There may be power distribution lines that supply
power to the attached modules.

Bus Interconnection Scheme

31
Data Bus

Data bus (lines) provide a path for moving data

between system modules.
The data bus consists of 8,16,32,64 separate lines
The number of lines being referred to as the width of
the data bus.
Each line can carry only 1 bit at a time. e.g. A 32 bit data
bus means that it can fetch 4 bytes (32 bits) of data from memory.
The number of lines determines how many bits can be
transferred at a time.
Width is a key determinant of performance. e.g. if the data
bus is 8 bits wide and each instruction is 16 bits long, then the processor
must access the memory twice during each instruction cycle. 32
Address bus

Identify the source or destination of data

e.g. CPU needs to read a word from memory, it puts
the address of the desired word on the address line.
The width (number of bits) of address bus
determines the maximum size of memory which
the processor can access.
If the address bus contains n electrical lines, the
processor can uniquely address up to 2^n bytes.
e.g. a Pentium has 32 bit address bus giving 4GB maximum
addressability.
The speed of the address bus is the same as the data
bus it is matched to.
33
Control Bus

Used to control the access to and the use of the

data and address lines.
Because the data and address lines are shared by all
components, there must be a mean of controlling
their use.
Control signals transmit both command and
timing information between system modules.
Timing signals indicate the validity of data and
address information.
Command signals specify operations to be performed

34
Control Bus (2)

control lines include the following:

É data on the bus to be written
Memory write: causes
into the addressed location.
Memory read: causes M data from the addressed
location to be placed on the bus.
I/O write: causes data on the bus to be output to the
addressed I/O port. t y
i
I/O read: causes data from the addressed I/O port to
be placed on the bus. t
in
Transfer ACK: indicates that data have been accepted
I from or placed on the bus.
p 35
we
ow 3
read write control

Control Bus (3)

2w w Ks w
Bus request: indicates that a modules needs to gain
control of the bus.
EmBusMia
grant: indicates that a requesting modules has
been granted control of the bus.
it's it a
Interrupt request: indicates that an interrupt is
pending
2 W wa
Interrupt ACK: acknowledges that the pending
interrupt has been recognized.
i g Clock: used to synchronize operations.
jj Reset: Initializes all modules. oik'd w
W 00 s A
in
36
The operation of the Bus
of
d
If one module wishes to send data
obtain the use of the bus. É
ont ye's 4143
2 transfer data via the bus. obtain ok'd
askmemor
If one module wishes to request data tosenddo
obtain the use of the bus. an

transfer request to the other module over the control

and address lines, then wait for that second module
to send the data.
then read
At
wait memory
lose my data
37
Reference

William Stallings, “Computer Organization and

Architecture Designing for Performance”, 10th
Edition. Pearson Education, Inc., 2016.

38