IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO.

4, AUGUST 2002 739

A Multilevel Inverter Approach Providing DC-Link

Balancing, Ride-Through Enhancement, and
Common-Mode Voltage Elimination
Annette von Jouanne, Senior Member, IEEE, Shaoan Dai, Student Member, IEEE, and Haoran Zhang, Member, IEEE

Abstract—This paper presents a simple control method for

balancing the dc-link voltage of three-level neutral-point-clamped
inverters, while providing enhanced ride-through and
common-mode voltage (CMV) elimination. The method uses
dc–dc converter technology on the dc link for balancing and
ride-through enhancement, and a modified pulsewidth-modula-
tion switching algorithm for CMV elimination. Simulation and
experimental results are supplied to confirm the validity of the
proposed method, which includes full digital signal processor
control.
Index Terms—Common-mode voltage, multilevel inverter, neu-
tral-point voltage.

I. INTRODUCTION

I N RECENT YEARS, there has been great interest in mul-

tilevel inverter (MLI) technology, including three-level neu-
tral-point-clamped (NPC) voltage-source inverters (VSIs) [1].
There are many advantages in the application of three-level NPC Fig. 1. DC bus and inverter circuit of the NPC VSI.
inverters over conventional two-level inverters. MLIs can reduce
harmonics in the output voltage and current due to the multi-
ence signals in order to control the dc-link voltage was given
level output voltage. Furthermore, NPC inverters are especially
in [2]. A variant of the space-vector PWM method which uses
suitable for high-power and high-voltage applications because
the sequence and the time distribution of the voltage vectors
the voltage across the switches is half that of conventional in-
was proposed in [3]. In [4], the selected voltage-vector method
verters. However, excessively high voltages may be applied to
for space-vector PWM to maintain the NP voltage is verified.
the switches while the neutral-point (NP) voltage varies from the
An analytical method for the analysis of the NP voltage vari-
center of the dc-link voltage [2]–[8]. In addition, the unbalance
ation and the dc-link capacitor design are proposed in [5]. A
in the dc-link NP voltage can cause significant distortion in the
closed-loop control method and its stability analysis for main-
output voltage during startup, to the point of preventing proper
taining the NP voltage of the dc-link voltage are given in [6].
startup operation. Standard MLIs also have the similar draw-
In [7], the authors proposed a zero-voltage-switching scheme to
backs of two-level inverters in that they generate common-mode
reduce the switching loss and balance the NP voltage variation.
voltage (CMV) and have ride-through concerns during fluctua-
In all of these approaches, the MLI continues to generate poten-
tions in the input voltage [9]–[11].
tially damaging CMV, and the ride-through concerns exist.
Fig. 1 shows the main circuit of the NPC VSI. The NP voltage
From the discussion above, [2], [5], and [6] are carrier-based
balancing problem of the three-level NPC VSI has been widely
PWM methods which are based on inducing some form of the
studied in recent years. Various methods have been proposed to
output zero-sequence voltage to balance the dc-link bus voltage.
maintain the center voltage of the dc link in references [2]–[8]
The NP voltage control for the space-vector modulation (SVM)
with a goal of reducing the NP voltage ripple to less than 1%
in [3] and [4] are based on using the selected output voltage
of the dc-link voltage. A modified sinusoidal pulsewidth mod-
space vectors to reduce the variation of the NP voltage. A further
ulation (SPWM) method of injecting NP voltage to the refer-
study of NP voltage control using redundant space vectors was
given in [8]. In [8], the authors showed the control over the NP
Manuscript received July 12, 2001; revised January 1, 2002. Abstract pub- current is limited at given modulation indexes and load power
lished on the Internet May 16, 2002.
A. von Jouanne and S. Dai are with the Department of Electrical and Com- factors. In addition, NP balancing and CMV cancellation cannot
puter Engineering, Oregon State University, Corvallis, OR 97331-3211 USA be achieved concurrently. The NP voltage low-frequency ripple
(e-mail: [email protected]; [email protected]). is decided by the size of the dc-link capacitors and the load
H. Zhang is with Texas Instruments Incorporated, Tucson, AZ 85706 USA
(e-mail: [email protected]). conditions under different modulation indexes and power-factor
Publisher Item Identifier 10.1109/TIE.2002.801233. angles.
0278-0046/02$17.00 © 2002 IEEE
740 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

regulating the voltage of one of the two split capacitors on the

dc link. When the switch turns on, the current to charge
flows from to to . When is off, the energy stored in
is transmitted to through the , , and loop. Note
that the described buck circuit is used to regulate . A PWM
method is used to control the voltage of .
In the boost dc–dc mode , the buck converter
does not operate. In this mode, the energy in capacitor is
indirectly transferred to capacitor because . The
current flows from , , and to ground. The energy is
stored in when the switch is on. When the switch is
off, the energy stored in is transmitted into through .
Thus, during this period, the balancing voltage is controlled by
regulating the voltage of . When is equal to half of ,
the variation of the NP voltage is zero.

C. Design of the Parameters of the Circuit

Because the maximum NP current is nearly equal to the in-
verter output current [5], in the worst case condition, the current
rating of the two additional switching devices is the same as the
rating of the multilevel inverter switching devices. The voltage
Fig. 2. Schematic of the NP voltage balancing circuit. rating of the additional switching devices is twice that of the
output switching devices. The size of the inductance and capac-
itance are determined by the voltage ripple requirement across
In this paper, a simple hardware method for balancing the the capacitors. The design process can be referenced to the boost
NP voltage is proposed, that allows enhanced ride-through per- and buck converter design [13].
formance and enables the SPWM algorithm to be modified to
eliminate the CMV. This method can effectively balance the NP D. Reduced-Device Balancing Circuit
voltage without the limitations of modulation methods and load
conditions. It also provides increased ride-through capabilities From Fig. 2, a reduced-device balancing circuit is obtained
for the inverter during input voltage sags, and because of the as shown in Fig. 3, when additional ride-through performance
NP balancing, the necessary size of the dc-bus capacitors is re- is not an issue. In Fig. 3, , , and are eliminated. The
duced. In this paper, both simulation and experimental results feedback diodes of and operate as and in Fig. 2, re-
are supplied to verify the proposed concepts, including full dig- spectively. The performance and operation of the circuit shown
ital signal processor (DSP) control. in Fig. 3 is the same as in Fig. 2. Thus, a simpler balancing cir-
cuit can be applied to the NP voltage control, however, without
increased ride-through capabilities.
II. PRINCIPLE OF OPERATION OF BALANCING CIRCUITS
A. Proposed NP Voltage Balancing Circuit III. NP VOLTAGE AND RIDE-THROUGH CONTROL
The NP voltage balancing topology is shown in Fig. 2. The A modified NP voltage balancing circuit with ride-through
circuit consists of boost and buck converters. In the balancing capabilities is shown in Fig. 4, through the addition of switching
mode, the boost and buck converters work in complementary pe- device . When there is no voltage sag, the switch is on,
riods. and are the dc-link capacitors. , , , and and the modified circuit works as described in Fig. 2. When
consist of a buck dc–dc converter. , , and work in a voltage sag occurs on the supply input that causes to
boost dc–dc converter mode. Note that a similar circuit for two- decrease below the undervoltage protection/trip setting, if no
level inverter ripple reduction was presented in [12] for nuclear additional ride-through operation mode is available, the MLI
magnetic resonance converters. Also, note that with a slight will trip offline. However, with the auxiliary ride-through cir-
modification to the topology in Fig. 2, enhanced ride-through cuit shown in Fig. 4, the switch will turn off and the circuit
performance can be achieved, which will be discussed in Sec- will operate in the ride-through mode as follows. The boost and
tion III. buck converters work together to balance the NP voltage and
maintain the dc-link voltage. The buck converter regulates the
B. Buck DC–DC Mode and Boost DC–DC Mode voltage of the capacitor . The current from flows through
When , the buck circuit ( , , , and ) , , and when switch is on. The energy is stored in
starts to operate and regulate the voltage of the capacitor to and . When the switch is off, the energy in is trans-
maintain the balance of the dc-link voltage. The boost converter ferred to . Meanwhile, the boost converter boosts the energy
does not operate during this period. Because from the capacitor to and regulates the voltage of .
and is constant, the voltage of decreases as increases. Note that the rating of the switching devices used during ride-
Thus, the variation of the NP voltage can be quickly balanced by through operation will be dependent on the desired ride-through
VON JOUANNE et al.: A MULTILEVEL INVERTER APPROACH 741

Fig. 5. Capacitor voltage V (C ), load current I (Phase1), and NP current

I (NP) without NP voltage control.

Fig. 3. Schematic of the NP voltage balancing circuit with reduced devices.

Fig. 6. Capacitor voltage V (C ) ripple without NP control and with NP

voltage control.

since the power is supplied through the lower capacitor .

Thus, and are different from and in order to main-
tain the same voltage ripple of and .

IV. CMV ELIMINATION

The CMV in three-level NPC inverters can be eliminated by
modifying the MLI switching algorithm in such a way that the
states producing CMV are not used [9]. This was proven by the
authors both in simulation and experimentally in [9], showing
very good performance. This paper significantly strengthens
that work by adding the additional features of dc-link balancing
and ride-through enhancement.

V. SIMULATION RESULTS
Fig. 4. Modified schematic of the NP voltage balancing circuit with
ride-through capabilities. A. Simulation Results of the Conventional PWM NPC VSI
The PSpice simulation results of the proposed MLI driving
performance. Furthermore, the size of the inductor and the a 10-hp load (460-V ac line input) are shown in Figs. 5–8 for
capacitor are determined by the voltage and current ripple, conventional SPWM NPC VSIs.
742 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

Fig. 7. Current waveform of the inductors of the NP voltage control circuit.

Fig. 9. CMV waveforms under the conventional SPWM, the

CMV-cancellation SPWM, one-phase current of the load, and the voltage of
one capacitor without NP control.

Fig. 8. Total dc-link voltage during a 40% single-phase sag, the differential
voltage of the two capacitors, the load current, and one of the controller inductor
current waveforms of the simulation with NP control in ride-through mode.

From Fig. 5, the dc-link capacitor voltage ripple is 4.8%. With Fig. 10. CMV waveform and the voltage waveform of one capacitor for the
proposed NP balancing scheme with CMV cancellation.
the proposed control techniques, the capacitor voltage ripple
is reduced to no more than 0.7% of the capacitor voltage as
shown in Fig. 6. Note that the capacitor voltage ripple (which B. Simulation Results With CMV Cancellation Implementation
is as large as the NP ripple) is controlled by the boost and buck Again, the modified PWM techniques used in this paper for
dc–dc converters. the cancellation of CMV in NPC inverters were presented and
The boost and buck converters operate in different intervals proven in [9]. The variation of the NP voltage with CMV-can-
in the proposed balancing scheme, as shown in Fig. 7. The cur- cellation SPWM is similar to that with conventional SPWM.
rent through is shown with the solid curve while The NP current variation is related to the output load and un-
is shown as the dashed curve. The maximum current of the con- balanced impedance variation.
verter’s switching device is decided by the converter inductance Fig. 9 shows the CMV of the conventional NPC inverter and
and the variation of the NP current. Note that is shown for the modified NPC inverter with CMV-cancellation SPWM. The
clarity. nonzero CMV during the modified SPWM operation is due to
Fig. 8 shows the voltage and current waveforms of the NP the variation in the NP voltage. The resulting load current under
voltage controller working in the ride-through mode. During CMV-cancellation SPWM is shown in Fig. 9. In addition, the
an example 40% single-phase voltage sag, the rectifier output capacitor voltage under CMV-cancellation SPWM is shown in
voltage is shown to be reduced to 520 . However, because Fig. 9.
the voltage of each capacitor is regulated to 310 V , the total The CMV and capacitor voltage with the proposed NP bal-
dc-link voltage is maintained at 620 V during the sag. Note ancing technique and CMV-cancellation SPWM is shown in
that the differential voltage of the two capacitors is . Fig. 10. Note the significant reduction in the CMV and capac-
Thus, the voltage variation about the NP voltage itor ripple with the proposed scheme. Fig. 11 shows the dc-link
is half of the varying magnitude shown in the second waveform voltage, the capacitor differential voltage, the load current, and
of Fig. 8. one controller inductor current in the ride-through and balancing
When the sag occurs, the boost and buck converters will both operation mode with CMV cancellation. Similar to the conven-
operate. The current waveform of one of the converter inductors tional SPWM, the NP voltage variation is half of the differential
is the fourth curve shown in Fig. 8. voltage of the two capacitors shown in Fig. 11.
VON JOUANNE et al.: A MULTILEVEL INVERTER APPROACH 743

Fig. 12. MLI line-to-line output voltage.

(ESR) of the output capacitor. The inductance and capacitance

are determined by the maximum NP current and voltage ripple
requirements, and are defined as follows:

(1)
Fig. 11. Total dc-link voltage, the differential voltage of the two capacitors,
the load current, and one controller inductor current with NP control and CMV (2)
cancellation during ride-through.

The details of the filter design process are described in [13]. For
VI. EXPERIMENTAL RESULTS simplicity, and .
A. Experimental System The reference NP voltage is obtained by . The
voltages across and are monitored and compared with the
An experimental prototype of the proposed three-level
reference NP voltage to obtain the voltage errors used to control
NPC inverter has been built and experimentally tested as an
the voltages across and . Note, a dead-band error voltage
adjustable-speed drive (ASD) for an induction motor load. The
of 5 V was set for the controllers.
prototype design is rated at 5 kVA to drive a 5-hp motor at a
The efficiency of the proposed additional circuit is high [12]
three-phase line voltage of 460 V, and employs insulated gate
because of the buck and boost topologies used. As detailed in
bipolar transistors (IGBTs). The MLI switching frequency is 5
[13], the efficiency of the buck converter is as follows:
kHz and the balancing circuit switching frequency is 10 kHz.
The fundamental output frequency can be varied from 6 to 60
(3)
Hz and the modulation index can be varied from 0.3 to 1.0.
The control signals for the inverter system are obtained using
a Texas Instruments TMS320F240 DSP. The TMS320F240 where is the output voltage, is the dc-bus voltage,
is a fixed-point 16-b low-cost DSP, incorporating a 20-MIPS is the switching device rise or fall time constant, and is the
processor designed specifically for motor drive applications. A switching period of the converter. From (3), the efficiency ap-
Tektronix TDS7104 Digital Phosphor Oscilloscope was used proaches 90%.
to capture all of the experimental waveforms. Again, while the proposed approach does add additional cir-
The buck and boost control loop designs are based on reg- cuitry and complexity to the MLI hardware, as detailed in Sec-
ular buck and boost controller design rules. The controllers are tions II and III, with the NP balanced, the necessary size of the
realized by software in the DSP controller. The sample rate for dc-bus capacitors can be reduced. The dc-link capacitance can
the two controllers is 10 ksamples/s. The neutral voltage ripple be calculated by [5]
frequency is the third harmonic of the output frequency. For the
maximum output frequency of 60 Hz, the maximum frequency (4)
of the NP voltage variation is 180 Hz. Considering the multi-
level inverter switching frequency of 5 kHz, the control band- where is the maximum current flow to or from the NP,
width was selected to be 900 Hz (five times the maximum fre- is the frequency of the NP voltage, and
quency of the NP voltage variation and close to one-fifth of is the maximum variation voltage of the NP. For example, for
the MLI switching frequency). This can supply a fast enough a 5-kVA 460-V 6.3-A inverter, Hz Hz ,
response for the NP voltage and prevent disturbance from the and V, the required dc-link capacitance is:
MLI switching frequency in the control loop. In order to sim- uF. With the NP balancing circuit, the dc-link capacitance
plify the design of the controller for the boost converter, it oper- can be reduced to approximately uF.
ates in discontinuous mode. This is guaranteed by setting the
maximum for the boost converter in the DSP code. The B. Experimental Results
compensator used in the control loop is “Type II” according to Fig. 12 shows the MLI line-to-line output voltage. The
feedback control theory and considering the effect of poles and dc-link voltage variation waveforms across are shown in
zeros in the loop. The poles’ and zeros’ positions are decided by Fig. 13, with and without the proposed NP balancing control.
the output inductor, capacitor and equivalent series resistance The peak-to-peak voltage variation is 30 V without NP
744 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

100 V/div). Also shown is the voltage across (300 V ) to

show that the voltages across and are balanced, and each
voltage is half of the total dc-bus voltage. Again, the magnitude
of the sag that the proposed MLI can ride-through is determined
by the selected ratings of the ride-through circuit.

VII. CONCLUSIONS
In this paper, a simple approach to balancing the dc-link
voltage has been presented, which provides enhanced
Fig. 13. DC-link voltage variation waveforms across C with and without the ride-through perform+ance and enables the MLI switching
proposed NP voltage balancing control. algorithm to be modified for CMV cancellation. Simulation
and experimental results with full DSP control verify the pro-
posed concepts. With the appropriate design of the balancing
controller, the NP voltage variation is shown to be significantly
reduced, while allowing enhanced ride-through performance
and CMV cancellation. The added features of NP balancing
and ride-through enhancement do come with additional com-
ponents, as detailed in Sections II and III, which increase the
cost and complexity of the MLI hardware, the extent of which
is dependent on the application.

ACKNOWLEDGMENT
Fig. 14. Motor shaft voltage with and without CMV-cancellation control.
The authors wish to thank the Toshiba International Indus-
trial Division, and Assistant Chief Engineer W. Gray, for the
generous hardware contributions to construct the experimental
setup.

REFERENCES
[1] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point clamped
PWM inverter,” IEEE Trans. Ind. Applicat., vol. 17, pp. 518–523,
Sept./Oct. 1981.
[2] K. R. M. N. Ratnayake, Y. Murai, and T. Watanabe, “Novel PWM
scheme to control neutral point voltage variation in three-lever voltage
source inverter,” in Conf. Rec. IEEE-IAS Annu. Meeting, 1999, pp.
Fig. 15. Ride-through performance during a 40% single-phase input voltage 1950–1955.
sag: regulated dc-bus voltage of V + V (600 V, top), the sagged rectifier [3] J.-H. Suh, C.-H. Choi, and D.-S. Hyun, “A new simplified space-vector
output voltage (520 V, middle), and voltage across C (300 V , bottom) to PWM method for three-lever inverters,” in Conf. Rec. IEEE-IAS Annu.
show that the voltages across C and C are balanced. Meeting, 1999, pp. 515–520.
[4] Y.-H. Lee, R.-Y. Kim, and D.-S. Hyum, “A novel SVPWM strategy con-
sidering dc-link balancing for a multi-level voltage source inverter,” in
balancing control and 15 V with NP balancing control. Note Proc. IEEE APEC’99, 1999, pp. 509–514.
that additional ripple across is induced by the three-phase [5] S. Ogasawara and H. Akagi, “Analysis of variation of neutral point
potential in neutral-point-clamped voltage source PWM inverters,” in
power rectifier. The difference between these experimental Conf. Rec. IEEE-IAS Annu. Meeting, 1993, pp. 965–970.
results and the simulation results of Section V can be partly [6] C. Newton and M. Sumner, “Neutral point control for multi-level
attributed to the fact that the simulations were performed under inverters: Theory, design and operational limitations,” in Conf. Rec.
IEEE-IAS Annu. Meeting, 1997, pp. 1336–1343.
ideal conditions for the balancing circuit and the experimental [7] X. Yuan and I. Barbi, “Soft-switched three level capacitor clamping
work has the practical effects of noise. In addition, the practical inverter with clamping voltage stabilization,” in Conf. Rec. IEEE-IAS
controller has a 5-V dead-band error setting. Annu. Meeting, 1999, pp. 502–508.
[8] N. Celanovic and D. Boroyevich, “A comprehensive study of neutral-
The voltage waveforms of the motor shaft isolated from point voltage balancing problem in three-lever neutral-point-clamped
ground are shown in Fig. 14 to demonstrate the high perfor- voltage source PWM inverters,” IEEE Trans. Power Electron., vol. 15,
mance of the developed CMV-cancellation scheme. pp. 242–249, Mar. 2000.
[9] H. Zhang, A. von Jouanne, S. Dai, A. Wallace, and F. Wang, “Mul-
The ride-through performance is demonstrated during an ex- tilevel inverter modulation schemes to eliminate common-mode volt-
ample 40% single-phase voltage sag, which reduces the rec- ages,” IEEE Trans Ind. Applicat., vol. 36, pp. 1645–1653, Nov./Dec.
tifier output voltage to 520 V . However, the proposed ride- 2000.
[10] F. Wang, “Motor shaft voltages and bearing currents and their reduction
through approach is set to regulate each capacitor to 300 V , in multilevel medium-voltage PWM voltage-source-inverter drive appli-
thus maintaining 600 V on the dc bus. Fig. 15 shows the rec- cations,” IEEE Trans Ind. Applicat., vol. 36, pp. 1336–1341, Sept./Oct.
tifier output dropping to 520 V during the sag, and the effect 2000.
[11] R. A. Hanna and S. Prabhu, “Medium-voltage adjustable-speed
of the ride-through scheme to regulate the total dc-bus voltage, drives—Users’ and manufacturers’ experiences,” IEEE Trans. Ind.
of , to 600 V during the sag (note the scale is Applicat., vol. 33, pp. 1407–1415, Nov./Dec. 1997.
VON JOUANNE et al.: A MULTILEVEL INVERTER APPROACH 745

[12] J. F. Silva, A. Galhardo, and J. Palma, “High-efficiency ripple-free power Shaoan Dai (S’00) received the B.S. and M.S.
converter for nuclear magnetic resonance,” in Proc. IEEE PESC, 2000, degrees from Harbin Institute of Technology,
pp. 384–389. Harbin, China, in 1987 and 1990, respectively. He
[13] A. I. Pressman, Switching Power Supply Design, 2nd ed. New York: is currently working toward the Ph.D. degree in the
McGraw-Hill, 1998. Department of Electrical and Computer Engineering,
Oregon State University, Corvallis.
From 1990 to 1996, he was an Assistant Professor
and, from 1996 to 1999, he was an Associate
Annette von Jouanne (S’94–M’95–SM’00) Professor in the Department of Control Engineering,
received the B.S. and M.S. degrees in electrical Harbin Institute of Technology. His interests are
engineering with an emphasis in power systems focused on circuits design, power electronics,
from Southern Illinois University, Carbondale, in adjustable-speed drives, and control engineering.
1990 and 1992, respectively, and the Ph.D. degree in
electrical engineering/power electronics from Texas
A&M University, College Station, in 1995.
While at Texas A&M University, she also
worked with the Toshiba International Industrial
Division and International Power Machines on joint
university/industry research. In 1995, she joined the Haoran Zhang (S’98–M’99) received the B.E.E.
Department of Electrical and Computer Engineering, Oregon State University degree from Tsinghua University, Beijing, China,
(OSU), Corvallis, where she is currently an Associate Professor, working in 1985, the M.E.E. degree from the Institute
primarily on power electronic converters, power quality, adjustable-speed drive of Electrical Engineering, Chinese Academy of
(ASD) ride-through, and investigating and mitigating the adverse effects of Sciences, Beijing, China, in 1988, and the Ph.D.
applying ASDs to ac motors. She is also the Co-Director of the Motor Systems degree in electrical engineering from Oregon State
Resource Facility (MSRF), an Electric Power Research Institute/OSU Center University, Corvallis, in 1998.
for power electronics, motors and drives research, and testing. From 1988 to 1995, he was an Assistant Professor
Dr. von Jouanne was the recipient of the 2000 IEEE Industry Applications in the Department of Control Engineering, Harbin In-
Society Outstanding Young Member Award, the IEEE Industry Applications stitute of Technology, Harbin, China. He is currently
Magazine Prize Paper Award, and the National Science Foundation CAREER an Integrated Circuit Design Engineer with Texas In-
Award. She also served as an Associate Editor of the IEEE TRANSACTIONS ON struments Incorporated, Tucson, AZ, working on power management and high-
INDUSTRIAL ELECTRONICS during 1997–2001. She is a Registered Professional precision analog ICs. His areas of interest include power electronics, power and
Engineer in the State of Washington. analog integrated circuits, electric machines, and adjustable-speed drives.