1.

Introduction- ASIC Design, Fabrication & Layout of

CMOS.

1. What we integrate:

Digital circuits and systems, eg. programmable microprocessor, elc.

Analog circuits and systems, eg. amplifiers for different applications.
Mixed Signal circuits and systems, eg. ADC, DAC, modern wireless transceciver
system on Chip (SoC) etc.
High frequency analog circuits, eg. radio frequency circuits in analog
communication.
Microwave Monolithic Integrated Circuits (MMIC) in the millimeter wavelength.
Micro Electro-Mechanical Systems (MEMS), used as sensors, digital switches or
on-chip inductors in RF chip.
3D integrated circuits and System in Package (SiP).
Silicon Photonic Circuits.
stimulators.
Biological transplant circuits -

sensors or

2. Substrate material:
Mainly Silicon.
Other application specific materials.

3. What we cannot integrate yet

DRAM cells in a standard CMOS fabrication process due extra mask layer needed
by a DRAM cel.
On chip LASER source on a integrated silicon photonic circuit due to high power

dissipation.
Others

4. Scale of Integration:

Scale # Application
Transistors
10-100 Discrete logic gate 1Cs
SmallScale
Integration (SSI) Small functional ICs like counters, registers etc.
Medium Scale 100-1000
Integration (MSI)
I.arge Scale 1000-1e4 Small processors ICs

Integration (LS Programmable 16/32-bit micro-controllers/

Very Large Scale le4-1e6
Integration (VLSI) processors/DSPs etc.
le6-le7 SoC (System on Chip) ICs, eg. ADSL Reciever-
Ultra Large Scale
Integration(ULSI)_ | Transmitter ICs, Mixed signal SoCs etc.
Giga Scale Integration le7 SoCs, Mixed Signal SoCs. SoC's with integrated
sensors, optical comnponents etc., 3D ICs, etc
 Microperlpheral

6%
DSP
Memory
6%
27%
Microcontroller

7%
Analog
11%

Microprocessor
Dis cretes
18%
10%
Logic
16%

Semiconductor market share [R. Jacob Baker).

Figure 1:

integrate) w.r.t. discrete circuits

5. Advantages (Why we

Device Matching
of transistors
Miniaturization and high packing density
resistances
Reduced parasitic capacitances and (analog/RF/MMIC
and higher bandwidth
Faster spccd of switching (digital ckt)
ckt)
life for mobile applications.
Low power consumption and higher battery
Computer Aided Design
.More functionalities per chip using VLSI-specific tools.
EDA (Electronic Design Automation)
(CAD) Lools. popularly known as
cost per chip by volume production.
Amortization of design cost and low
for low volume designs.
Enabling platform (FPGA chips)
Enabling platform (FPGA chips) for pre-Silicon (real ime) architecture
prototyping and evaluation.
Miniaturization of optical systems.

6. Disadvantages:
power dissipation.
High steady state leakage current and consequent leakage
Technological limitation of scaling down (Dennard Scaling) of transistors using
where high investment has
existing Silicon based technology and instruments,
been made over decades.
Search for new material with low cost of technology migration from Si-based

technology.
Sometimes, chiplet based SiP is cheaper than SoC. The recent datacenter CPU's
from Intel and AMD are all chiplet based SiP. This way Moores law continues
even though Dennard scalling does not.
7. Market forces for technological progress in microelectronics:

Microprocessors/DPSsfor telecommunication applications.

SoCs for sensors and loT applications.
RF systems for 5G/6G instruments.
GPU, TPUS etc for datacenter application enabling Deep Leaning based
applications.
Mobile processors.
Memory chips (DRAM, Flash Memories for SSD, etc.)
Others
8. Moore's Law (actually a rule of thumb):
Gordon Moore's Law (Electronics Magazine, April 19, 1965), Cofounder of
Fairchild Semi' & Intel: Number oftransistors doubles approximately every eighteen
months.
I t means, computing power of microprocessor shall double every 2 years.
If M, be the computing power of a microprocessor, say in MIPS (Million
Instructions per second), in the n" year, starting with the present computing power
Mo, then
o Ma M22)
o In 1988, Intel 386 SX microprocessor had 275,000 transistors.
o In 1997, Intel Pentium II could be predicted to have 275,000x26.2
millions transistors, as per Moore's Law.
o In 1997, Pentium 1l actually had 7.5 million transistors.
o In 2012, ~3 billion transistors were placed in a chip, and miniaturization
(known as scaling in field of VLSI study) continues even today.
 Microprocessor Transistor Counts 1971-2011& Moore's Law
18-Core SPARC TD
Stw Core Core
2,600,00o,000 SN-Core Keon 7 4 0 10-Core Xeon Wpstmere Ex
Dual Core hanium core PoWFR7
1,000.000,000 AND KIa fEU:E.c
Tu
e o n Nehalem.t
Nanium 2 t h
PoWERC' C O t e r e n 24c0
** AMD KI0 Core 7 (9uao)
t E 2 Duo
anlum
100.000,o0o
Barton om
Pertkm
Curve shows transistor AHB
10,000,000 twonyoa
t
ng oveny AuD m l
Pen un
AMD G
PenOum

1,000,000 Bo4B

BO380
100,000- eo2ne
08000 e O 180

10,000
sOBO
80O0 MOS esa2
2,300 4004 RCA 1002

1971 1980 1990 2000 2011

Date of introduction

o Methods of scaling:
Scale down dimension of all features of MOSFETs smaller.
Scale down area of cross-section and length of interconnects.
Constant ficld scaling. constant voltage scaling, or hybrid scaling

d(l/) Gate
Drain
Source
L(1/)

Fig. 25 Physical parameters

for MOSFET scaling. Scaling
N,) factors for constant-field are
indicated.

IS.M. Sze. Kwok K. Ng, "Physics of Semiconductor Devices," pp: 329, John Wiley &
Sons. Inc.]
Table 2
MOSFET Scaling
Parameter Constant-6 Constant-V Quasi-constant-V Actual Limitation

1/k 1/K 1/x

>1 >1 1
> 1/x Tunneling, defects
1/K 1/K 1/K
1/K >1/k >1/* 1/x Resistance
1/x 1/K »1/x Off current
»1/k System and V
1/k 1/
Vp Junction breakdown
K

In ideal constant-field scaling parameters are scaled by the same factor. In reality the
and skewed. 1<x<K
scalingfactors are limited by other reasons
S.M. Sze, Kwok K. Ng, "Physics of Semiconductor Devices," pp: 329, John Wiley &

Sons, Inc.]

o Motivation of scaling
More packing density, cheaper cost per transistors, faster switching8
speed, reduced electrical power consumption.
Need for system level implementation of advanced algorithms in

telecommunication. artificial intelligence, deep learning (both

datacenters and edge devices) etc.
Competition between manufacturers.
.International Technology Roadmap for Semiconductors (1TRS)
www.itrs2.net. Example See the table below.
 22 14
Technolog
nm nm
Node
Shape
Interconnect Features
type (nm)
Width 160 105
Global
Interconnect 96 63
Thickness
160
105 Microstrip
Spacing
Inter Layer 76.8 52.5
Distance
Intermediate Width 44 28
Interconnect 44 28
Thickness
44 28 Square
Spacing
Inter Layer 39.6 25.2
Distance
Local Width 22 14
Interconnect
Thickness 44 28
22 14 Tower
Spacing
Inter Layer 39.6 25.2
Distance

Gordon Moore (also said): 7This cannot continue for

ever.
o
cannot maintain
Michio Kaku (Physicist): computer power simply
Silicon lechnology.
its rapid exponential rise using standard
architectures &
Search for new Circuit Techniques, MOSFET
Process Engineering:
New circuit design approach:
standard CMOS
o Dynamic frequency scaling in
technology
standard CMOS
o Dynamic voltage scaling in
technology
(DVFS)
o Dynamic voltage and frequency scaling
o Multiple threshold (multi-VT) transistors technique
for better switch-off.
o Many more.

New Process & MOSFET: Silicon

over Insulator (SOOf)
technology: MOSFET
o Partially Depleted (PD) SOI
MOSFET
o Fully Depleted (FD) SOI
 o Vacuum can be the insulator (Silicon over nothing
(SON) technology).
o Double Gate MOSFET based on SOl concept
(DG)
back gate
Traditional gate and an additional
below the substrate.
MOSFET technology
o Gate All Around (GAA)
This eventually
evolved from DG MOSFET.
matured into FinFET structure.
Multi-die (each die called chiplet)
System-in-
o
3D-IC.
Package (SiP). Example:
MOSFET in 14nm & 10nm
FinFET is already standard
CMOS Technology. low value
researched upon for
TFET (Tunnel FET) is being current.
reduce OFF leakage
of Sub-threshold Swing to
quantum
Electron Transistor (SET): Exploits
Single
effects. Not mainline yet.

Search for new substrate material:

from SOI
Thin film transistors: Actually evolved
technology.
2D lattice
based thin film FET
o Graphene Nano Ribbon
FET (CNTFET).
o Carbon Nanotube based
o
MoS2 based FET.
o others.
frontier- Molecular Electronics and quantum
Final
computers.