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PROJECT2

The document describes a digital logic design project involving various components like a 2 to 4 line decoder, 4-bit 2-to-1 multiplexers, 4-bit registers, 4-bit 4-to-1 multiplexers, a 4-bit CCU, and a data path combining these components to regulate user temperature based on sensor temperature input.

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tdemirel23100
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22 views11 pages

PROJECT2

The document describes a digital logic design project involving various components like a 2 to 4 line decoder, 4-bit 2-to-1 multiplexers, 4-bit registers, 4-bit 4-to-1 multiplexers, a 4-bit CCU, and a data path combining these components to regulate user temperature based on sensor temperature input.

Uploaded by

tdemirel23100
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ELECTRICAL AND ELECTRONICS

ENGINEERING
&
COMPUTER ENGINEERING

EEE248|CNG232
Logic Design

SPRING23|24

Emre Okurlar-2585800
Tuba Nur Demirel-2585651

PROJECT 1
EEE 248| CNG 232 Logic Design Project#02

2.1) Each component has seperate verilog code and testbench

1) 2 to 4 Line Decoder

The verilog code and testbench is written according to decoder truth table which is given below.

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EEE 248| CNG 232 Logic Design Project#02

2) 4-bit 2-to-1 Multiplexers

2 to 1 mux's equation is Y=~sel.Q+sel.w


and the verilog code and testbench is written according to this equation.

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EEE 248| CNG 232 Logic Design Project#02

3) 4-bit registers

All four flip flops are do not have reset function, instead they recieve the multiplexer output and clock
signals. Input data is provided individually to each flip flop, and similarly, output data is collected
independently from each flip flop. Flip-flops has a funciton that when clock input is uprising or can be
called posedge, output recieve the input value.

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EEE 248| CNG 232 Logic Design Project#02

4) 4-bit 4-to-1 Multiplexers

In 4-1 multiplexer there is selected inputs which gives value to turn on the selected input. For
example, when selection is 00 output is 0001 which is the first input, and when selection 01 output is
0010 which is second input and it goes until selection becomes 11 and output becomes 1000 which is
the last input.

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EEE 248| CNG 232 Logic Design Project#02

5) 4-bit CCU

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EEE 248| CNG 232 Logic Design Project#02

CCU (Central Control Unit) gives the data which on the prework sheet. It has noop, set, decrement,
increment, load, store and copy functions with the output of L,E,G. In first loop x is lower than y thus L
flag is 1 while other flags are 0, in the second loop x is greater than y so G flag is 1 while other flags are 0, in
the last loop x is equal to y then E flag is 1 while other flags are 0.

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EEE 248| CNG 232 Logic Design Project#02

6)Data-Path

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EEE 248| CNG 232 Logic Design Project#02

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EEE 248| CNG 232 Logic Design Project#02

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EEE 248| CNG 232 Logic Design Project#02

The decoder, 2-1 mux, 4-1mux, ccu are coded separately after that the codes are combined in the
onother verilog according to datapath. The datapath is basically arranging the humuditiy and
temperature. Firstly the enable is choosing the which output will be open on the decoder after that input
sel choose the value of sensor temperature or user temperature. 4 bit value is goes to 2-1 mux and with
the help of load_data it goes to 2-1 mux right after and gates. when 2-1 mux is select one the data goes to
register. Register work with the clock and when clock is open it let the data go to 4-1 mux. rd_addr
choose the which output will open and the data goes to ccu. CCU firstly set the sensor temperature and
when user temperature come it compare the values with the help of L,E,G outputs. After that if it is low
or high than sensor temperature it will decrease or increase the user temperature. after that it send the
value to the data_out and from there the value which is user temperature will go again 2-1 mux and the
other steps comes this circulation will continue end of the sensor and user temperature will equal.

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