ELECTRICAL AND ELECTRONICS ENGINEERING

&
COMPUTER ENGINEERING

EEE 248|CNG 232

Logic Design
S P R I N G 2 3 | 2 4

PROJECT FINAL
Good Luck

Dr . Muham m ad Toaha | Dr . Muhamm ad Sohai l

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TABLE OF CONTENTS

REGULATIONS 3

EXPERIMENT #3 4

3.1 OBJECTIVE 4

3.2 PRELIMINARY WORK 5

3.2.1 OBJECTIVES 5
3.2.2 MEALY FSM 5
3.2.3 MOORE FSM 7

3.3 DATAPATH DESIGN 9

3.4 FSM DESIGN 11

3.5 TOP-LEVEL DESIGN 12

3.5.1 DECODER 12
3.5.2 PIN ASSIGNMENT 13

3.6 HIERARCHICAL SCHEMATIC ENTRY WITH MULTIBIT SIGNALS 15

3.6.1 SYMBOL CREATION 15
3.6.2 MODULE INSTANTIATION IN SCHEMATIC CAPTURE TOOL 15
3.6.3 MULTI-BIT SIGNAL ENTRY IN SCHEMATIC TOOL 15

3.7 PROJECT REPORT 16

3.7.1 STATE DIAGRAM OF THE FSM 16
3.7.2 PARAMETERIZED VERILOG CODE 16
3.7.3 TESTBENCH 16

3.8 EXPERIMENTAL WORK 16

3.8.1 Experimental Setup 16
3.8.2 EVALUATION 16

3.9 REFERENCES 16

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REGULATIONS

 Students are not permitted to perform an experiment without doing the preliminary work before coming
to the laboratory.
 It is not allowed to do the preliminary work at the laboratory during the experiment.
 Students, who do not submit the complete preliminary work before the evaluation session, cannot
attend the lab. No “make-up” is given in that case.
 No food or drink in the lab.
 There won’t be any extensions in the evaluation time for latecomers. Therefore, students must be at the lab
on time for the evaluation.
 Only the following excuses are valid for taking lab make-up:
1. Health Make-up: Having a health report from METU Medical Center.
2. Exam Make-up: Having an exam coinciding with the time of the laboratory session. The student needs
to notify the instructor in advance if this is the case.
 Experiments will be done in teams of two.
 Cheating or plagiarism is not tolerated. Plagiarism is a form of cheating as is using someone else’s
written word with minor changes and no acknowledgement. If you are caught cheating or
plagiarising, you will at the very least receive a zero for the whole experiment. Disciplinary action
may be taken.
 Students who miss the lab two times without a valid excuse get zero as the laboratory portion of the course
grade.
 Those who fail to get a satisfactory score from the laboratory portion may fail the class. This score is
expected to be 70% but may be adjusted up or down with the initiative of the course instructor.

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EXPERIMENT #3

3.1 OBJECTIVE
For your final project, you'll need to create and set up a Controller FSM for the 4-bit Smart Climate Control
System and connect it with the SCCS Datapath from Project 2. To accomplish this, you'll be using the Altera
toolkit and Modelsim® for programming, simulating, and executing the design.
In preparation for the lab demo, students are expected to compile and submit a detailed report
containing all the codes, diagrams, and simulation waveforms that will be showcased for each experiment
mentioned later on.
During the experiment, you and your partner will present the SCCS [FSM + Datapath] design to the lab
instructor, following the standard procedure. It's crucial that the report covers all module designs and
simulations. Moreover, the overall design (comprising the complete Datapath and FSM) should undergo testing
through simulation in Modelsim®. Practical implementation on the FPGA DE0 Board using the inputs provided
by the FSM will be done during the demo.

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3.2 PRELIMINARY WORK

Finite State Machines (FSM) are sequential circuit used in many digital systems to control the behavior of
systems and dataflow paths. Examples of FSM include control units and sequencers. This lab introduces the
concept of two types of FSMs, Mealy and Moore, and the modeling styles to develop such machines.

After completing this lab, you will be able to:

 Model Mealy FSMs

 Model Moore FSMs

A finite-state machine (FSM) or simply a state machine is used to design both computer programs and sequential
logic circuits. It is conceived as an abstract machine that can be in one of a finite number of user-defined states.
The machine is in only one state at a time; the state it is in at any given time is called the current state. It can
change from one state to another when initiated by a triggering event or condition; this is called a transition.

A particular FSM is defined by a list of its states, and the triggering condition for each transition. The behavior
of state machines can be observed in many devices in modern society performing a predetermined sequence of
actions depending on a sequence of events with which they are presented. Simple examples are vending
machines which dispense products when the proper combination of coins is deposited, elevators which drop
riders off at upper floors before going down, traffic lights which change sequence when cars are waiting, and
combination locks which require the input of combination numbers in the proper order.

The state machines are modeled using two basic types of sequential networks- Mealy and Moore. In a Mealy
machine, the output depends on both the present (current) state and the present (current) inputs. In Moore
machine, the output depends only on the present state.

A general model of a Mealy sequential machine consists of a combinatorial network, which generates the
outputs and the next state, and a state register which holds the present state as shown below. The state register
is normally modeled as D flip-flops. The state register must be sensitive to a clock edge. The other block(s) can
be modeled either using the always procedural block or a mixture of the always procedural block and dataflow
modeling statements; the always procedural block will have to be sensitive to all inputs being read into the block
and must have all output defined for every branch in order to model it as a combinatorial block. The two blocks
Mealy machine can be viewed as

Next State Current

Inputs
and Output State
Logic
Register

Clock
Outputs

Here are the state diagram of a parity checker Mealy machine and the associated model.

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1X/ 0
01/ 1

00/ 0 00/ 1
S0 S1

01/ 0

module mealy_2processes(input clk, input reset, input x, output reg parity);

reg state, nextstate;
parameter S0=0, S1=1;
always @(posedge clk or posedge reset) // always block to update state
if (reset)
state <= S0;
else
state <= nextstate;
always @(state or x) // always block to compute both output & nextstate
begin
parity = 1'b0;
case(state)
S0: if(x)
begin
parity = 1; nextstate = S1;
end
else
nextstate = S0;
S1: if(x)
nextstate = S0;
else
begin
parity = 1; nextstate = S1;
end
default:
nextstate = S0;
endcase
end
endmodule

The three blocks Mealy machine and the associated model are shown below.

Current Outputs
Inputs Next State Output
Logic
State Logic
Register

Clock

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module mealy_3processes(input clk, input reset, input x, output reg parity);

reg state, nextstate;
parameter S0=0, S1=1;
always @(posedge clk or posedge reset) // always block to update state
if (reset)
state <= S0;
else
state <= nextstate;
always @(state or x) // always block to compute output
begin
parity = 1'b0;
case(state)
S0: if(x)
parity = 1;
S1: if(!x)
parity = 1;
endcase
end
always @(state or x) // always block to compute nextstate
begin
nextstate = S0;
case(state)
S0: if(x)
nextstate = S1;
S1: if(!x)
nextstate = S1;
endcase
end
endmodule

The state assignments can be of one-hot, binary, gray-code, and other types. Usually, the synthesis tool will
determine the type of the state assignment, but user can also force a particular type by changing the synthesis
property as shown below. The state assignment type will have an impact on the number of bits used in the state
register; one-hot encoding using maximum number of bits but decodes very fast to compact (binary) encoding
using smallest number of bits but taking longer to decode.

A general model of a Moore sequential machine is shown below. Its output is generated from the state register
block. The next state is determined using the present (current) input and the present (current) state. Here the
state register is also modelled using D flip-flops. Normally Moore machines are described using three blocks,
one of which must be a sequential and the other two can be modelled using always blocks or a combination of
always and dataflow modelling constructs.

Current Outputs
Inputs Next State Output
Logic
State Logic
Register

Clock
Here is the state graph of the same parity checker to be modelled as a Moore machine. The associated model is shown
below.

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1X

01

00 00
S0/ 0 S1/ 1

01

module moore_3processes(input clk, input reset, input x, output reg parity);

reg state, nextstate;
parameter S0=0, S1=1;
always @(posedge clk or posedge reset) // always block to update state
if (reset)
state <= S0;
else
state <= nextstate;
always @(state) // always block to compute output
begin
case(state)
S0: parity = 0;
S1: parity = 1;
endcase
end
always @(state or x) // always block to compute nextstate
begin
nextstate = S0;
case(state)
S0: if(x)
nextstate = S1;
S1: if(!x)
nextstate = S1;
endcase
end
endmodule

The output block when it is simple, as in this example, can be modelled using dataflow modelling constructs.
The following code can be used instead of the always block. You also need to change the output type from reg
to wire.
assign parity = (state==S0) ? 1'b0: 1'b1;

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3.3 DATAPATH DESIGN

For the successful operation of a 4-bit Smart Climate Control system, the Datapath needs specific logic
components such as a 2-to-4 Line decoder, four 1-bit AND gates, six 4-bit 2-to-1 Multiplexers, five 4-bit
registers, two 4-bit 4-to-1 Multiplexers, and a 4-bit Control and Calculation Unit (CCU) illustrated in Figure 1.

Figure 1: SCCS FSM & Datapath

Every logic block in the Datapath needs to be individually designed and simulated before being integrated
into the top-level design. The connections between each logic block must be established in the top-level design,
SCCS_DATAPATH, using a hierarchical design approach.

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You are required to develop parameterized Verilog code to define your Datapath. The CLK and other
control signals should come from the FSM.

The FSM control signals and Datapath operations:

 wrt_addr signal provides an address to activate the required register as stated in Table 1.

Table 1: 2-to-4 Decoder Operation.

wrt_addr Registers
A B REG_3 REG_2 REG_1 REG_0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

 Toggle_TH is used to switch between temperature and humidity settings.

 The wrt_en signal collaborates with wrt_addr and Toggle_TH to choose either a new value or retain
the previous value of Temperature/Humidity.
 Input_sel is used to select either the Sensor value or the User-defined value. (Please note that in our
4-bit datapath, these values range between 0 and 15).
 The load_data signal selects either the output of the input selection mux or the CCU output result.
 The rd_addr1 and rd_addr2 signals specify the register addresses necessary for executing the CCU
operation between two registers using the provided ccu_opcode. The CCU must be designed to perform
the operations outlined in Table 2. You can use the behavioural approach to design the CCU.
Table 2: CCU Opcodes and Instructions.

alu_opcode Opr 1 Opr 2 Op Instruction

000 -- -- noop -- --
001 xx -- set R[xx] = 1
010 xx -- increment R[xx] = R[xx] + 1
011 xx -- decrement R[xx] = R[xx] - 1
100 xx -- load R[xx] = Data_in
101 xx -- store Data_out = R[xx]
110 xx yy compare R[xx] = C(R[xx],R[yy])
111 xx yy copy R[xx] = R[yy]

*** Please note that these signals must be used in Datapath testbench to test all possible conditions required to
perform operations for SCCS.

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3.4 FSM DESIGN

The control unit for this Datapath will be managed by the SCCS_FSM, which comprises two main
subcomponents: FSM and FSM_DECO.

The SCCS_FSM will be equipped with seven external inputs: START, TOGGLE, 3 LED Flags
(indicating the Sensor and User value comparison result), CLK, RESET and one output DONE to indicate
that the operation is complete. The FSM takes these inputs and carries out all necessary control functions and
generates three outputs: opcode, operand1, and operand2.

The FSM_DECO will then utilize these three outputs for decoding, following the guidelines outlined in
Table 3. The FSM_DECO's output will be key in steering the Smart Climate Control system via the Datapath,
as illustrated in Figure 2.
Table 3: FSM_DECO Operations.

Op op_code Opr1 Opr2 ALU Rd_addr1 Rd_addr2 wrt_addr wrt_en load_data Input_sel
noop 000 -- -- 000 -- -- -- 0 - -
set 001 xx -- 001 -- -- xx 1 0 -
inc 010 xx -- 010 xx -- xx 1 0 -
dec 011 xx -- 011 xx -- xx 1 0 -
load 100 xx -- 100 -- -- xx 1 1 1 or 0
store 101 xx -- 101 xx -- -- 0 - -
compare 110 xx yy 110 xx yy xx 1 0 -
copy 111 xx yy 111 yy -- Xx 1 0 -

Figure 2: SCCS Hardware Algorithm.

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Predefined USER and SENSOR value will be set. Once a START signal is asserted, the SCCS process
will start and continue until the USER = SENSOR.

Draw the state diagram for the control FSM showing all the inputs, outputs, and state transitions clearly.
Indicate the opcode required for each state.

3.5 TOP-LEVEL DESIGN

When the two core parts of the SCCS FSM design are done, connect the blocks in a top-level design as depicted
in Figure 1. This top-level implementation will be simulated in Modelsim® and programmed into your FPGA
Board using Quartus. You will use three LEDs to show the comparison of User and Sensor values and 2 seven
segment displays to show the output of the DATAPATH.

1. DE0 board has 4 adjacent 7-Segment Displays. By considering this, use combinational logic design
principles to design a 7-Segment Display decoding logic such that when a 4-bit signed binary number
is entered, the number will show up on the rightmost 7-Segment Display. Also, if the number is
negative, the sign will be displayed on the 7-Segment Display next to the one that shows the number
(Rightmost two 7-Segment Display will be employed). For example, when the user enters 0001, two of
the vertically aligned LEDs of the rightmost 7-Segment Display should light up. Similarly, when the
user enters 1110 (-2) in binary, five of the LEDs on the rightmost 7-Segment Display should light up,
and the LED located in the middle of the adjacent 7-Segment Display should light up to indicate the
number is negative. Please optimize your logic as much as possible to yield the lowest cost i.e. the
lowest number of input switches, gates, literals, and gate inputs. Input-to-Output delay is not a concern
in this application.
Hint: Remember each 7-Segment Display on DE0 board is characterized by 8 independent active low
outputs (including the dot in the lower right) that need to be all defined to determine the displayed
character, as depicted in Table 4.
Table 4: Mapping of DE0 7-Segment Display to Decoder

Table 5: Decoder Outputs

BINAR
Y
VALUE A B C D E F G H I J K L M N O P
-8 OF OF OF OF OF OF ON OF O ON O ON ON ON ON OF
F F F F F F F N N F
-7 OF OF OF OF OF OF ON OF O ON O OF OF OF OF OF
F F F F F F F N N F F F F F
-6 ...
… ...
+6 OF OF OF OF OF OF OF OF O OF O ON ON ON ON OF
F F F F F F F F N F N F
+7 OF OF OF OF OF OF OF OF O ON O OF OF OF OF OF
F F F F F F F F N N F F F F F

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2. Write a Verilog code to implement the decoder module designed in Section 3.5.1.1.1. Please follow the
procedural approach of behavioral modelling.

1. Pin assignments are made by using the Pin Planner. Select Assignments > Pin Planner to start.
2. Select x1 as the first pin to be assigned. To do this, double-click on the box in the column labelled
Location to the right of x1 entry. A drop-down menu appears. Scroll down and select PIN_J6.
Instead of scrolling down the menu to find the desired pin, you can just type the name of the pin (J6)
in the Location box.
3. Use the same procedure to assign input x2 to pin H5 and output f to pin J1
4. To save and close the assignments made, choose File > close.
5. Recompile the circuit, so that it will be compiled with the correct pin assignments. Run the Compiler
by selecting Processing > Start Compilation.
Table 6: DE0 Test Box Input Switch Cyclone III FPGA pin mapping

Table 7: DE0 Test Box Input Button Cyclone III FPGA pin mapping

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Table 8: DE0 Test Box HEX Output Cyclone III FPGA pin mapping for HEX0

Table 9: DE0 Test Box Output LED Cyclone III FPGA pin mapping

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3.6 HIERARCHICAL SCHEMATIC ENTRY WITH MULTIBIT SIGNALS

Multiple schematic or Verilog design modules can be pulled together in the schematic capture tool using their
symbols.

Once a design has been fully completed, choose File from Top Menu, and roll the mouse over to Create/Update
selection. A side menu appears, from this menu select Create Symbol Files for Current File in order to create
a symbol (.bsf file) for your design. The procedure is the same for both Schematic and Verilog design modules.

If the design module of interest has been created as part of another project, pull it into the current project using
File → Open …, browse and choose the relevant schematic or Verilog design file, making sure that Add file
to current project checkbox is selected. This can be repeated for all the modules that need to be pulled into the
current project. The symbols created by the user can be used for the current project in same fashion as other
symbols such as AND gate, OR gate, etc in schematic design.

Multi-bit signals are entered using Orthogonal Bus Tool. A signal is interpreted as multi-bit only after it is
labelled. Some examples of valid multi-bit signals names are:

X [3..0] : A 4-bit signal named using vector notation

A, B, C, D : Four 1-bit signals grouped together to form a 4-bit signal
Y [4..2] : A 3-bit signal; the name implies it may be a sub-branch of the Y signal with more bits

1-bit or multi-bit signals (or I/O ports) are sometimes combined into a multi-bit signal. Quartus II schematic
tool requires that a multi-bit signal and each net connected to it through a bus are all clearly labelled. One clean
way to do this is to right-click on the segment you need to name and select Properties. Below is an example of
multi-bit signal connectivity. As observed in the figure, different bits making up the signal Out [1..0] are
sourced from different single-bit signals.

Figure 3: Multi-bit signal connectivity and naming example.

The Figure 3 above is used as an example to explain multi-bit entry. Note that you don’t need to necessarily
connect the wires to the buses which is much easier than connecting them.

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3.7 PROJECT REPORT

Include your name, course name, course code, date, an objective statement, and a conclusion in your report. Add
comments to briefly explain each Verilog code, schematic, and simulation that you submit.

Show your state diagram and state table of the FSM designed in section 3.4. Show all the inputs, outputs and
the state transactions clearly.

Include your Verilog codes and block schematics of the FSM, Datapath and all other components you have
used in your design.

Write a test bench code for your Datapath to test the SCCS for user value 10 and sensor value 13. Add your
test bench code and simulation results. To debug your code, add output waveforms for your registers and check
if there are non-desired outputs observed.

3.8 EXPERIMENTAL WORK

 Verify to make sure your workbench has all of the following items:
 A Personal Computer (PC) with Altera Quartus II ISE 13.0 Service pack 1 Project Navigator
 DEO Demo Board with Cyclone III EP3C16F484C6 FPGA installed on a card with 10 input toggle
switches, three pushbuttons, and four 7-Segment LED displays, among other components.
 A cable connected between the demo board and the PC using a USB interface in order to transfer
design information from the PC to the Demo Board.

During your final demo, you will be evaluated on your understanding of:
o Combinational and sequential concepts,
o FSM design details,
o Verilog and schematic-based design entry, and
o Simulation flows.
You will program your final design onto an FPGA and demonstrate it. If something goes wrong with the
hardware demo or does not seem to work consistently using a manual clock (from push-button) or free-
running on-board clock, you should be ready to do a quick post-route simulation of your design to
demonstrate the corresponding functionality in simulation. (You can only do this if you understand your
simulations very well.) Prepare various test bench waveforms in advance to be able to do this. Remember,
you will have very limited time with the Teaching Assistant to demonstrate your working design, AND that
you fully understand your design. He/she will perform the debugging for you. Start your project early so
you can resolve any problems ahead of time during office hours and come to the final demo fully prepared!

3.9 REFERENCES
 DE0 Board User Manual, Terasic Technologies Inc.
 Digital Design with An Introduction to the Verilog HDL, 5th Edition, M. Morris Mano & Michael D.
Ciletti, Pearson
 Quartus II Introduction Using Schematic Design, ALTERA.

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