ELECTRICAL AND ELECTRONICS ENGINEERING

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COMPUTER ENGINEERING

EEE 248|CNG 232

Logic Design
S P R I N G 2 3 | 2 4

PROJECT 2
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TABLE OF CONTENTS

REGULATIONS 3

EXPERIMENT #2 4

2.1 OBJECTIVE 4

2.2 PRELIMINARY WORK 5

2.2.2 Objectives 5
2.2.3 Creating the Functional Unit 5
2.2.3.2 Shift Resisters 5
2.2.3.3 Parallel in Parallel out shift register 6
2.2.4 CCU 7

2.3 DATAPATH DESIGN 8

2.4 DATAPATH TESTBENCH DESCRIPTION 10

2.4.3 For the Temperature Setting: 10
2.4.4 For the Humidity Setting: 10

2.5 TOP-LEVEL DESIGN 11

2.6 PROJECT REPORT 11

2.6.3 TESTBENCH 11

2.7 EXPERIMENTAL WORK 11

2.7.3 Experimental Setup 11
2.7.4 EVALUATION 11

2.8 REFERENCES 11

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REGULATIONS

 Students are not permitted to perform an experiment without doing the preliminary work before coming to
the laboratory.
 It is not allowed to do the preliminary work at the laboratory during the experiment.
 Students, who do not turn in the complete preliminary work printout at the beginning of the laboratory session,
cannot attend the lab. No “make-up” is given in that case.
 No food or drink in the lab.
 Only the following excuses are valid for taking lab make-up:
1. Health Make-up: Having a health report from METU Medical Center.
2. Exam Make-up: Having an exam coinciding with the time of the laboratory session. The student needs
to notify the instructor in advance if this is the case.
 Experiments will be done in teams of two.
 Cheating or plagiarism is not tolerated. Plagiarism is a form of cheating as is using someone else’s written
word with minor changes and no acknowledgement. If you are caught cheating or plagiarising, you will at the
very least receive a zero for the whole experiment. Disciplinary action may be taken.
 Students who miss the lab two times without a valid excuse get zero as the laboratory portion of the course
grade.
 Those who fail to get a satisfactory score from the laboratory portion may fail the class. This score is
expected to be 70% but may be adjusted up or down with the initiative of the course instructor.

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EXPERIMENT #2

2.1 OBJECTIVE
In this project, you are required to design and implement a Datapath for a 4-bit Smart Climate Control
®
System. Altera toolset and Modelsim will be used to code, simulate, and implement the design.
Students should prepare and submit a report before the LAB demo including all the codes, diagrams, and
simulation waveforms that they will demonstrate for experiment mentioned below.
In this Experiment the Datapath design will be demonstrated with your partner to the LAB instructor as
usual. The report must include all the module designs and simulations. Also, you'll need to test the overall
Datapath design (the complete setup) in Modelsim® using inputs similar to what the Finite State Machine
(FSM) will provide in the upcoming project. However, for this particular project, follow the instructions
provided in the manual for feeding inputs.

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2.2 PRELIMINARY WORK

A data path is a collection of functional units such as arithmetic logic units (ALUs) or multipliers that perform
data processing operations, registers, and buses. Along with the control unit it composes the central processing
unit (CPU). This lab introduces the concept of data path.

2.2.2 Objectives
After completing this lab, you will be able to:

 Create the Functional units through hierarchical design

 Understand the working of the CCU

2.2.3 Creating the Functional Unit

A data path comprises various elements, such as decoders linked to logical gates, facilitating the storage of
values in registers. Subsequently, these registers transmit data to the Central Control Unit (CCU), where
operations are executed based on specified opcodes. The resultant data is then stored in registers. This process
entails the design of data paths using modular units, which are combined to form a complete data path, termed
as hierarchical design. Establishing a simple hierarchical design aids in project development, as exemplified by
the construction of a 4-bit shift register below.
2.2.3.2 SHIFT RESISTERS
Flip flops have the capability to retain a solitary binary digit, either a "1" or a "0". However, for the storage of
numerous binary digits, multiple flip flops are required. Since each flip flop is designed for the storage of one
binary digit, a series of n flip flops are interconnected to accommodate n bits of data. In digital electronics, a
Register serves as a mechanism employed for data storage purposes.

Below is an illustration of a D-flip flop alongside a sample module:

Figure 1: D-Flip Flop

module d_ff (Data,clk,Q);

input D,clk;

output reg Q;

initial
begin
Q=1'b0;
end

always @(posedge clk)

begin
Q <= D;
end

endmodule

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In digital systems, flip flops serve as fundamental components in constructing registers, which are arrangements
of flip flops employed to store multiple bits of data. For instance, to store 16-bit data, a computer requires a set
of 16 flip flops. Registers may adopt either serial or parallel input and output configurations, depending on
specific system requirements. The succession of data bits stored by registers is termed as a "Byte" or "Word,"
where a Byte consists of 8 bits and a Word comprises 16 bits (or 2 Bytes). When flip flops are interconnected
in sequence, they form a Register. The transfer of information within registers, known as 'Shift Registers,'
involves sequential circuits that store and shift data towards the output during each clock cycle. While various
types of registers exist, our project focuses on the parallel-in parallel-out shift register.

2.2.3.3 PARALLEL IN PARALLEL OUT SHIFT REGISTER

In this particular register configuration, data is simultaneously inputted and outputted in parallel. All four flip
flops within the register are synchronized by both the clear (CLR) and clock signals. Input data is provided
individually to each flip flop, and similarly, output data is collected independently from each flip flop. This
setup exemplifies a 4-bit Parallel In Parallel Out (PIPO) shift register.

Here is the 4- bit PIPO shift resister and sample module:

Figure 2: PIPO Shift Register

module four_reg(Q,Data,clk);

parameter size =4;

input [size-1:0]D;

input clk;

output wire [size-1:0]Q;

d_ff U1(D[0],clk,Q[0]);
d_ff U2(D[1],clk,Q[1]);
d_ff U3(D[2],clk,Q[2]);
d_ff U4(D[3],clk,Q[3]);

endmodule

For the given data path in figure 4, you need to construct this type of hierarchical design for proper functionality
for the project.

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2.2.4 CCU
The Central Control Unit (CCU) serves as a crucial digital logic circuit commonly integrated into
microcontrollers, microprocessors, and DSPs. Its role encompasses executing arithmetic, logical, and
comparison operations on input signals. The construction of the CCU relies on the inclusion of combinational
circuits like adders, multiplexers, comparators, and decoders, tailored to facilitate its functionalities.

Figure 3: CCU

In this project, the Central Control Unit (CCU) will incorporate specific inputs and outputs, accompanied by
flags for input comparison. For instance, if input equality is detected, the FLAG_E will indicate an output of
'1'. Similar comparisons will be conducted for other inputs. Detailed operational instructions for the CCU
under various OP_CODE scenarios are provided in Table 2.

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2.3 DATAPATH DESIGN

To realize the 4-bit Smart Climate Control system, the Datapath necessitates specific logical operations,
comprising a 2-to-4 Line decoder, four 1-bit AND gates, five 4-bit 2-to-1 Multiplexers, five 4-bit registers, two
4-bit 4-to-1 Multiplexers, and a 4-bit ALU, as illustrated in Figure 1.

Figure 4: Smart Climate Control Datapath

Each component of the Datapath must undergo individual design and simulation before integration into the
overarching structure. Interconnections among these components should be established within the top-level
design SCCS_DATAPATH, employing a hierarchical design methodology.

This approach should adhere to a parametric model, enabling flexibility in adjusting the controller's bit size.
Consequently, a parameterized Verilog code should be written to define the Datapath. The assignment of signals
such as CLK and others should align with the directives outlined in section 2.4.

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The control signals and Datapath operations:

 wrt_addr signal provides an address to activate the required register as stated in Table 1.
Table 1: 2-to-4 Decoder Operation.

wrt_addr Registers
A B REG_3 REG_2 REG_1 REG_0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

 wrt_en works together with the wrt_addr to select either a new value or hold the previous value.
 Toggle_T/H also works with the wrt_en and wrt_addr to set either the Temperature setting or the
Humidity Setting.
 load_data signal selects either the new Temperature/Humidity User/Sensor values from the 4_to_1
MUX or the ALU output result for feedback.
 Input_sel is used to select the User_Temperature, Sensor_Temperature, User_Humidity,
Sensor_Humidity. (Note: we use a 4-bit data path so these values should lie between 0-15)
 rd_addr1 and rd_addr2 signals provide the register addresses that are required to perform the CCU
operations between two registers using the ccu_opcode provided. The CCU must be designed with the
following operations stated in Table 2. You can use the behavioural approach to design the CCU.
Table 2: ALU Opcodes and Instructions.

ccu_opcode Opr 1 Opr 2 Op Instruction

000 -- -- noop -- --
001 xx -- set R[xx] = 1
010 xx -- increment R[xx] = R[xx] + 1
011 xx -- decrement R[xx] = R[xx] - 1
100 xx -- load R[xx] = Data_in
101 xx -- store Data_out = R[xx]
110 xx yy compare R[xx] = C(R[xx], R[yy])
111 xx yy copy R[xx] = R[yy]

*** Please note that these signals must be used in Datapath testbench to test all possible conditions required to
perform operations for SCCS.

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2.4 DATAPATH TESTBENCH DESCRIPTION

The Datapath will manage two distinct modes: Temperature setting and Humidity setting. To validate its
functionality, two separate testbenches should be written for each mode.

2.4.3 For the Temperature Setting:

First, activate the wrt_en signal and then set toggle_T/H to '1' for Temperature setting and '0' for Humidity
setting. Utilize the corresponding wrt_addr to write data to the designated registers. For instance, with wrt_en
set to '1' and toggle_T/H set to '1', data can be written to registers R1 and R0. One register is designated for
User_Temperature, while the other is for Sensor_Temperature. Given that the Datapath handles 4-bit data,
User_Temperature should be set to '8', and Sensor_Temperature can range from 0 to 15, with the current value
set at '12'. Subsequently, compare these values using the CCU. Since the sensor value ('12') exceeds the user
value ('8'), decrement the sensor value in the testbench until equality is reached.

2.4.4 For the Humidity Setting:

First, activate the wrt_en signal, then set toggle_T/H to '1' for temperature or '0' for humidity adjustment.
Utilize the corresponding wrt_addr to input data into designated registers. For instance, if wrt_en is '1' and
toggle_T/H is '0', data can be written into registers R3 and R2. One register stores the User_Humidity value
while the other stores the Sensor_Humidity value. Keep in mind that this datapath handles 4-bit data; hence, set
the User_Humidity value to '10', and the Sensor_Humidity value can range from 0 to 15, with the current setting
at '7'. After configuring these values in the registers, the next step involves comparing them through the CCU.
Given that the sensor value ('7') is lower than the user value ('10'), the testbench should increment the sensor
value until equality is achieved.

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2.5 TOP-LEVEL DESIGN

After completing the fundamental segment of the Smart Climate Control System (SCCS) datapath, integrate the
individual blocks into a comprehensive top-level design as illustrated in Figure 4. This overall arrangement will
undergo simulation using Modelsim®.

2.6 PROJECT REPORT

In your report, incorporate essential details such as your name, course title, course code, date, an objective
statement, and a concluding summary. Additionally, provide concise comments to explain each Verilog code,
schematic diagram, and simulation outcome. Ensure that all Verilog codes are parameterized.

2.6.3 TESTBENCH
Write a test bench code for your Datapath to test the various modes as described in the section 2.4. Add your
test bench code and simulation results accompanied by explanatory comments detailing your methodology.

2.7 EXPERIMENTAL WORK

2.7.3 Experimental Setup
 Verify to make sure your workbench has all of the following items:
 A Personal Computer (PC) with Modelsim®

2.7.4 EVALUATION
During your project demo, you will be evaluated on your understanding of:
o Combinational and sequential concepts,
o DATAPATH design details,
o Verilog-based design entry, and
o Simulation flows.
Prepare various test bench waveforms in advance to show your datapath is working properly. Remember,
you will have very limited time with the Teaching Assistant to demonstrate your working design, AND you
fully understand your design. He/she will perform the debugging for you. Start your project early so you
can resolve any problems ahead of time during office hours and come to the final demo fully prepared!

2.8 REFERENCES

th
Digital Design with An Introduction to the Verilog HDL, 5 Edition, M. Morris Mano & Michael D.
Ciletti, Pearson

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