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Day 59

The document discusses various procedural statements in SystemVerilog like initial, always, final, while, do-while, break-continue, fork-join, tasks and functions. It explains differences between final vs initial blocks, always_ff, always_comb vs always @*, final block, while vs do-while loops, fork-join types and their differences. It also covers features added for functions and tasks, why functions have 0 simulation time, callbacks, void functions, ref and const ref functions, difference between forever and for loops, use of return statement.

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Purna satya srinivas Vempala
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13 views2 pages

Day 59

The document discusses various procedural statements in SystemVerilog like initial, always, final, while, do-while, break-continue, fork-join, tasks and functions. It explains differences between final vs initial blocks, always_ff, always_comb vs always @*, final block, while vs do-while loops, fork-join types and their differences. It also covers features added for functions and tasks, why functions have 0 simulation time, callbacks, void functions, ref and const ref functions, difference between forever and for loops, use of return statement.

Uploaded by

Purna satya srinivas Vempala
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DAY 59

Procedural Statements: initial, always, final, while, do-while, break-continue, fork-join, tasks,functions,
forever loop

1. Difference between final and initial blocks?


The initial block occurs at the start of simulation whereas the final block occurs at end of the
simulation without having any delays. So, it is the same as a function call that can execute in zero
simulation time.

2. What is the use of always_ff?


SystemVerilog always_ff procedure is used to model sequential flip-flop logic. It has similar
improvements compared to using plain Verilog always. A always_ff procedure adds a restriction that
it can contain one and only one event control and no blocking timing controls.

3. Difference Between Always_comb and Always@(*)?


always_comb is sensitive to changes within the contents of a function, whereas always @* is only
sensitive to changes to the arguments of a function

4. What is final block?


Final block is used at end of simulation time, final block is similar to initial block it will executes at zero
simulation time. Final block is used final keyword to start the block.

5. What is the use of break-continue with an example.


Break and continue helps to control the looping statements, break is used to break the current
execution and come out from the simulation or loop whereas continue statements helps to leave the
current statement execution and continues the process as normal.
Example : in while loop if the break statement condition matches it terminates the loops, whereas in
continue if statement matches the current loop only leaves the execution others will continue
subsequently.

6. Difference between while and do while


While loop executes till the condition in loop meets fail whereas do while is executed first in do block
then onl it starts to executes the while loop.

7. What is fork-join and types of fork-join?


In system verilog fork-join helps to synchronization between the processes. Inside the fork join block
the procedural blocks or statements executes parallely.
Types of fork join :
Fork join
Fork join_any
Fork join_none

8. Difference between fork-join, fork-join_any, and fork-join_none


Fork join, it will come out from the block once it executed all processes inside the block.
Fork-join_any, it will come out from the block if atleast one processes is completed.
Fork-join_none,it will come out form the block it does not wait for to complete any processes in the
block.

9. What is the main limitation of fork-join in Verilog, and how is this overcome in System Verilog?
The main limitation of fork-join construct in Verilog is that it is static, that is, the execution of the code
beyond the join is suspended until all the processes within the fork-join are completed.

10. How to kill process in fork/join?


All active threads that have been kicked off from a fork join block can be killed by calling disable fork .
11. Illustrate how the errors of passing arguments to a function in incorrect order is eliminated in
System Verilog.
In SystemVerilog, one way to prevent errors related to passing arguments to a function in the wrong
order is by using named association when calling the function. Named association involves explicitly
assigning values to the function's arguments by specifying the argument names in the function call.
This approach is less error-prone than positional association, which relies on the order of arguments.

12. What are the features added in System Verilog for function and task?
Task can contain a declaration of parameters, input arguments, output arguments, in-out arguments,
registers, events, and zero or more behavioral statements. SystemVerilog task can be, static.
A Function can contain declarations of range, returned type, parameters, input arguments, registers,
and events. SystemVerilog function can be, static. automatic.

13. Why function has 0 simulation time?


A function will carry out its required duty in zero simulation time. Within a function, no event, delay
or timing control statements are permitted. In the invocation of a function there must be at least one
argument to be passed.

14. What is callback?


SystemVerilog callback specifies the rules to define the methods and placing method calls to achieve a
return call to methods. In simple words, Callbacks are empty methods with a call to them. or. A
method of the class is implemented with calls to dummy methods.

15. What is a "void" function? Why do we use it?


Void functions are simply functions that have no return value. The can be used wherever a statement
is allowed. They cannot be used as part of an expression. There are typically used to set up or initialize
a group of variables.

16. What is “ref” & “const ref” function in System Verilog?


Passing a class variable by ref means that you can update the handle the class variable has from
within the function. Making the argument a const ref means you will not be able to update the class
variable, but you can still update members of the class the variable references.

17. What is the difference between "forever" loop & "for" loop in System Verilog?
The keyword forever in Verilog creates a block of code that will run continuously. It is similar to other
loops in Verilog such as for loops and while loops. The main difference between these and the forever
loop is that the forever loop will never stop running, whereas for and while have a limit.

18. What is the use of "return" statement?


A return statement ends the execution of a function, and returns control to the calling function.
Execution resumes in the calling function at the point immediately following the call. A return
statement can return a value to the calling function.

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