SafeNet, Inc

EmbeddedIPTM-94-PLB

Appendix B: Register and Memory Map

System Architecture Specification

Revision: 1.5
Date: 22 May 2007
Document Number: EIP/2004/0100
Status: Accepted

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Revision History

Rev Page(s) Date Author Purpose of Revision

1.1 ALL 2005-01-17 HJA Initial version, split-of from master SAS
1.2 ALL 2005-07-07 JHO Corrected reported reset value mismatches
Requeste 11297 and 11378 Changed register addresses
1.3 ALL 2007-01-16 WSW
and Register names.
1.4 All 2007-02-09 WSW Changes after review.
1.4 All 2007-05-22 WSW Parent document updated.

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APPENDIX B REGISTER AND MEMORY MAP

This document is part of the EmbeddedIPTM-94-PLB System Architecture Specification and describes the
register and memory map of the EIP-94-PLB IP Core.
Registers in blue can be accessed by the PLB Master only via DMA initiated transfers.
Registers in red can be accessed by the PLB Slave only.
Registers in green can be accessed by either PLB Master & PLB Slave.
Memory gaps in gray parts should not be accessed.

Table 1: Register and Memory Map

REGISTER
ADDRESS REGISTER NAME R/W Reset Default DESCRIPTION
(byte)
PACKET ENGINE COMMAND REGISTERS via TCM0 and TCM_DESCR interface
0x00000 PE_CTRL_STAT R/W 0x00000042 Refer to section 4.11.2
0x00004 PE_SOURCE R/W 0x00000000 Refer to section 4.11.3
0x00008 PE_DEST R/W 0x00000000 Refer to section 4.11.4
0x0000C PE_SA R/W 0x00000000 Refer to section 4.11.5
0x00010 PE_LENGTH R/W 0x00000000 Refer to section 4.11.6
0x00014 SA_COMMAND_0 R 0x00500000 Refer to section 4.12.1
0x00018 SA_COMMAND_1 R 0x00000040 Refer to section 4.12.2
0x0001C- RESERVED - 0xXXXXXXXX Reserved
0x0003C
PACKET ENGINE CONTROL REGISTERS via TCM0 interface
0x00040 PE_DMA_CFG R/W 0x00145050 Refer to section 4.9.1 (bit 15..12 read only)
0x00044 PE_DMA_STAT R 0x02000C03 Refer to section 4.9.2
0x00048 PE_PDR_BASE R/W 0x00000000 Refer to section 4.9.3
0x0004C PE_RDR_BASE R/W 0x00000000 Refer to section 4.9.4
0x00050 PE_RING_SIZE R/W 0x00050000 Refer to section 4.9.5
0x00054 PE_RING_POLL R/W 0x80000000 Refer to section 4.9.6
0x00058 PE_INT_RING_STAT R 0x00000001 Refer to section 4.9.7
0x0005C PE_EXT_RING_STAT R 0x00000000 Refer to section 4.9.8
0x00060 PE_IO_THRESHOLD R/W 0x00080008 Refer to section 4.9.9
0x00064 PE_GATH_RING_BASE R/W 0x00000000 Refer to section 4.10.3
0x00068 PE_SCAT_RING_BASE R/W 0x00000000 Refer to section 4.10.4
0x0006C PE_PART_RING_SIZE R/W 0x00000000 Refer to section 4.10.5
0x00070 PE_PART_RING_CFG R/W 0x00000000 Refer to section 4.10.6
0x00074- RESERVED - 0xXXXXXXXX Reserved
0x004FC
PACKET ENGINE SA AND DMA REGISTERS via TCM_DESCR interface
0x00500 PE_PR_SRC_ADDR R/W 0x00000000 Refer to section 4.10.7.3
0x00504 PE_PR_SRC_CTRL R/W 0x00000002 Refer to section 4.10.7.4
0x00508- RESERVED 0xXXXXXXXX Reserved
0x0057C
0x00580 PE_PR_DEST_ADDR R/W 0x00000000 Refer to section 4.10.7.5
0x00584 PE_PR_DEST_CTRL R/W 0x00000002 Refer to section 4.10.7.6
0x0058C- RESERVED - 0xXXXXXXXX Reserved
0x105FC
CRYPTO CONTEXT REGISTERS via TCM1 and TCM_SA interface
0x10600 SA_COMMAND_0 W 0x00000000 Refer to section 4.12.1
0x10604 SA_COMMAND_1 W 0x00000000 Refer to section 4.12.2
0x10610 SA_KEY_1_L [31:0] W 0x00000000 Key word 1 (DES, 3-DES, AES, ARC4)
0x10614 SA_KEY_1_H [63:32] W 0x00000000 Key word 1 (DES, 3-DES, AES, ARC4)
0x10618 SA_KEY_2_L [31:0] W 0x00000000 Key word 2 (3-DES, AES, ARC4)

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REGISTER
ADDRESS REGISTER NAME R/W Reset Default DESCRIPTION
(byte)
0x1061C SA_KEY_2_H [63:32] W 0x00000000 Key word 2 (3-DES, AES, ARC4)
0x10620 SA_KEY_3_L [31:0] W 0x00000000 Key word 3 (3-DES, AES)
0x10624 SA_KEY_3_H [63:32] W 0x00000000 Key word 3 (3-DES, AES)
0x10628 SA_KEY_4_L [31:0] W 0x00000000 Key word 4 (AES)
0x1062C SA_KEY_4_H [63:32] W 0x00000000 Key word 4 (AES)
0x10630 SA_IN_HASH_DIG_0 [31:0] W 0x00000000 Inner Hash digest
0x10634 SA_IN_HASH_DIG_1 [63:32] W 0x00000000 Inner Hash digest
0x10638 SA_IN_HASH_DIG_2 [95:64] W 0x00000000 Inner Hash digest
0x1063C SA_IN_HASH_DIG_3 [127:96] W 0x00000000 Inner Hash digest
0x10640 SA_IN_HASH_DIG_4 [159:128] W 0x00000000 Inner Hash digest
0x10644 SA_OUT_HASH_DIG_0 [31:0] W 0x00000000 Outer Hash digest (write only)
0x10648 SA_OUT_HASH_DIG_1 [63:32] W 0x00000000 Outer Hash digest (write only)
0x1064C SA_OUT_HASH_DIG_2 [95:64] W 0x00000000 Outer Hash digest (write only)
0x10650 SA_OUT_HASH_DIG_3 [127:96] W 0x00000000 Outer Hash digest (write only)
0x10654 SA_OUT_HASH_DIG_4[159:128] W 0x00000000 Outer Hash digest (write only)
0x10658 SA_SPI R/W 0x00000000 IPsec SPI
0x1065C SA_SEQ_NO R/W 0x00000000 IPsec sequence number
0x10660 SA_SEQ_NO_MASK_L[31:0] R/W 0x00000000 IPsec sequence number mask (32 LSB)
0x10664 SA_SEQ_NO_MASK_H[63:32] R/W 0x00000000 IPsec sequence number mask (32 MSB)
0x10668 SA_NONCE R/W 0x00000000 Nonce value for AES CTR
0x1066C SA_PNTR R/W 0x00000000 Pointer to saved record (only for internal DMA)
0x10670 SA_ARC4_I_J_PNTR R/W 0x00000000 Saved ARC4 i & j pointers
0x10674 SA_ARC4_SBOX_PNTR R/W 0x00000000 Pointer to ARC4 SBOX data
0x10678- RESERVED - 0xXXXXXXXX Reserved
0x106BC
0x106C0 SA_IV_0 [31:0] R/W 0x00000000 Initialization Vector (DES, 3-DES, AES)
0x106C4 SA_IV_1 [63:32] R/W 0x00000000 Initialization Vector (DES, 3-DES, AES)
0x106C8 SA_IV_2 [95:64] R/W 0x00000000 Initialization Vector (AES)
0x106CC SA_IV_3 [127:96] R/W 0x00000000 Initialization Vector (AES)
0x106D0 SA_HASH_BYTE_CNTR R/W 0x00000000 Current hash byte count
0x106D4 SA_IN_HASH_MIR_0 [31:0] R 0x00000000 Inner Hash digest (mirror of 0x10630)
0x106D8 SA_IN_HASH_MIR_1 [63:32] R 0x00000000 Inner Hash digest …
0x106DC SA_IN_HASH_MIR_2 [95:64] R 0x00000000 Inner Hash digest …
0x106E0 SA_IN_HASH_MIR_3 [127:96] R 0x00000000 Inner Hash digest …
0x106E4 SA_IN_HASH_MIR_4 [159:128] R 0x00000000 Inner Hash digest (mirror of 0x10640)
0x106E8 SA_ICV_0 [31:0] R 0x00000000 HMAC result (Outbound/Inbound)
0x106EC SA_ICV_1 [63:32] R 0x00000000 HMAC result (Outbound/Inbound)
0x106F0 SA_ICV_2 [95:64] R 0x00000000 HMAC result (Outbound/Inbound)
0x106F4 SA_ICV_3 [127:96] R 0x00000000 HMAC result (Outbound/Inbound)
0x106F8 SA_ICV_4 [159:128] R 0x00000000 HMAC result (Outbound/Inbound)
0x106FC Context DONE W - Indicate Context is done (direct DMA mode)
ARC4 Buffer via TCM_SA interface
0x10700- ARC4_BUFFER R/W 0xXXXXXXXX ARC4 State Data – s-box array bytes 0 to 255
0x107FC
0x10800- RESERVED - 0xXXXXXXXX Reserved
0x17FFC
I/O BUFFER via TCM_DATA_IN
0x18000- INPUT_BUFFER W 0xXXXXXXXX Data Input Buffer (RAM)
0x187FC Address space depends on buffer size
0x18800- RESERVED - 0xXXXXXXXX Reserved
0x1BFFC
I/O BUFFER via TCM_DATA_OUT
0x1C000- OUTPUT_BUFFER R 0xXXXXXXXX Data Output Buffer (RAM)
0x1C7FC Address space depends on buffer size
0x1C800- RESERVED - 0xXXXXXXXX Reserved

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REGISTER
ADDRESS REGISTER NAME R/W Reset Default DESCRIPTION
(byte)
0x200FC
RNG REGISTERS via TCM2
Refer to 7.4 TRNG Registers
0x20100 TRNG_DATA R/W 0x00000000 32-bit random input/output word
0x20104 TRNG_STAT R 0x00000001 Status word
0x20108 TRNG_CTRL R/W 0x00000400 Control for TRNG
0x2010C TRNG_ENTA [15:0] R/W 0x00000000 Test register entropy A
0x20110 TRNG_ENTB [16:0] R/W 0x00000000 Test register entropy B
0x20114 TRNG_X0 [31:0] R/W 0x00000000 Test register for seed
0x20118 TRNG_X1 [63:32] R/W 0x00000000 Test register for seed
0x2011C TRNG_X2 [80:64] R/W 0x00000000 Test register for seed
0x20120 TRNG_CNTR [22:0] R/W 0x00000000 Counter register
0x20124 TRNG_ALARM_CNT R/W 0x00000000 4–bits indicating the alarm status
0x20128 TRNG_CFG R/W 0x00000FDC Configuration for TRNG
0x2012C TRNG_LFSR0_L [31:0] R 0x00000000 Test register
0x20130 TRNG_LFSR0_H [48:32] R 0x00000000 Test register
0x20134 TRNG_LFSR1_L [31:0] R 0x00000000 Test register
0x20138 TRNG_LFSR1_H [47:32] R 0x00000000 Test register
0x2013C TRNG_KEY0_L W 0x00000000 Key 0 register for X9.17
0x20140 TRNG_KEY0_H W 0x00000000 Key 0 register for X9.17
0x20144 TRNG_KEY1_L W 0x00000000 Key 1 register for X9.17
0x20148 TRNG_KEY1_H W 0x00000000 Key 1 register for X9.17
0x2014C TRNG_IV_L W 0x00000000 IV register for X9.17
0x20150 TRNG_IV_H W 0x00000000 IV register for X9.17
0x20154- RESERVED - 0xXXXXXXXX Reserved
0x307FC
PUBLIC KEY REGISTERS via TCM3
Refer to 6.6 PKA Registers
0x30800 PKA_A_PTR R/W 0x00000000 ‘A’ vector address pointer in Public Key RAM
0x30804 PKA_B_PTR R/W 0x00000000 ‘B’ vector address pointer in Public Key RAM
0x30808 PKA_C_PTR R/W 0x00000000 ‘C’ vector address pointer in Public Key RAM
0x3080C PKA_D_PTR R/W 0x00000000 ‘D’ vector address pointer in Public Key RAM
0x30810 PKA_A_LENGTH R/W 0x00000000 ‘A’ vector length in words
0x30814 PKA_B_LENGTH R/W 0x00000000 ‘B’ vector length in words
0x30818 PKA_SHIFT R/W 0x00000000 Number of bits to shift the vector
0x3081C PKA_FUNCTION R/W 0x00000000 Public key operation function code
0x30820 PKA_COMPARE R 0x00000000 Result of comparison operation
0x30824 PKA_RESULT_MSW R 0x00000800 Address pointer to MSW of result vector
0x30828 PKA_MOD_MSW R 0x00000800 Address pointer to MSW of modulus vector
0x3082C- RESERVED - 0xXXXXXXXX Reserved
0x40FFC
PUBLIC KEY RAM via TCM4
0x41000- PKM_RAM R/W 0xXXXXXXXX RAM for Public Key input and output vectors
0x41FF Address space depends on memory size.
Refer to section 6.2 Architecture.
0x42000- RESERVED - 0xXXXXXXXX Reserved
0x5001C
INTERRUPT CONTROLLER REGISTERS via TCM5
Refer to 9.4 Interrupt control registers
0x500A0 INT_UNMASK_STAT R 0x00000000 Interrupt source current state – prior to mask
INT_MASK_STAT R 0x00000000 Interrupt source current state – post mask
0x500A4
INT_CLR W 0x00000000 Clear selected interrupt(s)
0x500A8 INT_EN R/W 0x00000000 Interrupt mask register
0x500AC INT_CFG R/W 0x00000000 Host interrupt configuration register
0x500B0 INT_DESCR_RD W 0x00000000 Force Packet Engine to read next descriptor

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REGISTER
ADDRESS REGISTER NAME R/W Reset Default DESCRIPTION
(byte)
0x500B4 INT_DESCR_CNT R/W 0x00000001 # of Descriptors completed before Interrupt
0x500B8- RESERVED - 0xXXXXXXXX Reserved
0x6007C
DEVICE ID AND CONTROL REGISTERS (in Device and Control) via TCM6
Refer to 10.3 Device ID and control registers
0x60080 DC_CTRL R/W 0x00010001 Enables/Disables device functions
0x60084 DC_DEV_ID R 0x16AE0094 The Vendor ID and the Device ID of this part
0x60088 DC_DEV_INFO R 0x00C83720 A bitmap describing supported chip functions
The version number in the lowest order byte
may differ.
0x6008C- RESERVED - 0xXXXXXXXX Reserved
0x60090
DMA CONTROLLER REGISTERS (in Device and Control) via TCM6
Refer to 5.3 DMA register set
0x60094 DMA_USER_SOURCE R/W 0x00000000 Source address for user DMA transfer
0x60098 DMA_USER_DEST R/W 0x00000000 Destination address for user DMA transfer
0x6009C DMA_USER_CMD R/W 0x80000000 DMA burst length and command/status for user
DMA transfer
0x600A0- RESERVED - 0xXXXXXXXX Reserved
0x600D0
0x600D4 DMA_CFG R/W 0x00000003 Configuration and Status for DMA engine
0x600D8- RESERVED - 0xXXXXXXXX Reserved
0x6FFFC
PRNG REGISTERS via TCM7
Refer to 8.7 PRNG registers
0x70000 PRNG_STAT R 0x00000000 Status word
0x70004 PRNG_CTRL R/W 0x00000000 Control
0x70008 PRNG_SEED_L [31:0] W 0x00000000 Seed value
0x7000C PRNG_SEED_H [63:32] W 0x00000000 Seed value
0x70010 PRNG_KEY_0_L [31:0] W 0x00000000 Key register 0
0x70014 PRNG_KEY_0_H [63:32] W 0x00000000 Key register 0
0x70018 PRNG_KEY_1_L [31:0] W 0x00000000 Key register 1
0x7001C PRNG_KEY_1_H [63:32] W 0x00000000 Key register 1
0x70020 PRNG_RES_0 [31:0] R 0x00000000 Pseudo random result
0x70024 PRNG_RES_1 [63:32] R 0x00000000 Pseudo random result
0x70028 PRNG_RES_2 [95:64] R 0x00000000 Pseudo random result
0x7002C PRNG_RES_3 [127:96] R 0x00000000 Pseudo random result
0x70030 PRNG_LFSR_L [31:0] R/W 0x00000000 Counter register
0x70034 PRNG_LFSR_H [63:32] R/W 0x00000000 Counter register
0x70038- RESERVED - 0xXXXXXXXX Reserved
0x7FFFC

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END OF DOCUMENT

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