DFT Interview Questions from all Client Sites:

1. Scan chain stitching order in case of both positive edge & negative edge flops are present.

2. What approach was followed in scan chain stitching & balancing (bottomup/topdown) ?

3. ATPG flow related questions - Explain ATPG flow what you followed?

4. What is the procedure to generate toggle patterns?

5. Why do you toggle one capture clock at a time? If you toggle two capture clocks then what is
the problem?

6. LBIST related questions- How to debug LBIST failures on Silicon?

7. How to generate patterns for LBIST module if all scan related pins are internal?

8. LBIST logic & MBIST logic implementation techniques if any you know?

9. Questions on JTAG tap controller.

10. What are the differences between various JTAG standards?

11. What are the silicon failures I met & how did I debug those?

12. DRC violations related questions

13. Coverage Analysis related questions.

14. Team management related Questions

15. Silicon debugs related questions – What I faced in my previous projects.

16. Timing simulations – what switches did you use?

17. How do you test memory wrappers?

18. What are all the project done and its DFT futures ?

19. Is the project with JTAG ?

20. What you have done alone ?

21. What you did in RTL coding ?

22. Do you have any programing knowledge, like perl, TCL, verilog etc...

23. Which simulator you have used ?

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24. Explain capture operation in JTAG state machine

25. How many TCK(clocks) need, to reach CAPTURE IR state from UPDATE IR state?

26. Tell about project details

27. How many clocks were there?

28. How do you select the particular clock

29. If you use testclock how do you use it for capture procedure?

30. How do you handle multiple clock domains?

31. How do you specify capture clock using test procedure file?

32. Explain how sing le clock used top procedure three clocks?

33. During chain simulaton is there a clock skew how do you take care of it?

34. What changes do you expect from the PD team ?

35. what is the difference between clock skew & clock delay?

36. Explain clock leaker circuit and how it is controllable?

37. If clock domain cross over?how do you take care?

38. how do you take care of negative setup & hold viloation?

39. Howbidi are taken care during i/p and o/p if there is scan_in and scan_out how it is taken
care?

40. If data arrives before flops ie in previous flop what is the problem?

41. What is the pattern you used for mbist retention test?

42. Explain the retentioncb algorithm and what faults it is detecting?

43. out of three frequency which frequency u used for mbist?

44. what is the difference between functional and task

45. In perl, if we define array whether we can asses the array using scalar?

46. If clock is handled from top as single test clock whether you will loss coverage?

47. HOW 1/2 CYCLE delay is taken care in jtag?

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48. at what edge tdo is sampled ?

49. How many clock domain?

50. Do you have test clock separately?

51. How will you handle internal clock in the design?

52. How will you pulse these internal clock from top level?

53. Questions about clock divider circuit in the design

54. How TCG (test clock gating) circuit looks like?

55. Clock frequency used for shifting

56. The project # has how many clock domains and its frequency

57. How you are generating atspeed frequency ?

58. How you handled PLL

59. Explain clock leaker circuit and how it works

60. How do you get 250Mhz freq, do you have any logic for that?

61. Are you sharing scan pins in the top level of the design?

62. How do you share with BIDI pins

63. Why do you force it to "Z", any test logic you put, to control bidi's ?

64. During capture how you are handling bidi's ?

65. How you generated bist controller, which tool you have used?

66. How you are verifying the generated controller, is it in RTL level?

67. When you receive SDF with -ve delays, how will you handle it?

68. -ve HOLD means

69. Any violation in the SDF simulation

70. Any MCP (multi cycle path) in the design, if so, how you handled

71. How will you handle -ve and +ve edge Flip Flop in single scan chain?

72. Any problem if you stich randomly?

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73. Did you see any mismatch in the ATPG simulation?

74. How did you handle this mismatch?

75. What is your goal in next three years?

76. What kind of work you prefer?

77. What is your role in Network processor chip project?

78. Did you insert one MBIST controller for each memory?

79. What is the need of Bypass logic?

80. What were the issues faced in MBIST insertion?

81. Was there any critical issue you faced in clock domain?

82. What are the clocks that you used for shift & capture?

83. Did you shift to JTAG mode during capture?

84. What is the longest scan chain length?

85. In MBIST verification where did you inject the failure?

86. Which tool you used for MBIST verification?

87. Which tool you used for scan & Atpg?

88. What is the command for compiling NCSIM?

89. Have you written perl scripts? When did you use it?

90. Why do u interest to work with Cisco?

91. Have you worked in TestKompress?

92. How the EDT architecture looks like?

93. How to do EDT verification?

94. Do you know what are all the work that we are doing?

95. Which is Golden one (Pre -dft or Post dft)?

96. What will you do if the pre-dft & revised one differs?

97. How do you handle timing violations?

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98. What are all the recent projects involved?

99. What have you done in PBIST?

100. What are the issues faced?

101. Is there any failures and how to overcome it?

102. How the TCL is used?

103. How many bits are there in integer in verilog?

104. If we have 32 bit binary& '1' indicates the fail, how to find out the number of '1's in the
pattern?

105. If the pattern stream is 1234567, how to find out 34 in TCL?

106. Who gave the verification Environment? Is it verilog or C?

107. Have you done implementation phase in PBIST?

108. How was PBIST accessed? Either by JTAG, CPU, P1500?

109. Did you have diagnostic capability in your project?

110. How to diagnose from the top-level for PBIST?

111. Did u have external pin for data logger?

112. Did u have repairable memory? Have you involved in that?

113. How did you shift out the data from data logger and which clock have you used?

114. Is it serially shifted out?

115. Do you know the concepts of static timing analysis?

116. If we have the register array of 10 bits how to swap 5 bits of MSB with LSB?

117. How much are you aware of Perl? How it is helpful in your project?

118. If array @y={a,b,c,d } is assigned to a scalar variable what will be content of the scalar
variable?

119. Do you have experience in Design?

120. How to design a divided by 4 clock divider circuit?

121. It we want to add a synchronous reset in the circuit what will you do?

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122. Are u familiar with ATPG?

123. If we get the coverage 90% what are all things that you will consider?

124. Tell about the role in the current project

125. Description of the project

126. How do you choose the controller?

127. Are there any repairable memories in the design & will you consider those memories also
while doing controller partioning?

128. Tell about diagnostic logic & how it works?

129. How the data logger will shift out the data?

130. Is there any ROM in your design?

131. How will you conclude that ROM is working fine?

132. Which tool have you used for MBIST generation?

133. How will you test the MBIST? If there is any timing issue how will you handle it?

134. In which part will you insert pipeline registers?

135. Do you know about JTAG?

136. Are you using 1149.1 or 1149.6?

137. What are the mandatory instructions in JTAG?

138. Is there any mandatory opcode for any instruction? Why it’s all ones for Bypass?

139. How many numbers of clock domains & scan chains are in your design?

140. How do you handle the clock domains?

141. Tell about clock leaker circuit?

142. What is meant by transition faults? Which will cause the transition defect?

143. How do you do the at-speed testing in your design?

144. Did you do LOS or LOC?

145. If there is any defect in combinational logic thats slow functioning & other is functioning
fast, how will you find out?

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146. How the scan chain is stitched?

147. How will you handle the neg edge flops in the design?

148. If we put posedge flops in the beginning of the scan chain what will happen?

149. Have you done coverage analysis? How did you improve the coverage?

150. Have you written RTL coding?

151. Are you aware of dath path & control path implementation?

152. What is meant by full case & parallel case?

153. how many years of exp in DFT

154. for which client you have worked on

155. Tell me about your projects

156. How memories are verified in the design

157. How diagclk is given on tester

158. Why start padding bits and end padding bits in the scan out data

159. why we keep diagclk for two cycles after fail signal is de-aaserted

160. How Dp ram with two ports with different clk frequencies are handled in controller
generation

161. How depth of FIFO is decided

162. Have you done timing simulation?

163. How will you edit a SDF to overcome any particular critical path and to check weather
the rest of the design is working fine

164. Why you are interested in DFT

165. why we don't put BC cells for JTAG pins

166. which cell is kept for clk signals and why

167. How HIGHZ test is performed with state digram

168. what is the status of output2 pins in HIGHZ test

169. at which state we observe output and bidi pins in HIGHZ test

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170. how you did atpg verification

171. weather you faced any issues

172. what kind of patterns you have handled in ATPG Verification

173. draw the basic digram of scan operation

174. what is mathematical equivalent operator for logical OR

175. one puzzle question

176. Explain the flow followed for DFT.

177. What are C3 & C6 violations. How do you solve them.

178. Do you remember the command used to solve C6 in ATPG.

179. What is the purpose of having TMS signal.

180. Can you replace your Scan_en with TMS signal? If so what would be the result, will it
affect CAN/SHIFT/CAPTURE or others.

181. Explain the flow for DFT

182. Have you performed MBIST.

183. Do you have an idea about EDT

184. How do you verify MBIST

185. What is scan chain blockage

186. What is pattern failure? How you faced it any time if so, how do you handle it?

187. What is pattern simulation? How do you do that?

188. Have you worked on pattern simulation with respect to timing i.e. with SDF files?

189. Did you work on JTAG?

190. How do check the interconnection between 2 pins of two IC's using JTAG.

191. What are the tools you use for SCAN, ATPG& MBIST?

192. What is ATPG mode, Testmode, Scan mode & Funtional modes during testing. Explain
their differences.

193. What about your background

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194. What projects you have handled

195. what is your role in that

196. How was the reset in the design

197. How do you handle async and sync reset in ATPG

198. what is unit delay simulation

199. What is Zero delay simulation

200. if delay is specified in the verilog code and unit delay or zero delay switch is used then
what will happen

201. if negative values are present in sdf then which switch is used

202. what is negative setup

203. what is negative hold

204. what is the tck frequency in the design

205. can we run the tck at higher frequency

206. what you know in perl

207. pattern matching and replacement program

208. what are C6 C3 C4 violation

209. why lock up latches are required

210. how do you handled bidis while ATPG

211. how SE and test mode pins are different and what values are given to them

212. what is false path ,multicycle path explain with example

213. how many test clock domains in the design

214. weather scain chains were crossing clock domains and how you handled it

215. can we use functional clocks for test

216. why three different test clocks

217. How to decide the number of controllers for a given design (that is factors you consider).

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218. How many memories were there?

219. How many clock domains are in design?

220. What are the problems you faced?

221. Verification process, problems, scripts, automation, type of files used in the environment
in the project

222. Asked details about projects worked on (Based on what is given in resume).

223. Familiarity in DFT tools like COMBATADS and CUSION. How comfortable are you
using these tools.

224. Briefing about previous experience

225. DFT work involved in each project and what exactly was done by me

226. Issues faced in SDF simulations? Switches used

227. Questions on pipelining ,why to use of flops , where did you use , issues by using these

228. Do you familiar with IEEE 1149.1 and 1149.6?

229. Do you comfortable with C language and do work on it?

230. In RTL, blocking and non blocking statements use.

231. Previous Project related questions on verification

232. Do you familiar with ASIC, SOC, or FPGA.

233. What would you be interested to work? ( DFTverif or implementations)

234. Why you use FPGA in the USB-PHY project?

235. Tell me something about yourself?

236. How did u handle the clock domains in your design with in the scan chains?

237. What are the issues you faced during ATPG verification?

238. How many states are there in the JTAG tap machine?

239. What is the input which changes the tap states?

240. At what edge the shifting is done in the jtag ?

241. At what edge the TDO is activated?

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242. How did you handle Bidi and tristate buses in scan?

243. I have a random integer, i want to know that last bit is 1 how do you design the circuit?

244. How many bits an integer can have in verilog?

245. Were the reset were synchronous or asynchronous for scan insertion?

246. Divide by 2 counter using d-flipflop?

247. One question on cmos inverter? what happens if the gate is open?

248. How do you reset the flip flops in the design if there is no reset pin?

249. Timing issues in the ATPG verification?

250. What is multi-cycle path?

251. Had you worked on Prime-Time?

252. Did you use sdf-annotation file?

253. How do you handle clock domain crossing over in the RTL coding design?(clue
synchronizers)

254. If i give a task and you dont know anything about that task you have to start from the
scratch and you did not able to complete the task then what is your approach next?

255. In next 3 yrs where do you see yourself and in which domain?

256. Issues faced during the MBIST?

257. Issues faced during the JTAG?

258. Issues faced during the SCAN?

259. How did you decide the algorithm for the memory in MBIST?

260. How do you handle the multiple clock domains in the scan?

261. Design a divide by 4 counter ?

262. Explain the verilog code using Synchronous and Asynchronous Reset for the counter?

263. If there are Bidis in your design which are not sharing with the Scan pins does these
cause any roblem?

264. If Your mixing the clock domains there will be any problem during the atSpeed test
during capture?
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265. How do you write the Testbench in verilog ?

266. What tool you have used for MBIST?

267. What tool you have used for the simulation?

268. Why Jtag is Used?

269. What are the mandatory instructions in the jtag?

270. How do you do the board level testing using the jtag?

271. What is sample and Preload instruction?

272. What is Extest instruction?

273. What are the algorithms used?

274. Issues faced during the standalone verification of MBIST?

275. Have you worked on perl, TCL, C ?

276. What are the cell types you can use for BIDIs ?(clue BC_5 BC_7 and BC_1)

277. If there is a Mismatch in the Simulation how do you trace?(clue waveform)&which tool
you used?

278. How did you decide the controllers for a memory in MBIST?

279. If you do at the RTL level hw did you get the data on the Floor planning?

280. Did you had any routing congestions?

281. How did you test the memories?

282. Do you have any reparable memories in your design?

283. How do you shift the data which is failed?

284. What is the technology that you have used for your last project?

285. How many domains were there in your design?

286. Why you are comfortable in fastscan compared to Tetramax?

287. When multiple clock domains are there what are the things you need to take care?

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288. What are the setup and hold violations and how did you come to know the violation and
how u have analyzed? Have you used any debussy tool? How did you debug when there is X
on combo logic?

289. Which wave form window did you use?

290. Do you know any programming language?

291. What is $ in perl?

292. where do you use \ and \d+$ in perl?

293. when do you use .? ?

294. Do you know C language? What is the width of integer in C?

295. What is the width of integer in verilog?

296. Write a program for mux in verilog?

297. In a register how do you know whether LSB is one or zero?

298. Can you do it with bit wise operators? How?

299. Are you comfortable working in new technologies?

300. How do you improve coverage in ATPG? How do you start analyzing coverage in
ATPG?

301. Have you done ATPG verification? What are the issues you faced?

302. How you solved the issues?

303. Do you know named capture procedures? Explain

304. What are the TFT schemes you have? Which scheme do you use and why?

305. If I want to use LOS then what is the problem?

306. In scan suppose three clocks are coming from PLL and one test clock is coming from

307. Top level then what is your strategy for capture? How do you switch the test clock?

308. Can you explain about internal circuit of PLL and PLL clocking?

309. Do you have experience in RTL design?

310. Can you explain what are blocking and non blocking operators?

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311. In the RTL code for the flop whether you will go for blocking or non blocking
assignment?

312. How do you design PLI? Do you have any idea?

313. Have you written any test benches previously?

314. What is the structure of the test bench?

315. How you will apply the inputs from the test bench?

316. Have you worked on any MBIST generation insertion and verification?

317. Have you done any diagnostic verification? Explain.

318. How do you take care of bidis using test bench.

319. How many clocks where there in your design?

320. Did you used encounter test? for which vendor you have used?

321. Did you worked in ATPG timing/no-timing simulation?

322. What are the issues faced during timing/no-timing simulation?

323. Did your scan chain has clock domain mixing, what should be taken care while doing?

324. what will happens if you not insert lock-up latch during clock domain crossing?

325. If you insert lock-up latch will effect in functional mode?

326. Do you had -ve and +ve edge flops?

327. How do you design a ckt to check the bit of an integer is '1' or '0' in verilog.

328. What is integer length in verilog?

329. If you don't have reset pin for a flop then how do you handle during simulation?

330. What is the difference between JTAG EXTEST and SAMPLE instruction and why it is
used explain?

331. What clock TAP Controller is working?

332. What edge TDO is captured and why?

333. During ATPG did you faced any violations?

334. How do handle clocks during stuck-at and transition faults?

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335. If without time your vector simulation is failing then what will be approach?

336. What are the violations you have observed while doing ATPG timing simulation and how
do confirm same?

337. Do you know any verification languages?

338. If I give you new task which you don’t know and time for task is also very less then how
will be your approach?

339. Down the line in another 3 to 5 years where do will see yourself.

340. Do you have any questions for us?

341. Explain what is functional verification and how you will do it?

342. what are the problems you have faced during tracing the chains?

343. How lock-up latch enable pin is connected?

344. If you have async reset how do you handle while stiching?

345. How do you code asynchronous flop in verilog?

346. How will you design a divide by 4 clk?

347. How do you initialize the flop if it doesn’t have reset pin?

348. What is -negative hold violation?

349. Did you face any problem with negative delays in SDF?

350. If you have negative delay how do you handled during simulation?

351. Did you seen -negtive setup and hold information in the library file and what are those?
Why negative delays?

352. How do you handle async reset during insertion?

353. How do you handle clocks during stuck-at and transition faults?

354. Do had cross clock domain stitching?

355. Is there any need of timing clean for DFT mode?

356. Did you face any problem with ATPG coverage and how you have solved?

357. During memory BIST verification did you used production and diagnostic mode?

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358. Is there any other way that we confirm which memory is failing and why without seeing
waveforms?

359. What work you have done in scan &atpg

360. How many states in Jtag and how is working?

361. What test modes were there?

362. How mbist was being enabled? (jtag or any other means) and working of mbist
controller mbist_done and fail operation w.r.t combiner DID i implemented datalogger
circuit? What sequence you followed for mbist?

363. Explain bsr cell working

364. Explain the stuck at faults for a 2 - input AND gate andpatttern for detecting a@0?

365. Any issues faced in chain simulation? How you corrected it?

366. HOw many flops in your design

367. How many chains in your design and flops per chain

368. How i managed scan router to transform 16 chains to 8 chains

369. Wgat was the purppose of converting all chains into 1 chain

370. How were you selecting them through jtag?

371. Some questions on verilog integer values

372. What switch you used for 64 bit simulator?

373. How was scan pins were shared and its working if bidis?

374. In scan insertion, you have 2 clock domain and one scan chain. will you face any issue in
this case?

375. How to do Transition ATPG?

376. In LOC if you have problem in scan_en toggling, how will you take care?

377. How will you give dead cycles?

378. If you have low test coverage, how will you debug?

379. What about clock rule violation, do we need to take care?

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380. In a single flop who's clock line is connected both clock input and D input, what is this
violation how will you fix this in the ATPG?

381. In a single flop, 'Q' output has 'X' value , how will you debug this? (in both timing and
notiming)

382. How you did the MBIST verification (writing test bech and CMBIST)

383. List the steps followed for MBIST verification

384. At the tester side MBIST is failing, how will you debug which memory is failing?

385. Tool used for MBIST generation and insertion?

386. BIST and Memory uses the same clock or not?

387. At what frequency you will test the memory?

388. How you verified JTAG (tool used for this verification)

389. what is the input for this COMBATADS tool

390. Explain about the BSDL file, what are all the information you get from BSDL file?

391. Explain about sample and preload instruction?

392. If you have BC7 cell in the design how will you test this cell?

393. If you have a user defined cell, how will you handle this?

394. What is your goal? In which domain you would like to work.

395. How do you handle both negedge and posedge flops? Explain the reasons?

396. Do you combine multiclock domain flops in a single chain.. ?

397. How will u take care bidi testing ?

398. How will u handle multiple clock domains in SCAN and ATPG?

399. How will u improve coverge for a module ?

400. How will u analyze AU faults in fastscan ?

401. In TDL , if you want to insert dummy cycles before and after capture pulse , what u do in
fastscan ? (Adding dummy cycles in testproc file)

402. How do u test DDR interface?

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403. Explain the diagnostic operation in MBIST?

404. What are the values Diagnostic scan out has?

405. On what basis u select MBIST controller ?

406. Difference between cpubist and mist ?

407. How Pbist test the memories ? sequential or parallel ?

408. How will u handle multiple pbist controllers?

409. Diagnostic scanout operation in PBIST?

410. Do u know, pbist verfication flow?

411. TDO is sampled on posedge and negedge of tck ?

412. Explain the necassity of sample/preload instruction?

413. How will u verify the boundary scan?

414. What u see in BSDL file?

415. How will u verify the Boundary scan logic?

416. Explain, how will handle multiple taps in a design 24)what is bypass register length in
when 2 taps connected in seriel?

417. Frequency of TCk ?

418. How will u detect 'X' in a 8 bit data bus in verilog?

419. Code a verilog D flipflop with async reset?

420. Are there any repairable memories in the design & will you consider those memories also
while doing controller partioning?

421. Tell about diagnostic logic & how it works?

422. How the data logger will shift out the data?

423. Is there any ROM in your design?

424. How will you conclude that ROM is working fine?

425. Which tool have you used for MBIST generation?

426. How will you test the MBIST? If there is any timing issue how will you handle it?

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427. In which part will you insert pipeline registers?

428. Do you know about JTAG?

429. Are you using 1149.1 or 1149.6?

430. What are the mandatory instructions in JTAG?

431. Is there any mandatory opcode for any instruction? Why its all ones for Bypass?

432. How many number of clock domains & scan chains are in your design?

433. How do you handle the clock domains?

434. Tell about clock leaker circuit?

435. What is meant by transition faults? Which will cause the transition defect?

436. How do you do the at-speed testing in your design?

437. Did you do LOS or LOC?

438. If there is any defect in combinational logic thats slow functioning & other is functioning
fast, how will you find out?

439. How the scan chain is stitched?

440. How will you handle the neg edge flops in the design?

441. If we put posedge flops in the beginning of the scan chain what will happen?

442. Have you done coverage analysis?How did you improve the coverage

443. Have you written RTL coding?

444. Are you aware of dath path & control path implementation?

445. What is meant by full case & parallel case?

446. What was the complexity of the projects you have done so far?

Here, one should explain about No. of diffrent clock domains, No. of memories,

No. of MBIST controllers, PLL Clocking Scheme etc. depending on projects in the resume.

447. Have you faced problems in simulation?

Simulation Problems can be broadly described in two catagaries.

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 1. Module Level.

Problems in simulation will arise at this level, mainly due to mismatch between the Memory
models.

We will have two Memory Models of memories in our design.

a. MBIST / ATPG Memory Model. and b. Verilog Memory Model.

MBIST / ATPG Memory Model will be used to generate the MBIST Controller Logic, by
MBIST Generation tool (e.g. MBISTArchitect).

Whereas, Verilog Memory Model will be used by simulator in MBIST Verification phase.

These two Models should match with each other in describing the memory.

If they doesn't match, we will have mismatches in the simulation.

Another cause of Module Level Simulation Mismatch may be the

improper pipeline stages calculations while generating MBIST Controller Logic.

2. Top Level.

Here, problems may arise due to improper hook-up of MBIST Controller logic with J-TAG
circuitary.

448. If you have mismatch in simulation, how do you go about it? (How to Debug it?)

In case of mismatch in Module level simulation, we will check the dofiles for MBIST Logic
Generation. We will check if algorithms were correctly mentioned. Also, we will check if
MBIST / ATPG Memory Model and Verilog Memory Model matches with each other.

In case of mismatch in top level simulation, we will check the top J-TAG hook-up with
MBIST Logic. Also, we will check our "clock generation scheme". Most of the time, the
simulation will fail because of clock issues. Say, we have a PLL inside our design, and we
didn't wait till PLL gets locked up to the rated frequency; then we can have problems in
simulation.

449. What is hold time violation in general?

Hold Time Violation in general is due to mismatch between the clock edges at connected
FlipFlops. These violations will come up mostly due to the clock skew.

450. What is MBIST explain with a diagram and why is it needed?

MBIST eases the Memory testing. It takes care of Pattern Generation to check the memories.

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451. It takes care of feeding those patterns to deeply embedded memories in TEST MODE.
(Localized MBIST Controllers and Collars) .It takes care of at-speed memory testing. It
reduces the tester operations required to test the memory. As with MBIST; tester only
provides clock, enable signals and then waits for fail or test done signals. (With Intgration of
MBIST with J-TAG, even enable signals are fed through J-TAG.) Solves the problem of
deterministic ATPG for memories. Hence, ATPG work for memories is saved. It is more
suitable to target memory related faults, like neighborhood pattern sensitive faults.

452. Why is the Collar needed? Can you have any logic other than the Muxes in the Collar?

The basic function of Collar is to diffrentiate between Functional Memory Signals and Test
Memory Signals; and feed memory with proper signals in TEST MODE and FUNCTIONAL
MODE.

453. What is a Bypass circuit and why is it needed?

454. The Bypass ciruit is the mechanism by which we can gain OBSERVABILLITY on Input
Side and CONTROBILLITY on output side of Memories in ATPG Mode; which is
otherwise very difficult to obtain. Draw the Bypass circuitry. is the FlipFlops, driving data
output signals of memories (Thus, achieving CONROLABILITY on Output side of
Memories); fed by Ex-OR Logic driven by Input signals of memories (Thus, achieving
OBSERVABILITY on Input side of Memories).

455. Why do we need the flops in the bypass circuitry? Can we do away with the flops of the
bypass circuitry? What will be its impact on the design?

We certainly require flops in our bypass circuit. These flops we will be stitching in our scan
chains; to gain controllability and observability around Memories.

456. Can we go for scan in case of memories? whycant we go for scan in case of memories?

Deterministic ATPG is very difficult in case of Memories. Also, some memory faults are
difficult to target using conventional scan methodology. (e.g. Neighbourhood Pattern
sensetive faults) Testing of Memories at-speed will be a issue. Tester overhead will increase
to impractical level. No. of Patterns can also be the issue.

457. If you do not have the bypass circuitry in the MBIST; how will you handle the memory
in scan and atpg?

Say you are not allowed to introduce any extra logic around the memory during scan, how
will you gain coverage of the downstream logic being driven by the memory output. We will
loose coverage around the memories then.

458. What was the memory configurations for which mbist were done? How many bist
controllers were used? What was the strategy?
21
 This is to be answered with respect to: Single Port / Double Port / Multiport Memories.
Frequency of operation of Memories. Placement of Memories and level of embedding.
Repair Mechanism present or not, etc..

459. How is mbist insertion done?

MBIST insertion can be done at RTL level or Gate level. On RTL Level, it can be manual or
using tools like MBISTArchitect or BISTINPLACE. On gate Level, it can be using tools like
BISTINPLACE.

460. Please write the MBIST Architecture of single controller with mutiple memories and
explain how you insert this.

It is to be answered with respect to: If MBIST Controller was testing the Memories in
SERIAL or PARALLEL Fashion. And then, how the memories were portmapped to get
connected to MBIST Controller, through collar.

461. What is the function of collar?

Collar selects between TEST MODE and FUNCTIONAL MODE signals to reach to
Memory; depending on mode.

462. If you have a situation like memories are near or far in the netlist, what is your strategy
for MBIST insertion? Explain.

We will always try to group nearer memories; so that only one controller can take care of
their testing.

463. What problems you can face when Multiple memories with single controller executing in
parallel? Impact of this on the design?

The main problem will be the power consumption in IC, when controller is run in parallel.
When controller runs in parallel; there will be many transitions inside IC. This is going to
dissipate lot of power, and if it exceeds beyond rated power consumption of chip; that may
be hazardous to the chip.

464. Controller should be Sequential or parallel operation?

Depends on Testing Time, power, and testlogic budget.

465. How did you generate testbench for MBIST?

Module Level Testbench was generated by MBISTArchitect Tool. Top Level Testbench was
generated by CMBIST Tool. One can also generate the testbench manually on both the
levels.

22
466. Which takes more time sequential or parallel testing of memories?

467. Sequential testing of memories takes more time than the parallel testing.

468. What type of faults where targeted & their coverage ?

469. How many clock domains where there in your design & how it was handled during scan
chain ?

470. No. of scan chains & scan chain length in the design.

471. Transition fault pattern generation for multiple clock domain.

472. How Bidiswhere taken care during ATPG .

473. Individual clock domain frequencies for TFT & their coverage .

474. Where you lost the Coverage & why ?

475. For MBIST how many memories & controllers in the design , based on what you chose
the controllers?

476. How controllers where tested?

477. What approach was used (parallel / Serial) while testing memories?

478. Algorithms used by the controller for memory testing?

479. Strategy & test procedure followed while testing the controller.

480. Did you do retention testing for memories?

481. Did you do Gate level simulation for ATPG & issues faced?

482. Knowledge of skills (like Perl scripting, C modeling if mentioned in the resume ) ?

483. What is the HDL language used & your comfort level (Verilog / VHDL ) ?

484. Multi Pass flow in PMC:

Ans: DC, DC_NOCG, DC_NOCG_RCON, DC_RAM, DC_RAM_NOCOMP.

485. What is diff bw DC & DC_NOCG

Ans: Explained, In DC mode using with clock gating and in DC_NOCG using without clock
gating.

486. What is the use of clock gaters in design? Why they are keeping?

23
 Ans: Explained, to reduce the power dissipation, we are using clock gaters in design. Power
dissipation p= ½ cv2 f.(clock frequency =f)

487. Can u draw the internal diagram of clock gating cell?

488. What is use of latch in clock gating cell?

Ans: I explained to remove glitches.

489. How glitches can be remove through latch

Ans: I drew the wave forms; explanation was not much clear from my side.

490. What faults are targeting in DC and DC_NOCG mode.

Ans: I explained in DC mode SE is always “1” so we can not cover EN logic side faults. so
we are targeting EN logic side faults in DC_NOCG.

491. Why tool is not able to keep “1” for EN .

Ans: I explained we cannot keep one.

492. Can u explain any one of the coverage analysis mode.

Ans: I explained EXTEST mode and after I explained IOTOGGLE mode.

493. What faults are targeting in NOCOMP mode (draw any structure)

Ans: I explained we are using 13 bit UDR and for compression mode compressb is 0 and in
uncompression mode using 1. We can cover SA0 faults. (still more explanation was
expected by the interviewer)

494. Explain 8051 microcontroller.

Ans: I explained it is 8 bit microcontroller and basic microcontroller.

495. How many Timers and memory size of 8051.

496. What are the issues faced during timing simulation and how you resolved?

1) setup violation:

how to avoid this ?

ans: slowdown clock frequency, reduce delay in data path

(2) hold violation

24
 how to avoid this ?

ans: increase delay in data path, increase delay in clock path of launch flop (by adding delay)
than capture flop.

(3). netlist structure issue between pre-layout and post-layout netlist faced in SERIALS0

497. can hold violation resolve with respect to clock ? how ?

ans: yes. increase delay in clock path of launch flop (by adding delay) than capture flop.

498. what are the debug you did on post silicon ?

ans: 1. memory repairable process. The fault location of the entire column in the memory
are replaced with good redundancy column. Qualcom have column redundancy memories. If
failed a ROM in Tester, observed that delivered signature of ROM was wrong. Regenerated
signature with correct data and delivered to PE.

499. In what are the different phases the silicon will be tested?

ans: phase0: target pass from any one of the LV(low votage), NV(nominal voltage),
HV(high voltage)

phase1: target pass from all LV,NV,HV

phase2: target temperature

phase3: target slow/medium/fast parts

500. How the memory bist logic works ? What are the blocks inside BIST controller and how
it is working for different algorithm?

ans: 1. FSM, address generator, data generator, control signals generator, comparator, etc..

2. FSM will generate addr, data, control signals based on algorithm. The read data from
memory and the expected data from BIST logic are XNOR-ed to ensure both are same.

501. Can directly test the memory using tester instead using BIST logic ?

ans:1. accessing all memories from top level is difficult

2. generate required pattern to target the specific faults are difficult.

502. Other than BIST, what are the ways to test the memories ?

ans: Through ATPG we can test the faults on memory ports. But can not target the faults on
all the memory cells.

25
503. If a memory is failing on post silicon, what you do?

ans: find the failing location using FAT(Failure Analysis Test) and replace the fault cell with
good spare cell.

504. How the UDR programming happens?

ans: Through JTAG and explained about TAP controller.

505. What are the faults and how you are targeted those faults in ATPG ?

ans:transition and stuck-at faults. explained about various modes of ac and dc...

506. How the data retention test happens for memory?

ans: write data into memory at NV(nominal voltage) and dip the NV for some time then
again read data from the memory at NV to ensure data is retained in memory.

507. What are the different algorithms used to test memories? Describe working of each
algorithm? what kind faults are captured and not captured in each algorithm ?

ans: algorithm: march, CKX(checker board in X direction) , CKY(checker board in Y

direction), SDX (static decoder in X direction), SDY (static decoder in Y direction).

fauts: stuck-at, transition, coupling, address decoding fault, neighourhood transition fault,
etc..

508. Memory test is passing from your side. But the functional team says memory is not
behaving properly. What you do ?

ans: we ask them which address location is failing and what kind data is mismatching when
read back. based on that we try with different algorithm to test the memories.

509. How to identify base cell and neighborhood cells from memory.

ans: surrounding cells have unique values and base cell have different value.

510. What is the difference between timing and no-timing simulation? What happen if no-
timing simulation run with high frequency ?

Notiming sims will pass with any frequency.

511. PMC ET Flow?

Explained in detail about ET Flow process – Starting with Build model till commit the last
mode.

26
512. PMC multipass flow details?

Outlined about AC, AC_NOCG, AC_NOCG_RCON, AC_NOCOMP_NOCG, DC,

DC_NOCG, DC_NOCG_RCON, DC_COMP_NOCG & DC_NOCOMP_NOCG mode
initialization files

513. What is fault simulation?

After generating the PFT, will do fault simulation to determine which faults the patterns
detect. Thus we can evaluate the quality of a test set.

514. What is fault collapsing? What are they – explain?

It is process to reduce the overlapped stuck at faults. Two types of fault collapsing
techniques:

1.Equivalence fault collapsing: Two faults of a Boolean circuit are called equivalent if they
have exactly the same set of tests and have identical output functions.

2. Dominance fault collapsing: If all tests of fault F1 (in PI) detect another fault F2 (in PO),
then F2 is said to dominate F1, and fault F2 can be deleted.

515. Tell something about Compression techniques?

The compression in DFT is basically used for tester application time & test data volume. It is
the reduction in these parameters compared to a non-compressed scan chain. We will be
opting compression technique only when there are more number of scan chains compared
with limited number of io pins.

516. Tell delay-test in detail?

Two structural fault model are stuck-at fault model & transition fault model. Stcuk-at fault
affect the logical behavior of the system but transition faults affect the timing behavior of the
design. To test such delay inducing faults, scan based transition fault testing techniques are
usually used. Two existing methods are LOC & LOS.

In los the transition is launched during the last shift cycle from the scan path, the SE will be
high during this time and then immediately turned off to capture the response during the
capture cycle.

In loc SE wiil be turned off after loading; transition is launched at functional frequency & it
will capture immediately during capture cycle. Then SE willtrun ON and the captured value
will shift it out.

517. Pattern will be less in los than loc, why?

27
518. Tell me about coverage analysis you have done in your project in detail?

519. What are the various methods you have opted to improve it over 99%?

520. What are the post silicon activities you have done?

Chip test coverage verification.

521. How you are doing CFV? Tell in detail.

Explained about CFV what I did for TORRES, CONDOR & TORRES_MCM – How to
make nci file and inputting it.

522. Details about PMC atpg flow?

Explained in detail about ET Flow process – Starting with Build model till commit the last
mode.

523. Partial scan & full scan?

Full scan is a scan design methodology that replaces all storage elements in the design with
their scannable equivalents and connects them in to scan chains.

But in partial scan, only a certain percentage of storage elements are replaced & connected to
scan chain. This is mainly due to constrains on area & timing.

524. Why they are topup together & consider for total fault coverage?

525. Explain compression &uncompression ?

The compression in DFT is basically used for tester application time & test data volume. It is
the reduction in these parameters compared to a non-compressed scan chain.

We will be opting compression technique only when there are more number of scan chains
compared with limited number of io pins.

526. How you identify & fix compression ratio in your particular design?

527. What is test coverage & fault coverage?

Both are measures of test quality:

Test coverage is the ratio of percentage of detected faults by all testable faults.

Fault coverage is the ratio of percentage of detected faults by all allfaults(full faults).

528. Iddq fault model?

28
 There are three main types of defect categories: functional, IDDQ & at-speed. in which
IDDQ testing measures supply current going through the circuit in the quiescent state.

529. During path-delay, what is the min pattern number you have noticed?

530. What are all violations you have noticed & how you fixed them?

531. What Are all the debugging technique you have implemented for Coverage
improvements.

532. Why we are doing simulation ?

With a given test vector, we need to predict the logic values in the good circuit or fault-free
circuit at all the circuit outputs.

533. Timing simulation – why, how etc.. ?

We are running simulations at slow frequency for only SA faults.. for At speed testing, we
require functional frequency.

534. What is an sdf file ?why you are using it ? how it looks ?

Sdf file is the standard delay format for timing simulation. It is interpret the different timing
of data.

535. What re all the debugging technique you have used in timing simulation issues?

536. What is a broken scan chain?

A scan chain is getting broken during scan stitching. The effective way to test the scan chains
to detect any broken scan chains is to do scan flush. A chain test simply shifts a sequence
through the entire scan chain without exercising the functional circuitry.

537. What are all practical approaches you will take if found scan chain broken?

The effective way to test the scan chains to detect any broken scan chains, is to do scan flush.
A chain test simply shifts a sequence through the entire scan chain without exercising the
functional circuitry.

538. What are the disadvantages of MBIST logic you have noticed?

539. What is there in your memory library?

540. How will you do coverage analysis.

541. wrapper generation (P1500)

29
542. how will you test the isolation cells, level shifters and the glue logic if there are multiple
power domains

543. If there are two functional clocks how will you to transition fault anaylysis--I told I shall
try to control them from through the STIL file

544. What are the issues you ran into when working

545. how will you do fault grading ? Using the functional patterns use the same so that you
can reduce the total patterns

546. In between I told loadable and non-loadable cells.

547. how will you see if there are non-scan cell

548. were there multiple scan clocks , if so how did u take care of the DFT approach

549. If there are clock gating logic how will you test it ?

550. What other issues did u see

551. Did u use OCC and how did u test them.

552. Have you worked on compression--If yes then she said ok.

553. SOC level DFT how was the pattern generation take care..

554. Tell me some issues during scan insertion at SOC level

555. Told about the pattern diagnosis

556. If there are multiple functional clocks how will be the launch and capture be done.

557. If there are multiple clock domains how will you do transition or stuck-at and what other
fault models will you use

558. Do you have exposure with BSCAN

559. Why we do simulation, even though we generate the patterns on the same scan stiched
netlist. What are we expecting from simulation, as it is not the actual hardware we are
testing?

560. Why people prefer doing serial simulation though it takes very long time compared to
parallel simulation. Tester doesn't support parallel simulation. Still we don't prefer parallel
simulation on the netlist, why?

30
561. What are the disadvantages of the MBIST on the chip other than the extra logic
overheard? 4. Why the coverage for the transition faults is always less than Stuck-at faults?

562. Will MBIST be part of Scan logic?

563. How do we deduct to a particular net or node from a failure on the tester?

564. What are the main things to look for to improve the coverage?

565. Why latches are made transparent during scan?

566. What is the % overhead of the MBIST? 10. what is the typical vector count which gives
the maximum coverage?

567. What is the significance of scan-compression/EDT during ATPG?

To decrease the TDV and TAT

568. What is the reason for increase in pattern count for compressed mode?
Because the chain lenght is small,more number of chains exist.More number of control bits
toidentify faults in EDT.

569. The actual compression achieved will be less than the specified compression factor.Why?
Because of extra cycles(initialization cycles) in EDT.

570. Deciding factors of scan design?

Number of channels on tester, memory available on channel and number of scan pins.

571. Scan length, Scan chains, hierarchical scan concept?

572. How scan chains are handled from a 3rd party IP in the chip?By using "add subchain
command"

573. Use of LOCKUP latch? a) When two clock domains exist , b) When one domain with
different edges trigger the flops,c) When clock skew is more than half cycle of hold time.

574. Difference between LOS and LOC? Look for the basic differences in the guide. Other
difference is that in LOS,there is a chance of testing unrequired functional paths because of
last shift is done when SE=1.

31
575. Scan considerations required for At-speed test?
a) OCC that supports and generate 2 pulses for capture cycle. b) Free running functional
clocks.

576. What are advantages of LOS and disadvantages when compared to LOC?

577. How do you avoid limitations of LOS?

a) Consider SE as clock, b) Pipeline scan enable.

578. How do we manage chain balancing and what is the requirement?

579. Timing issues specific to scan chain clock domain mixing? Hold issues.Use lockup latch
to avoid them.Clock skew to be decreased.

580. How to avoid hold issues when scan chain is stitched from +ve edge to –ve edge flop?

581. Explain Launch-off-Capture.

1) What are the Hardware modifications? (Hint: Scan Enable.)
582. Explain Launch-on-Shift.
583. Compare Launch-off-Capture Versus Launch-on-Shift in terms of Test Generation.
584. Compare Launch-off-Capture Versus Launch-on-Shift in terms of Methodology (How
you pulse ? etc..).
585. Power Issues in Testing:
1) Why do we need to worry about power in Testing
2) Explain Short, Dynamic and Leakage power dissipation in CMOS.
3) Capture Power (Why is it happening? What does it affects ? Methods to control it.
Limitations)
4) Shift Power (Why is it happening? What does it affects ? Methods to control it.
Limitations)
586. Compare Transition delay model Versus Path Delay Model.
587. Given a circuit generate the pattern for both delay models.
588. Why Path delay model is used when we have Transition delay model ?
589. If you are to advise the test engineer which delay model do you prefer and why ?
590. Advantages and Dis Adv of Path delay model.
591. Hold time violation Versus Setup time Violation.
592. Given a circuit identify Hold/Setup time violation

32
593. How do you fix the Hold/Setup time violation
594. Explain Test Cost ?
595. JTAG Basics (TAP Controller, Inputs, 16 States etc...).
596. Memory Testing Basics (Main components and how they interact)
597. How do you perform Binary Search in Scan chain? ( Diagnostics ) Different methods ?
598. wht is the diffrence between verification and dft?
599. difference between defect, fault and failure?
600. wht is observability and controlability?
601. wht is scan?
602. how can we perform scan operation?
603. wht is serial and parallel loading?
604. wht is the difference between sequential and combinational atpg?
605. wht is atpg?
606. wht is drc violation?
607. wht is fault model?
608. how many fault models are there?
609. wht is scan stiching?
610. different command option….
611. wht is bist?
612. wht is bisa?
613. wht is bscan?
614. How is logic transition fault is different from memory transition fault.
615. What are RAM sequential patterns?
616. Diff b/w Named Capture Precedures and Clock Procedures
617. What are the typical scan clock frequencies?
618. How much is your design count? Complexity?
619. What is possible cause of simulation mismatches when you simulae the generated ATPG
patterns? what is right way to debug them?
620. how do you solve coverage issues?
621. what is normal mode and at-speed mode?
622. what is mbist?

33
623. what is dft coverage? how to get high dft coverage?
624. normal flow for dft ?
625. Whats the difference between structural and functional vectors?
626. What the major problem faced in dft with tri-state buffers and how is it resolved.
627. Which is advantageous, launch at shift or capture launch.
628. How to achieve high fault coverage. How to increase it.
629. latch – how is it used in dft for sync two clock domains.
630. Fault types?
631. Does the dft vectors test the functionality of the design also?
632. What does test procedure files have?
633. How is logic transition fault is different from memory transition fault.
634. What are RAM sequential patterns?
635. Diff b/w Named Capture Precedures and Clock Procedures
636. What are the typical scan clock frequencies?
637. How much is your design count? Complexity?
638. What is possible cause of simulation mismatches when you simulae the generated ATPG
patterns? what is right way to debug them?
639. How do you solve coverage issues?
640. Whats the difference between structural and functional vectors.
641. What the major problem faced in dft with tri-state buffers and how is it resolved.
642. How to achieve high fault coverage. How to increase it.
643. Does the dft vectors test the functionality of the design also?
644. What is scannability checking.
645. Give three Clock drc rules and how to fix them.
646. What does test procedure files have?
647. What problems u faced while inserting test points.
648. what's the different using sync reset or async reset?
649. what's the affect for the coveray of the two reset?
650. How to do IDDQ below 90nm?
651. What is the DFT process for an ASIC?
652. What factors that affect scan chains?

34
653. What is the purpose of DFT?
654. What are the major cost factors of DFT and what do you do to lower costs?
655. What are the errors/problems that occur during the DFT process and how do you resolve
them?
656. What tests do people use for DFT and what are their purpose?
657. How do clock domains affect DFT and how to you handle them?
658. Given a small circuit (see diagram) how would you generate tests for it?
659. for path-delay pattern, what is the min pattern number needed?
660. For mbist , what is the min pattern needed? 0/1; &|a/5
661. Why we do simulation, even though we generate the patterns on the same scan stiched
netlist. What are we expecting from simulation, as it is not the actual hardware we are
testing?
662. Why people prefer doing serial simulation though it takes very long time compared to
parallel simulation. Tester doesn't support parallel simulation. Still we don't prefer parallel
simulation on the netlist, why?
663. what are the disadvantages of the MBIST on the chip other than the extra logic
overheard?
664. Why the coverage for the transition faults is always less than Stuck-at faults?
665. Will MBIST be part of Scan logic?
666. How do we deduct to a particular net or node from a mismatch on the tester?
667. What are the main things to look for to improve the coverage?
668. why latches are made transparent during scan?
669. what is the % overhead of the MBIST logic?
670. what is the typical vector count which gives the maximum coverage?
671. During ATPG we use some models, and during simulation other one, the ATPG could
generate wrong patterns due to inconsistency in the model.
672. with serial simulation, you check also the worst hold time constraints.
673. hardcoded Bist is limited to a type of checks, if you need to extend or reduce it, you could
not.
674. well you do not check the same stuff, no?

35
675. To improve the coverage, you could report the uncovered faults, and after you need to
analysis this list.
676. which latch?, for the latch used for clock gating, need only to be transparent during the
shift phase, during the capture, this one could used the functional mode, to improve the
coverage.
677. That depend of the MBIST strategy, I means, did you want to have a BIST engine for
each memory, or for a group....
678. Too large question, that depend of your design, I means ratio combinational versus flop,
and which coverage you want to reach?
679. What constraints should be set and considerations should be taken while generation of the
ATPG patterns?
680. What common Interview Questions are asked for the Test Pattern Generation and
TetraMax usage?
681. wht is the diffrence between verification and dft?
682. difference between defect, fault and failure?
683. wht is observability and controlability?
684. wht is scan?
685. how can we perform scan operation?
686. wht is serial and parallel loading?
687. wht is the difference between sequential and combinational atpg?
688. wht is atpg?
689. wht is drc violation?
690. wht is fault model?
691. how many fault models are there?
692. wht is scan stiching?
693. different command option….
694. How is logic transition fault is different from memory transition fault.
695. What are RAM sequential patterns?
696. Diff b/w Named Capture Precedures and Clock Procedures
697. What are the typical scan clock frequencies?
698. How much is your design count? Complexity?

36
699. What is possible cause of simulation mismatches when you simulae the generated ATPG
atterns? what is right way to debug them?
700. how do you solve coverage issues?
701. what is normal mode and at-speed mode?
702. what is mbist?
703. what is dft coverage? how to get high dft coverage?
704. normal flow for dft ?
705. Whats the difference between structural and functional vectors?
706. What the major problem faced in dft with tri-state buffers and how is it resolved.
707. Which is advantageous, launch at shift or capture launch.
708. How to achieve high fault coverage. How to increase it.
709. latch – how is it used in dft for sync two clock domains.
710. Fault types?
711. Does the dft vectors test the functionality of the design also?
712. What does test procedure files have?
713. I have three memories in my design. I set_scan_element false for them when do DFT.
But it still report that :
Warning:Cell VPOST_FILTER/FILTER_C_LINE_BUFFER/T018SRF3X_368X16M4 has
no function specification.
Warning: Cell VPOST_FILTER/FILTER_Y_LINE_BUFFER/T018SRF3X_720X8M4 has
no function specification.
Warning: Cell VPOST_OSD/BIST_RA1SH_SR256X24S/T018SRF3X_256X24M4 has no
function specification.
Warning: the required number of observe test points can not be met. (TEST-147)
Warning: Violations occurred during test design rule checking. (TEST-124)
How to solve this kind violation?
714. When i write the netlist that has been inserted scan chains, there are "asign" statement in
my netlist. I have try to remove them from netlist and add some command like below:
set save_place [current_design]
foreach_in_collection design [ get_designs "*" ] {
current_design $design

37
 set_fix_multiple_port_nets -all -outputs -feedthroughs -constants -buffer_constants;
}
current_design $save_place
set_fix_multiple_port_nets -all -outputs -feedthroughs -constants -buffer_constants;

unset save_place;
But these commands can't affect the "assign" statement written in my netlist.
715. How to decide the observe and control points number?
I want to use set_testability_configuration command to set observe and control points
neumber? Who can tell me how to set it?
716. Is it recommend to have tri-state bus in the design, if so what precaution needs to be
taken during design
717. Functionally it is taken care that the existing tri-state bus drivers can never create bus
contention. Is this sufficient for Scan shift and capture? Do we need to take any extra care?
Why?
718. If the entire design is a shift register, do you need scan insertion, explain
719. How do you ignore the block which is already scan inserted from re-inserting scan?
720. What is the purpose of latches at the end of scan chains and is there any impact, explain
721. Is it recommend to have tri-state bus in the design, if so what precaution needs to be
taken during design
722. Functionally it is taken care that the existing tri-state bus drivers can never create bus
contention. Is this sufficient for Scan shift and capture? Do we need to take any extra care?
Why?
723. If the entire design is a shift register, do you need scan insertion, explain
724. How do you ignore the block which is already scan inserted from re-inserting scan?
725. What is the purpose of latches at the end of scan chains and is there any impact, explain
726.
727.
728.
729.
730.

38