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    Vlsi QB - 22-23 - Mid - New

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    Vlsi QB - 22-23 - Mid - New

    Uploaded by

    yadhardha Lingala
    5 views4 pages

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    Vlsi Qb _22-23 _mid_new (1)

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    5 views4 pages

    Vlsi QB - 22-23 - Mid - New

    Uploaded by

    yadhardha Lingala

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    © All Rights Reserved
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    of 4

    Narayana Engineering College:Nellore/Gudur

    Department of ECE
    Academic year: 2023-24

    Sub: VLSI DESIGN IV Year I Semester Branch: ECE


    ****************************************************************
    Question Bank /Topic Learning Outcomes
    Course Details

    Class: IV B. Tech Semester: I Year: 2023-24


    Course Title: VLSI DESIGN Course Code: Credits: 3
    Program/Dept.: ECE Section: ECE-A&B Batch: 2020-2024
    Regulation: R-20(A) Faculty:Dr. K. Murali/Mr. K V Bhanu Prakash

    Question Bank /Topic Learning Outcomes


    (Table format as given below is suitable for Theory, MCQ, Lab, and Tutorial. Columns can be added or
    deleted. No need to take printouts)

    Topic Learning Outcomes/ Question Bank/ MCQ/ Lab Experiments/


    Tutorial Task
    Quest
    TLO. Unit Labels to the right indicate: CO=Course Outcome, BL=BLOOMS Marks
    ion CO BL
    No: No: level. per Q
    No
    On completion of the Lecture/ Tutorial/ Lab on a topic, students
    must be able to:
    UNIT I: INTRODUCTION TO MOS TECHNOLOGIES
    1. 1 1 Explain the NMOS fabrication process flow with diagrams. 1 2 10
    2. 1 2 Describe VLSI Design flow 1 2 10
    3. 1 3 Explain in detail about the steps involved in CMOS IC fabrication 1 2 5
    process with essential diagrams
    4. 1 4 a) Explain clearly the n-well CMOS fabrication process with 1 2 5
    diagrams.
    5. 1 b) Explain the operation of the V-I characteristics of NMOS 1 2 5
    transistor with a diagram and derive the drain to source current
    6. 1 5 a) Draw the Ids-Vds relationship curve and discuss in detail about 1 2 5
    its role in the MOS design equations
    7. 1 b) Equation in saturation and resistance region. 1 2 5
    8. 1 6 Explain the latch-up effect in CMOS inverter 1 2 10
    9. 1 7 a) Explain the fabrication process of Twin Tub. 1 2 5
    10. 1 b) Compare CMOS and BI-CMOS technology. 1 2 5
    11. 1 8 Explain the operation of CMOS inverter with a diagram and derive the 1 2 10
    condition of the pull up and pull down
    12. 1 9 Interpret the Pull-up to pull-down ratio (Zpu-Zpd) for an nMOS 1 2 10
    inverter driven by another nMOS inverter.
    13. 1 10 Explain the Various forms of pull-ups Inverter circuits. 1 2 10
    14. 1 11 Describe the function BiCMOS Inverter 1 2 10
    15. 1 12 Explain the function of Pass Transistor and design 3 input AND gate 1 2 10
    Using Pass Transistor

    Page 1of 4
    UNIT II: VLSI CIRUIT DESIGN PROCESS

    Page 2of 4
    16. 2 1 Explain VLSI design flow . 2 2 5
    17. 2 2 Describe NMOS encoding 2 2 5
    18. 2 3 Draw the layout of Y= AB+C 2 2 5
    19. 2 4 Explain the operation of inverting and non inverting type nMOS super 2 2 10
    buffers
    20. 2 5 Describe the N MOS encoding for stick & layout diagrams 2 2 10
    21. 2 6 Draw the stick diagram 3 input NOR gate 2 2 10
    22. 2 7 Describe the CMOS encoding for stick & layout diagrams 2 2 10
    23. 2 8 Explain λ based Design rules for Layout design 2 2 10
    24. 2 9 Draw the layout of diagram 3 input NAND gate 2 2 10
    25. 2 10 Describe the scaling Models 2 2 10
    26. 2 11 Find the Scaling factors of Following Parameters: 1.Drain current 2. 2 2 10
    Power factor 3. Drain Resistance , 4. Oxide capacitance
    27. 2 12 Briefly discuss scaling of MOS circuits and its limitation 2 2 10
    UNIT III: GATE LEVEL DESIGN
    28. 3 1 Explain the pass transistor and transmission gate logic design. 2 2 10
    29. 3 2 Explain gate logic design for 2 input nMOS, CMOS and BiCMOS 2 2 10
    NAND gate
    30. 3 3 Derive the Pull up and pull down ratio of Pseudo nMOS Logic 2 10
    31. 3 4 a) Explain the Dynamic CMOS logic 2 5
    32. 3 b) Write short notes on the Clocked CMOS logic 2 5
    33. 3 5 Construct a color-coded stick diagram to represent the design of the 10
    following integrated nMOS and CMOS structures and indicate pull-
    up/pull-down ratios in each case: (i) three-input NAND gate; (ii) three-
    input NOR gate;
    34. 3 6 Design a complex CMOS Logic design for the equation 4 3 10

    35. 3 7 Describe the function of Domino Logic 4 2 10


    36. 3 8 Explain the function of N-P Logic 4 2 10
    37. 3 9 Design and Explain function Half adder using Pass transistor logic 4 2 10
    38. 3 10 a) Write short notes on ratioed logic 4 2 5
    39. 3 b) Discusse 4 input Pseudo NOR logic model 4 3 5
    40. 3 11 a) Discuss the operation of general pass transistor logic 4 3 5
    41. 3 b) Design Multiplexer using TG logic 4 2 5
    42. 3 12 a) Discuss the precharge and evaluation phases for dynamic 4 3 5
    CMOS gate design
    43. 3 b) Design 3 in put NAND gate using Dynamic Logic 4 2 5
    Unit IV DATA PATH SUBSYSTEMS
    44. 4 1. Design an arithmetic logic unit to perform both arithmetic and logic 4 3 10
    functions using a full adder.
    45. 4 2. Implement arithmetic logic unit to perform both arithmetic and logic 4 2 10
    functions using a Half adder
    46. 4 3. Explain Booth multiplier architecture in VLSI design. 4 2 10
    47. 4 4. Describe the design of parity generator with a neat sketch 4 2 10
    48. 4 5. Design a 4X4 Barrel shift register. 4 2 10

    49. 4 6. Construct a 4 bit Carry Look Ahead adder 4 2 10


    50. 4 7. Explain the 4 bit carry select adder 4 2 10
    51. 4 8. Explain the working principle of 6-transistor Static RAM with 4 2 10
    necessary diagrams.
    52. 4 9. Explain the working principle of 1-transistor Dynamic RAM with 4 2 10
    necessary diagrams.
    53. 4 10. Explain Working of ROM Architecture with example 4 2 10
    54. 4 11. Explain Timing diagram of RAM 4 2 10
    55. 4 12. Describe principle of 4 bit Array Multiplier 4 2 10

    Page 3of 4
    Unit V IMPLEMENTATION STRATETIES
    56. 5 1 Explain the architecture of a CPLD with circuit diagram 5 2 10
    57. 5 2 a) Compare the FPGA and CPLD 5 2 5
    58. 5 b) What are the types of programmable devices? 5 2 5
    59. 5 3 a) Explain Concept of LUT 5 2 5
    60. 5 b) Describe Configurable logic block used in FPGA 5 2 5
    61. 5 4 Describe the structure of Structure of a PLA with example 5 2 10
    62. 5 5 Explain the design flow of FPGA 5 2 10
    63. 5 6 Describe full custom ASICs 5 2 10
    64. 5 7 Explain the various functional blocks of FPGA 5 2 10
    65. 5 8 Describe the structure of Structure of a PAL with example 5 2 10

    66. 5 9 a) Define ASICs, Give an example for ASICs and Not ASICs 5 2 5
    67. 5 b) Compare the Full-custom and Semi-custom design 5 2 5

    68. 5 10 a) List out advantages and disadvantages of ASICs 5 2 5


    69. 5 b) Classify ASICs with examples 5 2 5
    70. 5 11 Explain Standard Cell Based ASICs 5 2 10
    71. 5 12 Explain Gate Array Based ASICs 5 2 10

    Page 4of 4

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