Article

A 12.4–32 GHz CMOS Down-Conversion Mixer

for 28 GHz 5G New Radio (NR)
Yo-Sheng Lin * and Kai-Siang Lan

Department of Electrical Engineering, National Chi Nan University, Puli 54561, Taiwan
* Correspondence: [email protected]

Featured Application: 28 GHz 5G communication receiver; 24 GHz radar system; 19 GHz low-
Earth-orbit (LEO) satellite communication (SatCom) receiver.

Abstract: We report a low voltage (VDD) and power (PDC) 12.4–32 GHz CMOS down-conversion
mixer with high conversion gain (CG) for 28 GHz 5G communications. A quarter-wavelength (λ/4)
transmission line (TL) and a coupling capacitor (Cc), named the λ/4-TL-C-based coupler, is pro-
posed. This is the way to attain low-VDD, independent RF transconductance (gm)-stage bias, har-
monic suppression, and near perfect coupling from the RF gm stage to the LO switch transistors.
The body-self-forward-bias (BSFB) technique, i.e., connection of the gm-stage transistors’ body to
drain via a large body resistance, is used for threshold voltage (Vth) and VDD reduction and substrate
leakage suppression. CG and noise figure (NF) enhancement at the same or even a lower PDC is
achieved because lower VDD and higher gm (due to larger bias current) are used. To facilitate the RF
measurement, a compact Wilkinson-power-divider-based balun with small-phase deviation and
amplitude imbalance is included at RF and LO inputs. The mixer consumes 6.5 mW and achieves a
CG of 14.4 ± 1.5 dB for 12.4–32 GHz (i.e., 3 dB bandwidth (f3dB) of 19.6 GHz), a lowest noise figure
(NFmin) of 7 dB, and figure-of-merit (FOM) of 0.023, which is one of the best results ever reported for
millimeter-wave (mm-wave) down-conversion mixers with an f3dB larger than 10 GHz and PDC lower
than 10 mW.

Citation: Lin, Y.-S.; Lan, K.-S. A

Keywords: CMOS; low voltage; low power; transmission line; coupler; down-conversion mixer
12.4–32 GHz CMOS
Down-Conversion Mixer for 28 GHz
5G New Radio (NR). Appl. Sci. 2023,
13, 2305. https://doi.org/10.3390/ 1. Introduction
app13042305 In a phased-array transceiver for 28 GHz 5G new radio (NR), the down-conversion
Academic Editors: Biao Pan and mixer is a crucial component in each digital channel for conversion of the receiving RF
Wang Kang signals to intermediate-frequency (IF) or baseband (BB) signals [1–10]. The basic require-
ments of a down-conversion mixer include a small chip area, low supply voltage (VDD)
Received: 5 January 2023
and power (PDC), and decent input impedance (Zin) matching, conversion gain (CG), 3 dB
Revised: 1 February 2023
Accepted: 8 February 2023
CG bandwidth (f3dB), noise figure (NF), LO–RF isolation, and power linearity (such as an
Published: 10 February 2023
input 1 dB compression point (P1dB) and third-order intercept point (IIP3)). Recently, sev-
eral millimeter-wave (mm-wave) down-conversion mixers have been reported [1–8]. For
instance, in [2], a wideband (24–40 GHz) down-conversion mixer employing body-effect
control for CG enhancement in 65 nm CMOS was demonstrated. However, a PDC of 10.3
Copyright: © 2023 by the authors.
mW and LO input power (LOin) of 5 dBm leaves room for improvement. In [3], a 23–25
Licensee MDPI, Basel, Switzerland.
This article is an open access article
GHz folded down-conversion mixer using cross-coupled PMOS transistors (CCPTs) for
distributed under the terms and
CG boosting in 0.13 μm CMOS is reported. However, a PDC of 16.8 mW and f3dB of 2 GHz
conditions of the Creative Commons are not satisfactory. In [8], a 88–100 GHz down-conversion mixer using the parallel of
Attribution (CC BY) license CCPT and series-RL as the core IF load (i.e., CCPT-RL-based core IF load) for CG and IF-
(https://creativecommons.org/license bandwidth enhancement in 90 nm CMOS is reported. Yet, a VDD of 1.2 V (due to the cas-
s/by/4.0/). code of three transistors) still has room for improvement. To demonstrate that low VDD

Appl. Sci. 2023, 13, 2305. https://doi.org/10.3390/app13042305 www.mdpi.com/journal/applsci

Appl. Sci. 2023, 13, 2305 2 of 11

and PDC, wideband, and decent CG and NF can be achieved for a down-conversion mixer
for 28 GHz 5G NR, we report a 6.5 mW 12.4–32 GHz down-conversion mixer with a CG
of 14.4 ± 1.5 dB and NF of 7–9.7 dB in 90 nm CMOS using the body-self-forward-bias
(BSFB) technique, the CCPT-RL-based core IF load, and λ/4-TL-C-based coupler (consti-
tuting a λ/4 transmission line (TL) and a coupling capacitor (Cc)). In this paper, mixer
circuit design is introduced in section II, the measurement results of the mixer and com-
parisons with previous work is discussed in section III, and a conclusion is presented in
section IV.

2. Circuit Design
Figure 1a shows the illustrative diagram of the proposed low-VDD and low-PDC down-
conversion mixer. In theory, the Zin of a grounded lossless λ/4-TL (denoted TLqw) is infinite
at the operation frequency of f0 (=ω0/2π) and the odd-harmonic frequencies (3f0, 5f0, etc.)
and is zero at DC and the even-harmonic frequencies (2f0, 4f0, etc.). Instead of the trans-
former coupling approach [7], two λ/4-TL-C-based couplers are used to achieve near per-
fect coupling from the RF transconductance (gm) stage to the LO switch transistors. The
λ/4-TL-C-based coupler has the merits of a straightforward design and layout, as well as
harmonic suppression. The low VDD and optimized noise, gain, and linearity design of the
mixer become possible due to the separate DC bias of the RF gm stage and the LO-tran-
sistors/IF loads. In brief, the bias currents of transistors M3/M4 and M5/M6 flow to the
ground through TLqw instead of the RF gm stage or transformer secondary coil. The out-
puts of the RF gm stage transmit to M3/M4 and M5/M6 near perfect through the λ/4-TL-C-
based couplers instead of direct transmit or the transformer coupling. This is the way to
achieve low VDD and optimized design. Moreover, CCPT-RL-based core IF load is used
for load-impedance (ZL)/CG enhancement while keeping a low PD and wide IF bandwidth.
The BSFB technique, i.e., connection of the gm-stage transistors’ body to their drain via a
large body resistance RB (13.1 kΩ in this work) is used for threshold voltage (Vth) and VDD
reduction, in addition to substrate leakage suppression. CG and NF enhancement at the
same or even a lower PD is achieved because of the lower VDD and higher gm due to larger
overdrive voltage (Vov) or bias current [11].

λ/4-TL-C-Based Zin2 ~ ∞ λ/4-TL Zin1 ~ 0

Near Perfect Coupler with ZC of ZT0 Cby
P1 o
P2
θ0 (=90 ), ZT0
(D1/D2) (VD1/VD2)
LOin+ M3 i /2 M4 M5
irf-/2
M6 Equivalent to ZT 0
rf+ irf+/2 irf-/2 LL =
TLqw TLqw ω0
θ=90° θ=90°
LOin- 1
CL LL CL CL =
ZT 0ω0
irf-
Cc irf+ Cc P1 P2 Z
(= -irf+) ZT 1 = T 0
Zin2 ~ ∞ Zin2 ~ ∞
Equivalent to sin θ1
RB RB
TL3 TL2 TL2 TL3 cosθ1
VD1 VD2 Cd =
θ1 ~ 60° D1 M1 M2 D2 θ1 ~ 60° ω0 Z T 0
Cby Cd Cd Cby Cd Cd
TL1 RG RG TL1 LL1 = LL
VG1 θ1 (~60o), ZT1
RFin+ RFin- P1 P2 CL1 = CL − Cd
(a) (b)
Appl. Sci. 2023, 13, 2305 3 of 11

0 30
S11 S22 25

S11 (dB)
-5 S33 20
MT9 TLqw -10
15
10
-15 λ/4-TL-C-based Coupler 5

S21 & S31 (dB)

-3 dB 0
P2 P3 -20
-5
(Source (Source S21
Cc -25
-10
of M3/M6) of M4/M5)
S31 -15
P1 -30 -20
0 20 40 60 80 100
(D1/D2, Drain of M1/M2) Frequency (GHz)
(c) (d)
Figure 1. Illustrative diagrams of (a) a mixer using a λ/4-TL-C-based coupler, and (b) the current-
source load. (c) Layout and (d) simulated results of the coupler.

Figure 1b shows the current-source-load design of the gm stage. A lossless TLqw with
an electrical length (θ) of 90o and characteristic impedance (ZC) of ZT0, such as the one in
Figure 1c (with ZT0 of 89.7 Ω), can be modeled by an inductance (LL) and two parallel end-
capacitance (CL) as follows [12].
ZT0
LL = (1)
ω0

1
CL = (2)
ZT0ω0

On the condition that Zin1 is equal to zero, Zin2 is infinite at ω0 since the parallel of LL
and CL exhibits an infinite impedance at ω0 from Equations (1) and (2). In the design of
the current-source load of the gm stage, the parasitic capacitance (Cd) at drain nodes
D1/D2 of M1/M2 should be considered. In theory, a TLqw with ZC of ZT0 is equivalent to a
TL (with smaller θ (of θ1), larger ZC (of ZT1), and the same inductance (LL1 = LL)) and two
extra parallel end-capacitance Cd values (=CL − CL1). One of the required Cd values is pro-
vided by the parasitic Cd and the other has no effect (due to in parallel with a short-circuit).
ZT1 and Cd are given by
ZT0
ZT1 = (3)
sinθ1

cosθ1
Cd = (4)
ZT0ω0

Suppose ZT0 is 65 Ω, then LL is 369.6 pH and CL is 87.4 fF at f0 of 28 GHz according to

Equations (1) and (2). From Equations (3) and (4), θ1 is 60° and ZT1 is 75.1 Ω due to a Cd
equal to 43.7 fF in this work.
Figure 1c shows the simplified layout of the λ/4-TL-C-based coupler in Figure 1a. A
compact spiral TLqw (with size of 73.6 × 76.1 μm2 and metal width/space of 3/2 μm) and a
Cc (with size of 32 × 36 μm2 and equivalent capacitance of 1.76 pF) are used. Figure 1d
shows the simulated reflection coefficients (S11, S22, and S33) and gain (S21 and S31) of the
coupler. The coupler achieves decent S21 and S31 of −3.595 dB at 28 GHz and S21 and S31
better than −4 dB for 8.7–46.9 GHz. At 56 GHz, decent second-harmonic suppression (S11
of −0.22 dB, S22 and S33 of 0 dB, and S21 and S31 of −89 dB) is achieved.
Figure 2a,b show the circuit diagram and chip of the down-conversion mixer with
the important component parameters labeled. The chip area is 0.879 × 0.562 mm2, i.e., 0.494
mm2. The mixer comprises a double-balanced Gilbert-cell-based mixer core (with a differ-
ential RF gm stage using the BSFB technique, two λ/4-TL-C-based couplers, and a CCPT-
RL-based core IF load), two Wilkinson-power-divider-based baluns, and differential out-
put buffer amplifiers. The mixer was designed and implemented in 90 nm CMOS. This
Appl. Sci. 2023, 13, 2305 4 of 11

process offers nine metal layers, named MT1 to MT9 from bottom to top. The interconnec-
tion lines, as well as the TL inductors, were implemented with the 3.4 μm-thick upmost
metal (MT9) to minimize the resistive loss. The Momentum three-dimensional (3D)-planar
EM simulator in ADS (Advanced Design System) is used for EM-circuit cosimulation.
Substrate and layer parameters of ADS Momentum are set up according to the process
information provided by the foundry. This ensures the post-layout simulation results of
the mixer close to the measurement ones. Instead of the transformer coupling approach
(with a pair of λ/4 TLs for harmonic suppression) [7], a straightforward λ/4-TL-C-based
coupler introduced in Figure 1 is used between the RF gm stage and the LO switch tran-
sistors. The BSFB technique, also shown in Figure 1, is used in the RF gm stage for Vth and
VDD reduction, as well as substrate leakage suppression. CG and NF enhancement at the
same or even lower PD is achieved because lower VDD and higher gm (due to larger bias
current) are used. To enhance ZL/CG and keep a low PD and decent IF bandwidth, a CCPT-
RL-based core IF load is used. At VDD = 0.8 V and VD1 = VD2 = VG1 = VG2 = 0.4 V, the mixer
dissipates 6.4 mW. Compared with the traditional mixer for the direct-conversion re-
ceiver, the mixer consumes low PD and achieves significant CG and NF enhancement.

Output Buffer Output Buffer

IFout+ IFout-
Rds10 Rds9 VDD = 0.8 V Rds11 Rds12

M10 Rf M9 M11 Rf M12

3x28 μm 3x28 μm
M7 M8

CCPT-RL-based
RL 0.203 nH RL
IF Core Load VG1 VG2 VD1
λ/4-TL-C-based Cby 258.5 Ω LL 258.5 Ω Cby

Coupler
G G
TL4 2x24 μm 2x24 μm 2x24 μm 2x24 μm
LOin IFout+
RG M3 θ= M4 M5 θ= M6
562 μm
LO VG2= 90°
TLqw
TL5 90°
TLqw G G
LOin 0.4V
TL5 TL5 TL5
Balun RG RFin IFout-
TL4 Cc Cc
G G
Cby RB RB Cby
879 μm
TL3 TL2 TL2 TL3
VD1 = 0.4V 4x16 μm
VD2 = 0.4V
4x16 μm
M1 M2 VDD VD2
RG RG
TL1 TL1
VG1=0.4V

RF
Balun

RFin
(a) (b)
Figure 2. (a) Schematic diagram, and (b) chip photo of the down-conversion mixer.

Figure 3 presents the illustrative diagram of the 28 GHz-band Wilkinson-power-di-

vider-based balun [12]. It is used as the RF and the LO baluns. The compact Wilkinson
power divider constitutes a noninverting coupled line with an electrical length (θ) of 22°,
a parallel grounded capacitance CP1 at the input, and a parallel RPCP between the outputs.
The coupled line, i.e., two noninverting spiral or meandering TLs with inductance of LL,
has a positive mutual inductance (M) and an equivalent parallel inductance LP (=LL(LL −
2M)/M) between the outputs. This leads to a significant TL-length reduction (from about
λ/10 to λ/16) for the power divider. The effect of LP can be cancelled by Cm (=M/[ω02LL(LL
− 2M)]) in Figure 3. The π-network comprised of CP2, LS1, and CP3 introduces a phase delay
of 90°, while the T-network comprised of CS1, LP1, and CS2 (or the π-network comprised of
LP2, CS3, and LP3) introduces a phase lead of 90°. This is the way to achieve balun operation
of the device.
Appl. Sci. 2023, 13, 2305 5 of 11

phase shift of -90o

Lumped-Distributed
θ (~λ/12), ZT phase shift of 90o
CP2 LS1 CP3 P2
P1 CP1 CP = RP P3
M CS3
0.5CP1+Cm phase shift of 90o LP2 LP3

θ (~λ/12), ZT
CS1 CS2 P3
Wilkinson LP1 Equivalent
Power Divider

Figure 3. Illustrative diagram of the power-divider-based balun.

Shown in Figure 4a is the simplified layout and chip photo of the first test balun,
balun-1. A spiral layout is used for LS1 and LP1 in order to achieve a compact size. Balun-1
occupies a chip area of only 0.225 × 0.148 mm2, i.e., 0.033 mm2. Figure 4b shows the sim-
plified layout of the RF and the LO baluns (i.e., dual balun-2) of the down-conversion
mixer in this work. A symmetrical layout is crucial for the differential mixer core to attain
good port-to-port isolation and overall performance. Therefore, the dual-balun-2 layout
in Figure 4b is used to fit the symmetrical layout of the mixer core. The dual balun-2 oc-
cupies a chip area of 0.089 mm2. According to our previous experience, measured results
of mm-wave passive devices are consistent with the simulated results of the EM simulator
HFSS and ADS Momentum [13]. To expedite the realization of the down-conversion mixer,
tape-out of the mixer is conducted based on the EM-circuit cosimulation result of the lay-
out, i.e., post-layout simulation result, via ADS Momentum. Therefore, tape-out of the test
device of dual balun-2 was not performed.

CP2 P2
MT9 81.9 fF CP3
81.9 fF

CP RP LS1
83.8 145.4 Ω
CP1 107.5 CP3
fF CS1 CS2 LOin RF+
fF
P3 Cp1
P1 (P1) (P2)
MT8 90.1 fF 90.1 fF
MT9 Lp1
Cp2
LO+
LP1
Ls Cp3 (P2)
MT8
Cp
Rp Lp2
225 μm P2 LS LO-
(P3)
Cs
LP2
RFin RF-
CP1
(P1) CP2 (P3)
P3
P1 CS
CP
148 μm RP
LP1

(a) (b)
Figure 4. (a) Layout and chip photo of balun-1. (b) Layout of dual balun-2.

The measured reflection coefficients (S11, S22, and S33), isolation between the outputs
S32, and gain (S21 and S31) of balun-1 are shown in Figure 5a. Balun-1 achieves a local min-
imum S11 of −21.6 dB at 32 GHz and S11 better than −10 dB from 26.2 GHz to over 50 GHz.
The corresponding −10 dB input, matching the bandwidth (f10dB), is wider than 23.8 GHz.
Balun-1 achieves a local minimum S22 of −19.5 dB at 32 GHz and S22 better than −10 dB
from DC to 36.7 GHz, equivalent to an f10dB of 36.7 GHz. Balun-1 achieves a minimum S33
of −23.4 dB at 32 GHz and S33 better than −10 dB for 25.7–39.7 GHz, equivalent to an f10dB
of 14 GHz. Moreover, balun-1 attains a local minimum S32 of −25.7 dB at 33 GHz and S32
better than −10 dB from DC to over 50 GHz, equivalent to a −10 dB isolation bandwidth
Appl. Sci. 2023, 13, 2305 6 of 11

(f10dB,iso) wider than 50 GHz. Balun-1 achieves S21 of −4.441 dB at 32 GHz and S21 better than
−5 dB for 26.3–36.7 GHz, close to the measured S31 (−4.131 dB at 32 GHz, and better than
−5 dB from 25.5 GHz to over 50 GHz).

20 12 10 270

S11, S22, S33 & S32 (dB)

10 S11 S33
9 5 225
0 S22 S32

AI (dB)
-10 -10 dB 6 0
0 dB 180
-20
3 -5 135
-30
-40 Balun-1 Measurement 0 -10 Balun-1 Measurement 90

S21 & S31 (dB)

PD (degree)
-50
-4 dB -3 -15 45
-60 o
-20
0 0
-70 -6
-80 S21
-9 -25 -45
-90 S31
-100 -12 -30 -90
24 26 28 30 32 34 36 24 26 28 30 32 34 36 38 40
Frequency (GHz) Frequency (GHz)
(a) (b)
Figure 5. Measured (a) S-parameters, and (b) AI and PD of balun-1.

Figure 5b shows the measured amplitude imbalance AI (equal to S21(dB) − S31(dB))

and phase deviation PD (equal to S21(degree) − S31(degree) − 180°) of balun-1. Balun-1
achieves the best AI of −0.127 dB at 28 GHz and AI within ±1 dB for 22.2–36.7 GHz, as well
as the best PD of −0.08° at 35 GHz and PD within ±5° for 28.6–40.3 GHz. Compared to that
with the commonly used Marchand balun with poor S22, S33, and S32 (of −6 dB in theory)
[8], better overall performance is achieved.
Figure 6a shows the simulated AI and PD of balun-2. Balun-2 attains the best AI of 0
dB at 27.5 GHz and AI within ±1 dB for 23.5–30.6 GHz, as well as the best PD of 0° at 26.4
GHz and PD within ±5° for 24.1–32.6 GHz. Figure 6b shows the simulated RF-port reflec-
tion coefficient (S11), LO–RF isolation, CG, and NF of the mixer. The mixer achieves a min-
imum S11 of −32.9 dB at 39 GHz and S11 better than −10 dB for 21.7–44.5 GHz (i.e., f10dB of
22.8 GHz). The good S11 is attributed to the decent input matching of the balun (see Figure
5a) and good matching between the balun outputs and the differential RF inputs. Due to
the symmetrical layout and Cby of the mixer core, the mixer achieves decent LO–RF isola-
tion of 44.9 dB at 28 GHz and 40.3–62.4 dB for 0–50 GHz. Moreover, the mixer achieves a
maximum CG of 15.8 dB at 26 GHz and CG of 14.3 ± 1.5 dB for 14.3–32.5 GHz (i.e., f3dB of
18.2 GHz). The decent CG and f3dB are attributed to the CCPT-RL-based core IF load and
the gain-enhanced gm stage. The mixer achieves a minimum NF of 6.2 dB at 24 GHz and
NF of 6.2–9.3 dB for 14–33 GHz. The good NF of the mixer is attributed to its high CG and
simultaneous noise and Zin matching of the gm stage.

10 270 60 45
S 11 & LO-RF Iso. (dB)

45
5 225 40
AI (dB)

30 LO-RF Iso.
0 dB
0 180 15 S11 35
0 -10 dB
-5 135 30
-15
-10 Balun-2 Simulation 90 -30 Down-Conversion Mixer 25
CG & NF (dB)
PD (degree)

-45
-15 45 CG NF 20
o -60
0
-20 0 -75 15
-90
-25 -45 10
-105
-30 -90 -120 5
22 24 26 28 30 32 34 14 18 22 26 30 34
Frequency (GHz) RF Frequency (GHz)
(a) (b)
Figure 6. Simulated (a) AI and PD of balun-2, and (b) S11, LO–RF isolation, CG, and NF of the down-
conversion mixer.
Appl. Sci. 2023, 13, 2305 7 of 11

3. Results
At VDD = 0.8 V and VD1 = VD2 = VG1 = VG2 = 0.4 V, the down-conversion mixer dissipates
6.5 mW, close to the simulated one (6.4 mW). The on-wafer S-parameter measurement of
the mixer was conducted using a Keysight N5245B four-port PNA network analyzer
(0.01–50 GHz). Figure 7a shows the measured and simulated RF-port reflection coefficient
(S11) of the mixer. The mixer achieves a measured minimum S11 of −34.6 dB at 40 GHz and
S11 better than −10 dB for 20.4–44.2 GHz (i.e., f10dB of 23.8 GHz), close to the simulated result
(minimum S11 of −32.9 dB at 39 GHz and f10dB of 22.8 GHz (21.7–44.5 GHz)). For a mixer or
amplifier using series RLC resonance matching, its f10dB (50/(3πLin) in theory) is inversely
proportional to the input inductance Lin [14,15]. For the differential RF inputs, Lin (i.e., sum
of the inductance of TL1 and TL2) is 435 pH, equivalent to f10dB of 12.2 GHz. The wideband
S11 of the mixer is attributed to the wideband matching between the RF-balun outputs and
the RF inputs due to the small Lin at RF inputs. Figure 7b shows the measured and simu-
lated IF+ port reflection coefficient (S33) of the mixer. The mixer achieves a measured S33
better than −10 dB for 0–10.2 GHz (i.e., f10dB of 10.2 GHz), close to the simulated one (f10dB
of 15.1 GHz (0–15.1 GHz)). The wideband S33 is attributed to the Zin matching at low fre-
quency (LF) since the design values of Rds9llRds10llRf and Rds11llRds12llRf are 50 Ω. The slight
deviation of the measured S11 and S33 (from the simulated ones) of the down-conversion
mixer is mainly attributed to the substrate- and layout-layer parameters provided by the
foundry being not accurate enough at mm-wave frequencies.
Figure 8a shows the measured and simulated LO–RF and LO–IF isolation versus LO
frequency characteristics of the mixer. The mixer achieves measured LO–RF isolation of
46.1 dB at 28 GHz and 41.6–55.9 dB for 0–50 GHz, close to the simulated one (44.9 dB at
28 GHz, and 40.3–62.4 dB for 0–50 GHz). Since the Miller capacitance (of Cgd) at D1/D2 of
M1/M2 has been taken into account in the Cd calculation, the decent LO–RF isolation is
attributed to the symmetrical layout of the mixer core, and unilaterilization of the Cgd ef-
fect of M1/M2. Moreover, the mixer achieves measured LO–IF isolation of 39.9 dB at 28
GHz and 36.6–82.7 dB for 0–50 GHz, close to the simulated one (43.3 dB at 28 GHz, and
36–84.8 dB for 0–50 GHz). The decent LO–IF isolation (especially at LF) is attributed to the
symmetrical layout of the mixer core and the inclusion of Cby between M3/M5 and M9/M10
(and M4/M6 and M11/M12) for low-pass filtering of the LO leakage. In brief, LO leakage
around f0 is suppressed by Cby. Therefore, LF (around DC) leakage at the IF output is min-
imized due to the effective suppression of the second-order nonlinearity of the CCPT-RL-
based core IF load and the output buffer amplifiers. Figure 8b shows the measured and
simulated CG versus LOin characteristics of the mixer at 28 GHz. Intrinsically, the mixer
is a nonlinear multiplier. Hence, it is reasonable that the CG of the mixer increases with
the increase in LOin until saturation of the LO switch transistors (i.e., close to perfect switch
operation). At LOin of 0 dBm, the mixer achieves a measured/simulated CG of 15.6/15.7
dBm, close to those (16.6/16.2 dBm) at LOin of 4 dBm. This indicates that LOin of 0 dBm is
a reasonable choice for the switch operation of the LO switch transistors.
The on-wafer NF measurement was performed using an Agilent N8975A noise figure
analyzer (0.01–26.5 GHz). An Agilent 1–50 GHz noise source with a 7–20 dB excess noise
ratio (ENR) is used at the RF input. The LO input signal is provided by an Agilent E8257D
signal generator (up to 67 GHz). Figure 9a shows the measured and simulated CG and NF
versus RF frequency characteristics of the mixer. IF frequency is fixed at 0.1 GHz. The
mixer achieves a measured CG of 15.6 dB at 28 GHz and CG of 14.4 ± 1.5 dB for 12.4–32
GHz, corresponding to an f3dB of 19.6 GHz. The result is close to the simulated CG (15.7
dB at 28 GHz and 14.3 ± 1.5 dB for 14.3–32.5 GHz, corresponding to an f3dB of 18.2 GHz).
The broadband CG of the mixer is attributed to the wideband RF- and LO-port Zin match-
ing (S11 and S22) and near perfect wideband-coupling of the λ/4-TL-C-based coupler. More-
over, the mixer achieves a measured NF of 7.6 dB at 28 GHz and 7–9.7 dB for 12.4–32 GHz,
close to the simulated NF (6.7 dB at 28 GHz and 6.2–9.3 dB for 12.4–33 GHz). Figure 9b
shows the measured and simulated CG and NF versus IF frequency characteristics of the
mixer. The mixer achieves a measured CG of 15.6–12.6 dB for 0.1–1.9 GHz. The 3 dB IF
Appl. Sci. 2023, 13, 2305 8 of 11

bandwidth (f3dB,IF) is 1.9 GHz, wider than the required 1.5 GHz for 5G NR band N257 (28
± 1.5 GHz) application. The result is close to the simulated one (15.7–12.7 dB for 0.1–2.2
GHz, i.e., f3dB,IF of 2.2 GHz). The mixer achieves a measured NF of 7.6–8.1 dB for 0.1–1.9
GHz, close to the simulated one (7.7–8.3 dB for 0.1–2.2 GHz). Furthermore, the mixer
achieves a decent P1dB and IIP3 of −10.6 dBm and −1 dBm, respectively. For a larger VDD of
1 V, a better IIP3 of 1 dBm is achieved (not shown here).

10 10
RF-port Measurement Measurement
Simulation Simulation
0 0
S 11 (dB)

S33 (dB)
-10 -10

-20 -20

-30 -30

-40 -40
20 25 30 35 40 45 0 5 10 15 20
Frequency (GHz) Frequency (GHz)
(a) (b)
Figure 7. Measured and simulated (a) S11, and (b) S33 of the mixer.

80 200 25
LO-RF Iso. (dB)

180 Measurement
60
Simulation
160 20
40
40 dB 140
CG (dB)

20 120 15
0 Measurement 100
LO-IF Iso. (dB)

Simulation
80 10
-20
60
-40
40 5
-60 40 dB
20
-80 0 0
0 10 20 30 40 50 -10 -8 -6 -4 -2 0 2 4
LO Frequency (GHz) LO Power (dBm)
(a) (b)
Figure 8. Measured and simulated (a) LO–RF and LO–IF isolation versus LO frequency, and (b) CG
versus LO input power characteristics of the mixer.

25 50
18 14
20 45
CG (dB)

16 13
CG (dB)

15 40 14
12
10 35 12
5 30 10 11
Measurement Measurement
0 25 8 10
Simulation Simulation
-5 20 6 9
NF (dB)
NF (dB)

-10 15 4
8
-15 10 2
0 7
-20 5
-25 0 -2 6
0.0 0.5 1.0 1.5 2.0 2.5
16 20 24 28 32
IF Frequency (GHz)
RF Frequency (GHz)
(a) (b)
Figure 9. Measured and simulated (a) CG and NF versus RF frequency, and (b) CG and NF versus
IF frequency characteristics of the mixer.
Appl. Sci. 2023, 13, 2305 9 of 11

Table 1 is a summary of the 28 GHz down-conversion mixer and recently reported

state-of-the-art mm-wave CMOS down-conversion mixers [1–7]. As can be seen, the mixer
in this work is designed and implemented via a relatively cost-effective 90 nm CMOS pro-
cess and achieves better overall performance than the mixer implemented with the costlier
40 nm CMOS technology in [6]. If a more advanced CMOS process is used for the mixer
in this work, the overall performance can be further enhanced. This means that the pro-
posed down-conversion mixer architecture has high potential for mm-wave communica-
tion systems. Overall, compared with that in [1–7], our mixer occupies a medium chip
area, requires a medium LOin, consumes low power, and achieves prominent CG, f3dB, NF,
LO–RF isolation, and IIP, and one of the best FOM1s and FOM2s. The remarkable results
indicate that the proposed down-conversion mixer architecture is suitable for 28 GHz 5G
NR and even a higher frequency system.

Table 1. Summary of the down-conversion mixer and recently reported state-of-the-art mm-wave
down-conversion mixers.

CMOS RF Freq. LOin CG f3dB BW LO–RF NF IIP3 PDC Area FOM2

Topology FOM1
Process (GHz) (dBm) (dB) (GHz) Iso. (dB) (dB) (dBm) (mW) (mm2) (mW−1)
This Gilbert-cell with λ/4- 19.6
90 nm 28 0 15.6 46.1 7.6 −1 6.5 0.494 0.023 0.14
Work TL-C-based coupler (12.4–32)
Double-balanced 6
[1] 90 nm 28 1 −3.3 47.4 14.3 −3.4 6.4 0.522 8.7 × 10−5 4.9 × 10−3
Gilbert-cell (25–31)
Double-balanced 13
[2] 65 nm 28 5 7.2 N/A 12.3 −2.5 10.3 0.4 6.1 × 10−4 0.017
Gilbert-cell + IF buffer (26–39)
Folded Gilbert-cell 2
[3] 0.13 μm 24 −3 26.1 58 7.7 −27.4 16.8 0.96 8.9 × 10−6 0.024
+IF buffer (23–25)
Gilbert-cell using 4 2.48 ×
[4] 0.18 μm 24 5 −4.5 N/A N/A 23 16 0.72 N/A
distributed DS tech. (22–26) 10−3
Single balance with 10
[5] 90 nm 60 1 6.95 50 14.4 0.2 16 0.35 4.2 × 10−4 0.011
CCP feedback (57–67)
Sub-harmonic+ 10.5 45
[6] 40 nm 60 5 −7.9 14.4 0.1 3.45 0.586 N/A 5.3 × 10−3
Current-reused (56.5–67) (2LO–RF)
Transformer-coupling 28
[7] 65 nm 60/77 −3 9.5 48 9.2 5.8 15 0.527 0.017 0.033
cascode topology (62–90)
−1
FOM1 = CG[1] ⋅ BW[GHz] ⋅ IIP3[mW]/ [(F −1)[1] ⋅ PDC[mW] ⋅ fT [GHz]], FOM2 [mW ] = CG[1] ⋅ BW[GHz] /[PDC[mW] ⋅ fT [GHz]] .

Finally, it would be informative to provide readers with a futuristic vision about what
the future holds for us as we move forward [16–19]. Considering the saturation of the
state-of-the-art microelectronic technologies in providing a faster operation speed, nowa-
days, hybrid optoelectronic platforms are considered a new solution to expand the oper-
ation bandwidth, while we can still enjoy the CMOS technology for implementing such
hybrid systems. One direction that is gaining large momentum in the field is the utiliza-
tion of hot-electron optoelectronic nano-devices. This concept relies on the fact that metals
have an abundance of free electrons, so they can nicely capture light if they are fashioned
as a nanoscale optical antenna. In addition, employing metals is a necessary part of elec-
tronic circuits, e.g., as electrical contacts. Therefore, if meticulously designed, a nano-
metal with optical antenna properties can be used as an electrical contact as well; there-
fore, one can access the hot electrons in metals for optoelectronic applications [16]. Such
hot carriers can enable the extremely fast switching of electrical signals [17]. In a capacitor
configuration, such high-energy hot electrons have the possibility of being transported
over a Schottky barrier in a very short timeframe. The injection of hot carriers into a die-
lectric/oxide/air material will change its conductivity in a very short timescale, thereby
allowing for ultrafast optoelectronic switching, which is inherently a frequency down con-
version process. The beauty of this technique is hidden in the fact that hot-electron opto-
electronic systems do not rely on the absorption of light in a semiconductor. Therefore,
Appl. Sci. 2023, 13, 2305 10 of 11

practically any oxide or metal combination can be employed to produce a hot-electron

optoelectronic convertor without being concerned about the intrinsic properties of em-
ployed materials or a capacitive nature of the circuit, which limits the bandwidth. Initial
demonstrations of such switches were proposed recently [18,19]. However, practical de-
vices are yet to be demonstrated.

4. Conclusions
We demonstrate a 6.5 mW 12.4–32 GHz CMOS down-conversion mixer with a decent
CG of 14.4 ± 1.5 dB and NF of 7–9.7 dB for 28 GHz 5G NR. A λ/4-TL-C-based coupler is
used for harmonic suppression and near-perfect coupling from the RF gm stage to the LO
switch transistors. The BSFB technique is used for Vth and VDD reduction. The CCPT-RL-
based core IF load is used for ZL (i.e., CG) and f3dB,IF boosting. CG and NF enhancement at
the same (or even a lower) PDC is achieved due to a lower VDD and higher gm and ZL. As a
result, low PDC and optimized CG, NF, and linearity are achieved for the mixer due to the
separate bias (i.e., optimized design) of the gm stage and the IF loads.

Author Contributions: Conceptualization, Y.-S.L. and K.-S.L.; methodology, Y.-S.L. and K.-S.L.;
software, K.-S.L.; validation, Y.-S.L. and K.-S.L.; formal analysis, Y.-S.L.; investigation, Y.-S.L.; re-
sources, Y.-S.L.; data curation, K.-S.L.; writing—original draft preparation, K.-S.L.; writing—review
and editing, Y.-S.L.; visualization, Y.-S.L.; supervision, Y.-S.L.; project administration, Y.-S.L.; fund-
ing acquisition, Y.-S.L. All authors have read and agreed to the published version of the manuscript.
Funding: This research was funded by the National Science and Technology Council (NSTC), Tai-
wan, grant number MOST111-2221-E-260-017.
Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.
Data Availability Statement: Not applicable.
Acknowledgments: This work was supported by the National Science and Technology Council
(NSTC) of Taiwan under Contract MOST111-2221-E-260-017. The authors would like to thank the
Taiwan Semiconductor Research Institute (TSRI) for the support of chip fabrication and measure-
ments.
Conflicts of Interest: The authors declare no conflict of interest.

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