This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPWRD.2020.2982512, IEEE
Transactions on Power Delivery

A New Protection Scheme for an SSSC in an MV

Network by Using a Varistor and Thyristors
Erfan Bashar, Student Member, IEEE, Dan Rogers, Member, IEEE, Ruizhu Wu, Li Ran, Senior
Member, IEEE, Mike Jennings, Timothy C. Green, Senior Member, IEEE, and Philip Mawby, Senior
Member, IEEE

Abstract— To control power flow and manage fault level in meshed

MV networks, back-to-back voltage source converters (B2B-
VSCs) are being used. However, their high cost and relatively low
efficiency are of concerns. Partially rated series compensators,
such as SSSCs or UPFCs, are desired but come with the challenge
of protecting the device during grid faults. Their potential of use
has been limited in comparison with the fully rated back-to-back
converters. This paper proposes a new system topology including
thyristor crowbars and a varistor to protect the SSSC in an MV
network and improve the reliability and flexibility of the network
operation. Using the proposed method, the time required for
isolating the series compensator from the grid is reduced from at
least 20 ms, corresponding to the interruption time of conventional
circuit breakers, down to 3 μs in the worst case in addition to the
grid fault detection delay. The performance is evaluated by
simulation. A small-scale single-phase prototype operating at 230
V/16 A is tested in order to demonstrate the concept. Figure 1 Typical MV network with multiple feeders including SSSC-
Convectional protection mechanism

Index term — Power system reliability, power system fault, DG. Other network management techniques to ease these
protection, static synchronous series compensator, power situations include the unified power flow controller (UPFC),
semiconductors, thyristor, varistor static VAR compensator (SVC), soft-open point and
transformer on-load tap changing. The UPFC is described as
‘universal’ due to its ability to independently control the real
I. INTRODUCTION and reactive power flows [1]. The series insertion of a voltage,

L ow-carbon distributed generation (DG) continues to be

added to medium voltage (MV) networks, presenting
challenges to the control of busbar voltage, branch power and
like in an SSSC, is most effective and many studies have been
carried out to find the optimal sizing and allocation in terms of
cost and dynamic response [2, 3].
operation of relays & circuit breakers. To increase the ability of Managing some of the devices under system fault conditions
the network to accommodate embedded generation, power has been difficult, especially those injecting a series voltage for
electronic compensators could play important roles by making control and compensation. Mechanical switches are too slow.
the network more flexible and controllable. Potential Therefore, solid-state circuit breakers (SSCBs) or other power
technologies include voltage source converters in different electronics-based schemes have attracted research attention in
combinations. Figure 1 shows a typical medium-voltage recent years involving thyristors, GTOs or IGBTs [3, 4].
distribution network with DG. The feeders are usually separated However, the high capital cost and large operational power loss
at the primary busbars, and the further ends are connected only have limited their deployment [5, 6]. Furthermore, increasing
when one of the feeders has lost connection to the mains supply. DG may cause large DC current offset which may delay the
With increasing DG, it is desirable to join the feeders at zero-crossing of the fault current and increase the duties of the
appropriate positions using devices based on power electronics, power semiconductors [7, 8]. Therefore, estimating the
such as a static synchronous series compensator (SSSC) as dynamic response is potentially important when designing a
shown in Figure 1. Issues such as busbar voltage fluctuation, protection scheme [9, 10]. Much of the existing literature
branch overloading, and excessively high fault levels are some focusses on the potential applications of series compensators by
of the main challenges to operate the system with increasing considering their cost and efficiency. Series compensators are

Erfan Bashar, Robert Wu, Li Ran, and Philip A. Mawby are with the School of Dan Rogers is with the Department of Engineering Science, the University of
Engineering, the University of Warwick, Coventry, CV4 7AL, U.K. (E-mail: Oxford, Parks Road, Oxford, OX1 3PJ, U.K. (E-mail: [email protected].
[email protected]; [email protected]; l.ran@warwick .ac.uk; ac.uk).
[email protected]). Timothy C. Green is with the Department of Electrical and Electronic
Mike Jennings is with the College of Engineering, Swansea University, Bay Engineering, Imperial College, South Kensington, London, U.K. (E-mail:
Campus, Fabian Way, Swansea, SA1 8EN, Wales, U.K. (E-mail: [email protected]).
[email protected]).

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inherently vulnerable to short circuit faults in the grid. But only

a few studies have been conducted regarding the protection of
the series compensator itself, which were related to the
mitigation of voltage dip [11, 12], limiting the fault current [13,
14] using a fault current limiter or different control designs
integrated with the static series compensator. This paper
presents a fast-acting scheme for protecting the SSSC, which
provides series voltage insertion using power electronics.
Table 1 compares the studied protection mechanisms with
the proposed method that is detailed next in the paper.
Table 1: Comparison of different protection mechanisms
Main
Categories Advantages Disadvantages
components
Poor maintenance,
Small size, low
Fuses unclear melting
cost
time
Electric arc with
Fast breaking Fast mechanical Small size, low
contact erosion, low
switches switch power loss
speed
[15],[16] Figure 2: Configuration of the SSSC in the power system
Hybrid circuit
breakers/solid- Complex structure, and Feeder 1 is lightly loaded with only 1 MW load of the same
Fast, small arcing
state circuit relatively high cost power factor. It is assumed that a load of 8 MW needs to be
breakers
transferred from Feeder 2 to Feeder 1 to balance the two
Switched Auto-limiting Feeders. Balance of DG can be similarly achieved.
High cost, large
superconductor with the resistive
size The SSSC is a partially rated compensating device, which by
devices current
Simple structure, High power injecting a voltage orthogonal to the current can manipulate the
PWM control
resistive current dissipation of MOV power flow and damp power oscillation in the grid. Figure 2
Gate voltage Simple structure,
High power shows the connection of the compensator in the power system.
dissipation of The network determines the required injection voltage, in this
Fault current control resistive current
semiconductors
limiter study an 1100 VDC converter is utilised to control the power
[15], [17] Controlled Controllable High current
bridge with current, no harmonics with flow. The ABB HiPak IGBT module 5SNE 0800M170100,
inductor additional heat thyristors which has the ratings of Vce=1700 V and Ic=800 A, is selected
Static
No additional for building the converter. A three-phase 500 kVA, 1000 V to
heat, controllable Complex structure, 1000 V coupling transformer is included in the SSSC,
synchronous
current, low total capacitor charging
series corresponding to a maximum of 6.5% compensation level
harmonic issues
compensators
distortion which is usually enough for a local distribution network with
Small size, low
Coordinating MOV low impedance. When transferring the 8 MW active power, the
MOV-gap and spark gap, high converter is at the maximum operating point and its output
MOV and spark cost, relatively
mechanism initial voltage,
gap fast, no current magnitude is about 520 A. Therefore, under the full load
[18-20] difficult turning-off
harmonics
process in cases condition, one IGBT module for each arm and 6 modules in
Small size, low total are sufficient. The SSSC does not use any active power
Proposed cost, very fast,
thyristor simple Thyristor
source, as long as the injected voltage stays in quadrature with
Thyristor and the line current. This is guaranteed by the closed-loop control.
crowbar- coordination, no temperature during
MOV
varistor arc issue, low surge condition By varying the magnitude (Vq) of the injected voltage, the SSSC
mechanism power loss, no
harmonics acts as a controllable reactance compensator, either capacitive

II. STATIC SYNCHRONOUS SERIES COMPENSATOR

The network topology shown in Figure 1 is selected as the
target system. Feeder 1 is connected to 3 load groups evenly
distributed along the 5 km cable and Feeder 2 also has 3 load
groups evenly distributed along the 10 km cable. The cable
resistance and inductance are 0.06 ohm/km and 0.134 mH/km,
respectively. An SSSC is then installed between Busbars 3 and
4 as the connection at the further ends of the two adjacent
feeders to control the power transferred across them and
manipulate the voltage or loss profiles. The following extreme
case is selected to determine the compensation scheme: Feeder
2 is heavily loaded, 17 MW in total with a power factor of 0.98, Figure 3: Closed-loop controller for voltage-sourced converter (VSC)

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132kV main grid

prevent damage. Using thyristors to provide a faster response
could be a potential solution. This paper proposes a new
thyristor-based protection scheme, which also includes a
varistor, as shown in Figure 4, to protect the SSSC in the MV
distribution network. Thyristor crowbars have previously been
used to mitigate unbalanced voltage dips under grid fault
11kV primary Feeder 2 Feeder 1 11kV primary
busbar 2 busbar 1
conditions for SSSCs [11, 12] but they have not been used for
Normally open point protecting the device during grid short-circuit faults.
The protection principles are that the thyristor crowbars
create another phase-to-ground current path upon the fault,
Load Load preventing the fault current from passing through the SSSC.
Before the thyristor crowbar is turned on due to fault detection
6 5 time delay of the relay, the voltage across the SSSC will be
Varistor limited by the varistor. The protection process is described in
Busbar 4 2 1 Busbar 3 detail in the following subsections.
SSSC
4 3 A) Protection system design
3-phase fault Thyristor
Thyristor Some details of the protection scheme are expanded in Figure
crowbar crowbar
5. The protection process is as follows. When a fault occurs on
Figure 4: Schematic of proposed method by using both thyristor crowbars either side of the SSSC, the voltage across the SSSC will
and varistor increase to the clamping voltage of the varistor. At this point,
or inductive. A low-pass LC filter is utilised to suppress the the varistor allows a current to pass through it and keeps the
switching harmonics and electromagnetic interference. In voltage at this level. Therefore, it prevents the voltage across
addition, a closed-loop control system is used to synthesize the the SSSC from rising excessively high, and this allows the
appropriate sinusoidal voltage waveform of the voltage-source control of the SSSC current. The threshold voltage of the
converter that is applied to the grid. The control system tries to protection relay is set to 50% of the varistor clamping voltage.
keep the injected voltage in quadrature with the reference line After detecting the fault, a delay of 1 ms is assumed before the
current and keep the DC link voltage constant. The voltage loop thyristor crowbars are gated on. Thyristors operate very quickly
controls the voltage difference between Busbars 3 and 4 and (<3 μs [21]) compared to the mechanical CBs, whose opening
determines the amplitude of the injected voltage on the q-axis. time delay is uncertain and at least 20 ms [22, 23]. By turning
on the thyristors, the varistor comes out of the clamping state
III. THYRISTOR-BASED PROTECTION SCHEME WITH and the fault current will pass through them instead of the
VARISTOR visitor and SSSC whose current is controlled to discharge the
A major challenge is to protect the series compensator during DC link capacitor and the current will eventually be zero; circuit
a grid short circuit fault; in this case, a large current will flow, breakers ①, ②, ⑤ and ⑥ are then opened. At this point, the
and the voltage applied to the series compensator will rise to the SSSC is completely isolated from the grid and the thyristor
full grid voltage. When a three-phase-to-ground fault occurs crowbars can be gated off. This technique can decrease the
close to an unprotected SSSC, as shown in Figure 4, the voltage effective response time of the SSSC protection from >20 ms to
across the SSSC will immediately rise to the full line voltage of about 3 µs. Circuit breakers ③ and ④ are backup of ① and
11 kV (while the device voltage rating of the converter is only ② in case of failure for the thyristors to turn off. All CBs
1700 V) and the current will also rise rapidly to several except ③ and ④ are of very low breaking duties. Stresses on
thousand amperes (while the continuous current rating of the the SSSC are immediately released.
converter is only 800 A). Over-voltage and over-current of such
magnitudes will simply destroy the converter and conventional
mechanical circuit breakers are not able to respond rapidly to
880V
6 (continuous) / 5
3200J (2ms) CB
CB

Varistor
4 3
CB CB CB CB
SSSC
9 x Series 2 1 9 x Series
thyristor 1100VDC/
thyristor
crowbars 800A
crowbars
1800V/ 1800V/
1660A 1660A

Figure 5: Protection circuit schematic Figure 6: A timing diagram of the protection system procedure

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Figure 7: A typical Foster thermal model for IGBT, PiN diode and Thyristor

B) Timing diagram
The procedure of this protection scheme from the fault
detection to isolating the SSSC can be summarised in the timing Figure 8: An equivalent circuit of a varistor (V881BA60, LittelFuse)
diagram in Figure 6. It shows the proposed protection scheme
For the PiN diode:
and also the required timing in sending the gate signals to the
thyristor crowbars and CBs that have to be at the same time, PPiN DIODE(t) = Pconduction(t) + Preverse recovery(t) (3)
otherwise any delay could cause severe damage to the thyristors where Preverse recovery(t) refers to the reverse recovery loss.
and definitely the SSSC. In order to keep the turning on delay For the thyristor:
of thyristor crowbars as low as possible, no voltage crossing
PTHYRISTOR(t) = Pconduction(t) (4)
detection is used in the control system.
Varistor devices demonstrate fairly complicated electrical
IV. THERMAL MODELS AND DEVICE LIMITS behaviour and their modelling can be approached in several
ways. The most common representation of the impedance is an
A) Thermal model equivalent circuit as shown in Figure 8 [25], which is added to
All devices must be kept below their maximum allowable the clamping voltage depending on the current direction. To
temperatures. The thermal behaviours of the IGBT chips, PiN simplify varistor modelling the following equation is often used
diodes, and thyristors are modelled using Foster networks [24, [26-28]:
33] as shown in Figure 7. I = I 0  (V V0 )  (5)
Ri is the thermal resistance and τi is the time constant of each
For the varistor used in this paper, I0, V0 and α are 1000 A,
section in the Foster network, which are provided in the device
2450 V and 35, respectively. V is the voltage across the varistor
datasheets (τi = Ri Ci) and as shown in Table 2. The junction
and V0 is the clamping voltage, so RX is derived as follows:
temperature can be calculated as follows:
t −t V V
n
Tvj (t) =  P(t)  Z thj (t − )  d + Tcase (t), Zthj (t) =  R i (t)  (1 − e i ) (1) Rx = = (6)
i=1
I I0  (V V0 ) 
0

where Zthj(t) is the total thermal impedance, Tcase is the case A varistor is typically pulse rated: as long as the peak current
temperature, Tvj is the junction temperature and P(t) is the and the absorbed energy do not exceed the datasheet
power loss. For the IGBT: specifications the varistor will remain intact [27, 29]. Therefore,
a Foster thermal network model is not used for the varistor. The
PIGBT(t) = Pconduction(t) + Pswitching(t) (2)
energy absorbed by the varistor is obtained by:
where Pconduction(t) refers to the transistor power loss when it T
conducts the current and Pswitching(t) is the summation of turn-on E =  Vc (t)I(t)dt (7)
and turn-off switching losses of the transistor. 0
where Vc(t) is the component voltage, and I(t) the current.
Table 2: Thermal impedance
Model i 1 2 3 4 B) Device limits
IGBT-5SNE Ri(K/kW) 15.2 3.6 1.49 0.74 According to the IGBT module datasheet, the maximum
0800M170100- withstanding junction temperature is 150°C for both of the
ABB τi(ms) 202 20.3 2.01 0.52
IGBT and the PiN diode and the maximum surge current of the
PiN diode-5SNE Ri(K/kW) 25.3 5.78 2.6 2.52 IGBT module is 6.6 kA for a 10 ms-pulse, when the junction
0800M170100- temperature is 125°C.
ABB τi(ms) 210 29.6 7.01 1.49
In terms of the thyristor surge current, junction temperature,
Thyristor- 5STP Ri(K/kW) 10.350 3.760 2.290 0.670 and voltage rating, the device utilised in this simulation can
18F1800-ABB τi(ms) 0.3723 0.0525 0.0057 0.0023 endure 17.5 kA during one pulse and 14.2 kA during two pulses,
when the initial junction temperature is 125°C where each pulse

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Table 3: Network Properties

Feeder 2 Feeder 1
Voltage level 11kV 11kV
Source fault level 250MVA 250MVA

Cable Resistance 0.06Ω/km 0.06Ω/km

Impedance Inductance 0.134mH/km 0.134mH/km
Cable length 10km 5km
Load 17MW 1MW
SSSC-Transformer 1100VDC/800A-600kVA,1kV/1kV
Varistor 880V (continuous), 2450V (clamping)
Thyristor 1800V/1660A
Figure 9: A schematic of three phase VSC-SSSC connected to the
network through a three-phase coupling transformer
unearthed, two strings of thyristors should always withstand the
is 10 ms, 50Hz, half sine wave. Since it is only used within the peak line-to-line voltage, to work in different fault types.
fault condition, the initial junction temperature can be assumed B) Selection of varistor
to the ambient temperature; in this simulation, it is set at 40°C.
The procedure of selecting the varistor is as follows:
The thyristor’s maximum non-repetitive withstanding
1. determine the clamping voltage of varistor according to
temperature during surge is 289°C, with Tvj=125°C and
the SSSC maximum peak voltage in normal condition;
VR&D=0.6VRRM; where VR&D and VRRM are the thyristor voltage
2. determine the operating time of the varistor;
after the surge current and the rated reverse blocking voltage,
3. calculate the surge current through the varistor;
respectively.
4. calculate the energy to be dissipated in the varistor.
Regarding the varistor, a metal-oxide, e.g. ZnO, varistor
made by Littelfuse (V881BA60) is used. It can absorb 3200 J VI. SIMULATION RESULTS
and endure 1 kA or 1.5 kA within a 1 ms- or 0.7 ms-pulse,
respectively. Because the varistor is used for up to 1 ms (the The parameters of the case study system are shown in Table
3 and a schematic of the three-phase SSSC is shown in Figure
required time delay for the relay to gate on the thyristors), the
9. The proposed method of protection is compared with an
mentioned data shows its ability during this period. The limited
energy capacity of a varistor means that it cannot be used alone unsuccessful conventional protection method using mechanical
switches.
to protect the SSSC. It is instead hybridized with the thyristor
crowbars to work in the system. Similarly, a spark-gap, which A) Conventional protection method
is also intended for short pulses, is not by itself sufficient for Figure 1 has shown previously the structure of the
the targeted application. conventional protection mechanism that only uses mechanical
circuit breakers. In this case, it is supposed that a fault happens
V. SELECTION OF THYRISTOR AND VARISTOR at t=1.58 s and voltages across the SSSC in phases A, B and C
Selecting proper thyristor and varistor is important for the will reach the threshold voltage (0.5 × 2450 V) of the relays at
effectiveness of the proposed protection scheme. A bad choice 0.205 ms, 0.230 ms and 2.625 ms after the fault inception. 1 ms
could lead to failure of the concept. after that, relays will send the tripping command to the CBs
which will then cut off the current after a further 20 ms. For
A) Selection of thyristor
instance, regarding phase A, the entire cutting off time is 0.205
The following aspects should be considered: ms+1 ms+20 ms. Figures 10 and 11 show the current and
1. the maximum short circuit current level including the voltage of a closed-loop SSSC during the fault. The fault
DC offset; current level through the SSSC can rise to 7 kA which can
2. the maximum number of surge current pulses that the severely harm the IGBTs. Moreover, the voltage overshoot is
thyristor has to conduct; around 18 kV which can saturate the transformer, causing large
3. the peak voltage that the thyristor has to withstand after core losses and differential relays to trip [30].
fault clearance. Regarding the calculation of IGBT module temperature, the
The making fault level of an 11 kV system is managed below converter and IGBT modules mentioned in Section II are used
600 MVA, meaning that the maximum rate of current rise in the in this simulation and the initial junction temperature is about
thyristor is about 14 A/µs (assuming 50 Hz). This can be easily 90°C, changing within a fundamental cycle. As can be seen in
satisfied and hence the main constraint will be the temperature Figure 10, phase B has the highest peak current of 7 kA which
rise of the device under the current surges. If the number of the exceeds the permissible surge current (6.6 kA). Subsequently,
current surge pulses to be carried by the thyristor increases, the phase A current peak reaches to 6 kA which causes the
amplitudes of the pulses have to reduce. temperature of the IGBT modules to exceed or become very
The maximum peak voltage determines the number of series close to the maximum allowable temperature 150°C as shown
thyristors in the crowbar. As an 11 kV system is usually neutral in Figures 12 and 13 for the worst cases. Figures 12 and 13 show

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the temperature response of an IGBT (blue line) and PiN diode absorbed energy is around 700 J, as shown in Figure 18. It can
(orange line), as it can be seen that the temperature in these legs be seen that the energy and also current are below the allowable
has exceeded 150°C for both the IGBT, and PiN diode chips, limits so it can be claimed that the varistor temperature will
especially in cases where the CBs need longer time to get certainly be lower than 125°C, its maximum allowable value.
opened (three cycles or more), which is not shown here. It Voltages in phases A, B and C will reach the threshold voltage
means that the conventional method is not fast enough to protect (0.5 × 2450 V) of relays at 0.095 ms, 0.230 ms, and 1.655 ms
the SSSC. after the fault. Then after a further 1 ms, the required time for
B) Proposed protection method detecting the fault and sending the gate signals, the crowbars
are turned on and then most of the fault current passes through
In the second case, thyristor crowbars are used in shunt to the
them because of the thyristor’s low turn-on impedance. For
SSSC and a varistor is in parallel with the SSSC as shown in
example, the required time to turn the thyristor on in phase A is
Figure 4. The voltage and current ratings of the SSSC
0.095 ms+1 ms. Figure 19 shows the thyristor current
semiconductors are 1700 V and 800 A respectively. Figure 14
waveforms. As mentioned, the surge current is an indicator of
shows the voltage across the SSSC and varistor, which are
the thyristor crowbar capability in tolerating the fault. Phase A
identical because they are in parallel. Figure 15 shows the SSSC
has the highest surge current which also repeats twice for
current. Figure 16 shows the thyristor crowbar schematic.
thyristor leg 1. The absorbed energy for this thyristor is
In this simulated case study, a three-phase-to-ground fault
calculated to be around 400 J.
occurs at t=1.58 s and the voltage across the varistor and SSSC
Figure 20 shows the thyristor temperature response for phase
increases immediately but is limited at the varistor clamping
A, legs 1 & 2, that are supposed to be the worst-case compared
voltage, 2450 V (Figure 14). Varistors in phases B and C will
with other thyristors in the system. It can be concluded that no
be activated after 0.275 ms and in phase A after 2.275 ms. thyristor temperature will exceed its allowable limit. In parallel
Therefore, until the thyristor crowbars are turned on, the with thyristors’ operation, after 20ms of detecting the fault,
varistor will pass the current through itself so as to limit the circuit breakers 1 and 2 are opened, and then the firing pulse is
SSSC voltage and current; the transformer impedance will limit removed from the thyristor crowbars’ gates in order to turn
the current surge into the converter. During this period, the them off. It is worth mentioning that the required thyristor
voltage of the varistor is similar to the SSSC, Figure14, and the blocking voltage after the operation has a great effect on its
varistor current is shown in Figure 17. Furthermore, the

Figure 10: The fault current passing through SSSC- Conventional method Figure 12: IGBT temperature in leg 1 top- Conventional method

Figure 11: The voltage of SSSC during the fault- Conventional method Figure 13: IGBT temperature in leg 2 bottom- Conventional method

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surge-tolerance ability. As mentioned, after the surge current, result is shown in Figure 22. As expected, the PiN diode
the voltage is applied across the thyristor must be 0.6 VRRM (0.6 temperature is 128°C which is well below the 150°C limit of
× 1800 V). Therefore, in this case, since the voltage peak value the module for either IGBT or PiN diode.
is 9 kV, as shown in Figure 21, at least 9 thyristor crowbars for
each phase are required in series. The thyristors turn on and turn
off relatively slowly, in µs, therefore connecting thyristors in
series, driven by the same gating signal, is much easier than
IGBTs. Snubbers are usually used to assist dynamic voltage
sharing, as in HVDC systems [34]. The pulse transformer and
the optically coupled firing methods can also be used [35].
Moreover, the thyristor current DC offset duration which is Figure 16: Thyristor crowbars schematic on one side of SSSC
generated during a fault is sufficiently less than one cycle (20
ms) in medium voltage networks and thus has no influence on
the turning-off process of the thyristor crowbars [8].
Consequently, as it was expected the short circuit current
passing through the SSSC is limited to 3 kA (peak value),
Figure 15, which is less than half of the previous value (7 kA,
peak value) and its duration is also reduced to only 4 ms, with
rising time of 1 ms. Besides, the voltage across the SSSC as
mentioned before is clamped by the varistor so that its value is
limited to 2450 V compared to 18 kV in the previous case study.
Regarding the IGBT temperature, first of all, the maximum
current passing through the devices is 3 kA which is much
smaller than their maximum allowable surge current (6.6 kA).
Also the phase B current is the worst case during this fault
situation, so the temperature of IGBT module leg 2 (lower leg)
will have the highest rise compared to other IGBTs and the Figure 17: Varistor current- Proposed method

Figure 18: Varistor energy- Proposed method

Figure 14: Voltage of SSSC & Varistor- Proposed method

Figure 15: SSSC Current- Proposed method Figure 19: Thyristor current during fault- Proposed method

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Apart from the IGBT and PiN diode protection, the capacitor
utilised on the DC side of the converter could be severely
damaged during the fault if the protection system does not act
fast enough. Figure 23 shows that the capacitor voltage could
reach to 22 p.u. in the conventional protection scheme but by
using the proposed method, it can be limited to 1.5 p.u. when
the original DC voltage is 1100 VDC.

VII. EXPERIMENTAL RESULTS

To demonstrate the protection concept, a scaled-down single-
phase lab model has been considered as illustrated in Figures
24 and 25. However, in this case, instead of using two thyristor
crowbars in shunt to the SSSC, one thyristor crowbar in parallel
has been used. In fact, the difference between these two
Figure 20: Thyristors’ temperature in phase A- Proposed method
methods is the control of the short-circuit level at the fault point,
meaning that by bypassing all current to the same side the fault
level would now be almost twice.
A single-phase H-bridge voltage source converter is
connected to the line via a 1:1 series-coupling transformer,
which mimics the SSSC. A 230 VAC 50Hz single-phase voltage
source mimics the grid. A resistor bank is connected between
the transformer and voltage source to create a relative phase
shift [31, 32] at Bus 3 by passing the current through the
interconnecting impedance. The measured voltages at Buses 1

Figure 21: Thyristor Voltage- Proposed method

Figure 22: Temperature of IGBT in leg 2 bottom- Proposed method

Figure 24: Single-phase protection scheme

Dspace
DC source for
the converter
Converter

Current clamp &

junction box

Thyristor
& Resistors,
varistor inductances, and
the capacitor

Figure 23: Capacitor voltage of the converter- DC side Figure 25: Laboratory prototype

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and 3 are equal to 230 V0 and at Bus 2 is 204.71V − 2.48 26 and 27. The utilised IGBT in this test is SEMIKRON
SK35GD126ET, and its heatsink temperature variations during
without the SSSC, and 211.14 V − 1.4 with the SSSC.
the fault is shown in Figure 27.
A) Conventional protection method
B) Proposed protection technique
In the absence of thyristor and varistor, a high-resistance
fault happens in the network in order to check the current, In the second case, the varistor and thyristor crowbar are used
voltage and temperature response of the converter. For to prove the effectiveness of the proposed technique. The used
monitoring the temperature, a thermocouple is applied to the
converter heatsink to record the temperature variation. In this
case, a fault happens at t=64 ms and then circuit breakers are
opened after 20 ms. The obtained results are shown in Figures

Figure 29: Thyristor & Varistor’s Current- Proposed method

Figure 26: SSSC Voltage & Current- Conventional method

Figure 30: Temperature variation of IGBT, varistor & Thyristor- Proposed

method
Figure 27: Temperature variation of IGBT- Conventional method

Figure 28: SSSC Voltage & Current - Proposed method Figure 31: Varistor energy- Proposed method

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during the whole fault event. Components can be realistically

selected for an SSSC in an 11 kV network. The SSSC’s IGBT
module temperature is maintained below its maximum
operating temperature. In addition, the proposed protection
scheme is also safe from temperature rise and transient over-
voltage points of view.
The simulation and experiment have focussed on
symmetrical three-phase faults. But the number of series
devices and their voltage ratings are selected such that the
proposed scheme can also work in other grid fault types. Series
connection of thyristors has been made in industry with the help
of snubbers for dynamic voltage sharing. It is expected that the
study could provide a stepping stone towards commercial
development of SSSC and its protection schemes for medium
voltage grids which are under pressure for accommodating
more low carbon distributed generation.
Figure 32: Thyristor temperature response- Proposed method
IX. REFERENCES
thyristor crowbar and varistor are SEMIKRON SKKT 273 and 1. M. Kano, T. Maekawa, T. Takeshita and Y. Kunii, "Comparison of converter
TDK metal oxide varistor B72210S0140K101. In this case, arrangement of series and shunt converters in UPFC for distribution system
fault happens at t=64 ms, and after 2 ms delay, the thyristors are control," 2016 IEEE International Conference on Renewable Energy Research
and Applications (ICRERA), Birmingham, 2016, pp. 431-436.
gated on. During the 2 ms, the varistor will limit the voltage doi: 10.1109/ICRERA.2016.7884374.
across the SSSC, providing a path for the fault current. After 20 2. X. Zhang, D. Shi, Z. Wang, B. Zeng, X. Wang, K. Tomsovic and Y. Jin,
"Optimal Allocation of Series FACTS Devices Under High Penetration of Wind
ms, the CBs interrupt the current. For measuring the Power Within a Market Environment," in IEEE Transactions on Power Systems,
temperature, a thermal copper is again connected to the vol. 33, no. 6, pp. 6206-6217, Nov. 2018.
converter heatsink, thyristor crowbar heatsink and varistor doi: 10.1109/TPWRS.2018.2834502.
3. Narain G. Hingorani; Laszlo Gyugyi, "FACTS Concept and General System
body. The results are presented in Figures 28 to 31. Considerations," in Understanding FACTS: Concepts and Technology of
These experimental results indicate that the proposed Flexible AC Transmission Systems, IEEE, 2000, pp.1-35
doi: 10.1109/9780470546802.ch1
technique can reduce the temperature variations of IGBTs 4. C. Meyer, M. Hoing and R. W. De Doncker, "Novel solid-state circuit breaker
within the safe operating range. Although in Figure 27 the case based on active thyristor topologies," 2004 IEEE 35th Annual Power
temperature is not changing significantly, in comparison with Electronics Specialists Conference (IEEE Cat. No.04CH37551), Aachen,
Germany, 2004, pp. 2559-2564 Vol.4.
Figure 30, by cutting off the current passing through the doi: 10.1109/PESC.2004.1355232
converter, it can be seen that the temperature increase, Figure 5. Mircea Eremia; Chen-Ching Liu; Abdel-Aty Edris, "VSC–HVDC
Transmission," in Advanced Solutions in Power Systems: HVDC, FACTS, and
30, has been considerably reduced. Moreover, the voltage Artificial Intelligence , , IEEE, 2016, pp.125-267
variations of the SSSC, as shown in Figure 28 is well controlled doi: 10.1002/9781119175391.ch4
by using the proposed technique compared to Figure 26 6. R. M. Kotecha, Y. Zhang, A. Rashid, N. Zhu, T. Vrotsos and H. A. Mantooth,
"A physics-based compact gallium nitride power semiconductor device model
corresponding to the conventional method. Also. Figure 31 for advanced power electronics design," 2017 IEEE Applied Power Electronics
shows the varistor energy absorption that is very low. Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2685-2691.
doi: 10.1109/APEC.2017.7931078.
In roder to analyse the temeprature behaviour of the thyristor 7. N. T. Stringer, "The effect of DC offset on current-operated relays," in IEEE
during the fault more accurate, the test has been repeated with Transactions on Industry Applications, vol. 34, no. 1, pp. 30-34, Jan.-Feb. 1998.
a smaller thyristor pair ( Philips BT151) with a lower current doi: 10.1109/28.658712.
8. E. Bashar, Q. Han, R. Wu, L. Ran, O. Alatise and S. Jupe, "Analysis of DC offset
rating. In this case, the temeprature variation of the thyristor in fault current caused by machines in a medium voltage distribution network,"
becomes significantly higher as shown in Figure 32. Due to in The Journal of Engineering, vol. 2019, no. 17, pp. 3494-3499, 6 2019. doi:
10.1049/joe.2018.8221
limitation of our laboratory, the experimental work has not been 9. P. Stachel and P. Schegner, "Estimation of DC time constants in fault currents
conducted towards the limit of the devices. and their relation to Thévenin's impedance," 2010 Modern Electric Power
Systems, Wroclaw, 2010, pp. 1-6.
10. Prachal Jadeja , Abhijeet Shrivastava., “Effects of DC Components on Circuit
VIII. CONCLUSION Breaker”, International Journal of Science and Research (IJSR), India, 2015, pp.
724-728,
Although SSSC has significantly higher efficiency during https://www.ijsr.net/search_index_results_paperid.php?id=SUB158832
normal operation and an exceptional performance-cost ratio, its 11. H. Awad, J. Svensson and M. Bollen, "Mitigation of unbalanced voltage dips
application is restricted due to its currently poor ability to using static series compensator," in IEEE Transactions on Power Electronics,
vol. 19, no. 3, pp. 837-846, May 2004.
survive network fault conditions. In this paper, a protection doi: 10.1109/TPEL.2004.826536.
scheme has been proposed and its behaviour verified by 12. H. Awad, H. Nelsen, F. Blaabjerg and M. J. Newman, "Operation of static series
compensator under distorted utility conditions," in IEEE Transactions on Power
simulation and demonstrated by experiment. The circuit Systems, vol. 20, no. 1, pp. 448-457, Feb. 2005.
consists of parallel thyristor crowbars that draw the fault current doi: 10.1109/TPWRS.2004.841238.
and a varistor, which limits the voltage rise across the SSSC 13. Z. Wu, D. Jiang, D. Lao, Q. Ying and Y. Du, "A novel topology of DC
distribution network with fault current limiting static synchronous series
before the thyristors are turned on. Simulation results show that compensator," 2017 IEEE PES Innovative Smart Grid Technologies
the voltage across and current through the SSSC are controlled

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Authorized licensed use limited to: University of Exeter. Downloaded on May 06,2020 at 03:28:57 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPWRD.2020.2982512, IEEE
Transactions on Power Delivery

Conference Europe (ISGT-Europe), Torino, 2017, pp. 1-5. on Power Delivery, vol. 27, no. 1, pp. 53-61, Jan. 2012.
doi: 10.1109/ISGTEurope.2017.826021. doi: 10.1109/TPWRD.2011.2171061.
14. W. Qiao and R. G. Harley, "Fault-Tolerant Optimal Neurocontrol for a Static 33. ABB, " Application Note , Surge Currents for Phase Control Thyristors, 5SYA
Synchronous Series Compensator Connected to a Power Network," Conference 21-2-00.", ABB, 2014, [Online]. Abailable:
Record of the 2006 IEEE Industry Applications Conference Forty-First IAS https://library.e.abb.com/public/4a1f7f8ebc5eb5c383257caf00430141/Surge%
Annual Meeting, Tampa, FL, 2006, pp. 642-649. 20currents%20for%20PCT_%205SYA%202102-00.pdf [Accessed:
doi: 10.1109/IAS.2006.256594. 10/02/2020].
15. C. Gu, P. Wheeler, A. Castellazzi, A. J. Watson, and F. Effah, “Semiconductor 34. N. Mohan, T. Undeland and W. Robbins, "Snubber Circuits," in Power
Devices in Solid-State/Hybrid Circuit Breakers: Current Status and Future Electronics, Converters, Applications and Design, in John Wiley & Sons, 2003,
Trends,” Energies, vol. 10, no. 4, p. 495, Apr. 2017. pp.678-680.
16. R. Mehl and P. Meckler, “Comparison of advantages and disadvantages of 35. P. C. Sen, "Characteristics of Semiconductor Devices," in Power Electronics,
electronic and mechanical Protection systems for higher Voltage DC 400 V, McGraw-Hill Education, 1987, pp.1-155, ISBN10: 0074624008.
” Intelec 2013; 35th International Telecommunications Energy Conference,
SMART POWER AND EFFICIENCY, Hamburg, Germany, 2013, pp. 1-7.
17. Cui Xiaodan et al., "Effects of fault current limiter on the safety and stability of
power grid and its application: A research review," 2016 IEEE PES Asia-Pacific
Power and Energy Engineering Conference (APPEEC), Xi'an, 2016, pp. 2494-
2498. doi: 10.1109/APPEEC.2016.7779937
18. Li Jing, Xiang Zu-tao, Hou Jun-xian, Ling Ji-min and Guo Qiang, "The impact
of model for MOV-protected series capacitors on system stability and available
transmission capability," 2012 IEEE International Conference on Power System
Technology (POWERCON), Auckland, 2012, pp. 1-5.
doi: 10.1109/PowerCon.2012.6401304
19. P. M. Khadke, N. R. Patne and G. A. Shinde, "Co-ordination of spark gap
protection with MOV in EHV transmission line with FSC," 2016 IEEE Erfan Bashar received the B.Sc. in
International WIE Conference on Electrical and Computer Engineering
(WIECON-ECE), Pune, 2016, pp. 16-20. Electrical Engineering from Islamic
doi: 10.1109/WIECON-ECE.2016.8009077 Azad University South Tehran Branch
20. Uman, M. (2008), “Surge protection for electronics in low-voltage electrical of Iran, in 2009; received M.Sc. in
systems”, In The Art and Science of Lightning Protection (pp. 99-110).
Cambridge: Cambridge University Press. Electrical Machines and Power
doi:10.1017/CBO9780511585890.007 Electronic from Iran University of
21. Datasheet for ABB, 1.8kV, 2.61kA Silicon Phase Control Thyristor, Science & Technology (IUST), in
5STP18F1800, 2019, [Online]. Abailable:
https://library.e.abb.com/public/e9572863245e4d4fbdf1526003bf2f47/5STP% 2012; He is currently a PhD student in
2018F1800_5SYA1028-05May%2007.pdf [Accessed: 12/07/2019] the School of Engineering, University
22. Jim Bowen, "Application Note, Medium Voltage Switchgear & Circuit Breaker of Warwick, UK working on the system protection and power
Ratings and Application," in IEEE Continuing Education, Armaco, 2019,
[Online]. Abailable: http://site.ieee.org/houston/files/2016/01/7-MV-
electronics applications.
Switchgear-Mar-24-25.pdf [Accessed: 12/07/2019]
23. ABB, " Application Note , Medium voltage indoor circuit breakers ANSI/IEC Daniel J. Rogers (M’09, SM’19) is an
solutions", ABB, 2019, [Online]. Abailable:
http://howoninc2.skyd.co.kr/images/VCB%20-%20ABB.pdf [Accessed: Associate Professor in the Department
12/07/2019] of Engineering Science at the University
24. Infineon, " Application Note , Thermal equivalent circuit models, AN2008-03.", of Oxford, UK. He received the M.Eng.
Infineon, 2008, [Online]. Abailable: https://docplayer.net/20772848-
Application-note-v1-0-2008-an2008-03-thermal-equivalent-circuit-models- and Ph.D. degrees in Electrical and
replaces-an2001-05-industrial-power.html. [Accessed: 25/06/2019] Electronic Engineering from Imperial
25. LittelFuse, " Application Note, Littelfuse Varistors - Basic Properties,
Terminology and Theory," LittelFuse, 2019, [Online]. Abailable: College London, London, U.K., in 2007
https://www.littelfuse.com/~/media/electronics_technical/application_notes/va and 2011 respectively. He conducts
ristors/littelfuse_varistors_basic_properties_terminology_and_theory_applicati
on_note.pdf. [Accessed: 25/06/2019]. research in collaboration with industry and is an investigator on
26. M. Abdel-Salam, N. A. Ahmed and I. S. Elhamd, "Varistor as a surge protection UK EPSRC research projects in the areas of power electronics,
device for electronic equipments," 2004 IEEE International Conference on
Industrial Technology, 2004. IEEE ICIT '04., Hammamet, Tunisia, 2004, pp.
grid-scale energy storage and microgrids. Dan’s research
688-694 Vol. 2.doi: 10.1109/ICIT.2004.1490158. interests in power electronic range from active control of
27. Jinliang He, ,"Simulation on Varistor Ceramics," in Metal Oxide Varistors: transistor switching, to circuit and control system design,
From Microstructure to Macro‐Characteristics, 11 March 2019, Wiley‐VCH
Verlag GmbH & Co. KGaA, 2019, pp. 149-193 DOI:10.1002/9783527684038. through to novel applications enabled by wide-bandgap
28. LittelFuse, " Application Note , Transient Suppression Devices and devices.
Principles," LittelFuse, 2019, {Online]. Abailable:
https://m.littelfuse.com/~/media/electronics_technical/application_notes/varist Ruizhu Wu received the B.Sc. in
ors/littelfuse_transient_suppression_devices_and_principles_application_note.
pdf [Accessed: 25/06/2019] Telecommunication Engineering from
29. M. v. Lat, "Thermal Properties of Metal Oxide Surge Arresters," in IEEE the University of Electronic Science and
Transactions on Power Apparatus and Systems, vol. PAS-102, no. 7, pp. 2194- Technology of China, Chengdu, China in
2202, July 1983. doi: 10.1109/TPAS.1983.318207
30. Neha Bhatt, Sarpreet Kaur and Nisha Tayal, "Causes and Effects of Overfluxing 2010; received M.Sc. in Engineering
in Transformers and Comparison of Various Techniques for its from Xihua University, Chengdu, China
Detection", IJCA Proceedings on International Conference on Advances in in 2014; and received the Ph.D. in
Emerging Technology ICAET 2016(11):17-22, September 2016.
31. H. Fujita, Y. Watanabe and H. Akagi, "Transient analysis of a unified power Engineering from the University of
flow controller and its application to design of the DC-link capacitor," in IEEE Warwick, Coventry, UK in 2019. He is currently a research
Transactions on Power Electronics, vol. 16, no. 5, pp. 735-740, Sept. 2001. fellow in the School of Engineering, University of Warwick,
doi: 10.1109/63.949506).
32. M. E. A. Farrag and G. A. Putrus, "Design of an Adaptive Neurofuzzy Inference UK working on reliability and applications of SiC power
Control System for the Unified Power-Flow Controller," in IEEE Transactions electronics.

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Li Ran (M'98-SM'07) received a PhD electronics to create electricity networks that can accommodate
degree in Power Systems Engineering greater amounts of low carbon technologies. In HVDC, he has
from Chongqing University, Chongqing, contributed converter designs that strike improved trade-offs
China, in 1989. He was a Research between power losses, physical size and fault handling. In
Associate with the Universities of distribution systems, he has pioneered the use of soft open
Aberdeen, Nottingham and Heriot-Watt, points and the study of stability of grid connected inverters.
at Aberdeen, Nottingham and Edinburgh Prof. Green is a Chartered Engineer in the UK and a Fellow of
in the UK respectively. He became a the Royal Academy of Engineering.
Lecturer in Power Electronics with
Northumbria University, Newcastle upon Tyne, the UK in 1999 Philip A. Mawby (S’85–M’86–SM’01)
received the B.Sc. and Ph.D. degrees in
and was seconded to Alstom Power Conversion, Kidsgrove, the
electronic and electrical engineering from
UK in 2001. Between 2003 and 2012, he was with Durham
the University of Leeds, Leeds, U.K., in
University, the UK and took a sabbatical leave at MIT, the USA 1983 and 1987, respectively. His Ph.D.
in 2007. He joined the University of Warwick, Coventry, the degree was focused on GaAs/AlGaAs
UK as a Professor in Power Electronics - Systems in 2012. His heterojunction bipolar transistors for
research interests include the applications of Power Electronics high-power radio frequency applications
for electric power generation, delivery and utilization. at the GEC Hirst Research Centre,
Wembley, U.K. In 2005, he joined the
Mike Jennings received his B.Eng. University of Warwick, Coventry, U.K.,
degree in electronics with as the Chair of power electronics. He was also with the
communications from the University of University of Wales, Swansea, U.K., for 19 years and held the
Wales, Swansea, U.K., in 2003. An Royal Academy of Engineering Chair for power electronics,
underlying interest in advanced power where he established the Power Electronics Design Center. He
devices led him to undertake a Ph.D, has been internationally recognized in the area of power
which he was awarded from the electronics and power device research. He was also involved in
University of Warwick, Coventry, U.K., in 2008. His Ph.D the development of device simulation algorithms, as well as
centred around wide bandgap semiconductor devices for optoelectronic and quantum-based device structures. He has
application in power converters. The manufacturing-focus of authored or coauthored more than 200 journal and conference
papers. His current research interests include materials for new
his research allowed him to establish a strong industrial
power devices, modeling of power devices and circuits.
network. This naturally progressed to a five-year Senior Professor Mawby is a fellow of the IET and a fellow of the
Science City Research Fellowship, where he provided business Institute of Physics as well as a senior member of the IEEE.
assistance to numerous industrial partners from the
semiconductor, power electronics and energy industry sectors.
His main research interest is in the field of new semiconductor
materials for power electronics applications. His current
research interests include silicon carbide and gallium oxide
power devices and the manufacturability of advanced silicon
MOSFETs and IGBTs. He currently holds a Royal Academy of
Engineering Industrial Fellowship, which focusses on bringing
the latest power semiconductor devices through to
commercialisation. Dr Jennings has served on many
international committees including the European Conference
on Silicon Carbide and Related Materials (ECSCRM) and
European Power Electronics (EPE).

Tim C Green (M’89–SM’03–F’19)

received a B.Sc. (Eng) (first class
honours) from Imperial College London,
UK in 1986 and a Ph.D. from Heriot-Watt
University, Edinburgh, UK in 1990. He is
a Professor of Electrical Power
Engineering at Imperial College London,
and Co-Director of the Energy Futures
Lab with a role of fostering
interdisciplinary energy research across
the university. His research uses the flexibility of power

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