Data Buffering and Minimum

Mode CPU
8086 Minimum Mode configuration
Requirements

• Three 8 bit Octal Latches (IC 8282/74LS373)

• Two 8 bit transceivers (IC 8286)
• One control signal generator
• One clock generator (IC 8284)
Latches : used to demultiplexed all multiplexed line.
Transceiver: separate the data bus from multiplexed address bus.
Control signal generator: generate four control signals.
Minimum Mode 8086 System
Microprocessor BUS types and buffering
techniques
• To ensure that the address is available on the memory or input output address lines
throughout the complete read write bus cycle, The 20 lines of address information or
(^BHE) have to be latched.

• Obviously external latch IC will have to be used.

• A popular latch IC 74LS 373 / 8280 used.

• This IC can cater only to 8 lines that is three such Ics can used.
• This is a transparent D type latch means when the enable G pin is high the Q
Output will follow the data D inputs.

• Thus the ALE pin Is connected to the G pin of the ic.

• The (^OC) Output Control is grounded for normal operation.

• This ic provides a buffered output i.e. it has the capability to drive high
capacitance buses that are normally encountered and the current driving
capabilities of address lines is raised so that more number of TTL loads may be
driven
Partial Buffered System/Address Bus Buffering
Fully Buffered System/Data bus buffering(74LS245)

• The (^DEN) of the processor is connected to the enable line (^G) of the buffer

• The (DT/^R) Line is high for data write and low for data read and this pin is
connected to the DIR pin of buffer.
Maximum Mode CPU
• In this mode more than one processor is present in the system.

• The other processor may be either a numeric co processor 8086 or

may other independent processor like 8086 or 8088.

• All the resources like memory, address bus, data bus are shared
between the two processors
• In this configuration the latches are used to demultiplex the
multiplexed address data lines and two transceivers Are used to
enable the data flow and direction of data flow.
• The control signal of maximum mode of operation are generated by
the bus controller chip 8288.

• The three output of the processor are connected to the inputs of

8288.

• The 8288 provides the control and command timing signals for 8086.

• The bus controller 8288 works in two operation mode that is input
output bus mode and system bus mode.
8288 Pin Configuration
Maximum Mode CPU
Clock Generator
• A clock is a square wave signal of its frequency.

• All timings of activities done by processor are calculated based on this

clock period.

• One cycle of the clock is called T state, And all timings and delays are
multiples of this T state duration.

• There is no circuitry inside the processor for generating the clock so

external clock generator ic (8284) is used.
• This generates a clock of frequency depending on the crystal
connected between two of its terminals.

• The crystal frequency must be three times the desired frequency for
the microprocessor.

• 8086 operates at frequencies of 5 to 15 MHz.

The clock generator ic performs a few more function than just

supplying a clock frequency to the processor.
8284 IC
• It is a 18 pin chip designed to provide the clock frequency, ready and
reset signals to 8086 processor.

• The ready and reset signals are applied to the clock generator and it
synchronise the ready and reset signals with clock and then apply
them to microprocessor.
Block Diagram of 8284
Operation of clock section
• The clock logic generates the three output signals named OSC., CLOCK and PCLK.

• Crystal oscillator has two inputs, generates square wave signal at the same frequency as
a crystal.

• This square wave is applied to AND gate and also to an inverted buffer that provides an
OSC output signal.

• The and gate is used to apply the oscillator output to the divide by three counter when
F/C(bar) is at logic 0. when it is logic 1, then EFI is passed through the counter.

• The output of divide by three counter generates the timing for ready and reset signals.
• If in a system there is more than one 8284 then those entire 8284
clock generators are synchronised by CSYNC input.

• The peripheral clock frequency (PCLK) is used to provide required

clock for supporting peripheral chips like 8254/53.
Operation of RESET Section
• The reset section of 8284 consist of Schmitt trigger buffer and single D type
FF.

• This circuit applies the reset signal to the microprocessor on the negative
edge of each clock.

• The RC circuit provide logic 0 to the RES input pin when power is first
applied to the system.

• The RES input becomes a logic one because the capacitor charges towards
+5 Volt through the Register.
Operation of READY section
• The Ready section generates the ready signal for 8086.

• The microprocessor introduces a wait state between T3 and T4 states of

the machine cycle whenever the Ready signal is low.

• Whenever the logic level of RDY1 and AEN1 becomes 01 or the logic level
of RDY2 and AEN2 becomes 01 the Ready output becomes low.

• The AEN1 is used for generating wait state in 8086 bus cycle whereas RDY1
is used for generating the wait state in the DMA bus cycle.
8284 IC
• RES (RESET IN): RES is an active low input signal which is used to
generate resets IN signal for 8284. This is connected to the power
supply of the microprocessor. When microprocessor wakes up at that
time a low signal is generated on this pin of 8284.

• X1and X2: An external crystal oscillator is connected to these inputs.It

is used as the timing source for the clock generator and all its
functions.

• F/C’: This pin is used to select whether an internal clock is generated

or the external clock is to be used when F/C’=0 , the clock is
generated by 8284 and if it is high then external source will be
generate the clock and applied through EFI pin.
• EFI (external frequency IN): When F/C bar Is high then this pin is used
through which the external clock frequency is applied.

• CSYNC: The clock synchronization pin is used whenever the EFI input
provides synchronization in systems with multiple processors. If the
internal crystal oscillator is used, this pin must be ignored.

• RDY 1 and AEN1 bar: These two signals are input signals to 8284.
These signals used together to provide the ready signal to the
microprocessor.

• RDY2 and AEN2’ : These two signals are additional set of ready and
address enable signals and the function of these pins are same as
previous. These bins are used for multi processing system.
• RESET : It is connected to reset signal of 8086 processor.

• OSC: Oscillator is the output signal and its clock frequency is the same
as that of the crystal oscillator.

• PCLK: The peripheral clock signal is one-sixth the crystal or EFI input
frequency, and has a 50-percent duty cycle. The PCLK output provides
a clock signal; to the peripheral equipment in the system

• READY: The output signal is connected to READY signal of the

processor.
Interfacing of Clock generator with 8086
(Power on RESET)
Timing Diagram 8086
Four Machine Cycles:
• Memory Read
• Memory Write
• I/O Read
• I/O write

• A bus cycle = 4T states

Important Signals: Minimum Mode
• AD16-AD19/S3-S6 and BHE’/S7
• AD0-AD15
• ALE
• M/IO’
• DT/R’
• RD’
• WR’
• DEN’
• READY
Minimum Mode (Read Cycle)
• 1) Place address on the address bus whose content has to read.

• Assert a read signal which is the part of control signal

• Wait until the content of address appears on the data bus.

• Transfer the data on the data bus to processor.

• Deactivate the read signal.

Important Signals: Maximum Mode
S0’-S2’

A16-A19, BHE’ & S3-S7

AD0-AD15

ALE

DT/R’

MRDC/IORC [ MWTC/IORC]

DEN
Memory Read Operation