CMOS Analog Integrated Circuits

Data Converters,
Phase-Locked Loops,
and Their Applications
CMOS Analog Integrated Circuits

Data Converters,
Phase-Locked Loops,
and Their Applications

Tertulien Ndjountche
CRC Press
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Contents

Preface xi
New to this edition . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Content overview . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv

1 Mixed-Signal Integrated Systems: Limitations and Chal-

lenges 1
1.1 Integrated circuit design flow . . . . . . . . . . . . . . . . . . 2
1.2 Design technique issues . . . . . . . . . . . . . . . . . . . . . 6
1.3 Integrated system perspectives . . . . . . . . . . . . . . . . . 7
1.4 Built-in self-test structures . . . . . . . . . . . . . . . . . . . 8
1.5 Concluding remarks . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 To probe further . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Data Converter Principles 11

2.1 Binary codes . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 Unipolar codes . . . . . . . . . . . . . . . . . . . . . . 15
2.1.2 Bipolar codes . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.3 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 Data converter characterization . . . . . . . . . . . . . . . . 19
2.2.1 Quantization errors . . . . . . . . . . . . . . . . . . . . 19
2.2.2 Errors related to circuit components . . . . . . . . . . 23
2.2.3 Static errors . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.4 Dynamic errors . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Bibliography 33

3 Nyquist Digital-to-Analog Converters 35

3.1 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . 36
3.1.1 Binary-weighted structure . . . . . . . . . . . . . . . . 38
3.1.2 Thermometer-coded structure . . . . . . . . . . . . . . 38
3.1.3 Segmented architecture . . . . . . . . . . . . . . . . . 38
3.2 Voltage-scaling DACs . . . . . . . . . . . . . . . . . . . . . . 39
3.2.1 Basic resistor-string DAC . . . . . . . . . . . . . . . . 39
3.2.2 Intermeshed resistor-string DAC . . . . . . . . . . . . 45
3.2.3 Two-stage resistor-string DAC . . . . . . . . . . . . . 46

v
vi Contents

3.3 Current-scaling DACs . . . . . . . . . . . . . . . . . . . . . . 49

3.3.1 Binary-weighted resistor DAC . . . . . . . . . . . . . . 49
3.3.2 R-2R ladder DAC . . . . . . . . . . . . . . . . . . . . 50
3.3.3 Switched-current DAC . . . . . . . . . . . . . . . . . . 51
3.3.3.1 Static nonlinearity errors . . . . . . . . . . . 58
3.3.3.2 Current source sizing . . . . . . . . . . . . . 62
3.3.3.3 Switching scheme . . . . . . . . . . . . . . . 63
3.3.4 NRZ and RZ SC DAC . . . . . . . . . . . . . . . . . . 67
3.4 Charge-scaling DAC . . . . . . . . . . . . . . . . . . . . . . . 68
3.5 Hybrid DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.6 Configuring a unipolar DAC for the bipolar conversion . . . 75
3.7 Algorithmic DAC . . . . . . . . . . . . . . . . . . . . . . . . 78
3.8 Direct digital synthesizer . . . . . . . . . . . . . . . . . . . . 79
3.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.10 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 82

Bibliography 89

4 Nyquist Analog-to-Digital Converters 91

4.1 Analog-to-digital converter (ADC) architectures . . . . . . . 92
4.1.1 Successive approximation register ADC . . . . . . . . 92
4.1.2 Integrating ADC . . . . . . . . . . . . . . . . . . . . . 108
4.1.3 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . 115
4.1.4 Averaging ADC . . . . . . . . . . . . . . . . . . . . . . 127
4.1.5 Folding and interpolating ADC . . . . . . . . . . . . . 131
4.1.6 Sub-ranging ADC . . . . . . . . . . . . . . . . . . . . 142
4.1.7 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . 143
4.1.8 Algorithmic ADC . . . . . . . . . . . . . . . . . . . . . 155
4.1.9 Time-interleaved ADC . . . . . . . . . . . . . . . . . . 159
4.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.3 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 164

Bibliography 179

5 Delta-Sigma Data Converters 183

5.1 Delta-sigma analog-to-digital converter . . . . . . . . . . . . 184
5.1.1 Time domain behavior . . . . . . . . . . . . . . . . . . 185
5.1.2 Linear model of a discrete-time modulator . . . . . . . 188
5.1.3 Modulator dynamic range . . . . . . . . . . . . . . . . 189
5.1.4 Continuous-time modulator . . . . . . . . . . . . . . . 194
5.1.5 Lowpass delta-sigma modulator . . . . . . . . . . . . . 197
5.1.5.1 Single-stage modulator with a 1-bit quantizer 197
5.1.5.2 Dithering . . . . . . . . . . . . . . . . . . . . 201
5.1.5.3 Design examples . . . . . . . . . . . . . . . . 202
5.1.5.4 Modulator architectures with a multi-bit
quantizer . . . . . . . . . . . . . . . . . . . . 210
Contents vii

5.1.5.5 Cascaded modulator . . . . . . . . . . . . . . 213

5.1.5.6 Effect of the multi-bit DAC nonlinearity . . . 222
5.1.5.7 Quantization noise-shaping and inter-stage co-
efficient scaling . . . . . . . . . . . . . . . . . 223
5.1.6 Bandpass delta-sigma modulator . . . . . . . . . . . . 224
5.1.6.1 Single-loop bandpass delta-sigma modulator 225
5.1.6.2 Cascaded bandpass delta-sigma modulator . 226
5.1.6.3 Design examples . . . . . . . . . . . . . . . . 227
5.1.7 DT modulator synthesis . . . . . . . . . . . . . . . . . 234
5.1.8 CT modulator synthesis . . . . . . . . . . . . . . . . . 235
5.1.9 Decimation filter . . . . . . . . . . . . . . . . . . . . . 238
5.2 Delta-sigma digital-to-analog converter . . . . . . . . . . . . 258
5.2.1 Interpolation filter . . . . . . . . . . . . . . . . . . . . 258
5.2.2 Digital modulator . . . . . . . . . . . . . . . . . . . . 266
5.3 Nyquist DAC design issues . . . . . . . . . . . . . . . . . . . 270
5.3.1 Vector-feedback DEM . . . . . . . . . . . . . . . . . . 270
5.3.2 Data-weighted averaging technique . . . . . . . . . . . 275
5.3.2.1 Element selection logic based on a tree struc-
ture and butterfly shuffler . . . . . . . . . . . 276
5.3.2.2 Generalized DWA structure . . . . . . . . . . 280
5.4 Data converter testing and characterization . . . . . . . . . . 282
5.4.1 Histogram-based testing . . . . . . . . . . . . . . . . . 282
5.4.2 Spectral analysis method . . . . . . . . . . . . . . . . 285
5.4.3 Walsh transform-based transfer function estimation . 286
5.4.4 Testing using sine-fit algorithms . . . . . . . . . . . . 287
5.5 Delta-sigma modulator-based oscillator . . . . . . . . . . . . 287
5.6 Digital signal processor interfacing with data converters . . . 290
5.6.1 Parallel interfacing . . . . . . . . . . . . . . . . . . . . 293
5.6.2 Serial interfacing . . . . . . . . . . . . . . . . . . . . . 294
5.7 Built-in self-test structures for data converters . . . . . . . . 295
5.8 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 298

Bibliography 319

6 Circuits for Signal Generation and Synchronization 325

6.1 Generation of clock signals with nonoverlapping phases . . . 327
6.2 Phase-locked loop . . . . . . . . . . . . . . . . . . . . . . . . 329
6.2.1 PLL linear model . . . . . . . . . . . . . . . . . . . . . 330
6.2.2 Charge-pump PLL . . . . . . . . . . . . . . . . . . . . 333
6.3 Charge-pump PLL building blocks . . . . . . . . . . . . . . . 334
6.3.1 Phase and frequency detector . . . . . . . . . . . . . . 334
6.3.2 Phase detector . . . . . . . . . . . . . . . . . . . . . . 337
6.3.2.1 Linear phase detector . . . . . . . . . . . . . 338
6.3.2.2 Binary phase detector . . . . . . . . . . . . . 339
6.3.2.3 Half-rate phase detector . . . . . . . . . . . . 340
viii Contents

6.3.3 Charge-pump circuit . . . . . . . . . . . . . . . . . . . 343

6.3.4 Loop filter . . . . . . . . . . . . . . . . . . . . . . . . . 346
6.3.5 Voltage-controlled oscillator . . . . . . . . . . . . . . . 348
6.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
6.4.1 Frequency synthesizer . . . . . . . . . . . . . . . . . . 355
6.4.2 Clock and data recovery . . . . . . . . . . . . . . . . . 366
6.4.2.1 Dual-loop CDR . . . . . . . . . . . . . . . . 372
6.4.2.2 Phase interpolator-based CDR circuit . . . . 374
6.4.2.3 CDR circuit based on a gated VCO . . . . . 377
6.4.2.4 Reference-less dual-loop CDR circuit . . . . 381
6.4.2.5 Reference-less single-loop CDR circuit using a
linear phase detector . . . . . . . . . . . . . . 384
6.5 Delay-locked loop . . . . . . . . . . . . . . . . . . . . . . . . 389
6.6 PLL with a built-in self-test structure . . . . . . . . . . . . . 393
6.6.1 Gain, capture and lock range, and lock time . . . . . . 394
6.6.2 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
6.7 PLL specifications . . . . . . . . . . . . . . . . . . . . . . . . 402
6.8 VCO-based analog-to-digital converter . . . . . . . . . . . . 404
6.9 PLL based on time-to-digital converter . . . . . . . . . . . . 406
6.9.1 Flash TDC . . . . . . . . . . . . . . . . . . . . . . . . 408
6.9.2 Vernier TDC . . . . . . . . . . . . . . . . . . . . . . . 409
6.9.3 Switched ring oscillator TDC . . . . . . . . . . . . . . 410
6.10 High-speed input/output link transceiver . . . . . . . . . . . 413
6.11 Relaxation oscillator . . . . . . . . . . . . . . . . . . . . . . . 425
6.12 Class D amplifier . . . . . . . . . . . . . . . . . . . . . . . . 426
6.13 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
6.14 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 432

Bibliography 447

Appendix A Logic Building Blocks 453

A.1 Boolean algebra . . . . . . . . . . . . . . . . . . . . . . . . . 453
A.1.1 Basic operations . . . . . . . . . . . . . . . . . . . . . 453
A.1.2 Exclusive-OR and equivalence operations . . . . . . . 454
A.2 Combinational logic circuits . . . . . . . . . . . . . . . . . . 454
A.2.1 Basic gates . . . . . . . . . . . . . . . . . . . . . . . . 454
A.2.2 CMOS implementation . . . . . . . . . . . . . . . . . . 457
A.3 Sequential logic circuits . . . . . . . . . . . . . . . . . . . . . 461
A.3.1 Asynchronous SR latch . . . . . . . . . . . . . . . . . 461
A.3.2 Asynchronous S R latch . . . . . . . . . . . . . . . . . 461
A.3.3 D latch . . . . . . . . . . . . . . . . . . . . . . . . . . 462
A.3.4 D flip-flops . . . . . . . . . . . . . . . . . . . . . . . . 462
A.3.5 CMOS implementation . . . . . . . . . . . . . . . . . . 464
A.4 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Contents ix

Appendix B Notes on Circuit Analysis 471

B.1 Radius of curvature . . . . . . . . . . . . . . . . . . . . . . . 471
B.2 Spectral analysis of PWM signals . . . . . . . . . . . . . . . 474
B.3 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Index 481
Preface

The second edition of the book, CMOS Analog Integrated Circuits, is moti-
vated by the scaling-down trend of the complementary metal-oxide semicon-
ductor (CMOS) process used for the fabrication of integrated circuits. The
shrinking of transistors is accompanied by the increase of chip density and
circuit speed, and a reduction of the power supply voltage. However, impor-
tant challenges (leakage currents, variability of technological parameters) for
the analog circuit design can be associated to the deployment of nanometer
CMOS process, especially below 65 nm. Approaches to overcome them rely on
the use of appropriate analog synthesis techniques and computer-aided design
tools at the circuit and physical levels.
The miniaturized silicon technology enabled the advent of various wireless
and wearable devices. The significant impact of the electrical energy con-
sumption on emerging applications has driven the need for low-power design
methodologies. The book describes the important trends of designing high-
speed and power-efficient front-end analog circuits, which can be used alone
or to interface modern digital signal processors and micro-controllers in var-
ious applications such as multimedia, communication, instrumentation, and
control systems.
The book contains resources to allow the reader to design CMOS analog
integrated circuits with improved electrical performance. It offers a complete
understanding of architectural- and transistor-level design issues of analog
integrated circuits. It provides a comprehensive, self-contained, up-to-date,
and in-depth treatment of design techniques, with an emphasis on practical
aspects relevant to integrated circuit implementations.
Starting from an understanding of the basic physical behavior and model-
ing of MOS transistors, we review design techniques for more complex com-
ponents such as amplifiers, comparators, and multipliers. The book details
all aspects from specifications to the final chip related to the development
and implementation process of filters, analog-to-digital converters (ADCs)
and digital-to-analog converters (DACs), phase-locked loops (PLLs) and delay
locked loops (DLLs). It provides the analysis of architectures and performance
limitation issues affecting the circuit operation. The focus is on designing and
verifying analog integrated circuits.
The book is intended to serve as a text for the core courses in analog
integrated circuits and as a valuable guide and reference resource for analog
circuit designers and graduate students in electrical engineering programs. It
provides balanced coverage of both theoretical and practical issues in hierar-

xi
xii Contents

chically organized format. With easy-to-follow mathematical derivations of all

equations and formulas, the book also contains graphical plots, and a number
of open-ended design problems to help determine the most suitable circuit ar-
chitecture satisfying a given set of performance specifications. To appreciate
the material in this book, it is expected that the reader has a rudimentary
understanding of semiconductor physics, electronics, and signal processing.

New to this edition

Every chapter in the second edition has been revised to reflect the evolu-
tion of modern CMOS process technology. Furthermore, the text emphasizes
paradigms that needed to be mastered and covers new materials such as:

1. DAC switching schemes

2. Element mismatch compensation techniques (optimal switching se-
quences, data-weighted averaging) for DACs
3. Generalized design method for continuous-time delta-sigma modu-
lators
4. Review of phase detectors
5. Architectures and circuits for clock and data recovery
6. High-speed input/output link design
7. Phase-locked loop based on time-to-digital converter
8. Relaxation oscillator
9. Class-D power amplifier

Content overview
The book contains six chapters and two appendices.

Chapter 1
Mixed-Signal Integrated Systems: Limitations and Challenges
The use of CMOS technologies with a low device geometry and new archi-
tectures has accelerated the trend toward the system on a chip design, which
merges analog, digital, and radio-frequency (RF) sections on a single inte-
grated structure. While the manufacturing technology appears to be funda-
mentally limited by the material characteristics, the computer-aided design
Contents xiii

tools have to face the computational intractability of design optimizations.

In this context, design techniques should be concerned with the automated
conception, synthesis, and testing of microelectronic systems.

Chapter 2
Data Converter Principles
The interface between real-world signals and digital-signal processors can be
realized by data converters (analog-to-digital converters and digital-to-analog
converters). An insight into the mathematical definitions of characteristics
(quantization noise, component imperfections), which can affect the perfor-
mance of data converters is provided. Depending on the sampling frequency,
Nyquist and oversampling data converters can be distinguished. Generally,
Nyquist converters are based on a parallel operation and can exhibit a high
speed. On the other hand, digital filtering is combined with oversampling,
which relies on using a sampling rate which is several times higher than two
times the signal bandwidth, to improve the converter resolution. For a given
dynamic range, the reduced sensitivity of oversampling structures to compo-
nent imperfections is the result of a trade-off between speed and accuracy.

Chapter 3
Nyquist Digital-to-Analog Converters
Digital-to-analog converters can be designed using various architectures, each
with its distinctive advantages and limitations. A review of various Nyquist
converter architectures illustrates the system-level trade-offs and performance
issues associated with the circuit design. For a given resolution, the difference
between converter architectures can be an important factor for the selection
of a specific application.

Chapter 4
Nyquist Analog-to-Digital Converters
A basic understanding of various ADC architectures is useful to meet the de-
sign challenges at the transistor level of high-resolution converters. There are
various ADC architectures, each with its peculiar advantages and limitations.
The description of Nyquist converters is presented along with their perfor-
mance modeling. Applications are key in selecting a given ADC architecture
even though some overlap can exist between the characteristics of various ar-
chitectures.

Chapter 5
Oversampling Data Converters
Oversampling data converters generally consist of a delta-sigma modulator
and digital (decimation or interpolation) filter. By combining the noise shap-
ing and oversampling, which is similar to the sampling of a signal at a rate
higher than twice the maximum frequency in the input signal, their quantiza-
tion noise is removed from the signal band and spread over a larger range of
xiv Contents

frequencies. Various modulator architectures will be reviewed, the effects of

circuit nonidealities on the converter performance are analyzed, and the digital
filters used to remove the out-of-band noise will be presented. An evaluation
and a comparison of the different delta-sigma modulation-based approaches
used to improve the linearity of Nyquist converters are also provided. Another
application area for delta-sigma modulators is the test and instrumentation
where a precise test signal is required.

Chapter 6
Circuits for Signal Generation and Synchronization
Due to the increase of the IC clock frequency and data rate, circuits (phase-
locked loop, delay-locked loop) for the clock signal generation and synchro-
nization are generally included in electronic systems to avoid data read and
transmission failures. They should be designed to operate with a low voltage,
feature a low timing jitter, and be less sensitive to process and temperature
variations. A tutorial survey of timing circuit and frequency synthesis archi-
tectures is presented. By combining timing and equalization circuits, power
efficient input/output transceivers for high-speed serial links can be designed.
Descriptions of relaxation oscillators, that generate non-sinusoidal signals, and
class-D power amplifiers are provided.

Appendices
Two appendices cover the following topics:
Appendix A: Logic Building Blocks
Appendix B: Notes on Circuit Analysis

Acknowledgments
Many of the changes in this edition were made in response to feedback received
from some readers of the first edition. I would like to thank all those who took
the time to send me messages.
I am grateful for the support of colleagues and students whose remarks
helped refine the content of this book.
I would like to thank Prof. Dr.-Ing. h.c. R. Unbehauen (Erlangen-
Nuremberg University, Germany). His continuing support, the discussions I
had with him, and the comments he made have been very useful.
I express my sincere gratitude for all the support and spontaneous help I
received from Dr. Fa-Long Luo (Element CXI, USA).
I wish to acknowledge the suggestions and comments provided by Prof.
Avebe Zibi (UY-I, CM) and Prof. Emmanuel Tonye (ENSP, CM) during the
early phase of this project.
While doing this work, I received much spontaneous help from some in-
Contents xv

ternational experts: Prof. Ramesh Harjani (University of Minnesota, Min-

neapolis, Minnesota), Prof. Antonio Petraglia (Universidade Federal do Rio
de Janeiro, Brazil), Dr. Schmid Hanspeter (Institute of Microelectronics,
Windisch, Switzerland), Prof. Sanjit K. Mitra (University of California, Santa
Babara, California), and Prof. August Kaelin (Siemens Schweiz AG, Zurich,
Switzerland). I would like to express my thanks to all of them.
I am also indebted to the publisher, Nora Konopka, the project coordi-
nator, Kyra Lindholm, the production editor, Michele Dimont, and the CRC
Press editorial team of the previous edition, Jessica Vakili, Karen Simon, Brit-
tany Gilbert, Stephany Wilken, Christian Munoz, and Shashi Kumar, for their
valuable comments and reviews at various stages of the manuscript prepara-
tion, and their quality production of the book.
Finally, I would like to truly thank all members of my family and friends
for the continual love and support they have given during the writing of this
book.
1
Mixed-Signal Integrated Systems: Limitations
and Challenges

CONTENTS
1.1 Integrated circuit design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Design technique issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Integrated system perspectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Built-in self-test structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 Concluding remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 To probe further . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

The objective of designing a complete system on a single chip has resulted

in the complexity increase of application-specific integrated circuits (ASICs),
application-specific standard parts (ASSPs), and very large-scale integrated
circuits. The system on a chip (SoC), as shown in Figure 1.1, generally pos-
sesses complex signal paths through both analog devices and digital com-
ponents (nonvolatile memory (NVM), random access memory (RAM), and
digital signal processor (DSP)).

Special-function processor
System control
Program NVM General-purpose & functionality
& data (Program) processor
storage
RAM
Processor bus Internal
NVM communication
(Data) Bus interface

Peripheral bus
Interaction with
Communication peripherals other systems

Interaction with Analog Mixed-signal

real world building
blocks Interface

FIGURE 1.1
Example of an SoC floorplan.

Examples include multimedia devices, wireless transceivers, sensor and

actuator controllers, instrumentation systems, and biomedical devices. The
functions, which are realized in the analog domain, include:

1
2 Data Converters, Phase-Locked Loops, and Their Applications

 Biasing
 Sensor and actuator signal conditioning
 Driver and buffer
 Signal down-conversion and up-conversion
 Mixed-signal DSP interfaces
 Clock signal generation and frequency synthesis
They are implemented using basic building blocks such as:
• Voltage and current references
• Low-noise and power amplifiers
• Variable-gain amplifier and automatic gain control circuit
• Filter
• Oscillator
• Mixer
• Sample-and-hold circuit
• Analog-to-digital converter
• Digital-to-analog converter
• Phase-locked loop (PLL) and delay-locked loop (DLL)
• Input/output link transceiver
The SoC digital section essentially requires microprocessors, digital signal pro-
cessors, memories, and control logics. The most important issues are then re-
lated to the integration of analog and digital sections. A fully monolithic chip
appears to be limited, for instance, by the problematic isolation of analog
sections with high-gain bandwidth from the noise generated by the substrate
and digital circuits. Furthermore, the device-level simulation of mixed-signal
integrated circuits in a realistic environment remains a challenge and testing
chips with several complex functions is a difficult task.

1.1 Integrated circuit design flow

The specification partition into subsystems is illustrated in Figure 1.2. Tools
such as SDL (Specification and Description Language), UML (Unified Model-
ing Language), and SystemC AMS are used to analyze the design at the higher
level. At the system level, the design specifications are partitioned into hard-
ware and software components. Note that SystemC AMS is particularly suited
to provide functional modeling, architectural exploration, virtual prototyping,
and integration validation for analog mixed-signal systems.
Mixed-Signal Integrated Systems: Limitations and Challenges 3

Specifications
Conceptual System level: SDL, UML, SystemC AMS

− RTOS
Hardware − User software
− Device driver

Algorithm level: MATLAB,

Behavioral C, C++ (with concurrency), Stateflow
SPW, COSSAP, DSP Station

Analog circuit Digital circuit C, C++

Structural
design design Assembler

IC Mask layout data

Cadence virtuoso (GDSII file)
Physical
IC fabrication

Chip/Board

FIGURE 1.2
Specification partition into subsystems.

MS−HDL Testbench
Circuit
behavioral model Post analysis
internal node response signals
Output response signals and

− Waveform
Test vector Circuit visual check
structural model − Specification
computation
− Fault analysis
Circuit schematic
Input signals

Circuit extracted Test hardware

from layout

FIGURE 1.3
Circuit design verification.

The development of signal processing algorithms can be performed us-

ing MATLAB® , SPW (Signal Processing Workbench), COSSAP (Communi-
cation System Simulation and Application Processor), DSP Station, C, and
C++ (extended to handle concurrency). To help manage the complexity, the
design implementation in hardware is supported by providing a link to hard-
ware synthesis tools.
The functional description is realized by an analog circuit and a digital
4 Data Converters, Phase-Locked Loops, and Their Applications

circuit, which can be designed and verified using various computer-aided de-
sign programs such Cadence, Synopsys, and Mentor Graphics tools. When
the data processing in the digital domain may require processors or micro-
controllers, the design of a real-time operating system (RTOS), application
software and device driver is necessary. Besides allowing a modular and scal-
able programming approach, the desirable features of an RTOS include the
ability to provide basic support for task scheduling, resource management,
inter-task and input-output communication such that the processor function-
ality is available to application software in an optimized and predictable way.
Stateflow is an interactive design and simulation tool that can be used to de-
scribe complex logic, such as an RTOS, in a form that can easily be coded
using C/C++ language or assembler.
The functional description can also be refined to analog and digital mod-
els, which can be analyzed and verified using a simulator that can interpret
mixed-signal hardware description languages (MS-HDLs). Verilog-AMS and
VHDL-AMS are two examples in this category (VHDL stands for very high-
speed integrated-circuit HDL). MS-HDLs are particularly well suited for the
verification of very large and complex mixed-signal integrated circuit designs.
An MS-HDL testbench, as shown in Figure 1.3, provides the stimulus re-
quired to drive various representations of a circuit while the response signals
at nodes of interest are monitored. Specifications are checked by comparing
the behavioral and structural models, while the implementation is verified
by emphasizing the similarities between the circuit schematic and the circuit
extracted from the layout.
The design flow of an integrated system is illustrated in Figure 1.4. The
top-down synthesis process consists of the topology selection, specification
translation or circuit sizing, and design verification (design rule check (DRC),
electrical rule check (ERC), and layout versus schematic (LVS)). It is then
followed by a bottom-up generation and verification of the circuit layout. The
performance specifications are required at each step. Throughout the design
flow, any change should be taken into account by propagating the associated
constraints down the hierarchy, thus ensuring that the top-level block meets
the target specifications.
Nowadays, the methodologies of top-down design and bottom-up verifica-
tion are well-accepted standards in the digital domain. From bit true models of
signal processing algorithms, C, Verilog, or VHDL code is generated or written
for custom hardware or a DSP-based software solution. By defining a digital
circuit at an architectural or behavioral level rather than at the gate level,
hardware description languages, such as Verilog or VHDL, can help manage
more large designs than tools based on schematic entry. An automated design
flow is then adopted to convert the high-level description of the circuit into
industry-standard output formats, such as GDSII, that can be integrated into
chip layout tools.
In the analog domain, the current design approach — design, simulate, op-
timize circuit specifications taking into account parasitic effects and process
Mixed-Signal Integrated Systems: Limitations and Challenges 5
Digital domain

Analog domain Specifications

Specifications RTL description & simulation

Test bench
− Architectural exploration Synthesis

− Schematic entry Scan insertion

− Transistor sizing
Gate−level simulation
Transistor−level simulation

Function No
No
Verification
Function & Verification & Timing
specifications Yes
Yes
Floorplanning
Layout design
Standard cell placement
No
DRC, ERC Verification
& LVS Clock tree generation
Yes

Post−layout simulation Routing

No No
Function Verification Timing Verification

Yes Yes
Layout integration & Verification

GDSII file

FIGURE 1.4
Design flow for an integrated system.

variations, repeat — can be very time consuming for large circuits and relies
mostly on designer experience. This is due to the fact that second-order effects
in analog circuits are difficult to model as the design evolves and automated
tools are actually not available. Furthermore, the use of deep submicrome-
ter CMOS processes contributes to making the verification of analog circuits
substantially more difficult, as self-calibration or error cancelation schemes
are often required to overcome the limitations of the components, thereby in-
creasing the number of operating modes, behavioral complexity, and size of
analog circuits.
The integration of circuit components takes place either during the phys-
ical design phase or after the fabrication. Physical design involves the floor-
planning, timing optimization, placement and routing, or layout. The system
timing and signal integrity verification is achieved by checking the electrical
and design rules and comparing the layout and schematic. Detailed physical
design information is required for accurate resistance, inductance, and capac-
itance parasitic extraction, and delay estimation. Note that the final system
should include both hardware and software. The software platform binds the
programmable cores and memories via the RTOS, the input-output interface
6 Data Converters, Phase-Locked Loops, and Their Applications

via the device drivers, and the network connection via the communication
subsystem.

1.2 Design technique issues

At the system level, an efficient solution is required for managing concurrency
or assuring a real-time data flow. This is important for complex chips, which
handle multiple tasks at the same time and in cases where the latency due
to the interconnect delay dominates the signal bandwidth. The design reuse
results in a reduction of the cost and development time. A higher level of
abstraction is necessary to create a library of subsystems that can be used for
different designs. The design of a complex chip should also include an adequate
strategy for the verification of the functional blocks. The logic simulation is
a suitable method for the functional verification. Here, the system is tested
over a wide variety of operating conditions using simulated input patterns.
However, the complexity of the chip can reduce the effectiveness of finding
possible design errors. This is related to the higher number of likely events
and the difficulty of determining whether the simulated behavior is correct.
SoC testing suffers also from the lack of effective coverage metrics, that is, it
is not always clear whether enough verification has been completed to confirm
the reliability of a chip.
During the design, the circuit optimization is made with respect to timing,
power, and area specifications for given values of interconnect load capaci-
tances which can be different from the ones extracted from the final layout,
specifically in deep submicrometer technologies. In addition, metal resistance
effects are topology dependent and increase with the routing length, and the
prediction of the delay propagation is not simple. That is, one-pass synthesis
success becomes unlikely due to the requirement of physical design informa-
tion. A possible solution can consist of using synthesis methods based on the
delay equalization of all subsystems and the wire planning among blocks. The
speed-power performance of a design based on a submicrometer integrated cir-
cuit (IC) process appears to be affected by the substrate and crosstalk-induced
noises, signal delay, and parasitic inductance. The coupling effects can be con-
trolled using low-swing differential pair structures, shield wires and repeater
insertions, upper and lower bounding slew times, and increased spacing be-
tween wires. The increase in functionalities and operating frequencies results
in more power dissipation. However, in addition to the supply voltage scaling,
power consumption can be reduced by switching off unused subsystems via
gated clocking modes.
It can be predicted that the use of an IC process with low geometries will
increase the impact of fabrication techniques on the design and verification.
The top-down design methodology provides a system-level model that can be
Mixed-Signal Integrated Systems: Limitations and Challenges 7

used for the chip testing. But the mixed-signal nature of SoCs makes different
test strategies suitable for each particular type of component, resulting in the
requirement of a design for test and manufacturability across all abstraction
levels.

1.3 Integrated system perspectives

The realization of integrated systems is influenced by several factors (IC pro-
cess, circuit structure, package, software). Common goals such as performance
optimization and development time reduction must be included in the suitable
design framework.
Mixed-signal building blocks should be designed for reuse. Such a design is
based on accurate high-level models, which can be used to evaluate the block
suitability for a new design. The performance achievable in the hardware de-
sign reuse methodology seems to be limited in situations where the loading
rules are highly complex or the circuit models exhibit interrelated features.
Due to the chip complexity, power and performance can be lost by using a
single clocked-synchronous approach to manage the on-chip concurrency. An
optimal implementation and verification of reliable communication among a
collection of components may then be necessary. The programmable platform-
based design emerges as a viable approach for the SoC implementation, and
the optimal power/performance is dependent on the trade-off between hard-
ware and software. Methodologies for re-mapping and redesigning blocks based
on physical information will be inessential only if the design approaches are
either based on an improved nonideality (delay, noise, distortion) prediction
or able to remove the requirement of predictability.
The performance of high-density ICs is mainly limited by noise and timing
faults. For instance, the simultaneous switching of more devices increases the
power supply noise. This can enlarge the timing delay by reducing the actual
voltage that is applied to a device. The effect of capacitive coupling in submi-
crometer designs is also important and affects the signal integrity. Since the
complexity of SoC makes a unified testing scheme difficult to implement, a
self-test mechanism is required at the component and system levels. It can be
developed based on new fault models with links to the layout and implemented
as a program executed by the processor core. This approach has the benefit of
eliminating any additional built-in self-test (BIST) hardware, such as linear
feedback shift registers. Another important issue in critical applications is re-
lated to self-repair techniques, which take advantage of the reconfigurability
provided by adding coprocessors, appropriate instruction sets, and peripheral
units to the embedded processor core.
To eliminate the need for external testers, the implementation of BIST for
analog blocks should preferably exploit the capability of the digital processor
8 Data Converters, Phase-Locked Loops, and Their Applications

for the signal generation and analysis and down-sampling techniques for the
specific case of RF circuits.

1.4 Built-in self-test structures

With the increase in the density and complexity of mixed-signal integrated

circuits (ICs), more complex measuring devices are required to meet ever more
severe test specifications. The built-in self-test (BIST) appears as a suitable
approach to resolve the problem related to the fact that mixed-signal circuits
are verified by functionality, the number of which can be high in a single chip.
Furthermore, a BIST section can facilitate the initialization and observation
of the circuit nodes. BIST structures for digital circuits have reached a good
level of maturity, and it can be expected that testing solutions for the analog
section in mixed-signal systems will exploit the computation capability of logic
gates and digital signal processors.

Input Output
Circuit
under test

Test Test
Test data
pattern response
output
generator analyzer
Control
signals

Control circuit

FIGURE 1.5
A chip including a built-in self-test structure.

The architecture of a chip including a BIST section is shown in Figure 1.5.

It consists of a test pattern generator, a test response analyzer, and a control
circuit, in addition to the circuit under test, which can be reconfigured by
the control signals to support the test mode and the normal operation mode.
Depending on the BIST flexibility, testing can be carried out while the circuit
is in an idle state or during normal operation. A generator is used to provide
the required test input signals and the analyzer features the capability of
detecting various faults in the output response of the circuit under test.
Mixed-Signal Integrated Systems: Limitations and Challenges 9

1.5 Concluding remarks

The use of a submicrometer process for the IC implementation extends the
operating frequency range, but also results in the enhancement of nonideal
effects related to the interconnect crosstalk and latency. The density of test
data is growing as the complexity and the number of intellectual property
cores required in a single chip is increasing. Thus, the viable development
of SoCs should take into account aspects of the design, manufacturing, and
testing at all abstraction levels.

1.6 To probe further

• Special issue on limits of semiconductor technology, Proc. of the IEEE,
vol. 89, no. 3, March 2001.
• W. Müller, W. Rosenstiel, and J. Ruf, Eds., SystemC Methodologies and
Applications, Dordrecht, The Netherlands: Kluwer Academic Publishers,
2003.
• D. Jansen et al., Eds., The Electronic Design Automation Handbook, Dor-
drecht, The Netherlands: Kluwer Academic Publishers, 2003.
• M. D. Birnbaum, Electronic Design Automation, Upper Saddle River, NJ:
Prentice Hall, 2004.
• Special issue on system on chip: Design and integration, Proc. of the IEEE,
vol. 94, no. 6, June 2006.
• Special issue on leading-edge computer-aided design solutions for advanced
digital and mixed-signal systems-on-chips, Proc. of the IEEE, vol. 59, no.
3, March 2007.
2
Data Converter Principles

CONTENTS
2.1 Binary codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 Unipolar codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.2 Bipolar codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.3 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 Data converter characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1 Quantization errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 Errors related to circuit components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.3 Static errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.4 Dynamic errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Data converters, or specifically analog-to-digital converters (ADCs) and

digital-to-analog converters (DACs), play an important role in the design of
data acquisition units in communication and microprocessor-based instrumen-
tation systems. They include analog and digital building blocks and form the
main interface component in mixed-signal processing systems (for some typical
applications, see Table 2.1).

TABLE 2.1
Data Converter Specifications for Some Applications

Applications Resolution (bits) Sampling Frequency

Audio device 14–24 < 200 kHz
Digital oscilloscope 8 150 MHz
Magnetic read channel equalizer 6–8 (50–200) MHz
Wireless local area network 6–10 (1–50) MHz
Digital video camera 8–12 20 MHz
TV baseband processor 8–10 20 MHz
Modem 8–10 (10–20) MHz

• The process of converting an analog signal into a digital sequence, as illus-

trated in Figure 2.1, involves three operations: sampling, quantization, and
coding. After the filtering operation, a sample-and-hold circuit first picks up
the signal representative, which is maintained constant for the duration re-

11
12 Data Converters, Phase-Locked Loops, and Their Applications

Anti−alias Sample & hold Analog−to−digital

In Out
filter circuit converter

FIGURE 2.1
Typical ADC system.

quired by the converter to provide a digital word. Note that a continuous-time

signal with the maximum frequency, fm , can adequately be represented by its
samples acquired at the rate fs ≥ fN = 2fm , where fN is termed the Nyquist
rate or frequency. To maintain the frequency content of the input signal within
the Nyquist bandwidth, an analog lowpass filter, also known as an anti-aliasing
filter, is placed before the sample-and-hold circuit. Ideally, this filter should
attenuate signal components with a frequency above fs /2. The sampled signal
is then transformed into one of a finite set of prescribed values by a quantizer,
the levels of which can be uniformly or nonuniformly spaced. The transfer
characteristic and error, e, of a uniform quantizer, whose implementation is
the simplest of both, is shown in Figure 2.2. The error caused by the quanti-

Two’s−complement ^x
code

011 3∆

010 2∆

001
−9∆ −7∆ −5∆ −3∆ −∆
2 2 2 2 2
000
∆ 3∆ 5∆ 7∆
x
2 2 2 2
111

110 −2∆

101 −3∆

100 −4∆
(a)
FSR
−FS +FS
eQ

∆/2
x
−∆/2
−9∆ −7∆ −5∆ −3∆ −∆ ∆ 3∆ 5∆ 7∆
(b) 2 2 2 2 2 2 2 2 2

FIGURE 2.2
(a) Transfer characteristic and (b) quantization error of a 3-bit ADC.

zation is defined as the difference between the discrete output level and the
Data Converter Principles 13

actual analog input, eQ = x̂ − x. It is in the range ±∆/2 as long as the quan-

tizer does not saturate. The transfer characteristic of Figure 2.2 belongs to a
quantizer of the mid-tread type because it follows the input axis about zero.
As a result, the output is insensitive to small input variation in the absence
of signal in contrast to the mid-riser characteristic, which is supported by the
output axis about zero. The coding then consists of assigning a unique binary
number to each quantization level. Assuming that the number of bits, N , is 3,
the 2N quantization levels can be coded in an N -bit number representation.
The step size of the converter, ∆, represents the least significant bit (LSB) of
the digital number and is given by ∆ = F SR/2N , where F SR is the quantizer
range or full-scale range (FSR). By using the two’s complement code, the sign
of the input sample is determined by the most significant bit (MSB). A real
number, X, which can be represented as
b1 b2 b3 · · · bN (2.1)
corresponds to the value
−b1 20 + b2 2−1 + b3 2−2 + · · · + bN 2−(N −1) (2.2)
where b1 is the MSB. Other codes can also be used depending on signal char-
acteristics and the desired application; however, the two’s complement repre-
sentation is a convenient way of representing signed numbers and the most
suitable for addition and subtraction operations.

Digital−to−analog Sample & hold Smoothing

In Out
converter circuit filter

FIGURE 2.3
Typical DAC system.

• A digital-to-analog conversion stage, as shown in Figure 2.3, generally con-

tains a DAC, a sample-and-hold (S/H) circuit, and a lowpass filter (LPF).
The DAC is used to transform a finite number of digital codes into the cor-
responding analog discrete-time signal. Its transfer characteristic is shown in
Figure 2.4 for a bipolar input code. In contrast to the ADC, which exhibits a
quantization error due to the fact that any voltage within a given step size is
mapped to the same output code, the DAC uniquely assigns each input code
to an output level without an inherent error. Therefore, DACs do not directly
realize the inverse function of ADCs.
In general, the DAC output signal, X0 , can ideally be put in the form
!
D
X0 = G · XREF K1 N + K2 (2.3)
2

where G is the gain, XREF is the reference signal, D is the decimal equivalent
14 Data Converters, Phase-Locked Loops, and Their Applications

^
x

3∆

2∆

∆
100 101 110 111 0 Digital
x input code
001 010 011
−∆

−2∆

−3∆

−4∆

FIGURE 2.4
Transfer characteristic of a 3-bit DAC.

of the binary input code, and K1 and K2 are the gain and offset constants,
respectively. In the case of unipolar conversion, K1 = 1 and K2 = 0, and the
output range is from 0 to G · XREF . For bipolar DACs based on the offset
binary input coding, the constants are chosen as K1 = 2 and K2 = −1 to
produce an output swing between −G · XREF and G · XREF . Note that the
two’s complement representation is converted into offset binary code only by
inverting the MSB.
The digital-to-analog conversion process should be realized with the high-
est fidelity and minimal lag in time. The S/H introduces a delay in the output
of the DAC to allow the current sample at the DAC output to reach the steady
state. An LPF, often referred to as a smoothing (or reconstruction) filter, is
used to remove the frequency components above fs /2 from the converter out-
put. It also smooths the signal provided by the S/H by removing all sharp
discontinuities.
Various architectures are known for the implementation of data convert-
ers. They can be divided into two main groups: Nyquist and oversampling
converters. Nyquist converters operate at a sampling rate close to the Nyquist
frequency or slightly higher than twice the bandwidth of the input signal;
therefore their output data rate can be very high. On the other hand, the op-
eration of oversampling converters, which can achieve a higher resolution even
with low-precision components, requires a sampling rate that is several times
higher than the Nyquist frequency. By relying on the averaging of multiple
samples performed by a digital filter for each conversion, oversampling con-
verters feature a longer acquisition time than the one of Nyquist converters,
which process each input sample independently.
Data Converter Principles 15

2.1 Binary codes

One feature of data converters such as DAC and ADC is that either the input
or output is in digital form and can be represented using binary codes.
Digital systems generally use a binary number coding rather than the most
familiar decimal number representation. For binary codes, the base or radix is
2 and the digits are called bits and take the values 0 or 1. Positive integers with
the value in the range 0 to 2N − 1 can be encoded using N bits. Starting with
the LSB, which has a weight of 20 or equivalently, 1, the weight is increased
by a factor of 2 from one bit to the next and up to the value of the MSB
weight, 2N −1 . The binary representation is said to be positional because the
location of a bit in the resulting sequence determines its weight. The value of
a binary number corresponds to the sum of the weights of all nonzero bits.
In practice, the operating range of a data converter is bounded by the full
scale (FS). Scaling down the full-scale range requires representing all of the
numbers as fractions [1]. Any binary integer can be set into a fractional format
by dividing its value by 2N . With the binary point assumed to be at the left of
the MSB, it is possible to encode the numbers in the range from 0 to 1 − 2−N
of the converter full-scale. The bit weight, which is inversely proportional to
a power of 2, varies from 1/2 for the MSB down to 1/2N for the LSB.

2.1.1 Unipolar codes

Unipolar codes are used to represent signals with a predetermined sign. The
most common unipolar codes, as shown in Table 2.2 for 4-bit converters, are
natural binary, Gray, and binary-coded decimal (BCD) representations.
The natural binary representation is a positional system of numeration that
uses the digits 0 and 1 and a radix of 2. Each successive digit of the binary
code, which is generally adopted for a data converter, represents an inverse
power of 2. The all-zero code corresponds to the zero-scale signal, while the
all-one code is associated to the signal value, which is one LSB below the full
scale.
Gray codes are used in the design of encoders for data converters in order
to prevent errors due to the fact that all the required bit transitions between
any two neighboring numbers may not occur at the same time. In general, the
Gray code can be obtained by rearranging a binary sequence such that there is
only one bit change between two adjacent numbers. The possibility to obtain
multiple Gray code representations for a given number then increases with the
resolution. The 4-bit example shown in Table 2.2 is known as binary-reflected
Gray codes. From an initial binary sequence where all bits are set to zero,
consecutive binary-reflected Gray codes are formed by changing the state of
only one bit while starting from the rightmost bit side. Let bk and gk be the
bits of the natural binary code and Gray code, respectively. The conversion
16 Data Converters, Phase-Locked Loops, and Their Applications

TABLE 2.2
Common Unipolar Codes for 4-Bit Converters

Decimal Fraction Natural Gray 8421

Number of the FS Binary Code BCD
15 15/16 1111 1000 1001 0011
14 14/16 1110 1001 1000 0111
13 13/16 1101 1011 1000 0101
12 12/16 1100 1010 0111 0010
11 11/16 1011 1110 0110 1000
10 10/16 1010 1111 0110 0010
9 9/16 1001 1101 0101 0110
8 8/16 1000 1100 0101 0000
7 7/16 0111 0100 0100 0011
6 6/16 0110 0101 0011 0111
5 5/16 0101 0111 0011 0001
4 4/16 0100 0110 0010 0101
3 3/16 0011 0010 0001 1000
2 2/16 0010 0011 0001 0010
1 1/16 0001 0001 0000 0110
0 0 0000 0000 0000 0000

from the binary to Gray code is based on the next algorithm:

gN = bN (2.4)
gk = bk+1 ⊕ bk for k =N −1 down to 1 (2.5)

while the Gray-to-binary conversion is obtained as follows:

bN = gN (2.6)
bk = bk+1 ⊕ gk for k =N −1 down to 1 (2.7)

where ⊕ denotes the exclusive or (XOR) logic operation and N is the number
of bits of the code.
In the BCD code, each decimal digit, Dk , with a value of 0 through 9
is replaced by its 4-bit binary equivalent, bk,j , where j = 1, 2, 3, 4. Table 2.2
shows 8421 BCD codes of the first two fractional digits of FS fractions. The
designation 8421 indicates the binary weights of the four bits representing each
digit. Note that different versions of BCD codes can be obtained using other
weight combinations. A further digit can be appended to a BCD code just by
adding another 4-bit sequence. One advantage of BCD over binary representa-
tions is that the range of numbers that can be represented is not limited. The
BCD code is particularly useful for interfacing to printing or display devices,
which can process individual decimal digits (e.g., digital multimeter, digital
Data Converter Principles 17

instruments for physical measurements). On the other hand, the natural bi-
nary code for a given number requires fewer bits than the corresponding BCD
code. The BCD representation is a relatively inefficient coding due to the fact
that only 10 of the 24 or 16 combinations allowed by any 4-bit sequence are
exploited.
Note that additional bit combinations are sometimes used in the BCD code
in order to take into account the data sign or other meaningful indications.

2.1.2 Bipolar codes

TABLE 2.3
Common Bipolar Codes for 4-Bit Converters

Decimal Fraction Sign One’s Offset Two’s

Number of the FS Magnitude Complement Binary Complement
7 7/8 0111 0111 1111 0111
6 6/8 0110 0110 1110 0110
5 5/8 0101 0101 1101 0101
4 4/8 0100 0100 1100 0100
3 3/8 0011 0011 1011 0011
2 2/8 0010 0010 1010 0010
1 1/8 0001 0001 1001 0001
0 0 0000 0000 1000 0000
1000 1111
−1 −1/8 1001 1110 0111 1111
−2 −2/8 1010 1101 0110 1110
−3 −3/8 1011 1100 0101 1101
−4 −4/8 1100 1011 0100 1100
−5 −5/8 1101 1010 0011 1011
−6 −6/8 1110 1001 0010 1010
−7 −7/8 1111 1000 0001 1001
−8 −8/8 — — 0000 1000

Bipolar codes are used to represent signals that can be either positive or
negative. The most common bipolar codes, which are sign magnitude, one’s
complement, offset binary, and two’s complement representations, are shown
in Table 2.3 for a resolution of 4 bits.
In the sign-magnitude representation, the bit in the MSB position is re-
served for the number sign and the remaining bits indicate the number mag-
nitude. The sign bit can be either 0 for positive numbers or 1 for negative
numbers. The sign-magnitude representation has the drawback of having two
different codes for zero and requiring a rather complex hardware for the real-
ization of arithmetic operations.
18 Data Converters, Phase-Locked Loops, and Their Applications

The one’s complement representation is formed by inverting each bit of the

natural binary code for the number to be converted. It can also be obtained by
subtracting each bit of the natural binary code from one. The bit in the MSB
position can be set either to 0 for positive numbers, or 1 for negative numbers.
Even if the one’s complement representation can help reduce the algorithm
complexity for some arithmetic operations, it still leads to ambiguity because
there are two different codes for zero.

The offset binary coding is a binary representation that is shifted so that a

signal with the zero value corresponds to the mid-scale code, that is, the code
consisting of a one at the MSB position followed by zeros at all the remaining
bit positions. The all-zero code is then used for the negative full scale and the
all-one code is assigned to the signal value that is one LSB below the positive
full scale.

In the two’s complement representation, zero and positive signal values

have the same code as in the natural binary format while the negative signal
values are represented by forming the two’s complement of the corresponding
positive number. The two’s complement is formed by complementing each bit
of the binary code and then adding one LSB without taking into account
any carry-out. The MSB is either 0 for positive numbers, or 1 in the case of
negative numbers. The two’s-complement representation is an efficient coding
approach for bipolar signal values in microprocessors because it allows the use
of only an adder to implement both the addition and subtraction. Note that
the conversion from the offset binary format to two’s complement code only
requires the inversion of the MSB logic state.

2.1.3 Remarks

The choice of a number representation system has repercussions on the com-

plexity of algorithm implementations for arithmetic operations and the in-
put or output interface of the data converter with other circuits. The two’s
complement representation is used in most digital systems, and hence is com-
monly considered for data converter implementations. Sign-magnitude and
BCD codes are mainly used for instrumentation applications.

Number expressions and dynamic ranges in common binary representa-

tions are summarized in Table 2.4, where X0 denotes the encoded signal value
and XF S designates the data converter full-scale. Note that the variable X
can stand for a voltage or current signal.

In some data converter configurations, it is required to use the aforemen-

tioned codes with all bits inverted, also known as complementary codes. In
differential structures, the required inversion is carried out simply by permut-
ing the input or output nodes.
Data Converter Principles 19

TABLE 2.4
Number Expressions and Dynamic Range in Common Binary Representations

Representation Range
Natural binary
X N
X0 X0
= bk 2−k 0≤ ≤ 1 − 2−N
XF S XF S
k=1
8421 BCD
N
X
X0
= Dk 10−k
XF S X0
k=1
4
X 0≤ ≤ 1 − 10−N
XF S
where Dk = bk,j 2−j+1
j=1
Offset binary
N
X
X0 X0
= −1 + bk 2−k+1 −1 ≤ ≤ 1 − 2−N +1
XF S XF S
k=1
Sign-magnitude
N
X
X0 X0
= (−1)b1 bk 2−k+1 2−N +1 − 1 ≤ ≤ 1 − 2−N +1
XF S XF S
k=2
One’s complement
N
X
X0
X0
= 2−N +1 − 1 b1 + bk 2−k+1 2−N +1 − 1 ≤ ≤ 1 − 2−N +1
XF S XF S
k=2

Two’s complement
N
X
X0 X0
= −b1 + bk 2−k+1 −1 ≤ ≤ 1 − 2−N +1
XF S XF S
k=2

2.2 Data converter characterization

In addition to the errors introduced by the quantization process [2], the per-
formance of data converters can be affected by device nonlinearities.

2.2.1 Quantization errors

Let x and x̂ be the input and output samples of the quantizer, respectively.
According to the rounding quantizer model depicted in Figure 2.5, the quan-
20 Data Converters, Phase-Locked Loops, and Their Applications

tization error is defined as

eQ (k) = x̂(k) − x(k) (2.8)

x̂(k) = Q(x(k)) (2.9)

where Q denotes the quantizer operation. Its value should not exceed half of
the quantization level,
∆ ∆
− < eQ (n) ≤ (2.10)
2 2
where ∆ is the quantizer step size. However, for input signals with a high
dynamic range, the samples that go over the quantizer limit are clipped and
eQ can be greater than ∆/2. Note that, for the rounding quantizer, the signal
values that are below an integer multiple of ∆ located between two adjacent
transitions are quantized to the lower level; otherwise they should be mapped
to a higher level.
The converter performance can be described by the signal-to-noise ratio
(SNR) given by  
Px
SNR = 10 log10 in dB, (2.11)
PQ
where Px = σx2 = E[x2 (k)] is the input signal power or variance, and PQ =
2
σQ = E[e2Q (k)] is the variance or power of the quantization noise.

The SNR can also be expressed in terms of root-mean square (rms)

amplitudes. By exploiting the fact that the average power is proportional
to the square of the signal rms amplitude, we can write that
!  
A2x Ax
SNR = 10 log10 = 20 log10 in dB, (2.12)
A2Q AQ

where A is the rms amplitude. The logarithmic decibel scale helps de-
scribe signal-level ratios, that span many orders of magnitude, with num-
bers of modest size without losing information.

eQ p(e Q )
^ 1/∆
x x
x x^
eQ
−∆/2 0 ∆/2
(a) (b) (c)

FIGURE 2.5
(a) Quantizer; (b) linear quantizer model; (c) probability density function of
the quantization error.
Data Converter Principles 21

It is convenient to deal with an input signal, x, that is zero mean, sta-

tionary, and uncorrelated with eQ . Furthermore, by assuming that eQ is a
uniformly distributed white noise sequence over the interval −∆/2 to ∆/2,
the probability function p (see Figure 2.5(c)) is given by

1 ∆
for |eQ | ≤
p(eQ ) = ∆ 2 (2.13)

0 otherwise.

The power of the quantization noise can be obtained as

Z ∆/2 Z ∆/2
2 1 ∆2
PQ = σQ = e2Q p(eQ )deQ = e2Q deQ = (2.14)
−∆/2 ∆ −∆/2 12

where ∆ is the quantizer step size.

Compute the power of the discrete-time sinusoidal signal given

by
x(k) = A sin(ωk) (2.15)
where ω = 2π(f /fs ), f is the frequency of the sinusoid, fs rep-
resents the sampling frequency, and A is the amplitude.
The power is defined as
N −1
1 X 2
Px = σx2 = E[x2 (k)] = x (k) (2.16)
N
k=0

With the substitution of x(k) and using the fact that the cosine
has a zero mean, we obtain

A2 NX
−1
A2 NX
−1
1 A2
Px = sin2 (ωk) = [1 − cos(2ωk)] = (2.17)
N N 2 2
k=0 k=0

The power is proportional to the square of the sinusoidal signal

amplitude.

Assuming a sinusoidal input signal with an amplitude equal to half of the

quantizer full-scale range, the power can be written as

(F SR/2)2
Px = (2.18)
2
where F SR denotes the full-scale range. With the full-scale range of the N -bit
22 Data Converters, Phase-Locked Loops, and Their Applications

quantizer given by F SR = 2N ∆, the SNR can take the next form

!
3 2N
SNR = 10 log10 2
2
= 6.02N + 1.76 (dB). (2.19)
The SNR increases by about 6 dB for each additional bit of the quantizer.
However, practical implementations rarely achieve the theoretical SNR due to
various imperfections associated to circuit components.
An approach to improve the SNR can consist of using the oversampling
technique, which distributes the power of the quantization noise over a wider
frequency band. A digital filter is then required to reduce the quantization
noise to a great extent without affecting the signal of interest, thereby in-
creasing the number of bits.
By increasing the value of the sampling rate, the initial power of the quan-
tization noise, which remains unchanged, can be expressed as a function of
the quantization noise spectral density, EQ . Hence,
Z fs /2 Z fs /2
2 2
PQ = |EQ (f )| df = |EQ (f )| df = |EQ (f )|2 fs (2.20)
−fs /2 −fs /2

Consequently, we have
∆2 1
|EQ (f )|2 = (2.21)
12 fs
The quantized signal is then processed by an ideal lowpass filter with the
frequency response (
1 |f | ≤ fB
H(f ) = (2.22)
0 otherwise,
where fB represents the cutoff frequency. The resulting quantization noise
power is now due to the spectral contributions of EQ , which are confined
between −fB and fB . That is,
Z fs /2 Z fB
PQ′ = [EQ (f )H(f )]2 df = [EQ (f )]2 df
−fs /2 −fB

∆2 2fB ∆2 1
= = (2.23)
12 fs 12 OSR
where OSR = fs /2fB is the oversampling ratio. Recalling the signal-to-noise
ratio definition, we have
! !
Px 3 2N
SNR’ = 10 log10 = 10 log10 2 + 10 log10 (OSR) (2.24)
PQ′ 2

Thus
SNR’ = 6.02N + 1.76 + 10 log10 (OSR) (dB). (2.25)
Data Converter Principles 23

It should be emphasized that for every doubling of the OSR, the signal-to-
noise ratio is increased by 3 dB or equivalently 0.5 bit of resolution. With the
oversampling technique, the sampling frequency must be multiplied by a factor
of 22N to yield an increase of N bits. It should be noted that oversampling has
the advantage of relaxing the requirements of the anti-aliasing or smoothing
analog filter.

P P P Input
Quantization signal
Input Input
signal signal noise In−band
noise
In−band Quantization In−band Quantization
noise noise noise noise

f f f
− fs /2 − fB fB fs /2 −OSR fs /2 − fB fB OSR fs /2 −OSR fs /2 − fB fB OSR fs /2

(a) (b) (c)

FIGURE 2.6
Power spectrum of the quantization noise: (a) Nyquist ADC, (b) oversampling
ADC, (c) delta-sigma ADC.

An efficient architecture used to improve the resolution without requiring

an excessive high oversampling is the delta-sigma ADC [3], which modulates
the quantization noise so that its magnitude is attenuated in the signal band
and increased for out-of-band frequencies. The quantization noise outside the
signal bandwidth is reduced using a digital filter, which can also adjust the
rate of the output data, if necessary. The delta-sigma converter can achieve a
resolution up to 24 bits without the need for high-precision components. For its
implementation, the choice of an architecture depends on the characteristics
required for the quantization noise shaping.
The frequency spectrum of the digitized signal, which includes the contri-
butions of the input signal and the quantization noise, is shown in Figure 2.6
for Nyquist, oversampling, and delta-sigma ADCs. Due to the oversampling,
the quantization noise inherent in the conversion process is spread over a large
band of frequencies, including the signal bandwidth. For delta-sigma convert-
ers, only a small fraction of the quantization noise falls in the frequency range
of interest.

2.2.2 Errors related to circuit components

In addition to the quantization errors, the overall noise available at the con-
verter output is related to the component noise and the nonuniform allocation
of the sampling instants or clock jitter. In the particular case of ADCs, the
contribution due to the comparator ambiguity should also be taken into ac-
count. Furthermore, the dynamic performance of data converters is limited by
the frequency characteristics of passive and active components.
24 Data Converters, Phase-Locked Loops, and Their Applications

• The noise caused by the different components of a converter can be an-

alyzed using equivalent models. It is dominated by the thermal and flicker
noise contributions.

• For the jitter analysis, let us consider an input sinusoid

x(t) = A sin(2πf t + φ) (2.26)

where A is the amplitude, and f and φ are the frequency and phase of the
signal, respectively. Ideally, the sampling instants should be given by

tk = kT, k = 0, 1, 2, · · · , K − 1. (2.27)

However, they are affected by errors, δk , due to the clock jitter and can be
written as
tk = kT + δk (2.28)
The samples of the input signal can be obtained using

x̄(k) = A sin(Ωk + Jk + φ) (2.29)

where the digital angular frequency, Ω, and the phase jitter, Jk , are given by
Ω = 2πf T and Jk = 2πf δk , respectively. The error due to the jitter can be
computed as
eJ (k) = x̄(k) − x(k) (2.30)
where x(k) is the uniformly sampled version of the input signal, especially,
x(k) = A sin(Ωk + φ). The SNR contribution of the jitter is
!
σx2
SNR = 10 log10 2 in dB, (2.31)
σQ

where σx2 = E[x2 (k)] is the input signal variance and σQ2
= E[e2J (k)] is the jit-
2
ter noise variance. The value of σQ is dependent on the jitter statistical model
and ADCs generally exhibit a clock jitter in the range of 0.5 to 2 ps. In prac-
tice, high-precision oscillators are used in conjunction with phase-locked loop
or delay-locked loop circuits to minimize the effects of clock and timing errors.

• Input signals around the decision level of the comparator, which often
consists of an amplifier stage followed by a latch, may result in ambiguous
output codes. Let vQ and vQ be the voltages related to the positive and
negative outputs of the comparator. The difference , vd = vQ − vQ , can be
obtained by solving a differential equation of the form

dvd (t) 1
− vd (t) = 0 (2.32)
dt τ
Data Converter Principles 25

where the time constant, τ , characterizes the latch ability to resolve interme-
diate voltage levels and depends on the loading conditions, transistor param-
eters, and the IC process. That is,

vd (t) = vd (0) exp(t/τ ) (2.33)

with vd (0) being the initial condition at the beginning of the metastable region.
Ideally, the latch requires an extra time, T , to generate a valid output, which
can be processed by the next circuit section. This requires that vd reaches a
given value, say VF S /2, within the time period, T . Otherwise, an inaccurate
decision will be made if vd (T ) < VF S /2. Taking into account the fact that vd
is equal to the amplifier output at t = 0, we have

vd (0) = A(|vi (0) − Vth |) = A∆vi (0) (2.34)

where vi is the input voltage, and Vth and A denote the threshold level and
gain of the comparator, respectively. Hence, the failure condition reads

VF S
∆vi (0) < exp(−T /τ ) = ∆Vi (2.35)
2A

Assuming uniformly distributed input sample over the comparator range, the
probability, Pe , to produce an uncertain output voltage is given by

2∆Vi
Pe = P [∆vi (0) < ∆Vi ] = (2.36)
VL

where VL is the effective LSB voltage. The error likelihood Pe can be consid-
ered an additive contribution to the quantization noise, that is,

2 ∆2
σQ = (1 + Pe ) (2.37)
12

Note that Pe should include the contribution of all comparators used in the
ADC.

Data converters are limited by various error sources. Static errors affect the
accuracy of converters during the conversion of dc signals, whereas dynamic
errors essentially degrade the high-speed performance. Offset, gain, differen-
tial nonlinearity, and integral nonlinearity errors are generally associated with
static performance of data converters. Their impact on the signal level can
also be characterized in the frequency domain by estimating dynamic char-
acteristics such as the signal-to-noise ratio, total harmonic distortion, and
spurious-free dynamic range. On the other hand, dynamic errors can also be
related to the limitations (acquisition time, settling time, glitches) of the tran-
sient response.
26 Data Converters, Phase-Locked Loops, and Their Applications

111 111
Ideal
110 110

Digital output code

Digital output code
Ideal
101 Offset 101
error Gain
100 100 error
011 011
010 010
001 001
000 000
0 1/4 1/2 3/4 1 0 1/4 1/2 3/4 1
Analog input (FS) Analog input (FS)

FIGURE 2.7 FIGURE 2.8

ADC offset error. ADC gain error.

111 111 Code 101

110 Ideal 110 missing
Digital output code
Digital output code

101 −DNL 101 INL

100 100 Ideal
011 DNL 011
010 010
001 001
000 000
0 1/4 1/2 3/4 1 0 1/4 1/2 3/4 1
Analog input (FS) Analog input (FS)

FIGURE 2.9 FIGURE 2.10

ADC differential nonlinearity. ADC integral nonlinearity.

2.2.3 Static errors

The converter can be affected by the following static errors [2, 4] (see Fig-
ures. 2.7 through 2.14) when it transforms a signal. These errors are most
commonly expressed in LSB units, or as a percentage of the converter FSR.

• Offset error — The offset error corresponds to the converter output devia-
tion obtained by applying an input signal with a zero-scale to the converter.
It can be either positive or negative, and affects all the output data in the
same way (see Figures 2.7 and 2.11).

• Gain error — The gain of the transfer characteristic is given by the slope of
the straight line joining the two endpoints. The gain error results in a slope
Data Converter Principles 27

1 1

Ideal

Analog output (FS)

3/4
Analog output (FS)
3/4
Offset Ideal
error
1/2 1/2 Gain
error
1/4 1/4

0 0

000
001
010
011
100
101
110
111
000
001
010
011
100
101
110

Digital input code 111 Digital input code

FIGURE 2.11 FIGURE 2.12

DAC offset error. DAC gain error.

1 1
Ideal
Analog output (FS)

Analog output (FS)

3/4 Ideal 3/4

1/2 1/2 INL

DNL

1/4 1/4

0 0
000
001
010
011
100
101
110
111

000
001
010
011
100
101
110
111

Digital input code Digital input code

FIGURE 2.13 FIGURE 2.14

DAC differential nonlinearity. DAC integral nonlinearity.

difference between the ideal and real converters. All the codes exhibit the
same percentage of deviation.

• Differential nonlinearity (DNL) error — The DNL is the deviation of either

the step width for the ADC (see Figure 2.15) or the step height for the DAC
from the ideal value of 1 LSB. In the specific case of a data converter, where
a quantization step size can be associated with each code k, it is defined as

△k
DNLk = −1 (2.38)
VLSB
where △k represents the actual quantization step size for the code k and
28 Data Converters, Phase-Locked Loops, and Their Applications

VLSB is the ideal quantization step size. Generally, the highest value of
|DNLk | is considered the DNL of the data converter. The missing code is the
result of a DNL equal to or less than −1 LSB. In this case, the corresponding
step does not appear in the transfer characteristic. It is possible that the
converter becomes nonmonotonic for DNL values greater than 1 LSB. The
magnitude of the converter output diminishes as the input data increases.

Transfer characteristic
VLSB
Output code
∆k
DNL k = 1
VLSB
∆k
∆ k Actual step width
VLSB Ideal step width

Vk V k+1

Input voltage

FIGURE 2.15
Illustration of the DNL error.

• Integral nonlinearity (INL) error — The INL denotes the deviation at any
point of the transfer characteristic of output data from a reference straight
line drawn through the zero and full scale. Its value can depend on the defi-
nition of the two endpoints. Assuming that the computation of quantization
levels is possible, we can obtain

Vk − V0
INLk = −k (2.39)
VLSB
where Vk is threshold level associated with the code k, V0 is the threshold
level corresponding to the lowest transition code, and VLSB is the ideal
quantization step size. It can also be shown that
k
X
INLk = DN Lj (2.40)
j=0

where the first output code index is supposed to be zero.

Linearity errors are more important than the ones due to offset and gain
deviations, which can be adjusted using a suitable calibration technique.

2.2.4 Dynamic errors

In addition to static errors, the converter performance is also affected by er-
rors whose root is related to the time-varying nature of the input signals. The
signal-to-noise ratio (SNR), total harmonic distortion (THD), signal-to-noise
and distortion (SINAD) ratio, effective number of bits (ENOB), and spurious-
free dynamic range (SFDR), together with specifications in the time domain
Data Converter Principles 29

such as the settling time, slew rate, and glitch impulse, are generally used
to specify the converter dynamic performance. Parameters that are normally
specified in dB, can also be given in units of dBc (decibels to carrier) when
the absolute power of the fundamental is used as the reference, or dBFS (deci-
bels to full-scale) when the power of the fundamental is extrapolated to the
converter full-scale range.
In general, all the spectral components available at the converter output
and that are different from the one of the input signal are considered to be
noise. However, a better insight into the conversion process is provided by
separately estimating the noise floor and harmonic distortion levels. Hence,
the harmonic distortion components are excluded in the measurement of the
SNR, but are taken into account in the determination of the SINAD.

• The SNR is the ratio of the power of the fundamental input signal to
the noise power, which is caused by all spectral components from dc to half of
the sampling frequency, excluding noise at dc and harmonic distortion com-
ponents. By considering a full-scale input signal and only the noise due to
quantization errors, the SNR in decibels (dB) of a Nyquist converter is given
by !
P1
SN R = 10 log10 = 6.02N + 1.76 (2.41)
PQ

where P1 is the power of the first harmonic component or fundamental sig-

nal, PQ denotes the noise power, and N is the number of bits. In the case of
oversampling converters, the SNR includes additional terms depending on the
OSR and modulator feedback structure.

• The dynamic range (DR) is the ratio of the power of a full-scale sinu-
soidal input signal to the power of the noise delivered by the converter with
inputs shorted together.

• The THD is the ratio of the rms sum of the powers of the harmonic
components above the fundamental frequency to the power of the fundamental
signal at the converter output. The THD can be derived as
!
PD
T HD = 10 log10 (2.42)
P1

where PD is the sum of the powers, Pj (j ≥ 2), of all distortion spectral com-
ponents. The distortion measurement is realized with an input signal whose
amplitude is generally 0.5 dB to 1 dB below the full scale to avoid clipping, and
only takes into account harmonic components within the Nyquist bandwidth.
In practice, the distortion effects are directly observable on time-domain wave-
forms for a THD value of about −30 dB.
30 Data Converters, Phase-Locked Loops, and Their Applications

• The SINAD is the ratio of the power of the fundamental signal to the
power of all the remaining spectral (except dc) components below half of the
sampling frequency. It can be expressed as
!
P1
SIN AD = 10 log10 (2.43)
PQ + PD
where PD is the sum of all distortion spectral component powers. The SINAD
is also known as the signal-to-noise and distortion ratio (SNDR) and is mea-
sured in dB at a specified input frequency and sampling rate. In the case of
an ideal converter, the quantization error is the only source of noise and the
SINAD is reduced to the SNR.

• The ENOB specifies the resolution that an ideal converter would realize
in order to exhibit the same SINAD as the one measured on the real converter.
It can be derived for Nyquist converters as
EN OB = (SIN AD − 1.76)/6.02 (2.44)
The difference between the ENOB and the nominal number of bits indicates
the impact of circuit imperfections on the conversion process.

Assuming that an input signal with the same amplitude and fre-
quency is used for all measurements, determine the relationship
between the SINAD, SNR, and THD.
From the definitions of the SNR, THD, and SINAD, we obtain
PQ
= 10−SN R/10 (2.45)
P1
PD
= 10T HD/10 (2.46)
P1
and
PQ + PD
= 10−SIN AD/10 (2.47)
P1
It can then be shown that
!−1
P1 PQ PD  −1
= + = 10−SN R/10 + 10T HD/10 (2.48)
PQ + PD P1 P1
Hence,
!
P1
SIN AD = 10 log10
PQ + PD (2.49)
 
= −10 log10 10−SN R/10 + 10T HD/10
Data Converter Principles 31

The degradation of the SINAD for high frequencies is primarily

due to the fact that the importance of distortion effects increases
with the input signal frequency.

• The SFDR can be obtained as the ratio of the power of the fundamental
signal to the power of the highest spurious component in the converter spec-
trum (excluding dc). It is generally plotted as a function of the test signal
amplitude. The SFDR is commonly used in communication applications, as
an indication of the usable dynamic range.

• The two-tone intermodulation distortion (IMD) is measured by connect-

ing the converter input to the sum of two sinusoidal signals with the same
magnitude, but having slightly different frequencies. It is computed as the ra-
tio of the power of the worst third-order intermodulation product to the power
of either input tone. The IMD is a key specification used in the selection of
building blocks for multi-carrier communication systems. With the use of test
signals at frequencies f1 and f2 , the determination of the third-order IMD can
rely only on the distortion products occurring at 2f2 − f1 and 2f1 − f2 , or
relatively near the fundamental signals, as the distortion components at the
higher frequencies, or say at 2f2 + f1 and 2f1 + f2 , usually fall outside the
passband, where they can be filtered out easily.

It should be noted that the specifications of different converters can be

fairly compared only if the measurements are realized with the same funda-
mental input frequency or are valid over the same bandwidth, which is defined
as the frequency range over which the input signal can be converted with an
amplitude attenuation less than or equal to 3 dB.

• The glitch impulse represents the undesired signal transients that can
appear at the DAC output. It is characterized by measuring its area at the
mid-scale code transition where the logic states of the maximum number of
bits are changed. The unit of measurement can be chosen as nV ·s, for instance.

• The settling time is the time elapsed from the application of the input
signal until the converter output reaches and remains within a given error
range about the final value. It can include components such as a short delay
time related to the propagation delay, the slew time required for the output
to reach its highest value, and the ring time needed by the output to recover
from the overload condition associated with the slewing and to settle to within
the specified error band, which can be a certain percent of the final value or
±1/4 LSB. The settling time is usually specified for a full-scale transition.

• The latency time denotes the time elapsed from the initiation of one
input conversion to the next. It includes the conversion time, which is defined
32 Data Converters, Phase-Locked Loops, and Their Applications

as the time required for a single conversion, and data retrieval time. For ADCs,
the latency time is measured by assuming that the signal is already sampled.

2.3 Summary
Data converters are generally designed to meet the requirements of various
applications such as imaging, video, instrumentation, control, and communi-
cation systems. For most commonly used architectures, the specifications for
the resolution and sampling frequency generally extend beyond the range from
8 bits, 250 Msps (digital oscilloscope) to 24 bits, 2.5 Msps (seismic monitoring
systems) for ADCs, and from 8 bits, 330 Msps (digital radio modulation) to
24 bits, 200 ksps (DVD systems) for DACs. The distribution of resolution ver-
sus sampling frequency can furnish insight into the performance limitations
of data converters.
The resolution appears to be limited at low frequencies by the component
mismatches and thermal noise. It tends to be reduced on the order of one bit
when the sampling frequency is increased by two times. This is due to the
enhanced effect related to the comparator ambiguity and clock jitter at high
frequencies. Furthermore, the maximum sampling frequency of the converter
cannot exceed the transition frequency of the transistor, which is determined
by the IC process.
Data converters used in portable equipment should meet the requirement
of low supply voltage and low power consumption. In this case, the important
limitation, which is introduced on the dynamic range and speed, depends on
the architecture and IC technology.
Bibliography

[1] B. M. Gordon, “Linear electronic analog/digital conversion architectures,

theirs origins, parameters, limitations, and applications,” IEEE Trans. on
Circuits and Systems, vol. 25, no. 7, pp. 391–418, July 1978.
[2] Understanding data converters, Application notes, Texas Instruments,
1999.
[3] S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds., Delta-Sigma Data
Converters: Theory, Design, and Simulation, New York, NY: Wiley-IEEE
Press, 1996.
[4] J. R. Naylor, “Testing digital/analog and analog/digital converters,” IEEE
Trans. on Circuits and Systems, vol. 25, no. 7, pp. 526–538, July 1978.

33
3
Nyquist Digital-to-Analog Converters

CONTENTS
3.1 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.1 Binary-weighted structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.2 Thermometer-coded structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.3 Segmented architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 Voltage-scaling DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.1 Basic resistor-string DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.2 Intermeshed resistor-string DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.3 Two-stage resistor-string DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3 Current-scaling DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.1 Binary-weighted resistor DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.2 R-2R ladder DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.3 Switched-current DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.3.1 Static nonlinearity errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.3.2 Current source sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3.3.3 Switching scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.3.4 NRZ and RZ SC DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.4 Charge-scaling DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.5 Hybrid DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.6 Configuring a unipolar DAC for the bipolar conversion . . . . . . . . . . . . . . . . . . 75
3.7 Algorithmic DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.8 Direct digital synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.10 Circuit design assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Digital-to-analog converters (DACs) enable the interfacing of digital systems

with the real world. They are used to transform binary code into an analog
output signal, either in the form of a voltage or current.
Ideally, signals from dc up to the Nyquist frequency, which is defined as
half of the DAC sampling frequency, can be generated by a converter. In
practice, in addition to the increased difficulty to meet the specifications of
the reconstruction filter, the converter performance tends to degrade signifi-
cantly when approaching the Nyquist frequency. Nyquist DACs are based on
various architectures (binary-weighted, thermometer-coded, and segmented
structures) and conversion techniques such as voltage scaling, current scal-
ing, charge scaling or redistribution, and hybrid methods. In each of these
types of DACs, the conversion is achieved by summing all the output signal
contributions associated with the different bits of the input digital code. The
resolution of high-speed DACs based on each of the aforementioned techniques

35
36 Data Converters, Phase-Locked Loops, and Their Applications

is generally limited by the circuit size and complexity. One approach adopted
to reduce the number of elements (transistors, resistors, and capacitors) is to
use a segmented DAC. In a segmented converter, a first stage decodes the
most significant bit (MSB) part of the input digital code and a second stage
is driven by the remaining least significant bits (LSBs). A further issue with
high-resolution DACs is that the linearity and monotonicity of the conversion
characteristic is limited by component matching. The effect of mismatches,
which are generally caused by IC process gradients, can be alleviated either
by adding a calibration stage to the DAC or by laser trimming components
to adjust their values after wafer fabrication.

3.1 Digital-to-analog converter (DAC)

The transformation of a digital code by an N -bit digital-to-analog converter
(DAC) can rely on the use of switches to select the appropriate reference volt-
ages, which are then summed to provide a discrete time signal. The format of
the analog output generated by a DAC is dependent on the switching scheme.

According to the digital input code, a DAC ideally operates by

updating its analog output, which is then held for a certain time.
The timing of this operation is controlled by a clock signal with
a frequency fs = 1/T . Assuming a zero-order hold, the analog
output, x(t), reconstructed from the discrete-time sample, x(n),
available at time intervals spaced by T , can be written as,
N
X  
t − (n + 1/2)T
x(t) = x(n) · rect (3.1)
n=0
T

where rect(t) is the rectangular function. The impulse response

is of the form,

  1
1 t − T /2 if 0 ≤ t < T
h(t) = · rect = T (3.2)
T T 
0 otherwise.

In the frequency domain, the Fourier transform of the impulse

response, h(t), is given by

1 − e−j2πf T
H(f ) = F {h(t)} = = e−jπf T sinc(f T ) (3.3)
j2πf T
where the sinc function is defined as, sinc(f T ) = sin(πf T )/(πf T ).
Nyquist Digital-to-Analog Converters 37

The desired signal frequency in the first Nyquist zone, that ex-
tends from 0 to fs /2, is reflected as mirror images, but with
attenuated amplitudes due to the sinc frequency response, into
higher Nyquist zones. A lowpass or bandpass filter is often used
to attenuate these image signals. Increasing the clock frequency
helps reduce but does not eliminate the sinc-frequency roll-off ef-
fect. In applications that require a response remaining flat over
the entire frequency range, a pre-equalization digital filter (or
post-equalization analog filter), whose frequency response is the
inverse of the sinc function, should be placed in front of (or after)
the DAC.
Here, the hold time is equal to the clock signal period, and the
signal power is essentially delivered over the first Nyquist zone
that encompasses the DAC operating range.
Alternatively, by choosing the hold time that is equal to a frac-
tion of the clock signal period, the magnitude of the DAC re-
sponse is much lower and flatter in the first Nyquist zone and
significantly higher in the second Nyquist zone (or other Nyquist
zones) than that of the previous case. As a result, the DAC op-
eration now becomes possible in other Nyquist zones.

1 1 1
Magnitude

Magnitude

Magnitude

0 0 0

−1 −1 −1

(a) Time (b) Time (c) Time

FIGURE 3.1
DAC output for the digital code 1101001: (a) NRZ, (b) RZ, (c) HRZ.

A 1-bit DAC output can be represented, as shown in Figure 3.1, for

nonreturn-to-zero (NRZ), return-to-zero (RZ), and half-clock-period delayed
return-to-zero (HRZ) pulses. The output of a DAC with NRZ pulse remains
constant over a full clock period, T , while the output of a DAC with RZ
pulse is held constant only between 0 and T /2, and the output of a DAC with
HRZ pulse is a half-clock-period delayed version of the one of a DAC with RZ
pulse. In general, a DAC generates a stepwise output signal that can then be
transformed into an analog signal using a lowpass smoothing filter.
Intuitively, DACs with NRZ pulse are less affected by clock signal jitter
(or clock edge fluctuation) due to the fact that jitter errors can occur only
during the clock edges at which the data sample is changing. On the other
hand, DACs with RZ or HRZ pulse are the most sensitive to clock signal
jitter because random variations can affect the rising and falling edges of the
38 Data Converters, Phase-Locked Loops, and Their Applications

waveform at every clock cycle. However, DACs with NRZ pulse can be severely
limited by the inter-symbol interference (ISI) that is caused by mismatches of
the clock signal rise and fall times than other DACs. In the presence of ISI,
the DAC output is no longer dependent on only the current data sample, but
also on the previous data sample.
The performance of the converter is related to the choice of the IC tech-
nology and switching scheme.

3.1.1 Binary-weighted structure

The simplest and area-efficient way to control the switches consists of using
the digital input directly. However, the resulting structure has some draw-
backs. The components, which determine the reference voltages, are required
to be binary weighted. They should be matched to within ±1/2 LSB to meet
the specifications of a high-precision DAC. This is equivalent to achieving a
relative accuracy of less than 1/2N LSB for the MSB. The statistical spread
appears to be a limiting factor for the realization of this objective, and the
monotonicity of the DAC is not guaranteed. Furthermore, the output data
can exhibit a large spike or glitch at the mid-code transition, such as from
0111 to 1000 in a 4-bit example, due to the required asymmetrical switching.
Hence, the state of all bits is modified. The LSBs all can switch faster than
the MSB and the DAC output will first attempt to change toward zero before
returning to the right state. A glitch can be characterized by measuring its
energy, which is expressed in units of picovolt-seconds for high-performance
DACs. A sample-and-hold circuit can be used to maintain the DAC output
constant during the code transition, reducing in this way the glitch effect.

3.1.2 Thermometer-coded structure

An N -bit thermometer-coded DAC consists of 2N unit elements, which are
connected to switches, whose control signals are generated by a binary-to-
thermometer decoder. The switching of only one element is needed when the
input code changes by 1 LSB. That is, the relative accuracy to be realized is
1/2, corresponding to a relaxed matching constraint. Furthermore, the glitch
energy is considerably reduced. The monotonicity is guaranteed because the
output remains constant or follows the variation of the input code. The pri-
mary inconvenience of the thermometer-coded DAC is the need for a large
chip area.

3.1.3 Segmented architecture

A segmented DAC is based on an array of binary-weighted elements directly
controlled by the L least significant bits and an array of unit elements steered
by the remaining (N − L) bits, which are thermometer encoded. It is then
Nyquist Digital-to-Analog Converters 39

a compromise between both aforementioned structures and can combine the

high accuracy and conversion rate.
Note that the glitch problem at the mid-code can also be solved by never
turning off elements as the digital code is increased. This results in the in-
terpolated architecture. However, the drawback in this case is related to the
requirement of a complicated switching scheme.

3.2 Voltage-scaling DACs

In response to a digital input code, voltage-scaling DACs produce an out-
put voltage by exploiting the voltage-divider principle. As simple in operation
as a digitally controlled potentiometer, voltage-scaling DACs can easily be
designed to meet the high-speed and low-power specifications without affect-
ing their inherent monotonicity. While such DAC architectures are generally
widely used for applications requiring a resolution not exceeding 8 bits, they
are not suitable in cases where the resolution is high. This is due to the fact
that the required number of resistors and switches increases exponentially
with the resolution, making the resulting chip area very large.

3.2.1 Basic resistor-string DAC

The simplest architecture used to design a DAC based on the voltage divider
principle consists of a series of resistors connected between two supply volt-
ages, switches controlled by the digital input code, and a buffer to drive low
impedance loads. Each digital code is converted by selecting a node between
two resistors so that the appropriate voltage level is transferred to the con-
verter output.
A 3-bit resistor-string DAC based on a binary-tree structure is shown in
Figure 3.2. For an N -bit resolution, such a converter requires 2N resistors and
2(2N − 1) switches. Using the voltage divider rule, the voltage at node j of
the resistor string can be expressed as

j−1
Vj = VREF j = 1, 2, · · · , 2N (3.4)
2N
where VREF is the reference voltage. The input and output characteristics
of the unipolar DAC of Figure 3.2 are shown in Figure 3.3(a). Ideally, the
DAC establishes a unique correspondence between an input digital code and
a reference voltage. Because the reference levels are separated by an LSB or
equivalently VREF /2N , the characteristic can be shifted upward by LSB/2,
as shown in Figure 3.3(b), where the output level corresponding to the zero
digital code is now LSB/2. The resistor-string DAC based on the output char-
acteristic of Figure 3.3(b) is depicted in Figure 3.4. In comparison with the
40 Data Converters, Phase-Locked Loops, and Their Applications
V REF b3 b3 b2 b2 b1 b1

5 −
V0
R +
Buffer
4

FIGURE 3.2
Block diagram of a 3-bit binary-decoded resistor-string DAC.

1 1
7/8 7/8
Analog output (FS)

Analog output (FS)

3/4 3/4
5/8 5/8
1/2 1/2
3/8 3/8
1/4 1/4
1/8 1/8
0 0
000
001
010
011
100
101
110
111

000
001
010
011
100
101
110
111

Digital input code Digital input code

(a) (b)

FIGURE 3.3
Transfer characteristics of a 3-bit DAC.

previous structure, the overall number of resistors increases by one. Using the
topmost and bottommost resistors with a value of R/2, the voltage at the
node j of the resistor string is given by

j − 1/2
Vj = VREF j = 1, 2, · · · , 2N (3.5)
2N
Nyquist Digital-to-Analog Converters 41
V REF b3 b3 b2 b2 b1 b1

R/2

5 −
V
0
R +
Buffer
4

R/2

FIGURE 3.4
Block diagram of a 3-bit binary-decoded resistor-string DAC with code tran-
sitions at multiples of LSB/2.

In addition to its simple structure, the resistor-string DAC exhibits an inherent

monotonicity [1, 2]. For increasing input values, a DAC with a monotonic
characteristic generates strictly increasing output values. The linearity of the
resistor-string DAC then appears to be less affected by resistor mismatches.
However, the resistor-string DAC architecture is limited by the number of
resistors and switches, which grows exponentially as the resolution increases.

b3
b2 3−to−8 decoder
b1 t7 t6 t5 t4 t3 t2 t1 t0 −
V0
+
Buffer

VREF
R R R R R R R R

FIGURE 3.5
Block diagram of a 3-bit resistor-string DAC with a 3-to-8 decoder.
42 Data Converters, Phase-Locked Loops, and Their Applications

The number of switches can be reduced using an N -to-2N decoder, as

shown in Figure 3.5 for a resolution of 3 bits. Because only one switch is
included in the signal path for a given digital code conversion, the effects of
switch resistances and parasitic capacitance are reduced, yielding an improved
speed performance.

TABLE 3.1
Truth Table and Logic Equations of the 3-to-8 Decoder

Binary Code 1-out-of-8 Code

b1 b2 b3 t0 t1 t2 t3 t4 t5 t6 t7
0 0 0 0 1 0 0 0 0 0 0 0 t0 = b1 · b2 · b3
1 0 0 1 0 1 0 0 0 0 0 0 t1 = b1 · b2 · b3
2 0 1 0 0 0 1 0 0 0 0 0 t2 = b1 · b2 · b3
3 0 1 1 0 0 0 1 0 0 0 0 t3 = b1 · b2 · b3
4 1 0 0 0 0 0 0 1 0 0 0 t4 = b1 · b2 · b3
5 1 0 1 0 0 0 0 0 1 0 0 t5 = b1 · b2 · b3
6 1 1 0 0 0 0 0 0 0 1 0 t6 = b1 · b2 · b3
7 1 1 1 0 0 0 0 0 0 0 1 t7 = b1 · b2 · b3

b3

b2

b1

t7 t6 t5 t4 t3 t2 t1 t0

FIGURE 3.6
Circuit diagram of a 3-to-8 decoder.

The digital input code is translated into a format suitable for the switch
control by the 3-out-of-8 decoder, which can be implemented using various
architectures.
The 3-out-of-8 decoder detects the occurrence of a specific bit combination
in the input code, as illustrated by the truth table in Table 3.2. The decoding
leads to the activation of only the output with the subscript that is the same as
the decimal equivalent of the input code. Figure 3.6 shows the circuit diagram
of a 3-out-of-8 decoder using inverters and AND gates. This implementation
is directly related to the decoder logic equations and is simple. However, the
Nyquist Digital-to-Analog Converters 43

TABLE 3.2
Truth Table of the 3-Bit Binary-to-Thermometer Decoder and 1-out-of-8 En-
coder

Binary Code Thermometer Code 1-out-of-8 Code

b1 b2 b3 T 0 T 1 T 2 T 3 T 4 T 5 T 6 t0 t1 t2 t3 t4 t5 t6 t7
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0
2 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0
3 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0
4 1 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0
5 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0
6 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0
7 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1

b3
b2

b1

T6 T5 T4 T3 T2 T1 T0

V DD

t7 t6 t5 t4 t3 t2 t1 t0

FIGURE 3.7
Circuit diagram of a modular 3-out-of-8 decoder.

maximum number of digital inputs that a single AND gate can support can
be quickly reached as the input code resolution is increased.
For high resolutions, an implementation solution of the N -out-of-2N de-
coder is to use an N -bit binary-to-thermometer decoder, followed by a 1-out-
of-2N encoder. This results in a structure that is modular and realizable with
two-input gates. In the specific case of N = 3, let Tp , p = 0, 1, 2 · · · , 6, and tq ,
q = 0, 1, 2 · · · , 7, denote, respectively, the thermometer code and the 1-out-of-
8 code for the binary code, bk , k = 1, 2, 3. Table 3.2 shows the correspondence
between the logic states of bk and Tp , and all possible combinations of Tp and
44 Data Converters, Phase-Locked Loops, and Their Applications

tq . The logic equations derived from the truth table are given by

T 0 = b1 + b2 + b3 T 1 = b1 + b2 T 2 = b1 + b2 · b3 T 3 = b1
(3.6)
T 4 = b1 · b2 + b1 · b3 T 5 = b1 · b2 T 6 = b1 · b2 · b3

and 

T 0 for j = 0
tj = Tj−1 · T j for j = 1, 2, · · · , 6 (3.7)


T6 for j = 7

The circuit realization of the 3-out-of-8 decoder is shown in Figure 3.7. It

should be noted that the required number of gates can be high as the converter
resolution increases.

Design a 4-bit binary-to-thermometer decoder based on a 3-bit

binary-to-thermometer decoder.

3−bit binary−to−thermometer decoder

b1
b2

b3

b4

T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

FIGURE 3.8
Circuit diagram of a 4-bit binary-to-thermometer decoder.

The circuit diagram of a 4-bit binary-to-thermometer decoder

is shown in Figure 3.8. The encoding of a 4-bit binary code pro-
duces a thermometer code with j consecutive zeros followed by
15 − j consecutive ones. The number of ones in the thermometer
code is equal to the decimal equivalent of the binary input code.
The logic equations of the 4-bit binary-to-thermometer decoder
Nyquist Digital-to-Analog Converters 45

are given by

T 0 = b1 + b2 + b3 + b4 T 1 = b2 + b3 + b4
T 2 = b1 · b2 + b3 + b4 T 3 = b3 + b4
T 4 = b1 · b3 + b2 · b3 + b4 T 5 = b2 · b3 + b4
T 6 = b1 · b2 · b3 + b4 T 7 = b4
(3.8)
T8 = (b1 + b2 + b3 ) · b4 T9 = (b2 + b3 ) · b4
T10 = (b1 · b2 + b3 ) · b4 T11 = b3 · b4
T12 = (b1 · b3 + b2 · b3 ) · b4 T13 = b2 · b3 · b4
T14 = b1 · b2 · b3 · b4

In general, the required number of AND and OR gates for an

N -bit binary-to-thermometer decoder is equal to 2N − (N + 1).

Switches are used to connect the different reference voltages provided by

the resistor string to the output. Fully decoded architectures have the advan-
tage of providing a monotonic output, even if the resistances drift from their
nominal values. The output resistance of the DAC is dependent on the digital
code. This results in a code-dependent settling time when charging a capac-
itive output load. The switches must be appropriately sized or compensated
to reduce the effect of this nonideality on the converter performance.

3.2.2 Intermeshed resistor-string DAC

The complexity of the digital decoder can be reduced by using a DAC with
intermeshed resistor strings [3, 4]. The reference voltage is subdivided into
2P coarse voltage segments using a P -bit coarse resistor string with a low
impedance. Each coarse resistor is related in parallel to a Q-bit fine resistor
string with a relatively high impedance. The conversion of an input digital
code then consists of selecting the nodes of the fine resistor string connected to
the appropriate coarse voltage segments. With an overall resolution of N bits,
where N = P + Q, the resulting intermeshed resistor-string DAC required a
P -out-of-2P decoder and a Q-out-of-2Q decoder. Because the integers P and
Q are less than N , the complexity of the required decoders remains low in
comparison with a single N -out-of-2N decoder. Furthermore, by connecting
in parallel each coarse resistor with a fine resistor string, the converter output
impedance value and its variations with the input code are reduced, resulting
in an improved settling time.
The circuit diagram of a 5-bit intermeshed resistor-string DAC is shown
in Figure 3.9. The proper switches are selected by splitting the 5-bit input
code in the three MSBs and the two LSBs, that are applied to a 3-out-of-8 de-
coder and a 2-out-of-4 decoder, respectively. Latches can be inserted between
the decoders and switches, if necessary, to reduce glitch errors during a code
transition. In general, an N -bit intermeshed resistor-string DAC requires 2P
46 Data Converters, Phase-Locked Loops, and Their Applications
b1 b2 b3

3−to−8 decoder
VREF

b4
RF RF RF RF

RC
RF RF RF RF
b5

2−to−4 decoder
b4

RF RF RF RF
RC

RF RF RF RF b5

RF RF RF RF
RC

RF RF RF RF

RF RF RF RF −
RC V0
+
RF RF RF RF Buffer

FIGURE 3.9
Circuit diagram of a 5-bit intermeshed resistor-string DAC.

resistors RC in addition to 2N resistors RF . For resolutions greater than 8

bits, the overall number of resistors can be too high to be practical.

3.2.3 Two-stage resistor-string DAC

The number of passive elements in the DAC can be further reduced by adopt-
ing a design technique based on a segmented architecture [5], that consists
of a cascade of P -bit and Q-bit resistor-string DACs through buffer ampli-
fiers to realize a resolution of N bits, where N = P + Q. In a segmented
DAC, the input code is partitioned so that the P MSBs are processed by
the first stage of the converter, while the remaining Q LSBs are converted
by the second stage. The switch control signals are then obtained using P -to-
2P and Q-to-2Q decoders. Figure 3.10 shows a segmented converter based on
two 3-bit resistor-string DACs. Buffer amplifiers are required to prevent the
second-stage resistor string from loading the first-stage resistor string.
With the switch configuration defined by the P MSBs of a given input
code, the first resistor string can generate two reference voltage levels of the
form
VREF
Vp = p (3.9)
2P
Nyquist Digital-to-Analog Converters 47
.
t 0 b3
V REF t’7
−

+ .
t 1 b3 R .
t 7 b3
R t’6 + t’7 Buffer 1

t’7 .
t 2 b3 R .
t 6 b3
t’6 R t’5 + t’6
3−to−8 decoder

b1 t’5

b2
t’4 .
t 3 b3 R .
t 5 b3
t’3 R t’4 + t’5
b3 t’2
t’1 .
t 4 b3 R .
t 4 b3 −
t’0 R t’3 + t’4 V
0
+
t7 .
t 5 b3 R .
t 3 b3
Buffer 3

t6 R t’2 + t’3
3−to−8 decoder

b4 t5

b5
t4 .
t 6 b3 R .
t 2 b3
t3 R t’1 + t’2
b6 t2
t1 .
t 7 b3 R .
t 1 b3
t0 R t’0 + t’1

R .
t 0 b3
R t’0 −

+
Buffer 2

FIGURE 3.10
Circuit diagram of a 6-bit two-stage resistor-string DAC.

and
VREF
Vp+1 = (p + 1) (3.10)
2P

where p is the decimal equivalent of the P MSBs and p = 0, 1, 2, · · · , 2P − 1.

These voltages are applied at the inputs of the buffer amplifiers, whose outputs
are connected to the top and bottom of the second resistor string. Using the
superposition theorem, the converter output voltage generated in accordance
with the remaining Q LSBs of the input code can be expressed as

V01 V02 V01 − V02

V0 = q + (2Q − q) Q = V02 + q (3.11)
2Q 2 2Q

where V01 and V02 denote the output voltages of the first and second buffer
amplifiers, respectively; q is the decimal equivalent of the Q LSBs; and
q = 0, 1, 2, · · · , 2Q − 1. The output voltage is then generated by linearly inter-
polating between V01 and V02 . The step size by which the output voltage of
the second resistor-string DAC can change has a value of (V01 − V02 )/2Q . If
the buffer amplifiers are assumed to be ideal, V01 = Vp+1 and V02 = Vp , the
48 Data Converters, Phase-Locked Loops, and Their Applications

voltage V0 will be given by

VREF
V0 = p · 2Q + q (3.12)
2N
With k being the decimal representation of the input code, the converter
output voltage is reduced to

VREF
V0 = k (3.13)
2N
where k = p · 2Q + q. For an N -bit unipolar DAC, the value of k can vary from
0 to 2N − 1.
A resistor-string DAC is inherently monotonic. However, the monotonicity
in a segmented string DAC can be affected by the offset voltage of practical
buffer amplifiers. By taking into account the offset voltages Vof f 1 and Vof f 2
of the first and second buffer amplifiers, we have V01 = Vp+1 + Vof f 1 and
V02 = Vp + Vof f 2 . The converter output voltage is then given by

VREF
V0 = k + Vof f (3.14)
2N
where
Vof f 1 − Vof f 2
Vof f = Vof f 2 + q (3.15)
2Q
Assuming that the buffer offset voltages are identical, the output voltage for
each input code is shifted by the same amount and the monotonicity of the
converter characteristic is preserved. However, this last requirement is rarely
met in practice.
When q reaches its highest value, 2Q − 1, the voltage V0 becomes

V01 − V02 V01 − V02

V0 = V02 + (2Q − 1) Q
= V01 − (3.16)
2 2Q
where V01 = Vp+1 + Vof f 1 and V02 = Vp + Vof f 2 . Hence, the output voltage is
one step size below Vp+1 + Vof f 1 . The next increase of the converter output
occurs when the input codes of the second and first resistor-string DACs are,
respectively, reset and incremented by one.
With a switching scheme designed such that only the value of V02 is
changed to Vp+2 +Vof f 2 as a result of the digital code decoding, the digital-to-
analog conversion can preserve the numerical order of the input codes. Because
Vp+1 and Vp+2 are two adjacent voltage levels of the first resistor-string DAC,
we have
Vp+2 − Vp+1 = VREF /2P (3.17)
In the worst case, Vof f 2 = −Vof f 1 , and a monotonic conversion is guaran-
teed provided the magnitude of the buffer offset voltage remains lower than
VREF /2P +1 , or equivalently, half of the LSB of the first resistor-string DAC.
Nyquist Digital-to-Analog Converters 49

The polarity of the voltage supplied to the second resistor string is reversed
whenever the input code of the first resistor-string DAC is incremented by one.
This polarity inversion should be compensated by appropriately changing the
order used in the selection of the tap voltages of the second resistor-string
DAC. The switches responsive to the Q-bit LSBs are then configured such
that the tap voltages can be selected in either a top-down or a bottom-up
fashion.
The circuit diagram of a 6-bit two-stage resistor-string DAC using the
foregoing reversal switching scheme is depicted in Figure 3.10. The decoder
responsive to the three LSBs selects one of the eight tap voltages of the sec-
ond resistor string, starting with the node connected to either V01 or V02 ,
depending on the state of b3 .
The two-stage architecture can be used to implement a DAC with a reso-
lution on the order of 16 bits. The required number of resistors and switches
is reduced to 2P + 2N −P for a resolution of N bits. However, the main dis-
advantages are the offset voltage and settling-time requirements placed on
the design of buffer amplifiers to meet the monotonicity and conversion speed
specifications.
In general, even with the use of improved IC process technology, resistor-
string DACs can feature nonlinearity errors only in the 4 LSB range, and
are then essentially used in closed-loop applications such as motor control or
process control, where the INL and DNL specifications are undemanding.

3.3 Current-scaling DACs

Current-scaling DACs generally consist of a number of current sources that
are selectively switched into a summing node in response to a digital input
code. Various structures can be used in the implementation of a switchable
current source, while the sum of currents is generally formed at the inverting
node of an amplifier.

3.3.1 Binary-weighted resistor DAC

A binary-weighted resistor DAC is realized by summing the current contribu-
tions associated to the different bits of a digital input code. It then consists of
weighted current sources, which can simply be a set of resistors with power-
of-two values and connected in parallel to either the reference voltage or the
ground, depending on each bit state. Figure 3.11 shows the circuit diagram
of a binary-weighted resistor DAC. This architecture allows only unipolar
digital-to-analog conversion. The output voltage can be computed as,

V0 = −RF (I1 + I2 + I3 + · · · + IN ) (3.18)

50 Data Converters, Phase-Locked Loops, and Their Applications
RF

−
I1 I2 I N−1 IN V0
N−1 N
2R 4R 2 R 2 R +

b1 b1 b2 b2 bN−1 bN−1 bN bN

−VREF

FIGURE 3.11
Circuit diagram of a binary-weighted resistor DAC.

where N represents the DAC resolution. Because various binary-weighted re-

sistors are used to convert the reference voltage VREF into the currents Ik ,
the voltage V0 is found to be
! N
RF b1 b2 b3 bN RF X bk
V0 = VREF + 2 + 3 + · · · + N = VREF (3.19)
R 2 2 2 2 R 2k
k=1

The converter full scale, which is the difference between the output voltages
for the highest and smallest input codes, is obtained as

(2N − 1)RF
FS = VREF (3.20)
2N R
The resolution of the binary-weighted DAC depends on the precision achieved
for the resistor values. The ratio between the resistor values associated with
the MSB, b1 , and the LSB, bN , is given by

R1 2R 1
= N = N −1 (3.21)
RN 2 R 2
In the specific case of an 8-bit binary-weighted resistor DAC, the range of
resistor values can vary by a factor of 128. The spread of resistances can then
be very large for high resolutions, resulting in a difficulty to design resistors
with accurate values using classical integrated-circuit fabrication methods.
Furthermore, by increasing the DAC resolution, the current related to the
MSB can be slightly smaller than the sum of all currents due to the other
remaining bits, leading to a nonmonotonic conversion characteristic. In gen-
eral, the binary-weighted resistor architecture is used with a resolution not
exceeding 4 bits as a building block in the design of large systems.

3.3.2 R-2R ladder DAC

One of the most common DAC structures is based on the R-2R resistor ladder
network, which is symmetric and uses only two values of resistors, thus greatly
Nyquist Digital-to-Analog Converters 51

simplifying the matching requirements. The block diagram of a DAC using the
R-2R ladder network is shown in Figure 3.12. The switches are controlled by
digital logic. A 2R resistor can be connected either to the amplifier inverting
node or to the ground. In the first case, the corresponding bit, bk , assumes
the high state, while it is in the low state in the latter. Ideally, the load of

R R R
−VREF
I1 I2 I N−1 IN
2R 2R 2R 2R 2R
RF

b1 b1 b2 b2 b N−1 bN−1 bN bN
−
IA
V
0
+
IB

FIGURE 3.12
Block diagram of R-2R ladder DAC.

each 2R resistor has a resistance of 2R. That is, the currents can be obtained
according to
I1 = 2I2 = 4I3 = · · · = 2N −1 IN (3.22)
where I1 = −VREF /(2R). The DAC output is given by

N
X
V0 = −RF bk Ik (3.23)
k=1
N
RF VREF X bk
= (3.24)
R 2k
k=1

where Ik = −VREF /(2k R) and bk is either 1 or 0. The voltage V0 is propor-

tional to the switched-on bits. The R-2R DAC can exhibit a lower noise and
nonlinearity errors of only ±1 LSB. However, without involving some amount
of resistor trimming to reduce the matching errors, the resolution of an R-2R
DAC is limited to 12 bits. Furthermore, the glitch caused by switch timing
differences has a more significant effect on R-2R structures than on resistor-
string architectures. Hence, the R-2R DAC is less attractive for glitch-sensitive
applications such as waveform generation.

3.3.3 Switched-current DAC

In general, switched-current DACs or current-steering DACs are preferred
for applications requiring a resolution on the order of 10 bits and several
megahertz of signal bandwidth. By driving a resistive load directly without
the need for a voltage buffer, it can exhibit a very high power efficiency because
52 Data Converters, Phase-Locked Loops, and Their Applications

almost all power is directed to the output load. Furthermore, the switched-
current DAC has the advantage of featuring a low power consumption and
requiring a small chip area for low to medium resolutions. Switched-current
DACs can be designed using a binary-weighted, or thermometer-coded current
array, as shown in Figure 3.13, where RL is the load resistor. The number of
current sources required to achieve N bits of resolution is, respectively, N and
2N − 1 for the binary-weighted and thermometer-coded architectures because
the converter state without any switched-current contribution represents the
zero input code.

bN bN−1 bN−2 b1

Binary−to−thermometer decoder

VDD VDD

I 2I 4I 2 N−1 I I I I I

bN bN−1 bN−2 b1 T0 T1 T2 T2 N −2

I Out I Out

RL RL

(a) (b)

FIGURE 3.13
Block diagram of the (a) binary-weighted and (b) thermometer-coded
switched-current DACs.

A binary-weighted DAC consists of current sources that are sized to have

power-of-two values and are associated with switches directly controlled by the
input code. Even though it has a simple structure, its operation can be limited
by mismatches between the current sources. The worst-case error affecting the
conversion transfer characteristic can be observed at mid-code transitions, or
when the MSB current source is enabled, and all other current sources are
disconnected from the output. As it is difficult to match the value of the MSB
current source and the sum of remaining current sources to within 0.5 LSB,
the DAC monotonicity cannot be guaranteed. Furthermore, glitches can arise
in the DAC output as a result of the effects of asynchronous current switching
and parasitic capacitive coupling.
For a thermometer-coded DAC, 2N − 1 current sources of equal weight
are required to achieve a resolution of N bits. Each unit current source is
connected to a switch controlled by a signal generated by the binary-to-
thermometer decoder. For each increase in the input digital code by one,
only one additional current source is switched to the converter output, and
the connection configuration of the other current sources is maintained un-
changed. This greatly reduces the effect of glitches and the monotonicity of
the DAC characteristic is guaranteed. However, the main drawback of the
Nyquist Digital-to-Analog Converters 53

thermometer-coded DAC is the large chip area required as the resolution is

increased.
RF

−
V0
+
b1 b1 b N−1 b N−1 b N bN

2 N−1 I 2I I

VSS

FIGURE 3.14
Block diagram of a binary-weighted switched-current DAC.

Switched-current DACs can also be designed to generate an output voltage,

as shown in Figure 3.14, for a converter of the binary-weighted type. The DAC
operation principle relies on summing the digitally selected outputs of a set
of current sources. Each bit is assigned to a switch, which directs the current
flow either to the common summing node or to the ground, depending on the
bit state. The current direction adopted here allows the inverting amplifier of
the DAC to generate a positive output voltage of the form

V0 = RF I(bN + 2bN −1 + · · · + 2N −1 b1 )
N
X bk
= 2N RF I (3.25)
2k
k=1

where I denotes the LSB current and N is the converter resolution. Note that
the operation of the switched-current DAC with an output current can be
affected by the finite output impedance.
The circuit diagram of a binary-weighted switched-current DAC is depicted
in Figure 3.15. Each current source is formed by superposing a power-of-two
multiple of unit currents obtained by duplicating the current I. This is realized
by a current mirror with the number of output transistors associated with a
current source equal to the weight of the corresponding bit.
The major drawbacks of the thermometer-coded switched-current DAC are
the complexity of the decoder and the high number of the required current
sources. On the other hand, the binary-weighted switched-current DAC archi-
tecture is limited by its large element spread. A common practice is to divide
a high-resolution DAC into subconverters with a small number of bits, and
then either combine their output currents with a weighting network or scale
the weights of the current sources used in the subconverters [9]. The MSBs,
which require a high level of accuracy, are thermometer coded and the LSBs
can either be implemented using the binary-weighted or thermometer-coded
design technique.
54 Data Converters, Phase-Locked Loops, and Their Applications
RF

−
V0
+
VDD b1 b1 b N−1 b N−1 b N bN

R I
2 N−1 I 2I I

VSS

2 N−1 Transistors

FIGURE 3.15
Circuit diagram of a binary-weighted switched-current DAC.

VDD

2 N−P I 2 N−P I I I I

I/2 I/4 I/2N−(P+Q) I/2N−(P+Q)

To dump

To summing
nodes

Binary−to−thermometer Binary−to−thermometer
decoder decoder
bP+Q+1 bP+Q+2 bN
Input P MSBs Q ULSBs
code N

FIGURE 3.16
Block diagram of a segmented switched-current DAC.

The block diagram of a segmented switched-current DAC is shown in Fig-

ure 3.16, and its transistor implementation is depicted in Figure 3.17. Cur-
rent sources with weight values determined according to the subconverter
resolutions are used to ensure the monotonicity of the conversion character-
istic. They are implemented using p-channel MOS transistors, which can al-
low an output swing from the ground level. The segmented DAC combines
thermometer-decoded current cells, which are associated with the P most sig-
nificant bits (MSBs) and the Q upper least significant bits (ULLSBs), and
binary-decoded current sources, which determine the N − (P + Q) lower least
significant bits (LLSBs). With the LLSB transistor array being driven by a
ULLSB transistor, an extra LLSB transistor connected to the ground is re-
quired to make the sum of the LSBs equal to 1 ULLSB.
Note that, by eliminating the intermediate ULSB segment, the segmented
DAC can be reduced to an upper array of thermometer-decoded MSB current
sources and an additional MSB current source loaded by a lower array of
Nyquist Digital-to-Analog Converters 55
VDD

VB1 VB2

VB3

I−
Out
I+
Out

Q Q Q Q Q Q Q Q Q Q Q Q Q Q
R S R S R S R S R S R S R S

Binary−to−thermometer Binary−to−thermometer
decoder decoder
bP+Q+1 bP+Q+2 bN
Input P MSBs Q ULSBs
code N

FIGURE 3.17
Transistor implementation of a segmented switched-current DAC.

b8
b7
b6
b5
b4
b3
b2
b1

Dummy
Binary−to−thermometer decoder logic cells

2 6 −1 Current sources Binary−weighted

I− + current sources
Out I Out

FIGURE 3.18
Block diagram of a (6 + 2)-bit segmented DAC.

binary-decoded LSB current sources. In this way, the use of multiple reference
currents, which can be difficult to match in practice to ensure the linearity
between the DAC segments, is no longer necessary. Fig 3.18 shows a DAC
architecture including a thermometer-encoded segment controlled by the 6
MSBs and a binary-weighted segment connected to the 2 LSBs.
With the number of components required in the thermometer-coded seg-
ment of the DAC remaining large for high resolutions, the current sources
and switches can be arranged in a two-dimensional pattern to enable efficient
routing of switch control signals.
In the structure of Figure 3.19 [10, 11], the output signal is generated
by summing the contributions of the thermometer-coded and binary-weighted
DAC segments, which are, respectively, controlled by the 6 MSBs and 2 LSBs.
The number of thermometer-coded current sources, which are sized to have a
value of 4 LSBs and arranged in a matrix form, is 63 since no current source
56 Data Converters, Phase-Locked Loops, and Their Applications
b8
b7
b6
b5
b4
b3 Column
b2 decoder Dummy
b1 logic
cells

V
DD

Binary−weighted
current sources
Column j

Row j

Row j+1 S R
Q Q

V
DD
+
I Out Local encoder I
& current source

I−
Out

Row Thermometer−coded
decoder current sources I −0 I +0

FIGURE 3.19
Block diagram of a (2 × 3 + 2)-bit segmented DAC.

VDD

VREF +
− bk bk

+ I−
I Out Out
R I

FIGURE 3.20
Circuit diagram of a single switched-current cell with a bias circuit.

is enabled for the input code 0. The values of the two binary-weighted current
sources are 2 LSBs and 1 LSB, respectively. The first 3 MSBs steer the column
decoder, the next 3 bits are applied to the row decoder, and the remaining 2
bits are equalized to have equal delay with the MSBs and used to select the
binary-weighted current sources.
By using a two-stage decoding process for the 6 MSBs, the decoder can be
implemented with a minimum gate delay. The first stage is carried out by the
row and column decoders, and the second stage is completed by a local decoder
provided for each current cell. A given current source is enabled according
to the output state of the local decoder in response to the selection signals
generated by the row and column decoders. The output signal of each local
decoder can be derived simply by combining two of the row selection signals
Row j and Row (j + 1) and one of the column selection signals Column j
(j = 1, 2, · · · , 7). This is due to the fact that, for the conversion of a given
Nyquist Digital-to-Analog Converters 57

input code, the matrix of current sources is configured to exhibit, at most,

three types of rows. The first rows in which all the current sources are enabled
are followed in succession by a row in which only the first current sources
are enabled, and the remaining last rows in which all the current sources are
disabled. As the digital input code is increased, current cells are enabled along
the rows.
The decoders are implemented with inverters, NAND and NOR gates. The
skew between the signals of the row and column decoders is eliminated by the
latch connected to the switching transistors of each current cell. Figure 3.20
shows the detailed circuit diagram of a switched-current source, which is nec-
essary to build the DAC. The current source is implemented by applying the
reference voltage, VREF , to the noninverting input of an amplifier with a high
input impedance, which helps maintain the voltage at the inverting input also
equal to VREF . The current flowing through the resistor R as a result of the
conduction of the MOSFET included in the negative feedback of the amplifier
is given by
I = VREF /R (3.26)
The duplication or scaling of the current I can then be achieved using a current
mirror.
The matching errors at the edge of the array can be eliminated by sur-
rounding the active current cells with layers of dummy cells. Because the
smallest difference between the values of the current sources is 1 LSB, a DNL
error of 0.5 LSB can still be achieved with a relative current mismatch as
large as ±12.5%. The segmented DAC architecture has the advantage of re-
ducing the linearity error caused by random errors in the current source array.
However, the INL characteristic is especially sensitive to graded and symmet-
rical errors caused, respectively, by a voltage drop along the power supply
lines and thermal distribution inside the DAC chip. In practice, for converters
with resolutions greater than 8 bits, the linearity error due to nonuniform cur-
rent sources can be reduced using improved switching schemes or calibration
circuits [12, 13].
The performance of switched-current DACs can also be affected by the
limited output impedance of current sources. A different number of current
cells is connected to the output, depending on the digital input code. This
results in a nonlinearity caused by the variation of the output impedance,
which can be reduced by using current sources with a cascode configuration
as shown in Figure 3.21, where each switch is implemented using a pMOS
transistor with the gate connected to the inverted input code.
A cascode current source has the advantage of featuring an output
impedance greater than the one of a single transistor. To provide the highest
possible voltage swing at the output terminal, the current-source bias circuit
is designed to maintain the transistors in the cascode configuration in the
saturation region.
For the normal operation of the structure illustrated in Figure 3.21(a),
two reference currents are required to establish the dc bias levels. The output
58 Data Converters, Phase-Locked Loops, and Their Applications
VDD VDD
VREF −
+
R2
−
+ VB
R1 I
I REF/4 I REF bk bk
bk bk

I+ I−
Out Out I+ I−
Out Out
(a) (b)

FIGURE 3.21
(a) Circuit diagram of a cascode current source; (b) circuit diagram of an
active cascode current source.

current is approximately equal to the reference current IREF , provided the

sizes of transistors are identical.
In the current source of Figure 3.21(b), a pair of active cascode transistors
is used to further improve the output impedance. The output of the oper-
ational amplifier having the noninverting input connected to the reference
voltage, VREF , and the inverting input connected to the voltage at the node
between resistors R1 and R2 , drives the transistor gate to set the delivered
current at the value I = VREF /R1 . The voltage divider including R1 and
R2 helps maintain the transistor drain at the voltage VREF (1 + R2 /R1 ). The
duplication of the current I is realized by applying the amplifier output to
the gate of other transistors. An additional amplifier uses the bias voltage VB
applied to its noninverting input to regulate the voltage at its inverting node,
which is connected between the drain and source of the transistor. In this way,
the output impedance of the current source is enhanced by the gain of the
amplifier in the negative feedback loop. For high values of the output current,
the performance of the active gain enhancement technique may be limited by
stability requirements, which can become critically dependent on the parasitic
capacitances.

3.3.3.1 Static nonlinearity errors

Given a digital input code k, the differential nonlinearity (DNL) (in LSBs)
can be expressed as
IOut (k) − IOut (k − 1)
DN Lk = −1 (3.27)
ILSB
where IOut is the analog output current. The DAC DNL is the maximum
value of DN Lk . For monotonic operation, the DAC should exhibit a DNL
value that is less than 1 LSB.
The integral nonlinearity (INL) (in LSBs) is given by
IOut (k) − IOut (0)
IN Lk = −k (3.28)
ILSB
Nyquist Digital-to-Analog Converters 59

where k = 1, 2, · · · , 2N − 1 for an N -bit DAC. The DAC INL is taken as the

maximum value of DN Lk . The DAC exhibits a monotonic characteristic if
the INL value remains less than 0.5 LSB.
It can be remarked that

DN Lk = IN Lk − IN Lk−1 (3.29)

and
k
X
IN Lk = DN Lj (3.30)
j=1

Generally, precise analog levels required in the DAC implementation are

generated by using an array of identical unit current sources. Due to transistor
mismatches, each unit current source, Ij , of an N -bit current-switched DAC
can be modeled by adding a current variation △Ij to the nominal current, I.
Hence,
Ij = I + △Ij (3.31)
where △Ij is the unit current error and the average current I, that is almost
equal to the ideal LSB current, can be expressed as
N
2X −1
1
I= N Ij (3.32)
2 − 1 j=1

The errors △Ij are normally distributed with zero mean and variance σI2 , and
are assumed to be uncorrelated with each other.
For a thermometer-coded DAC, the output current related to the input
digital code k can be written as
k
X
IOut (k) = kI + △Ij (3.33)
j=1

where k = 0, 1, 2, 3, · · · , 2N − 1. For large numbers of unit current sources, the

INL at the digital code k can be computed as
N N
k
X 2X−1 k
X 2X−1
k k
△Ij − N △Il △Ij − N △Il
j=1
2 −1 j=1
2 −1
l=1 l=1
IN Lk = N
≃ (3.34)
1 2X −1 I
I+ N △Il
2 −1
l=1

The variance of IN Lk is given by

  2
2 k σI
σIN Lk = k 1− (3.35)
2N − 1 I 2
60 Data Converters, Phase-Locked Loops, and Their Applications

Assuming that the maximum value of the IN Lk variance occurs at midcode,

or for k = 2N −1 , we can obtain
 
2 N −1 2N −1 σI2
σIN L = 2 1− N (3.36)
2 − 1 I2

Considering the DNL at the digital code k, it can be shown that

N
2X−1
1
△IOut (k) − I − N △Il
2 −1 △IOut (k) − I
l=1
DN Lk = N
≃ (3.37)
1
2X −1 I
I+ N △Il
2 −1
l=1

where
△IOut (k) = IOut (k) − IOut (k − 1) = I + △Ik (3.38)
The variance of DN Lk can be expressed as

2 σI2
σDN Lk = 2 (3.39)
I
2
The variance σDN Lk is essentially dependent on the standard deviation of a
single unit current source and may appear to be rather small.
The performance difference between thermometer-coded and binary-
weighted DACs is related to the way the current sources are combined to
form the output current. In the thermometer-coded DAC, the unit current
sources are individually switched on and off, while in the binary-weighted
DAC, the unit current sources are first gathered into groups of 2j , with j
being an integer, one of which is selected by closing or opening just one of the
switches.
The output current of a binary-weighted DAC can be put into the form,
N 
X  2X
j
−1 
IOut (k) = kI + bk+1,j △Ii (3.40)
j=1 i=2j−1

where k = 0, 1, 2, 3, · · · , 2N − 1 and bk+1,j are the elements of the 2N × N

switching matrix given by
 
0 0 0 0 ··· 0
1 0 0 0 ··· 0
 
0 1 0 0 ··· 0
 
 0
B = (bk,j ) = 1 1 0 0 ···  (3.41)
0 0 1 0 ··· 0
 
 .. .. .. .. .. .. 
. . . . . .
1 1 1 1 ··· 1
Nyquist Digital-to-Analog Converters 61

It should be noted that bk+1,j refers to the element in row k+1 and column j of
matrix B. The rows of matrix B are determined by the binary representation
of the first 2N −1 integers, the LSB being in the left-most column. The 1’s and
0’s represent the current sources that are switched on and off, respectively, for
the conversion of a given digital code.
The IN Lk is approximately given by

N 
X  2X
j
−1  2X N
−1
k
bk+1,j △Ii − N △Il
j=1
2 −1
i=2j−1 l=1
IN Lk ≃ (3.42)
I

The maximum INL variance of the binary-weighted DAC is almost identical

to that of the thermometer-coded DAC.

The DN Lk can be roughly estimated as

△IOut (k) − I
DN Lk ≃ (3.43)
I

where

△IOut (k) = IOut (k) − IOut (k − 1) (3.44)

X N   2
X
j
−1  N
X   2
X
j
−1 
=I+ bk+1,j △Ii − bk,j △Ii (3.45)
j=1 i=2j−1 j=1 i=2j−1

The worst-case transition occurs at mid-scale, or between the digital code k =

2N −1 (associated to the row [1111 · · · 10] of B) and k = 2N −1 + 1 (associated
to the row [0000 · · · 01] of B) and involves all 2N − 1 current sources. The
maximum INL variance can then be computed as,

2 N σI2
σDN L ≃ (2 − 1) 2 (3.46)
I

where N is the converter’s resolution in number of bits.

Due to transistor mismatches, the non-linearity characteristic of DACs
implemented using the same IC process technology can vary randomly. A
yield-analysis technique for predicting the values of this characteristic within
certain boundaries is necessary to improve the sizing of the unit current
sources [14–17]. Especially, analytical methods or Monte Carlo simulations
can be used to relate the current matching error variance to the non-linearity
characteristic and yield that is defined, for instance, as the percentage of
functional devices that have an INL less than 1/2 LSB in a set of fabricated
devices.
62 Data Converters, Phase-Locked Loops, and Their Applications

3.3.3.2 Current source sizing

Typical DAC current sources are implemented using transistors in a cascode
configuration. Assuming that the cascode transistor has a high gain, the gen-
erated current is reduced to
I = ID = K(VGS − VTn )2 (3.47)
where ID is the drain current, K is the transconductance parameter, VTn is
the threshold voltage, and VGS is the gate-source voltage. Due to variations
of the transistor parameters, the current can deviate from its nominal value.
By differentiating the current, it can be shown that
∂I ∂I
δI = δK + δVTn (3.48)
∂K ∂VTn
= (VGS − VTn )2 δK − 2K(VGS − VTn )δVTn (3.49)

and
δI δK 2δVTn
= − (3.50)
I K VGS − VTn
The relative error of the current is given by
△I △K 2△VTn
= + (3.51)
I K VGS − VTn
The variance of the current error can be obtained as
σI2 2
σK 4σV2 Tn
= + (3.52)
I2 K2 (VGS − VTn )2
The transconductance parameter and threshold voltage differences between
two identically drawn and closely spaced transistors can be approximately
characterized by the following variances:
2
σK A2
2
≃ K (3.53)
K WL
A2VTn
σV2 Tn ≃ (3.54)
WL
where AK and AVTn are technology-dependent constants.
The LSB current exhibits the smallest magnitude and can then be the
most critical in terms of accuracy. The use of the transistor mismatch model
and square law equation to size the transistor of the LSB current source leads
to
4A2VTn
A2K +
1 (VGS − VTn )2
WL = (3.55)
2 σI2LSB
2
ILSB
Nyquist Digital-to-Analog Converters 63

and
W ILSB
= ′ (3.56)
L K (VGS − VTn )2
where ILSB was assumed to be equal to the transistor drain current, and
K ′ = µn Cox /2. For a given overdrive voltage, VGS − VTn , the transistor sizes
can be estimated as follows:
  1/2
ILSB A2K 4A2VTn
W = + (3.57)
2K ′ (σI2LSB /ILSB
2 ) (VGS − VTn )2 (VGS − VTn )4
 1/2
K′ 2 2 2
L= [A (V GS − VTn ) + 4A ] (3.58)
2ILSB (σI2LSB /ILSB
2 ) K VTn

Hence, the transistor sizes of the current source are dependent on matching
errors.

3.3.3.3 Switching scheme

High-resolution current-switched DACs are generally based on segmented
structures consisting of an LSB binary-weighted array and an MSB
thermometer-coded unary array.
In contrast to the thermometer-coded DAC, the binary-weighted DAC
exhibits a low overhead because it does not require a decoding logic. The
advantage of the thermometer-coded DAC over the binary-weighted DAC is
its inherent monotonicity and relaxed matching requirements to meet the same
DNL specification. In addition, the worst-case glitch that occurs at mid-code
in the binary-weighted DAC is eliminated because only one current source can
be switched at once. However, the large area required by the thermometer-
coded DAC, especially when a resolution greater than 10 bits is of interest,
places a limitation on the achievable current source matching.
VDD

I1 I2 I3 I4 I5 I6 I7 I8

S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S7 S7 S8 S8

+
I Out −
I Out

RL RL

FIGURE 3.22
Block diagram of a 3-bit current-switched DAC.

In practice, transistor mismatch errors attributable to process variations

include both stochastic (or random) and gradient errors. The reduction of
64 Data Converters, Phase-Locked Loops, and Their Applications

TABLE 3.3
Comparison of 4 switching sequences for a 3-bit DAC
I1 I2 I3 I4 I5 I6 I7 I8
1.86 1.90 1.94 1.98 2.02 2.06 2.10 2.14 (µA)
Sequence 1 1 2 3 4 5 6 7 8
Error (%) −7 −5 −3 −1 1 3 5 7
IN Lk (%) −7 −12 −15 −16 −15 −12 −7 0 IN L = 16
Sequence 2 7 5 3 1 2 4 6 8
Error (%) −1 1 −3 3 −5 5 −7 7
IN Lk (%) −1 0 −3 0 −5 0 −7 0 IN L = 7
Sequence 3 2 6 4 8 5 1 7 3
Error (%) 3 −7 7 −3 1 −5 5 −1
IN Lk (%) 3 −4 3 0 1 −4 1 0 IN L = 4
Sequence 4 5 3 7 1 8 2 6 4
Error (%) −1 3 −5 7 −7 5 −3 1
IN Lk (%) −1 2 −3 4 −3 2 −1 0 IN L = 4

stochastic errors leads to the chip area increase that in turn induces system-
atic (or gradient) errors in oxide thickness and along wires or voltage drops
across supply-voltage interconnection lines resulting in linear matching errors
that are primarily dependent on the DAC layout techniques or the current
source location in the DAC array. Thermometer-coded DACs can be imple-
mented with various switching schemes that assign a selection order to each
of the current sources as the digital code changes. Appropriate DAC switch-
ing schemes [10, 18–20] can help reduce the effect of gradient matching errors.
They determine the interconnection between the thermometer decoder/latch
outputs and the switch control terminals, and then affect the DAC layout
drawing.
Consider the block diagram of a 3-bit current-switched DAC with differ-
ential outputs is shown in Figure 3.22. Each unit element can be realized as
a cascoded pMOS transistor current source in order to increase the current
source output resistance and reduce the effect of parasitic capacitance between
the current source and switches. The switches can be implemented using MOS
transistors or transmission gates. The output load resistances are 50 Ω.
The nominal value of the unit current is defined as the average current
generated by all current sources in the DAC array. Hence,
8
1X
I= Ij (3.59)
8 j=1

The INL (in LSBs) for the digital code k is approximately computed as
k
X
IN Lk ≃ ǫj (3.60)
j=1
Nyquist Digital-to-Analog Converters 65

where ǫj = △Ij /I. The DAC INL is the maximum value of IN Lk .

Table 3.3 presents the comparison of 4 switching sequences for a 3-bit
DAC. The actual values of unit currents and the corresponding relative errors
are listed in the first and second rows, respectively.
The conventional sequential switching sequence (sequence 1) leads to an
INL of 16%. The use of the alternating switching sequence (sequence 2)—here,
the current sources are switched in alternating fashion relative to matching
errors with identical absolute value, starting with the current source whose
negative error is the highest −1% up to the one whose positive error is the
highest 7%—helps reduce the INL to 7%. For the optimal switching sequences
(sequence 3 and 4), the resulting INL takes the minimum value of 4%.
The switching sequence 3 starts with a current source, whose relative error
is equal to or less than the INL lower bound. The remaining current sources
are then switched so that each of the IN Lk values remains within the negative
and positive lower bounds of the INL as the digital code is increased. Note
that, when the IN Lk maximum and minimum are symmetrical about zero,
their identical absolute value is equal to the minimum INL.
Considering the switching sequence 4, the first and last current sources to
be switched are the ones with the highest negative error and lowest positive
error, respectively. The error sign changes from one current source to the next
and the remaining current sources are switched so that there is a symmetry
between current sources with negative and positive errors of the same absolute
value. As a result, a further reduction of the error variance can be achieved.

Linear error
distribution

Quadratic error
distribution
Column x axis
0 1 2 3 4 5 6 7

Normalized linear gradient error

−7 −6 −5 −4 −3 −2 −1 0

1
INL (% LSB)

2
Row y axis

3
INL (% LSB)

0 1 2 3 4 5 6 7
Normalized linear gradient error

FIGURE 3.23
Structure of a 8 × 8 DAC array showing error distributions.
66 Data Converters, Phase-Locked Loops, and Their Applications
Column x axis Column x axis
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

Normalized linear gradient error Normalized linear gradient error

−16 −7 −6 −5 −4 −3 −2 −1 0 −7 −7 −6 −5 −4 −3 −2 −1 0

0 −12 1 9 23 35 45 53 59 63 0 −6 7 14 27 38 47 54 59 63

1 −8 16 2 10 24 36 46 54 60 0 1 −5 21 5 12 25 36 45 53 60 0
INL (% LSB)

INL (% LSB)
2 −6 29 17 3 11 25 37 47 55 −1 2 −4 33 19 3 10 23 35 46 55 −1
Row y axis

Row y axis
3 −4 40 30 18 4 12 26 38 48 −2 3 −3 43 31 17 1 9 24 37 48 −2

INL (% LSB)

INL (% LSB)
4 −2 49 41 31 19 5 13 27 39 −4 4 −2 51 41 29 16 2 11 26 39 −3

5 −1 56 50 42 32 20 6 14 28 −6 5 −1 57 49 40 30 18 4 13 28 −4

6 0 61 57 51 43 33 21 7 15 −8 6 0 61 56 50 42 32 20 6 15 −5

7 64 62 58 52 44 34 22 8 −12 7 64 62 58 52 44 34 22 8 −6

0 1 2 3 4 5 6 7 −16 0 1 2 3 4 5 6 7 −7
(a) Normalized linear gradient error (b) Normalized linear gradient error

Column x axis Column x axis

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

Normalized linear gradient error Normalized linear gradient error

−4 −7 −6 −5 −4 −3 −2 −1 0 4 −7 −6 −5 −4 −3 −2 −1 0

0 −4 2 10 24 36 46 54 60 63 0 4 5 13 27 39 47 55 59 63

1 −3 17 6 14 28 38 48 53 59 0 1 −3 20 3 11 25 37 45 53 60 0
INL (% LSB)

INL (% LSB)

2 −3 30 21 4 12 26 39 45 55 1 2 4 33 18 7 15 23 35 46 54 −1
Row y axis

Row y axis

3 −2 41 34 19 8 13 27 35 47 −2 3 −3 44 31 22 1 9 24 36 48 −2
INL (% LSB)

INL (% LSB)
4 −2 50 43 32 20 5 9 23 37 −2 4 −2 51 42 29 16 8 10 28 38 −3

5 1 57 52 44 33 16 1 15 25 −3 5 −1 58 49 40 30 17 2 14 26 4

6 0 62 56 49 40 29 22 7 11 −3 6 0 61 56 50 41 34 21 6 12 −3

7 64 61 58 51 42 31 18 3 −4 7 64 62 57 52 43 32 19 4 4

0 1 2 3 4 5 6 7 −4 0 1 2 3 4 5 6 7 4
(c) Normalized linear gradient error (d) Normalized linear gradient error

FIGURE 3.24
Four possible switching sequences for a 8 × 8 DAC array.

The aforementioned switching schemes can be applied to current sources

arranged in a two-dimensional or matrix array. Figure 3.23 shows the structure
of a 8 × 8 DAC array that can provide a resolution of 6 bits. Each current
source is identified by the coordinates (x, y), where x and y are the column
and row positions, respectively.
Gradient error distributions across a thermometer-coded DAC matrix can
be reduced to linear (first-order) and quadratic (second-order) terms in x and
y. Their representations use the center of the DAC array as the origin. The
normalized linear gradient error is determined for the set of current sources
along each dashed line. Its maximum absolute value is associated to the current
sources at (0, 0) and (7, 7), while its minimum value is related to current
sources that are located along the diagonal dashed line from (0, 7) to (7, 0).
Nyquist Digital-to-Analog Converters 67

A switching sequence, together with the corresponding digital code INL, is

associated to each dotted line along the direction indicated by the arrow.
Figure 3.24 shows 8 × 8 DAC arrays making use of each of the four possible
switching sequences, as well as the corresponding digital code INL. The max-
imum absolute value of INL for each of the four switching sequences is 16, 7,
4, and 4, respectively. Optimal switching sequences help reduce significantly
the effects of nonlinearities due to gradient errors.

3.3.4 NRZ and RZ SC DAC

A switched-current DAC is suitable for high-speed applications (with clock
signal frequency up to the GHz range) requiring a moderate resolution. It
consists of an array of current sources and switches controlled by the digital
code to be converted.
VDD VDD

RL RL RL RL

V0 V0
T3 T4 T3 T6
VB CK RZ T5 T4 CK RZ

CK RZ
bk T1 T2 bk
D Q D Q T1 T2
CK NRZ Q CK NRZ Q

IB IB

(a) (b)

FIGURE 3.25
Switched-current DAC cell with (a) NRZ and (b) RZ switching schemes.

CK NRZ

t
Q

t
V0
NRZ
t
CK NRZ
t
V0
RZ

FIGURE 3.26
Waveform representation for NRZ and RZ DACs.
68 Data Converters, Phase-Locked Loops, and Their Applications
100 10
RZ
90 0 NRZ

SFDR (dB)
80 −10

Gain (dB)
70 −20

RZ
60 −30
NRZ

50 −40
10 −2 10 −1 10 0 0 1 2 3

(a) Frequency (GHz) (b) Normalized frequency, f/f CK

FIGURE 3.27
SFDR plots (a) and gain response (b) for NRZ and RZ DACs.

Various switching schemes can be adopted to minimize the correlation

between the input code and the resulting DAC error. Figure 3.25(a) shows a
switched-current DAC cell with a non-return-to-zero (NRZ) switching scheme.
The NRZ output response is obtained by holding constant the code bk during
each clock signal period. In a DAC cell with a return-to-zero (RZ) switching
scheme, as depicted in Figure 3.25(b), an additional clock signal is used to
periodically return the output to a known state in order to reduce the data
dependencies of switching glitches. To ensure that cell data path delay errors
do not propagate to the output, transitions of the flip-flop outputs should
occur during the reset phase (signal CKRZ in the low state). Figure 3.26
shows the waveforms illustrating the operation of NRZ and RZ DACs.
For NRZ and RZ DACs with a resolution of 12 bits, Figure 3.27(a) presents
spurious-free dynamic range (SFDR) plots. The SFDR corresponds to the ratio
between the output signal power and the largest magnitude of any spectral
component (excluding the DC component). RZ DACs exhibit the best SFDR
performance because they are less sensitive to switching errors.
However, RZ DACs are two times more sensitive to random clock jitter
due to output transitions that can occur on both (rising and falling) edges of
the clock signal. Furthermore, they can exhibit a 6-dB reduction of the output
signal power at dc and a flatter frequency response with the first null shifted
at two times the clock frequency, as illustrated in the output gain response of
Figure 3.27(b).

3.4 Charge-scaling DAC

A typical charge-scaling DAC exploits the principle of charge transfer between
capacitors for the conversion of the digital input code. Charge-scaling DACs [6]
that are capable of achieving a high linearity can be fabricated using CMOS
technology.
Nyquist Digital-to-Analog Converters 69

The circuit diagram of a binary-weighted capacitor-array DAC is shown in

Figure 3.28, where b1 and bN are the MSB and LSB, respectively. With the
assumption that all capacitors are initially discharged, the converter operation
requires a two-phase, nonoverlapping clock signal. The converter is based on
the charge redistribution principle. The amplifier is assumed to have an offset
voltage Vof f and an infinite dc gain.
φ
1

N
2 C φ
2

N−1 N−2
2 C 2 C 2C C φ
φ φ φ φ 1
2 2 2 2

φ
φ b . φ b . .
φ b φ b . − 2
1 1 1 2 1 N−1 1 N V0
+
V REF

FIGURE 3.28
Circuit diagram of a binary-weighted capacitor-array DAC.

During the first clock phase, the amplifier operates as a unity-gain volt-
age follower. Each input capacitor 2N −k C is connected between the amplifier
inverting node and either the reference voltage or the ground, depending on
whether the corresponding bit is high or low, while the capacitor 2N C is
connected between the amplifier inverting node and the ground. The charge
stored on the input capacitors is of the form
N
X N
X


2N −k bk CVREF − 2N −k CVof f = CVREF bk 2N −k − (2N − 1)CVof f
k=1 k=1
(3.61)

and the capacitor 2N C is charged to Vof f . Note that the capacitor array has
a total capacitance of (2N − 1)C. During the second clock phase, the input
capacitors are connected between the ground and the amplifier inverting node
and are then charged to Vof f , while the voltage Vof f − V0 is applied across the
capacitor 2N C, which is now included in the amplifier feedback path. Applying
the charge conservation rule at the amplifier inverting node, we obtain

2N C(Vof f − V0 ) − 2N CVof f
N
X (3.62)
= −(2N − 1)CVof f − CVREF bk 2N −k + (2N − 1)CVof f
k=1

Hence, the resulting output voltage can be expressed as

N
X bk
V0 = VREF (3.63)
2k
k=1
70 Data Converters, Phase-Locked Loops, and Their Applications

where VREF is the reference voltage. For resolutions greater than 8 bits, the
capacitance spread, which increases exponentially with the number of bits, can
become too high, thereby greatly limiting the achievable matching accuracy.
φ
1

N−P φ
2 C 2

N−P−2 N−P−1
C 2C 2 C 2 C φ
φ φ φ φ 1 φ
2 2 2 2 2

φ P φ
C 2 C
φ b .
1 N 1
.
φ b
N−1
.
φ b
1 P+2
.
φ b
1 P+1
− 2 1

+
V REF φ φ
1 2

φ
− 1
P−2 P−1 V0
C 2C 2 C 2 C
φ φ φ φ
+
1 1 1 1

φ b .
2 P 2
.
φ b
P−1
φ b .
2 2
φ b .
2 1

V REF

FIGURE 3.29
Circuit diagram of an N -bit cascaded binary-weighted capacitor-array DAC.

One technique to reduce the capacitance spread can consist of using an

architecture with two conversion stages as shown in Figure 3.29. The capacitor
array of the first conversion stage is responsive to the (N − P ) LSBs of the
N -bit input code, while the P MSBs are applied to the capacitor array of
the second conversion stage. The final result is produced by exploiting the
inverting node of the amplifier used in the second conversion stage to combine
the output of the first stage with the signal due to the input code MSBs. The
output voltage, V0 , can then be computed as
P
X N
X N
X
bk 1 bk bk
V0 = VREF k
+ P
VREF k−P
= VREF (3.64)
2 2 2 2k
k=1 k=P +1 k=1

Note that the reference signal sampling and the charge transfer phase take
place during opposite clock phases in the first and second stage of the DAC.
Using the above two-stage architecture, the capacitance spread for an N -bit
DAC can be reduced from 1/2N to max(1/2P , 1/2N −P ).
Because the charge is simply redistributed between the capacitors of a
charge-scaling DAC, the power consumption is significantly reduced compared
with other DAC structures. However, precise clock signals are indispensable
for the control of the charge transfer; otherwise glitches may appear at the
converter output. In addition, because of the charge slowly leaking from the
capacitors over time, the accuracy of charge-scaling DACs starts to decrease
within a few milliseconds after the beginning of the conversion. Charge-sharing
DACs then appear to be unsuitable for general-purpose DAC applications,
Nyquist Digital-to-Analog Converters 71

and are preferably used in successive-approximation ADCs, whose conversion

cycle, by lasting only about a few microseconds, is generally ended well before
the effect of the leakage current can become significant.

3.5 Hybrid DAC

An effective method to reduce the component spread and still achieve a high
resolution is to use hybrid DAC architectures. By dividing the input code into
two subwords to be processed by different sections of the DAC, it is possible
to realize the conversion using a reduced number of components.

VREF
V02 VDD
I3
t7 T2
R
VDD
I2
R t6 T1
T2
VDD
I1
R t5 T0
t7 T1
t6 VDD
3−to−8 decoder

b1 t5 R t4 I0
t4
b2 T0
t3
b3 t2 R t3
t1 +
t0 V0
R −
t2
T2 T1 T0
Binary−to−thermometer

R t1 VSS
decoder

R t0

V01 b4 b5

FIGURE 3.30
Circuit diagram of a 5-bit unipolar hybrid DAC including a resistor-string
network and an interpolation amplifier stage (P = 3, Q = 2).

The unipolar hybrid DAC, as shown in Figure 3.30, includes a 3-bit resis-
tor string and a 2-bit interpolation amplifier stage. This architecture has the
advantages of improving the conversion speed and output settling character-
istics [7].
With an N -bit input code assumed to be of the form N = P + Q, the resis-
tor string is composed of 2P resistors and the interpolation amplifier requires
2Q differential transistor pairs, each having their source nodes connected to
the corresponding current source. Two consecutive voltages, V01 and V02 , of
72 Data Converters, Phase-Locked Loops, and Their Applications

the resistor string are selected according to the decoding of the P MSBs and
connected to the interpolation amplifier by switches controlled by the Q LSBs.
All the inputs of the interpolation amplifier, except the first one which is driven
by V01 , can be switched to either V01 or V02 .
In general, the output voltage representing the DAC input code can be
obtained as
V02 − V01
V0 = V01 + q (3.65)
2Q
where V02 is greater than V01 and q is the decimal equivalent of the Q LSBs.
Both the resistor string and the interpolation sections are inherently mono-
tonic, and the monotonicity of the entire DAC is related to the operation
principle consisting of adding the value interpolated from V01 and V02 to the
voltage V01 .
Let us assume that all the inputs of the interpolation amplifier are initially
connected to V01 . The negative feedback from the amplifier output forces V0
to be equal to V01 and all the differential transistor pairs become balanced.
Furthermore, all differential transistor pairs are actively loaded with the same
current mirror, whose output current should be the same as the input current.
By incrementing the Q LSBs by one, one of the interpolation amplifier
inputs is switched from V01 to V02 . The drain current flowing through the cor-
responding input transistor is then decreased by △ID . The negative feedback
provided by the amplifier responds to this imbalance by inducing an increase
in △V0 in the output voltage, where △V0 is equal to (V02 −V01 )/2Q . The drain
current through each of the transistors with the gates connected to V0 , except
the transistor forming a differential stage with the transistor connected to V02
and whose drain current is increased by △ID , is augmented by △ID /3 due
to the variations in their gate-source voltages. Because the input and output
currents of the current mirror are to be maintained equal, the drain current
through each of the input transistors connected to V01 is increased by △ID /3.
In general, for a given value of the P MSBs, the interpolation controlled
by the Q LSBs is realized to allow variation in the output voltage from V01 to
V01 + (2Q − 1)(V02 − V01 )/2Q in a step of (V02 − V01 )/2Q .
Due to the transistor sizes required to determine the transconductances
in the differential stages of the interpolation amplifier, the effect of parasitic
capacitances becomes critical as the number P of LSBs exceeds 8. Taking into
account the fact that the converter linearity is also limited by mismatches in
the resistor string, the maximum resolution of a DAC including a resistor-
string network followed by an interpolating amplifier stage should be on the
order of 16 bits.
The aforementioned hybrid DAC uses an amplifier in the interpolation
stage. To achieve a high resolution, the amplifier should have a large common-
mode rejection ratio to maintain the accuracy over the entire input range and
a low offset voltage. An alternative design solution can consist of combining a
resistor-string network with a capacitor array DAC. The resulting DACs can
exploit the operation principles of switched-capacitor circuits to reduce the
Nyquist Digital-to-Analog Converters 73

effect of the amplifier offset voltage and to achieve a bipolar conversion with
a single reference voltage. In addition, the operation of the required amplifier
is not affected by common-mode input signals.
φ C/16 φ
2 1
V REF

φ
1

32C φ
2

16C 8C 4C 2C C C
φ
1

φ
− 2
V0
+

V REF

R/2

0 8
MUX

1
R

7
φ 0
MUX

1 R
φ 1
2
6
b1
b2 R

b3 5
b4
b5 R

b6 4

b7 R

3
b8
R

b9 2

R/2

FIGURE 3.31
Circuit diagram of a bipolar hybrid DAC with a 3-bit resistor-string LSB
network and a 5-bit binary-weighted capacitor MSB array.

The circuit diagram of a bipolar hybrid DAC is depicted in Figure 3.31.

It is based on the voltage-scaling and charge-scaling principles [8]. This DAC
structure features a resolution of 8 bits plus the sign bit and has the advantage
of performing a bipolar conversion with only a single reference voltage. The
input code is supposed to be in two’s complement format, which is commonly
found in DSP applications.
The absolute value of the two’s complement representation equivalent to a
negative value is obtained by first inverting all the bits, and then adding one
to the result. For the realization of the first step, it is usual to perform the
74 Data Converters, Phase-Locked Loops, and Their Applications

exclusive OR operation on the sign bit, b1 , and each of the remaining bits, b2 −
b9 . To implement the second step, the DAC is designed such that the output
swings associated with positive and negative input codes can appear to be,
respectively, shifted upward and downward by an offset voltage corresponding
to 1/2 LSB. The MSBs of the input code are applied to a 5-bit binary-weighted
capacitor array, while the remaining bits are used to control a 3-bit resistor-
string network with the topmost and bottommost resistors chosen to have the
value of R/2 so that the aforementioned offset voltages can be produced. The
operation of adding a value of −1/2 LSB to the output voltage of the DAC is
required to set the converter output for the zero input code to 0 V.

φ C/16 φ
2 1
V REF

φ
1

32C φ
2

16C 8C 4C 2C C C C/16
φ
1

φ
− 2
V0
+

V REF

0 8
MUX

1
R

7
φ 0
MUX

1 R
φ 1
2
6

b9 R
b8
b7 5

b6 R
b5
4
b4
R

b3 3

b2 R
b1
2

FIGURE 3.32
Circuit diagram of a bipolar hybrid DAC with a 3-bit resistor-string MSB
network and a 5-bit binary-weighted capacitor LSB array.

The DAC operation requires two nonoverlapping clock phases. In the case
of a positive input code, the multiplexer configuration defined by the state of
the sign bit, b1 , which is a logic low, allows the reference voltage sampling and
charge transfer to occur, respectively, during the clock phases φ1 and φ2 , and
the DAC operates as a noninverting gain stage. For a negative input code, the
Nyquist Digital-to-Analog Converters 75

state of b1 is a logic high, leading to the role interchange between φ1 and φ2 in

the input branch, and the DAC is now equivalent to an inverting gain stage.
The output voltage of the DAC will be expressed as
" ! #
b2 b3 b6 1 b7 b8 b9 11 1 VREF
V0 = VREF + 2 + ···+ 5 + 5 + 2+ 3 + 8 −
2 2 2 2 2 2 2 22 2 28
(3.66)
if b1 = 0, and
" ! #
b2 b3 b6 1 b7 b8 b9 11 1 VREF
V0 = −VREF + 2 + ··· + 5 + 5 + 2+ 3 + 8 −
2 2 2 2 2 2 2 22 2 28
(3.67)
if b1 = 1. Hence,

 V

 REF 27 b2 + 26 b3 + · · · + 21 b8 + 20 b9 if b1 = 0
2 8
V0 = (3.68)


− VREF 27 b + 26 b + · · · + 21 b + 20 b + 1 if b = 1

2 3 8 9 1
28
Note that the conversion is not affected by the dc offset voltage of the ampli-
fier. The DAC accuracy is mainly determined by the achievable component
matching.
Another approach for the hybrid-DAC design consists of using the MSBs
to control a resistor-string network and the LSBs to drive a binary-weighted
capacitor array. Figure 3.32 shows the circuit diagram of a bipolar hybrid DAC
with a 3-bit resistor-string MSB network and a 5-bit binary-weighted capacitor
LSB array. The input digital code is supposed to be in two’s complement
representation.
A set of node voltages is defined on the resistor string as the result of the
reference voltage division by resistors with equal values. After the MSB decod-
ing, two adjacent nodes of the resistor string are selected and connected to the
binary-weighted capacitors, depending on the decoded state of the remaining
LSBs. If the decoded state of an LSB is a high logic, the corresponding capac-
itor will be switched between the node with the highest voltage and ground;
and if it is a low logic, the capacitor switching will take place between the
lowest voltage and ground. In both cases, the initial position of the switches
and the polarity of the output voltage are determined by the sign bit, b1 .

3.6 Configuring a unipolar DAC for the bipolar conver-

sion
In general, DACs can be designed to operate in either a unipolar or bipolar
mode. But, unipolar DACs can be associated with a differential amplifier stage
to achieve conversions with a bipolar output-voltage range.
76 Data Converters, Phase-Locked Loops, and Their Applications
R1 R2
Vi2
V REF

b1 −
R3 V0
b2 Vi1
Unipolar
+
DAC

bN R4

FIGURE 3.33
Circuit diagram of a unipolar DAC with a bipolar output-voltage range.

The circuit diagram of a unipolar DAC with a bipolar output-voltage range

is shown in Figure 3.33. Here, the DAC uses an input code in the offset bi-
nary representation and an incoming two’s complement code is converted to
the offset binary format by inverting the MSB, b1 . Using the voltage divider
principle, we have
R4
V+ = Vi1 (3.69)
R3 + R4
and
R2 R1
V− = Vi2 + V0 (3.70)
R1 + R2 R1 + R2
PN
where Vi1 = k=1 (bk /2k ) and Vi2 = VREF . For the usual case of an amplifier
with a high dc gain, the relation V + = V − is exploited to express the output
voltage in the form
! N
R4 R2 X bk R2
V0 = 1+ − VREF (3.71)
R3 + R4 R1 2k R1
k=1

When R2 /R1 = R4 /R3 , the DAC output stage operates as a differential am-
plifier, and !
N
R2 X bk
V0 = − VREF (3.72)
R1 2k
k=1
The DAC output voltage depends on the resistor ratios. However, due to mis-
matches in the resistor ratios, the effect of common-mode signals on the con-
verter characteristics can become critical. Furthermore, the amplifier should
be designed to exhibit a low offset voltage.
An alternative design solution consists of using a differential stage with
more than one amplifier to improve the common mode rejection. In the special
case of DACs based on R-2R resistor network, a converter with a bipolar
output range can be realized as shown in Figure 3.34. From the analysis of an
R-2R network, the currents IA and IB can be expressed as
N
VREF X bk
IA = − (3.73)
2R 2k
k=1
Nyquist Digital-to-Analog Converters 77
RX
−VREF
R
b1
IA R R
b2 R−2R
−
network
V0
bN − +
IB
+

FIGURE 3.34
Circuit diagram of a bipolar R-2R ladder DAC.

and
N
VREF X bk
IB = − (3.74)
2R 2k
k=1

The output voltage of the DAC is given by

R
V0 = −R(IA − IB ) − VREF (3.75)
RX

Exploiting the sum formula for geometric series,1 it can be deduced that
N
!
VREF X 1 VREF 1
IA + IB = − =− 1− N (3.76)
2R 2k R 2
k=1

and
N
!
VREF X bk VREF 1
IA − IB = 2IA − (IA + IB ) = − −1 + − (3.77)
R 2k R 2N
k=1

This last expression without the term VREF /(2N R) is proportional to the
offset binary representation of the DAC input code. By choosing the value of
the resistor RX such that
RX = 2N R (3.78)
1 For the geometric series with the common ratio r, the sum S is given by
n
X 1 − r n+1
S= rk = 1 + r + r2 + · · · + rn =
k=0
1−r

and if the sum is taken starting at k = 1, we have

n
X r(1 − r n )
rk =
k=1
1−r
78 Data Converters, Phase-Locked Loops, and Their Applications

the DAC output voltage is reduced to

N
!
X bk
V0 = VREF −1 + (3.79)
2k
k=1

The performance of this DAC architecture depends on the achievable matching

between the resistors.
When an ac source is used as the reference voltage, it is amplified by
a factor determined by the digital input code. In this case, the converter
is then referred to as a multiplying DAC. Two-quadrant or four-quadrant
multiplications are performed, depending on whether the multiplying DAC is
designed for unipolar or bipolar conversion.

3.7 Algorithmic DAC

The algorithmic DAC operates according to a selection tree structure. It can
be efficiently implemented with less power dissipation and fewer circuit com-
ponents than other conversion architectures for a given resolution and band-
width [21].

φ
R
Buffer

V REF 1 Vr (k)
1
bk
2 C1 bk

φ φ
2 1 φ
R
C2 2
bk
1 bk
φ
Buffer 2

1 V (k)
0 φ
1
φ C3
R
l
bk
(a) (b)

FIGURE 3.35
(a) Circuit diagram and (b) clock timing of an algorithmic DAC.

Starting from the MSB, a reference voltage, VREF , is added or not to the
previous output, depending on the state (low or high) of the present bit, blk
(l = 1, 2). During the k-th cycle, the output voltage, V0 , is computed as

V0 (k) = V0 (k − 1) + blk Vr (k) (3.80)

Nyquist Digital-to-Analog Converters 79

where

V0 (0) = 0 (3.81)

VREF if k = 0
Vr (k) = Vr (k − 1) − V0 (k − 1) (3.82)
 otherwise.
2
At the end of N cycles, the analog output is obtained as the sum of the
voltages associated to each bit of the digital input code. An implementation
of the algorithmic DAC with its clock timing is shown in Figure 3.35. The
converter consists of three identical capacitors C1 , C2 , and C3 and two unity
buffers. Initially, the pulse signal, φR , is used to allow the capacitors C1 and
C3 to be charged by the initial voltages Vr (0) = VREF and V0 (0) = 0. The
charge transfer is controlled by two nonoverlapping clock signals, φ1 and φ2 ,
and the state of the bits, blk . For the high state of the bits, Vr (k − 1) is held
by C1 and V0 (k − 1) is updated because the charge stored on C2 during the
clock phase φ1 is redistributed between C2 and C3 during the clock phase φ2 .
In the case of low-state bits, the charge produced by V0 (k − 1) on C3 remains
unchanged and the update of Vr (k − 1) is achieved as the result of the charge
sharing between C2 , which was first connected to V0 (k − 1), and C1 .
However, it should be mentioned that component nonidealities (mismatch,
charge injection, clock feed-through) limit the resolution of the algorithmic
DAC to no more than 10 bits.

3.8 Direct digital synthesizer

Direct digital synthesis is a method that can be used to produce analog wave-
forms, such as square, triangular and sinusoidal signals, by generating a time-
varying signal in digital form and then performing a digital-to-analog conver-
sion. Direct digital synthesizers (DDSs) are also known as numerically con-
trolled oscillators. They find applications in communication systems (quadra-
ture synthesizers) and test equipment (arbitrary waveform generators), where
it is necessary to produce and control waveforms of various frequencies and
profiles.
The block diagram of a DDS is shown in figure 3.36. It consists of a
phase accumulator, a phase-to-amplitude converter (conventionally a read-
only memory (ROM) used as look-up table (LUT)), a digital-to-analog con-
verter (DAC) and a lowpass filter.
The phase accumulator is a digital integrator that is realized using a regis-
ter and an adder. The input binary number, M , represents the phase increment
that is added, at each clock pulse, to the data previously held in the phase
register. The N -bit phase accumulator steps through each of the 2N possible
80 Data Converters, Phase-Locked Loops, and Their Applications

N
N
M Σ Phase P LUT Lowpass
DAC Out
register ROM filter

CK

FIGURE 3.36
Block diagram of a direct digital synthesizer.

phase increment values before it overflows and the cycle begins again. The
overflow rate corresponds to the DDS output frequency that is given by
M · fCK
f0 = (3.83)
2N
where M is the binary tuning word, fCK is frequency of the clock signal, and
N is the length (in bits) of the phase accumulator.
The smallest incremental change in frequency, or the frequency resolution,
is of the form,
fCK
△f = N (3.84)
2
The output frequency of a DDS can range from fCK /2N (in the case where
M = 1) up to the Nyquist frequency fCK /2 imposed by the sampling theorem.
To reduce the power consumption and the size of the LUT ROM (or die
area), the output of the phase accumulator is truncated and only P most
significant bits are passed to the phase-to-amplitude converter or used to in-
dex the LUT ROM with 2P entries. The phase truncation results in a small
increase of the output phase noise, but it does not affect the frequency reso-
lution.

A DDS uses an addressing scheme with an appropriate LUT

ROM to produce samples of an arbitrary sinewave. The content
of the LUT for a sinewave with an offset B and a peak amplitude
A can be obtained as follows,
   
2πk 1
LU T (k) = B + A sin + (3.85)
2P 2
where ⌊ ⌋ denotes the floor operator and the range of the index
k is from 0 to 2P − 1.
The DDS can be designed to generate two quadrature output
signals by using the LUT ROM contents, especially, LU T (k)
and LU T (k + 2P /4) for the sine and cosine waves, respectively.
A square wave can be generated with no computational over-
head by exploiting the fact that the most significant bit of the
Nyquist Digital-to-Analog Converters 81

phase accumulator toggles periodically at one-half of the phase

represented by the accumulator. However, this square wave can
be corrupted by a phase jitter of one clock signal period.

Quarter wave symmetry in the sine waveform can be exploited

to design a DDS that uses a LUT ROM with reduced size. This is
achieved by storing the sine wave, sin(φ), only for 0 ≤ φ ≤ π/2,
instead of 0 ≤ φ ≤ 2π, and then using the two most significant
bits of the quantized phase angle to perform quadrant mapping
(or to deduce the remaining waveform samples). As a result,
only 2P −2 entries are required in the LUT ROM, leading to a
size compression ratio of 4-to-1 for the LUT ROM.

The output of the LUT ROM is quantized to the number of bits of the
DAC. However, this quantization results in an increase of the signal-to-noise
ratio. The resolution of the DAC is then typically 1 to 4 bits less than the
output word length of the LUT ROM so as not to significantly increase the
noise level.

DDSs are generally designed with N ranging from 24 to 32 bits and can
generate periodic waveforms at frequencies from less than 1 Hz up to 400 MHz
with 1-GHz clock signal. The DDS performance for a particular application
can be evaluated using the phase noise (in dBc/Hz), jitter (in degrees rms),
and spurious-free dynamic range (in dB) specifications.

3.9 Summary

Depending on the trade-offs between the power consumption, resolution, con-

version speed, and latency, Nyquist-rate DACs can be designed using parallel,
pipeline, or serial architecture.

Parallel DAC structures can require a high power consumption to meet the
speed and settling requirements of the amplifier, which is used to perform the
charge transfer or current summing. Pipeline DACs can help reduce the power
consumption and the spread of component values. However, this is achieved
at the cost of an increase in latency time. Serial DAC structures often require
a low circuit area, but they can be very slow. Hybrid or segmented DACs can
be adopted to reduce the spread of component values, and thereby the effect
of the amplifier loading on the converter performance.
82 Data Converters, Phase-Locked Loops, and Their Applications

3.10 Circuit design assessment

1. Analysis of R-2R DACs
A multiplying DAC can be implemented as shown in Figure 3.37.
R R
−VREF
I1 I2 I3
2R 2R 2R 2R
RF

b1 b1 b2 b2 b3 b3
−
IA V
0
+
IB

FIGURE 3.37
Multiplying DAC based on current-mode R-2R network.

−
R R V0
+
I1 I2 I3
2R 2R 2R 2R

b1 b1 b2 b2 b3 b3
VREF

FIGURE 3.38
DAC based on voltage-mode R-2R network.

The R-2R network generates a current that is proportional to the

input digital code and is converted by the feedback structure con-
sisting of the amplifier and resistor RF to the required voltage level.
Find the output voltage V0 as a function of the input digital code.
Show that the output resistance of the R-2R network is given by
3R
R0 = (3.86)
(3/2)b1 + (9/23 )b2 + (33/25 )b3 + (3/23 )b2 b3

To reduce the effects of nonlinear errors on the converter perfor-

mance, the DAC can be realized using the voltage-mode R-2R net-
work, as illustrated in Figure 3.37.
Verify that the output resistance of the R-2R network is constant
and equal to R.
Nyquist Digital-to-Analog Converters 83

Determine the output voltage V0 .

2. Implementation of the R-2R DAC using MOS transistors

Vi

Ii

I1 I2

VG
T1 T2
V

FIGURE 3.39
Current division principle based on two transistors.

The two-transistor circuit of Figure 3.39 can be used to divide an

input current Ii into two components, I1 and I2 . Assuming that V
and VG are chosen so that the transistors remain in the on-state,
show that
I1 W1 /L1
= (3.87)
I2 W2 /L2
where Wi and Li (i = 1, 2) are the width and length of the corre-
sponding transistors, respectively.

Current
reference

I REF

VB
RF

bN bN bN−1 bN−1 b1 b1
−
V0
+

FIGURE 3.40
Transistor implementation of a R-2R DAC.

Using the current division principle [22], it is possible to implement

an R-2R ladder using MOS transistors as shown in Figure 3.40.
To improve the linearity, the transistors are assumed to operate in
the triode region. The switches are realized using transistors driven
either by bk or bk .
84 Data Converters, Phase-Locked Loops, and Their Applications

Use SPICE simulations to verify that the small-signal equivalent

resistance seen between the drain and source terminals of the MOS-
FETs is not identical throughout the transistor network.
Ideally, each stage of the transistor network splits its input current
into two equal parts, that is,

I0,k = Ii,k /2 = bk 2−k IREF (3.88)

Due to transistor mismatches, the current division is affected by an

error of the form
∆I0,k = ǫk IREF (3.89)
Assuming that the requirementsP INL < 0.5 LSB and DNL < 1 LSB
are met, provided that max( k |bk ǫk |) < 1/2N +1, determine the
worst-case error for a converter resolution, N = 8 bits.
3. Segmented DAC

−VREF b6 b6 b5 b5 b4 b4

R
8

4
−
R
+ RF
3 xR

R IX
−
2 I3 I2 I1 V0
2R 4R 8R +
R

1
b3 b3 b2 b2 b1 b1

−VREF

FIGURE 3.41
Segmented DAC.

Consider the segmented DAC depicted in Figure 3.41, which is

based on resistor string and binary weighted resistors.
Nyquist Digital-to-Analog Converters 85

Assuming ideal amplifiers, determine x to realize a 6-bit segmented

DAC.
Express the output voltage, V0 , as a function of the input digital
code, bk , k = 1, 2, 3, 4, 5, 6.
Put the output voltage into the form
6
X bk
V0 = VF S
2k
k=1

where VF S is the full-scale output voltage to be determined.

Assuming that the DAC is designed to feature a slew rate, SR, of
0.75 V/µs, use the equation, fmax = 1/tmax , where tmax = △V0 /SR
and △V0 = VF S , to estimate the maximum data rate, fmax , for
VF S = 5 V.
4. Binary-weighted charge-scaling DAC

S2

N
2 C

S1
−
V0
2
N−1
C 2
N−2
C 2C C +

b1 b2 b N−1 bN

VREF

FIGURE 3.42
Binary-weighted charge-scaling DAC.

The circuit diagram of an N -bit binary-weighted charge-scaling

DAC is shown in Figure 3.42. A digital-to-analog conversion starts
with the discharge of all capacitors, and each switched capacitor is
then connected either to the ground or the reference voltage, de-
pending on the state of its corresponding bit.
With the assumption that the operational amplifier is ideal, verify
the following charge conservation equation.
N
X
△Q = CVREF 2N −k bk (3.90)
i=1
= 2N CV0 (3.91)

Deduce the expression of the output voltage, V0 .

86 Data Converters, Phase-Locked Loops, and Their Applications

In practical DAC implementations, the capacitors exhibit a varia-

tion of ±△C. Let VLSB = VREF /2N and use

|DN Lmax | = V0△C (100 · · · 0) − V0△C (011 · · · 1) − VLSB (3.92)

and

IN L(k) = V0△C (k) − V0 (k) (3.93)

where
C + △C VREF
V0△C (100 · · · 0) = 2N −1 (3.94)
C 2N
N
VREF C − △C X N −k
V0△C (011 · · · 1) = 2 (3.95)
2N C
k=2
 
△C VREF △C N −k
V0 (k) = 1+ 2 (3.96)
2N C

and
VREF N −k
V0 (k) = 2 (3.97)
2N
to show that
△C VREF
|DN Lmax | = (2N − 1) (3.98)
C 2N
and
△C VREF
IN L(k) = 2N −k (3.99)
C 2N
respectively. In the case of the DNL, it is assumed that the MSB
capacitor takes its maximum value, while the remaining capacitors
exhibit their minimum values.
Deduce the worst-case INL value given by |IN Lmax | = IN L(1).
Determine the number of bits, N , if the capacitor tolerance, △C/C,
is equal to ±0.5% and IN L = ±0.5 LSB.
5. Sensor signal conditioner
Consider the conditioner circuit of Figure 3.43 that is required to
make the sensor output suitable for further processing. The voltage
VDAC is provided by a digital-to-analog converter.
Assuming that the operational amplifiers are ideal, use

VA − VB VB − V0+
= (3.100)
R2 R1
Nyquist Digital-to-Analog Converters 87

+
−
2 V0
−

R1
R2
R1
C

R
−
R +∆R 3 +
A B V
0
+
I
R
R +∆R

−
D
1
+ RB

VDAC

FIGURE 3.43
Sensor signal conditioner.

and

VB − VA VA − V0−
= (3.101)
R2 R1
to verify that
 
2R1
V0 = V0+ − V0− = 1+ (VB − VA ) (3.102)
R2

where VB − VA = △R · I/2 and I = VDAC /RB .

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[20] K.-C. Kuo, and C.-W. Wu, “A switching sequence for linear gradient error
compensation in the DAC design,” IEEE Trans. Circuits Syst. II, vol. 58,
no. 8, pp. 502–506, Aug. 2011.
[21] K. Watanabe, G. C. Temes, and T. Tagami, “A new algorithm for cyclic
and pipeline data conversion,” IEEE Trans. on Circuits and Systems, vol.
37, no. 2, pp. 249–252, Feb. 1990.
[22] C. M. Hammerschmied and Q. Huang, “Design and implementation of
an untrimmed MOSFET-only 10-bit A/D converter with −79-dB THD,”
IEEE J. of Solid-State Circuits, vol. 33, pp. 1148–1157, Aug. 1998.
4
Nyquist Analog-to-Digital Converters

CONTENTS
4.1 Analog-to-digital converter (ADC) architectures . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.1.1 Successive approximation register ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.1.2 Integrating ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.1.3 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.1.4 Averaging ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.1.5 Folding and interpolating ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.1.6 Sub-ranging ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
4.1.7 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.1.8 Algorithmic ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.1.9 Time-interleaved ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
4.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.3 Circuit design assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

In general, analog-to-digital converters (ADCs) are required for any applica-

tion where an analog or continuous-time signal must be processed by digital
systems. A variety of architectures is available for the design of ADCs with
different characteristics, such as resolution, bandwidth, sampling frequency,
power consumption, latency, and chip area.
For the special case of Nyquist ADCs, the sampling frequency can be at
least two times the maximum frequency of the input signal. This converter
group includes, but is not limited to, successive approximation register (SAR)
ADC, integrating ADC, flash ADC, pipelined ADCs, and cyclic ADC. All
techniques for analog-to-digital conversion rely on at least one operation of
comparison between the input signal and a reference level. The flash ADC,
which uses one comparator for each comparison, exhibits a higher speed than
the SAR ADC, whose operation involves various comparisons realized by the
same comparator. Because of the parallelism of the flash ADC, the number of
comparators grows exponentially with the resolution, leading to an increase
in the power consumption and chip area, and a decrease in the bandwidth as
a result of an augmentation in the input capacitance. Some variations of flash
architecture, such as the folding and interpolating ADC, and pipelined ADC,
have been proposed in order to reduce the effect of some of these limitations.
In general, the trade-offs between the converter characteristics (speed, res-
olution, power consumption, size, linearity) play an important role in deter-
mining the better ADC architecture for a given application. For instance, a
significantly faster conversion is usually achieved at the price of a reduction in

91
92 Data Converters, Phase-Locked Loops, and Their Applications

the initial resolution. Due to the component matching requirement, the reso-
lution of a flash ADC is limited to 9 bits. SAR ADCs most commonly exhibit
a resolution in the range from 8 to 16 bits and provide a low power consump-
tion as well as a small IC size. They are ideal for many real-time applications.
On the other hand, resolutions up to 18 bits can be achieved by integrating
ADCs, which can work well also with low-level signals. However, this architec-
ture generally has a low conversion speed and is only suitable for applications
such as portable instruments, where the signal bandwidth remains low.
ADC architectures offer different compromises between the performance
metrics. They are then chosen to be consistent with the specifications of the
target application.

4.1 Analog-to-digital converter (ADC) architectures

Generally, trade-offs between resolution, power consumption, chip area size,
conversion time, static performance, and dynamic performance play an impor-
tant role in the choice of the proper ADC architecture for a given application
(data acquisition, measurement, voiceband audio, image and video, wireless
communication systems).

4.1.1 Successive approximation register ADC

Successive approximation register (SAR) ADCs can be designed using either
a single-ended architecture or a differential architecture.

• Single-ended architecture

The block diagram of a SAR ADC is shown in Figure 4.1. It consists of a

digital control logic, a clock generator, a comparator, a successive approxima-
tion register (SAR), a digital-to-analog converter (DAC), and an output buffer
based on latches. The operations of resetting the SAR, enabling the clock sig-
nal, cycling each bit, and halting the clock signal at the end are conducted by
the control logic.
For positive input signals, the operation principle of a SAR ADC can be
based on the algorithm illustrated in Table 4.1. The SAR ADC exploits the
concept of the binary search algorithm to find the nearest digital code to an
input voltage.
The principle is to compare the analog version of various DAC digital
codes with the input analog signal. Starting with the DAC most-significant
bit (MSB), each bit is initially set to the logic high state. If the signal to be
converted is higher than the one generated by the DAC and which actually
represents one-half of the full scale (FS), the initial value of the MSB is main-
Nyquist Analog-to-Digital Converters 93

Control

Reset
Status
logic

EOC
Start/Stop

Clock

Latch

CK
generator

Analog
input + Data
SAR MSB
−
Comparator Output Digital
buffer output

DAC LSB

FIGURE 4.1
Block diagram of a SAR ADC.

FS=1
Analog input

3/4

1/2

DAC output
1/4
1 0 1
Time index
MSB Bit 2 Bit 3

FIGURE 4.2
Three-bit successive approximation of the input signal.

tained and the comparison procedure continues with the next DAC output
signal of (3/4) FS. Otherwise, the MSB is reset to the logic low state. In this
case, the output signal of the DAC required for the next comparison step cor-
responds to (1/4) FS. This successive conversion (see Figure 4.2) continues
until the least-significant bit (LSB) is reached, that is, the DAC output is
within ±(1/2) LSB of the input voltage. For an N -bit ADC with 2N levels of
resolution, the conversion is carried out in N clock periods.
The SAR of Figure 4.3 is built with two sets of N -bit registers (control
and data registers), the function of which is to store and guess the conversion
result, respectively. Each flip-flop in the data register is sequentially set by
the control register to a state such that on the next rising edge of the clock
pulse, the current value of the input data is transferred to the output. This
approach has the advantage of simplifying the layout design, which consists of
reproducing each bit cell containing two D flip-flops. However, this approach
can require a large chip area (19 D flip-flops for an 8-bit SAR). Furthermore,
while the flip-flops of the control register use the same clock signal, the clock
input of a given flip-flop of the data register is obtained from the next flip-
94 Data Converters, Phase-Locked Loops, and Their Applications

TABLE 4.1
The Computation Scheme of a SAR ADC

Begin
1. Initialization:
Acquire a sample of Vi
Specify the initial time index, k ← 1
Set the most significant bit, b1 , to the logic high and clear the
remaining bits
Assign Vr1 = VF S /2
2. Repeat
(a) Compare Vi with Vrk
If Vi ≥ Vrk then
return the actual logic state of the bit under test
else
invert the logic state of the bit under test
End If
(b) Adjust the time index, k ← k + 1
(c) Set the bit bk to the logic high
(d) Update Vrk
If Vi ≥ Vrk−1 then
VF S
Vrk ← Vrk−1 + k
2
else
VF S
Vrk ← Vrk−1 − k
2
End If
until the DAC output is within ±(1/2) LSB of the input voltage, Vi
End

flop output. As a result, the SAR output can be affected by a three-flip-

flop propagation delay in the worst case. If this delay is comparable to the
DAC settling time or the comparator response time, its effect can become
significant [1, 2].
The design of Figure 4.4 makes use of a single register with N + 1 JK flip-
flops for the generation of the digital code and the end of conversion signal. The
k-th cell consists of a JK flip-flop and two OR gates. The input terminals are
labeled Reset and Data, and the N -bit code and End represent the output
variables. The JK flip-flops are cleared by Reset = 1, and then Reset = 0 is
maintained. A 1 at the Data input shows that the analog version of the SAR
Nyquist Analog-to-Digital Converters 95
Reset
PR PR PR PR PR PR
D Q D Q D Q D Q D Q D Q EOC

Q Q Q Q Q Q
CLR CLR CLR CLR CLR CLR

CK

Data

PR PR PR PR PR
D Q D Q D Q D Q D Q

Q Q Q Q Q
CLR CLR CLR CLR CLR

b1 b2 b3 bN

FIGURE 4.3
Circuit diagram of a SAR using two sets of registers (b1 is the MSB and bN
is the LSB).

b1 bk bN

CK
1
J Q J Q J Q J Q EOC

K Q K Q K Q 0 K Q
CLR CLR CLR CLR

Reset
Data

X
k X
1

FIGURE 4.4
Circuit diagram of a SAR with a reduced number of registers.

code provided by the DAC is greater than the input signal and the current
approximation must be reduced.
A given flip-flop is initialized to 0 and held in this state as long as Xk = 1.
On the other hand, its behavior will be described by referring to the truth
table of a JK flip-flop if Xk = 0 (see Appendix A). The output of the flip-flop
is changed to 1 for J = 1. This state is held during the next clock pulse if
Data = 0, otherwise the current output bit is modified to 0. As the next
bit is set to 1, Xk will take the value 1 and the flip-flop output state will be
maintained. At this step, a further change can only be initiated by the Reset
signal.
Because capacitors are easily fabricated in CMOS technologies, the charge
redistribution technique is generally adopted in the SAR ADC implementa-
tion [3]. Figure 4.5 shows the block diagram of a SAR ADC exploiting the
charge redistribution on weighted capacitors. Note that the extra LSB ca-
96 Data Converters, Phase-Locked Loops, and Their Applications

2
N−1
C 2
N−2
C 2C C C’ +

b1 b2 b N−1 bN

Vi
Latches

VREF D Output
Q code
CK
SOC In
Reset SAR
CK EOC

FIGURE 4.5
Block diagram of a charge-redistribution unipolar SAR ADC (C ′ = C).

Reset

SOC

EOC

Output
code Data i Data i+1

FIGURE 4.6
Timing diagram of the SAR ADC.

pacitor, C ′ , of value C is required to make the total value of the capacitor

array equal to 2N C, where N is the number of bits, so that a binary voltage
division can be performed by switching any weighted capacitor of the DAC.
The timing diagram of the SAR ADC is illustrated in Figure 4.6. A start-of-
conversion (SOC) signal is used to initiate the conversion process, while the
end-of-conversion (EOC) signal is asserted by the SAR to indicate the con-
version completion. Before each conversion cycle, the Reset signal is enabled
to initiate the discharge of capacitors through the ground connection and the
reset of all the bits in the SAR to the logic low. Note that a clock signal is gen-
erally necessary for proper operation of the SAR ADC, even if it does not have
to be synchronized with other control signals. Its frequency depends on the
conversion resolution and speed. The conversion process consists of a sequence
of three operations: the sample phase, the hold phase, and the redistribution
phase (or bit testing mode).
In the sample phase, all capacitors are connected to the input voltage,
Vi , and the comparator feedback switch is closed. The voltage VC across the
capacitor array at the end of the sampling period is actually

VC = Vi − Vof f (4.1)
Nyquist Analog-to-Digital Converters 97

Start
SOC = 1

1− Reset
2− Input sample acquisition
1,V −
0
k V DAC

b k = 1, V − V − + VREF /2 k

No
V + −V −> 0

Yes b k = 0, V − V − − VREF /2 k

k k+1

No
k>N

Yes

End
EOC = 1

FIGURE 4.7
Binary search algorithm of the SAR ADC.

where Vi is assumed to be positive, and the offset voltage, Vof f , plays the role
of the comparator threshold voltage.
During the hold phase, the comparator feedback switch is open and the
bottom plates of capacitors are connected to ground. Because the charge on
the top plate is conserved, the top plate potential goes to −VC and the voltage
applied to the negative terminal of the comparator can be expressed as

V − = −VC (4.2)

The input node is now connected to the reference voltage, VREF , instead of
the input voltage.
The redistribution phase begins with the determination of b1 or MSB. The
largest capacitor is then connected to the reference voltage and the equivalent
circuit of the capacitor array seen from the input node is a voltage divider
consisting of two equal capacitors 2N C. Hence, the voltages at the negative
and positive terminals of the comparator are given by

V − = VREF /2 − VC = −Vi + Vof f + VREF /2 (4.3)

+
V = Vof f (4.4)

The logic state of the MSB depends on the sign of the voltage difference,
98 Data Converters, Phase-Locked Loops, and Their Applications

V + − V − , provided by the comparator. It will remain unchanged, that is,

b1 = 1, if V + − V − > 0, or equivalently Vi > VREF /2. But, if V + − V − < 0,
then Vi < VREF /2, and the MSB will be set back to the logic low, b1 = 0, by
switching back the largest capacitor to the ground. The determination of the
bit from b2 to bN also proceeds in the same manner. The bottom plate of the
capacitor associated with the bit bk is connected to the reference voltage, and
the previous value of V − is increased by VREF /2k as a result of the voltage
division carried out by the capacitor array. The final logic state is assigned to
the bit under test, and the SAR either maintains the capacitor connected to
VREF or connects it to the ground, depending on the polarity of V + − V −
detected by the comparator. At the end of the conversion, we have
!
− b1 b2 bN −1 bN
V = −Vi + VREF + 2 + · · · + N −1 + N (4.5)
2 2 2 2

and the value of V − should be as close to zero as possible. The valid output
code can then be stored in the output buffer consisting of latches.
The conversion process of the charge-redistribution unipolar SAR ADC
0
is based on the algorithm shown in Figure 4.7, where VDAC = −Vi + Vof f .
Furthermore, the code transitions of the transfer characteristic actually occur
at k LSB, where k is an integer. However, the quantization error will be
reduced if the code transitions can arise at k/2 LSB. This can be achieved
by switching the lower plate of the capacitor C ′ to VREF /2 rather than the
ground after the sample phase.

2
N−1
C 2
N−2
C 2C C C +

b1 b2 b N−1 bN

VREF
Latches

Vi+ VCM D Output

Q code
CK
SOC In
Reset SAR
CK EOC

FIGURE 4.8
Block diagram of a charge-redistribution bipolar SAR ADC.

To allow the conversion of positive and negative input voltages, the capac-
itor switching scheme of the charge redistribution SAR ADC must be some-
what modified. Figure 4.8 shows the block diagram of a charge-redistribution
bipolar SAR ADC, whose operation involves the next steps.
Nyquist Analog-to-Digital Converters 99

In the sample phase, the largest capacitor is connected to the reference

voltage, VREF , while the remaining capacitors are connected to the input
voltage, Vi , and the comparator feedback switch is closed. The charge QC
stored on capacitors is given by

QC = 2N −1 C(Vi + VCM − Vof f ) (4.6)

During the hold phase, the comparator feedback switch is open and the
bottom plates of capacitors are now switched to the ground. Because the
capacitor array is equivalent to a voltage divider consisting of two equal ca-
pacitors, the voltage applied to the negative terminal of the comparator now
becomes
V − = −(Vi + VCM )/2 + Vof f (4.7)
The input node is actually connected to the reference voltage, VREF , instead
of the input voltage.
The redistribution phase begins with the determination of b1 or MSB. The
SAR is initialized so that the MSB is set to the logic high. With the assumption
that the comparator threshold is modeled as an offset voltage, Vof f , in series
with the positive input, we have

V + = Vof f (4.8)

In the case where V + − V − > 0, that is, if Vi > 0, the comparator output will
be a logic high and the state of the MSB will remain unchanged. However,
if V + − V − < 0, then Vi < 0, and the comparator output will be a logic
low. The SAR is then configured to set the first bit of the output code to
a logic low and switch the MSB capacitor from the ground to VREF . Here,
the MSB is used as a sign bit. For the determination of each of the remaining
bits, the corresponding capacitor is switched from the ground to VREF and the
comparison trial proceeds as in the unipolar case. At the end of the conversion,
the voltage V − can be written as
!
− Vi + VCM VREF b2 bN −1 bN
V =− + −b1 + + · · · + N −2 + N −1 (4.9)
2 2 2 2 2

where VCM denotes the common-mode voltage. An appropriate choice of VCM

is useful for handling bipolar input signals. It can be assumed that the con-
verter input signal is biased about

VCM = VREF + VLSB = VREF (1 + 1/2N ) (4.10)

where VLSB = VREF /2N . Hence, the converter features a two’s complement
output coding with the zero code, which is actually 1/2 LSB above the mid-
scale. It should be noted that the converter full-scale still exhibits a dynamic
range of VREF as in the case of the charge redistribution unipolar SAR ADC.
An alternative design approach can consist of modifying the switching
100 Data Converters, Phase-Locked Loops, and Their Applications

scheme of the SAR ADC to control the connection between the reference volt-
+ −
age terminal and either VREF for a positive input or VREF for a negative input.
The sample phase and hold phase remain similar to the ones of the unipolar
structure, except that the sign bit should be detected by the comparator just
before the redistribution phase and used to select the suitable reference volt-
age. This latter is required for the determination of the remaining bits of the
output code.
The accuracy of the charge redistribution SAR ADC is mainly limited by
the achievable capacitor matching. Because the settling time of the comparator
increases as the minimum overdrive signal becomes smaller for high resolu-
tions, the time delay of the comparator appears to be a critical limiting factor
in the achievable speed of the data conversion. Furthermore, the stability re-
quirements of the comparator should be specified, taking into account the fact
that the offset voltage estimation is performed in the unity-gain configuration.

• Effects of capacitance mismatches on linearity characteristics

To improve the matching accuracy, large capacitors are generally realized

by combining identical unit capacitors. The j − th capacitor in the SAR ADC
can be modeled as,

Cj = 2N −j C + δN +1−j j = 1, 2, · · · , N (4.11)

where C is the unit capacitor and δj is the error term. Assuming that the error
distributions of unit capacitors are independent and identically distributed
Gaussian random variables, the mean and variance of the error terms can be
expressed as,
2 N −j 2
E[δN +1−j ] = 0 and E[δN +1−j ] = 2 σ (4.12)

where σ is the standard deviation of the unit capacitor.

Given a DAC digital input, X, the corresponding analog output provided
by the N -bit capacitive-array DAC can be written as,
N
X
C + δ1 + (2N −j C + δN +1−j )bN +1−j
j=1
VDAC (X) = N
VREF (4.13)
X
2N C + δ1 + δN +1−j
j=1

where the value of bN +1−j is either 0 or 1, the input X corresponds to the

code b1 b2 · · · bN , and VREF is the reference voltage.
Capacitance mismatches can affect the SAR ADC accuracy parameters:
integral nonlinearity (INL) and differential nonlinearity (DNL) that are espe-
cially useful in the high-resolution applications.
Nyquist Analog-to-Digital Converters 101

The INL specification due to capacitance mismatches can be defined as

follows:
VDAC,real (X) − VDAC,ideal (X)
IN L(X) = (4.14)
VLSB
VDAC (X) − VDAC (X)|δj =0
= (4.15)
VLSB
where VLSB = VREF /2N . The MSB is found out by the first comparison
without any capacitor switching. Hence, its determination is not affected by
capacitance mismatches.
The maximum INL value is obtained for the code transitions that are
performed by switching the largest number of capacitors. Assuming that the
mismatch error terms in the denominator of (4.13) can be neglected, it can
then be shown that
" N −1
! #
1 X 1
E{[VDAC,real (X) − VDAC,ideal (X)]2 } = E 2N δj2 V2
2 REF
2 j=1
C
 
1 (2N − 1)σ 2 1 2
= E N +1 V
2 2N −1 C 2 REF
σ2 2
≃ N 2 VREF (4.16)
2 C
The variance of the maximum INL value can be obtained as,
!s √
1 σ2 2 σ 2N
σIN L,max ≃ V ≃ (4.17)
VLSB 2N C 2 REF C

The INL specification provides a measure of how closely the ADC output
matches its ideal response.
The definition of the DNL specification can be stated as follows,
DN L(X) = IN L(X) − IN L(X − 1) (4.18)
VDAC,real (X) − VDAC,real (X − 1)
= (4.19)
VLSB
The maximum DNL value is expected to occur at the transition between
the digital codes X = [10 · · · 0] and X − 1 = [01 · · · 1]. Assuming that the
determination of the MSB is not affected by capacitance mismatches, we arrive
at
!v
u " N −1
! #
1 u 1 X 1
σDN L,max = tE δ2 V2
VLSB 22N j=1 j C 2 REF
!s √
1 σ2 2 σ 2N
≃ V ≃ (4.20)
VLSB 2N C 2 REF C
102 Data Converters, Phase-Locked Loops, and Their Applications

A DNL specification of greater than 1 LSB may indicate non-monotonicity,

that is not desirable for control and video applications. An ADC is said to
be monotonic when the output code always increases as the input gets larger
and always decreases as the input is reduced.

• Calibration

Due to mismatches of passive components, resolutions higher than 12 bits

can only be realized by means of self-calibrating converters [4]. This technique
is illustrated with the ADC shown in Figure 4.9. The data conversion, which is

2
N−1
C 2
N−2
C C CX CY +
l l l
b 1 b 2 b N Sub−DAC
Start

VREF VREF
Vi
Calibration
DAC
VREF Switch Switch
array 1 array 2

Load
In
Load SAR Shift
Start SAR Register
Shift
Σ
Out Clear
EOC

Shift
Control RAM
CK logic In
Calib Start Load
Out
R/W
Address

FIGURE 4.9
Block diagram of a self-calibrating SAR ADC. (Adapted from [4], ©1983
IEEE.)

achieved in three steps, is based on the charge redistribution. First, the reset
switch is closed and the comparator is configured as a unity gain buffer. The
top and bottom plates of capacitors are then connected to the virtual ground
and input voltage, respectively. During the next phase, the reset switch is
open while the bottom plates are switched to the ground. Due to the charge
conservation, the potential at the top plates is changed from Vi to −Vi . The
last operation consists of finding the digital version of the analog input sig-
nal. The conversion process starts with the determination of the MSB. The
bottom plate of the largest capacitor is connected to VREF . The connection
will be maintained if the comparator output is high. Otherwise, the capaci-
tor is switched to the ground. The following MSB and the remaining bits are
determined in the same way. The MSBs are resolved by the binary weighted
capacitor DAC. The resistor-string DAC, which is connected to the coupling
Nyquist Analog-to-Digital Converters 103

capacitor CX , provides the LSBs. Basically, it is not affected by the differential

nonlinearity.
Ideally, the voltage contribution of the binary-weighted capacitor DAC at
the comparator input is given by
N
VREF X j−1 l
V = 2 bN +1−j (4.21)
2N j=1

where VREF is the reference voltage and blN +1−j (l = 0, 1) is the logic value of
the (N + 1 − j)-th bit. Due to the fluctuations of the IC fabrication process,
the value of a weighted capacitor can be written as

Cj = 2j−1 C(1 + ǫj ), j = 1, 2, · · · , N, (4.22)

where ǫj denotes the matching error and C is the unit capacitor, which is the
ratio of the total capacitance CT to 2N , that is,
CT
C= (4.23)
2N
The voltage V then becomes
N
VREF X
V̂ = Cj blN +1−j (4.24)
CT j=1

Substituting Equations (4.22) and (4.23) into Equation (4.24), we obtain

N
VREF X j−1
V̂ = 2 (1 + ǫj )blN +1−j (4.25)
2N j=1

The error voltage can be computed as

N
X
△V = V̂ − V = Vǫj blN +1−j (4.26)
j=1

where
VREF j−1
Vǫj = 2 ǫj (4.27)
2N
The calibration stage is necessary for the reduction of nonlinearities intro-
duced by the capacitor mismatches. Starting from the largest capacitor to the
smallest one, the different error contributions are estimated. For a given ca-
pacitor Ck , this is achieved first by connecting VREF to all capacitors except
Ck . Then, the charge is redistributed by switching all capacitors except Ck to
the ground. It follows that the charge stored at the top plate of the capacitors
is
△Q = VREF (2Ck − CT ) (4.28)
104 Data Converters, Phase-Locked Loops, and Their Applications

Substituting Equations (4.22) and (4.23) into Equation (4.28), it can be shown
that
△Q = CVREF 2k ǫk (4.29)
and the corresponding residual voltage is given by
△Q
Vxk = = 2Vǫk (4.30)
CT
Starting from the MSB capacitor, the residual and error voltages can be com-
puted as

 VxN

 if k = N
 2 
Vǫk = 1 XN (4.31)

 Vxk − V  otherwise.

2 ǫj
j=k+1

The correction signals are obtained from the digital version of the residual
voltages. A random access memory (RAM) is used to store the error voltages
Vǫj , which are estimated during the calibration cycle carried out just after the
converter power-up. If the k-th bit assumes the high level, the error Vǫk will be
added to the ones accumulated from the MSB through the (k − 1)-th bit and
the result is stored in the accumulator. Otherwise, Vǫk is discarded and the
previous error voltage contained in the accumulator remains unchanged. The
accumulator output is then converted by the calibration DAC into an ana-
log signal, which is summed with the appropriate sign to the output voltage
of the binary-weighted capacitor DAC. The calibration is equivalent to the
cancelation of the error voltages due to capacitor mismatches from the cor-
responding ADC output signal during the normal conversion cycle. It works
well provided the linearity error on the coupling capacitor CX = C is less
than 1/2M for an M -bit sub-DAC. In the layout, CX should preferably be lo-
cated near the center of the array to counteract the effect of fabrication errors.

• Differential architecture

In a conventional singled-ended SAR ADC, the reference voltage VREF is

used to digitize the input signal that is comprised between 0 and VREF . The
input signal range can be extended from −VREF to VREF , equivalent to an
absolute range of 2VREF , by using a SAR ADC with differential switched-
capacitor (SC) DACs.
The circuit diagram of a SAR ADC with differential SC DACs is shown
in Figure 4.10, where Vi+ and Vi− are the differential sampled-and-held input
voltages, VCM represents the common-mode voltage and the reference voltages
+ −
can be defined as, VREF = VCM + VREF /2 and VREF = VCM − VREF /2. It
consists of two SC DACs, a latched comparator, and the necessary SAR logic
to determine the switching sequence.
Each conversion starts with a sampling phase during which the input sig-
nal and the common-mode voltage are connected to the SC DACs. At the
Nyquist Analog-to-Digital Converters 105
S
Vi+

V+
REF

S
2 N−1 C 2 N−2 C 2 2C 2C C C N

SC DAC Comparator
& latch
S −
VCM SAR &
Output
+ output buffer
S code
Enable CK
SC DAC

2 N−1 C 2 N−2 C 2 2C 2C C C φ
S
N
−
VREF

Vi−
S

FIGURE 4.10
Circuit diagram of a SAR ADC with differential SC DACs.

VDAC + VDAC −

Sampling Comversion

CK

Vi+

VCM

Vi−
Output code 1 1 0 1 1 0

FIGURE 4.11
Waveforms of the SAR ADC with differential SC DACs.

beginning of the conversion phase, the input signal and the common-mode
voltage are disconnected. The DAC capacitors are then successively switched
between the reference voltages or the ground, starting from the MSB. The
voltages applied at the comparator inputs is determined by the difference be-
tween the charge stored during the sampling phase and the one related to the
reference voltages. Hence,

+ N
X
VREF
V + = −Vi− + VCM + 2j−1 bN +1−j (4.32)
2N j=1
106 Data Converters, Phase-Locked Loops, and Their Applications

and

− N
X
VREF
V − = −Vi+ + VCM + 2j−1 bN +1−j (4.33)
2N j=1

where V + and V − denote the comparator inputs, and the output bits, bN +1−j ,
are determined after each comparison. Waveforms of the SAR ADC with dif-
ferential SC DACs are shown in Figure 4.11, where VDAC + and VDAC − rep-
resent the reference voltage contributions to the SC DAC outputs, in order to
illustrate an example of the conversion process.

• Split capacitor array

V VCM

S CS

2 K−1 C 2C C 2 N−K−1 C 2C C C
S

VREF

V
i
S
MSB LSB

FIGURE 4.12
Circuit diagram of the SC DAC with a split capacitor CS .

V VCM

S
C

2 K−1 C 2C C 2 K−1 C 2C C

V
REF

V
i
S

FIGURE 4.13
Circuit diagram of the SC DAC with a unit split capacitor.

The major limitation of the SAR ADC speed is related to the RC time
constant of the comparator input network. For a conventional binary-weighted
SC DAC, the total capacitance increases exponentially with the resolution in
number of bits.
One solution to reduce the total capacitance consists of using split
DACs [5], as shown in Figure 4.12, where V denotes the DAC output (or
Nyquist Analog-to-Digital Converters 107

comparator input). For a DAC with an N -bit split capacitor array consisting
of a K bit MSB section and an N − K bit LSB section joined together by a
split capacitor CS , we have

N
X
CLSB = C + 2j−K−1 C = 2N −K C (4.34)
j=K+1
K
X
CMSB = 2j−1 C = (2K − 1)C (4.35)
j=1

CS · CLSB 2N −K
=C and CS = C (4.36)
CS + CLSB 2N −K − 1

where CLSB and CMSB are the total capacitances of the LSB and MSB ca-
pacitor array sections, respectively. The DAC output voltage can be expressed
as
X
K 
2j−1 bK+1−j C
j=1
V = VCM − Vi + VREF
CS CLSB
CMSB +
CS + CLSB
 XN 
CS
2j−K−1 bN +K+1−j C
CS + CLSB
j=K+1
+ VREF (4.37)
CS CLSB
CMSB +
CS + CLSB

Note that the LSB contribution is scaled by the voltage ratio of the capacitive
divider consisting of CS and CLSB . It then follows that

 K
X N
X 
VREF
V = VCM − Vi + 2N −K 2j−1 bK+1−j + 2j−K−1 bN +K+1−j
2N j=1 j=K+1
(4.38)

In practice, due to the non-integer value of CS and IC process limitations, it is

difficult to match the capacitors. Furthermore, the split DAC can be affected
by the nonlinearity distortion, that is caused by the parasitic capacitances at
the terminals of CS .
Alternatively, the split DAC can be realized with a unit split capacitor, as
illustrated in Figure 4.13. However, the suppression of the dummy capacitor
C introduces a gain error of 1 LSB, that can be compensated by an adequate
digital calibration. The compensated output code is generated by adding the
pre-measured digital error codes to the raw output code of the SAR ADC.
108 Data Converters, Phase-Locked Loops, and Their Applications

4.1.2 Integrating ADC

By using time to quantize a signal, which represents the integral or average of
an input voltage over a fixed period of time, an integrating ADC can exhibit
good linearity performance and high-frequency noise rejection. In comparison
with a successive approximation converter, the integrating ADC is simple, low
cost, and slow. Generally, its speed is approximately 500 times slower than
the one of a typical successive approximation converter. Integrating ADCs can
be implemented using single-slope, dual-slope, or multiple-slope architectures.
The primary advantage of a dual-slope ADC over a single-slope architecture is
that the final conversion result is insensitive to errors in the component values.
A multiple-slope ADC still features the advantages of a dual-slope converter,
but its conversion speed can be greatly increased at the cost of extra hardware
complexity.
The dual-slope architectures are suitable for digitizing low bandwidth sig-
nals in instrumentation devices such as the digital multimeter, which require
a high resolution (10 to 20 bits or 3 21 to 5 21 digits) and a low conversion speed
in the range of 100 sps (samples per second).
The dual-slope ADC, as shown in Figure 4.14, uses an analog integrator
with switched inputs, a comparator, a control logic, and a counter. Figure 4.15
shows the conversion timing of the converter. The input voltage is assumed
to be positive.
Reset

Vi R
VX − Comparator

−VREF − VC
V0
+
+

Integrator CK

Control logic
CK
Digital
output
Counter
Q S CLR

Q R

Q S

Q R
Carry

FIGURE 4.14
Circuit diagram of a dual-slope ADC.

The operation of the dual-slope ADC starts with a reset phase, which con-
sists of shorting the capacitor C to drive the integrator output to zero and
clearing the counter, followed by the input signal integration phase and the
reference signal integration phase.
Nyquist Analog-to-Digital Converters 109

Reset
0 t
VX
Vi
0 t
− VREF

V0
Reset Charging Discharging

Tc Td
0 t

FS
VC
1

0 t

FIGURE 4.15
Conversion timing of the dual-slope ADC.

− Input signal integration phase

After the reset phase, the unknown input signal Vi is applied to the integrator,
while at the same time the process of counting clock pulses is started. The
integrator output voltage is given by
Z
1 t
V0 (t) = − Vi (t)dt (4.39)
τ 0
where τ = RC is the time constant of the integrator. The voltage Vi is then
integrated for a duration Tc , which is generally known as the charging (or
ramp-up) time. Assuming that Vi is time invariant, the output of the integrator
at the end of the integrating phase can be written as

Vi
V0 (Tc ) = − · Tc (4.40)
τ
Here, the integration of the input signal takes place until the N -bit counter
overflows; this corresponds to a fixed time of Tc = 2N T , where T is the clock
period. Note that the integrator output voltage is directly proportional to the
input signal.

− Reference signal integration phase

When the input signal integration phase is completed, the counter is reset. A
known reference voltage, VREF , with a polarity opposite to that of Vi is con-
nected to the integrator input and the counting of clock pulses resumes. The
110 Data Converters, Phase-Locked Loops, and Their Applications

integrator output voltage is now ramping down at a constant slope according

to the expression
Z t
− VREF VREF Vi
V0 (t) = − dt + V0 (Tc ) = (t − Tc ) − · Tc (4.41)
Tc τ τ τ

The counter is stopped after a discharging (or ramp-down) duration of Td

when the comparator output takes the logic low level because the integrator
output reaches zero, that is, V0 (Td ) = 0. Hence,

VREF Vi
· Td − · Tc = 0 (4.42)
τ τ
The time Td is then given by

Vi
Td = Tc · (4.43)
VREF
On the other hand, Td can be expressed in terms of the clock period, T , as

T d = Nr · T (4.44)

where Nr is the number of clock periods recorded during the connection of

VREF to the integrator input. Thus, it can be found that

Vi
Nr = 2 N (4.45)
VREF
The digital output of the counter is proportional to the magnitude of the input
signal, and is independent of the integrator time constant, which is supposed
not to change during an individual conversion cycle. When the input voltage is
negative, the dual-slope ADC operates according to the same basic principle
as described above for a positive input voltage, except that all the signal
polarities are reversed.
The accuracy of the dual-slope ADC seems to be only affected by the
fluctuations of the reference voltage and clock timing. But, the behavior of
a practical circuit can also be plagued by the nonideal characteristics of the
amplifier, MOS switches and capacitors, and the response time or switching
delay of the comparator. Figure 4.16 shows the effects of the offset voltage and
input over-range on the integrator output waveform. Additional conversion
phases are required in order to improve the accuracy of the dual-slope ADC.
The dual-slope ADC can be designed to allow bipolar operation and to
incorporate a phase for the converter offset compensation. Figure 4.17 shows
the circuit diagram of a dual-slope ADC with an auto-zero (AZ) capacitor [6].
The conversion cycle includes an auto-zero phase, an input signal integration
(ISI) phase, a reference signal integration (RSI) phase, and an integrator-
output zero (IZ) phase.
Nyquist Analog-to-Digital Converters 111
V0 Auto−zero
phase
Tc Td
0 t
Offset Integrator output
zero phase

Over−range hangover

FS Output saturation

FIGURE 4.16
Effects of the offset voltage and input over-range on the integrator output
waveform.
Input switch control signals

Vi R C
−
V REF
+
V REF CAZ
VX
− CK Digital
Control output
+ VC logic Counter
V0
+ AZ IZ
−
Integrator
Comparator
Carry

FIGURE 4.17
Circuit diagram of the dual-slope ADC with an auto-zero capacitor.

RSI +
RSI −
C REF
AZ AZ
V REF

RSI +
RSI −

ISI Buffer
Vi + Integrator
input
VX −

FIGURE 4.18
Circuit diagram of the input section of a bipolar dual-slope ADC with a single
reference voltage.

During the auto-zero phase, the converter input is connected to the ground
and a feedback loop is closed around the system such that the error voltage
can appear across the auto-zero capacitor, CAZ , whose charge is used for
offset voltage correction during the subsequent phases. By including all active
components in the loop, the accuracy of the auto-zero calibration is limited
only by the noise of the system. Note that a larger value of CAZ should be
112 Data Converters, Phase-Locked Loops, and Their Applications

used to minimize the noise sensibility for a converter with a small resolution.
Typically, the capacitor CAZ is at least two times greater than C.
In the input signal integration phase, the auto-zero switch is open and the
voltage Vi is connected to the converter input. The input signal polarity is
determined at the end of this phase.
During the reference signal integration phase, the control circuit connects
the reference signal with the polarity such that the integrator output can be
driven with a fixed slope to the zero level established in the auto-zero phase.
In the integrator output zero phase, the switch controlled by the IZ control
signal is closed and the negative feedback from the output of the comparator
to the converter input drives the integrator output to zero. This phase is used
to completely discharge the feedback capacitor of the integrator following the
occurrence of an over-range condition (see Figure 4.16), which is characterized
by the integrator output remaining far from the initial level after the maximum
time allowed to the reference signal integration phase.
Due to the need to accurately estimate the occurrence time of the zero-
crossing at the end of the reference signal integration phase, the operation
speed of the dual-slope ADC is generally slow. Although the frequency of the
clock signal may be increased, the use of a high clock rate is limited by the de-
lay of the comparator in detecting the zero-crossing. For a typical converter,
the comparator delay should not be greater than the duration of one-half
clock pulse, yielding a clock frequency on the order of a few hundred kilohertz
based on a comparator with a delay of a few microseconds. An improvement
in the performance may be achieved by modifying the structure of the con-
ventional dual-slope ADC such that the discharging time of the integrator can
be measured with a precision greater than the pulse width of the clock signal.
In the approach relying on the use of two reference voltages to design a
dual-slope ADC with a bipolar input range, the symmetry of the converter
transfer characteristic may be affected by the independent fluctuation of each
reference source. A solution can consist of using the input section of the dual-
slope ADC shown in Figure 4.18, where the charge stored by a capacitor
can induce balanced reference voltages [7, 8]. Switches controlled by the sig-
nal RSI + and RSI − are closed for the positive and negative input signals,
respectively.
During the AZ phase or an idle phase, the reference capacitor, CREF , is
charged by the reference voltage. For a stable storage of the charge due to the
reference voltage, the capacitor CREF must exhibit a low leakage current and
the effect of stray capacitances appearing on the reference capacitor nodes
must also be minimized. A capacitor in the microfarad range is required to
prevent rollover error, which arises as a consequence of the difference in the
reference voltage value for positive and negative input signals. The polarity
of the input signal determined by the comparator at the end of the signal
integration phase is used by the control logic to connect the capacitor CREF
to the input buffer such that the integrator output can return to the zero level.
Hence, depending on the polarity of the analog input, the reference capacitor
Nyquist Analog-to-Digital Converters 113

is used to generate either a positive or negative voltage during the reference

signal integration phase.
Input switch control signals

Integrator C
A
Vi R
Comparator CK
V−
REF − CRA
Control Up/down Digital
+
V REF + VC logic Counter output
V0
VX +
C’RA −

A+IZ

Rest
FIGURE 4.19
Circuit diagram of the dual-slope ADC with extra amplification and feedback
circuitry.

VI

Zero reading Normal conversion cycle

Amplification
Rest
Charging Discharging T’d
Tc Td IZ

0 t

Zero−crossing
detection

FS Zero−crossing
occurrence
CK
1
0 t

FIGURE 4.20
Integrator output during each conversion phase.

The block diagram of a dual-slope ADC including an amplification and

feedback circuitry to improve the conversion accuracy [9] is depicted in Fig-
ure 4.19. The conversion phases are illustrated on the integrator output shown
in Figure 4.20.
Initially, a conventional dual-slope integration consisting of an input sig-
nal integration phase and a reference signal integration phase is performed.
The converter operates by integrating an unknown input analog signal for a
predetermined time period, Tc , and then integrating a known reference sig-
nal until the integrator output reaches a predetermined zero level. Due to the
comparator delay, the zero-crossing is actually detected on the first clock pulse
after its occurrence, even if the integrator output reached the zero level within
114 Data Converters, Phase-Locked Loops, and Their Applications

the clock period. The duration, Td , of the reference signal integration phase
measured by counting clock pulses is then larger than its true value. Because
the integrator output continues to ramp down below the zero level until the
end of the clock period, a residual voltage appears across capacitors C and
′
CRA .
A rest phase is required to maintain constant the residual integrator
charge, which is then scaled up by a given negative factor, −k, and fed back
to the input node of the integrator amplifier in order to account for the mea-
surement error on the phase duration during the amplification phase.
In general, the absolute value of the multiplication factor depends on the
converter number system and is of the form, k = 2p for a binary system, where
p is the resolution increase in number of bits and k = 10q for a decimal system,
where q represents the resolution increase in number of digits. Typically, the
residual voltage is multiplied by −8 in a binary converter or −10 in a decimal
converter. In practice, the multiplication of the residual integrator charge is
′
achieved by sizing capacitors CRA and CRA such that
′
CRA = kCRA (4.46)

At the start of the amplification phase, the comparator output is fed back to
the integrator input, the voltage across CRA is zero, and the charge stored on
′
CRA is
′
Q = CRA Vres = kCRA Vres (4.47)
where Vres is the residual voltage. To establish a virtual ground at the positive
′
input of the comparator, a charge transfer is initiated between CXR and CXR ,
ending with the induction of a voltage across the capacitor CXR given by

VCRA = −Q/CRA = −kVres (4.48)

The voltage across the capacitor C is also −kVres because VCRA ′ is actually
almost equal to zero.
The converter enters a second reference signal integration phase, where the
capacitor CRA is short-circuited again, and the feedback connection between
the comparator output and integrator input is open. To keep the effect of
the charge redistribution between the capacitors negligible, the capacitor C is
′
designed to be much larger than the capacitor CRA . Thus, for this phase, the
initial value of the voltage at the positive input of the comparator remains
close to −kVres .
A second reference signal integration phase is initiated. The time, Td′ , which
is measured as the number of clock pulses required by the integrator output to
cross the zero level again, is proportional to the residual error. The net count
resulting from the subtraction in the same scale of Td′ from Td represents the
value of the time effectively needed by the integrator output to cross the zero
level. This calibration scheme can be implemented using up-down counters
incremented and decremented by the control logic.
The accuracy of the actual time measurement can be further improved
Nyquist Analog-to-Digital Converters 115

by resorting to subsequent rest, amplification, and reference signal integration

phases.
After the occurrence of an over-range condition, the comparator output
and the input analog signal are of opposite polarity. The feedback connection
realized between the comparator output and the integrator input during the
integrator output zero phase forces the integrator output voltage to change in
a direction such that its magnitude is decreased toward zero, thereby causing
the discharge of the capacitor C.
In this approach, the zero reading, that is, the result of the conversion with
the input voltage shorted to the ground, should be subtracted from each mea-
surement. This helps minimize the effect of offset voltages on the conversion
process.
For proper operation of a dual-slope ADC, the period of each clock pulse
should be greater than the comparator delay. Hence, the conversion speed is
primarily limited by the comparator delay, which is dependent on the con-
verter overdrive, defined as the maximum integrator output voltage swing
divided by the maximum number of clock pulses during the reference signal
integration phase. By augmenting the number of times the rest, amplification,
and reference signal integration phases are repeated, a decrease in the du-
ration of each phase becomes feasible, thereby yielding an overall conversion
with a faster speed.

4.1.3 Flash ADC

The most straightforward way to perform the N -bit analog-to-digital con-
version is to compare the sampled-and-held version of an analog signal with
2N reference voltages. The flash ADC, which generally consists of a resistive
divider, comparators, and a binary encoder, is based on this principle. The
foregoing track-and-hold (T/H) circuit samples the analog input and holds
it for half a clock cycle. This operation can be performed by exploiting the
inherent sampling properties of latched comparators. However, the use of a
T/H circuit is preferred because the operation of the comparator array is often
affected by clock skews, which can degrade converter linearity.
The block diagram of a 3-bit flash ADC is shown in Figure 4.21. In this
case, N = 3 and 23 − 1 = 8 comparators are used. Furthermore, the input
signal is supposed to be positive. The reference voltage at the k-th node can
be expressed as
R/2 + (k − 1)R VREF VREF
Vk− = VREF N
= k N − N +1 (4.49)
R/2 + (2 − 2)R + 3R/2 2 2
The difference between the reference voltages of two adjacent comparators is
VREF /2N , that is,
− VREF
△ = Vk+1 − Vk− = (4.50)
2N
where △ denotes the voltage level of an LSB. The output of a comparator will
116 Data Converters, Phase-Locked Loops, and Their Applications
Binary encoder
VREF

3R/2 T6 b1
+ − D Q

7 − + D Q

R T5
+ − D Q

6 − + D Q

R T4
+ − D Q

5 − + D Q
b2
R T3
+ − D Q
In T/H
Vi 4 − + D Q

CK1 R T2
+ − D Q

3 − + D Q

R T1
+ − D Q

2 − + D Q b3

R T0
+ − D Q

1 − + D Q

R/2
CK2

FIGURE 4.21
Block diagram of a 3-bit unipolar flash ADC.

TABLE 4.2
Thermometer Code for a 3-Bit Unipolar Flash ADC (with △ = VREF /8)

Thermometer Code Binary Code

Input Range T6 T5 T4 T3 T2 T1 T0 b1 b2 b3
7 13△/2 < Vi < 8△ 1 1 1 1 1 1 1 1 1 1
6 11△/2 < Vi < 13△/2 0 1 1 1 1 1 1 1 1 0
5 9△/2 < Vi < 11△/2 0 0 1 1 1 1 1 1 0 1
4 7△/2 < Vi < 9△/2 0 0 0 1 1 1 1 1 0 0
3 5△/2 < Vi < 7△/2 0 0 0 0 1 1 1 0 1 1
2 3△/2 < Vi < 5△/2 0 0 0 0 0 1 1 0 1 0
1 △/2 < Vi < 3△/2 0 0 0 0 0 0 1 0 0 1
0 0 < Vi < △/2 0 0 0 0 0 0 0 0 0 0

be at the high state if its input voltage is higher than the reference voltage.
Otherwise, the comparator output is at the low state. The outputs of all
comparators form a thermometer code that is then converted into a binary
Nyquist Analog-to-Digital Converters 117

code by an encoder. Table 4.2 lists the thermometer and binary coding schemes
for a 3-bit word. Note that the number of consecutive 1’s in the thermometer
code corresponds to the count of reference voltages less than the input signal.
By choosing the bottom resistor in the comparator resistor string to be R/2,
the transitions of the ADC transfer characteristic are at multiples of △/2.

VREF

3R/2 T6
+ − D Q Gray encoder
7 − + D Q

R T5
+ − D Q

6 − + D Q

R T4
+ − D Q

5 − + D Q
Binary encoder
R T3 g1
+ − D Q
In S/H b1
Vi 4 − + D Q

CK1 R T2
+ − D Q
g2
3 − + D Q b2

R T1
+ − D Q

2 − + D Q
g3
T0 b3
R
+ − D Q

1 − + D Q

R/2
CK2

FIGURE 4.22
Block diagram of a flash ADC with improved encoder.

In practice, due to mismatches and imperfections in the reference resistor

string and in the latched comparators, as well as high speed limitations, er-
rors can be introduced in the thermometer code produced at the comparator
outputs. They show up as bubbles,1 which are zeros surrounded by ones, or
vice versa. This may happen in the specific case where a comparator switches
more slowly than expected, so that the output is latched before reaching the
final state. When the bubble error cannot be detected by the digital encoder,
the ADC will produce an output code not representative of the input signal
value.
The effect of bubble errors can be reduced by first converting the ther-
mometer code into the Gray code, which is then used for the computation of

1 The use of the term “bubble" is justified by the fact that such a code error is analogous

to a bubble occurring in the mercury of a thermometer.

118 Data Converters, Phase-Locked Loops, and Their Applications

TABLE 4.3
Encoder Truth Table (△ = VREF /8)

Thermometer Code Gray Code Binary Code

T6 T5 T4 T3 T2 T1 T0 g1 g2 g3 b1 b2 b3
7 1 1 1 1 1 1 1 1 0 0 1 1 1
6 0 1 1 1 1 1 1 1 0 1 1 1 0
5 0 0 1 1 1 1 1 1 1 1 1 0 1
4 0 0 0 1 1 1 1 1 1 0 1 0 0
3 0 0 0 0 1 1 1 0 1 0 0 1 1
2 0 0 0 0 0 1 1 0 1 1 0 1 0
1 0 0 0 0 0 0 1 0 0 1 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0

TABLE 4.4
Thermometer-to-Gray and Gray-to-Binary Encodings

N =3 g1 = T3 b1 = g1
g2 = T1 · T5 b2 = g2 ⊕ b1
g3 = T0 · T2 + T4 · T6 b3 = g3 ⊕ b2
N =4 g1 = T7 b1 = g1
g2 = T3 · T11 b2 = g2 ⊕ b1
g3 = T1 · T5 + T9 · T13 b3 = g3 ⊕ b2
g4 = T0 · T2 + T4 · T6 + T8 · T10 + T12 · T14 b4 = g4 ⊕ b3

the binary code. Gray encoding itself has no correction ability. But its toler-
ance to bubbles is due to the fact that only one bit changes between adjacent
codes, leading to a small difference between the ideal and incorrect codes.
The logic equations for the thermometer-to-Gray and Gray-to-binary encod-
ings are summarized in Table 4.4 for the 3-bit and 4-bit flash ADCs. The
circuit diagram of a 3-bit flash ADC including a Gray-code-based encoder is
shown in Figure 4.22. In order to equalize the propagation delay of the dif-
ferent signal paths, additional NAND and XOR gates were inserted in the
encoder according to the following Boolean algebraic identities:

A=A (4.51)
A= A⊕0 (4.52)
where A is a logic variable. Note that long wiring structures can be required
to logically combined signals as the number of bits is increased, resulting in an
irregular circuit layout. Furthermore, latches can be introduced between the
Nyquist Analog-to-Digital Converters 119

logic stages to improve the operation speed and to reduce the metastability
error probability.
Due to their regular structure, ROM-based encoders are preferred over
gate-based encoders for converter implementations with a resolution greater
than 5 bits. A ROM can consist of bit lines, word lines, and MOS-type memory
cells. The storage of a logic 0 is carried out using an n-channel pull-down
transistor, while no connection is required for the storage of a logic 1. A
precharged logic is generally used to eliminate the static power dissipation and
to help keep the pull-up and pull-down transistors as close as possible to the
minimum size. However, the converter speed can be limited by the ROM pre-
charge time. Ideally, the 1-out-of-2N code obtained by detecting the location
of the 1-to-0 transition in the thermometer code is commonly used to enable a
single word line of the ROM. Hence, only the bit representing the location of
the detected transition can take the logic 1 and all the remaining bits are at
the logic 0. However, if bubbles exist in the thermometer code, there will be
multiple 1-to-0 transition points and the 1-out-of-2N encoder will select more
than one ROM line. As a result, errors are introduced in the binary output,
which is actually the representation of the bitwise logical OR between the
ROM lines.
An approach for the bubble correction consists of using a majority logic
function [10] whose output takes the same logic state as the greater number
of inputs. The block diagram of the 3-bit flash ADC with the bubble error
correction based on a majority logic (ML) is illustrated in Figure 4.23. With
the assumption that T−1 = 1 and T7 represents the over-range signal, the
corrected thermometer code, Ti∗ , is given by the Boolean equation,

Ti∗ = Ti−1 · Ti + Ti · Ti+1 + Ti−1 · Ti+1 (4.53)

where i = 0, 1, · · · , 6. The state of a given bit in the thermometer code is

then determined by one of its two neighbors. The ML encoder can efficiently
suppress the bubbles, which affect the 1-0 transition in the thermometer code.
However, the power consumption and chip area can be increased because the
required number of gates tends to be high. The ROM line selection can be
carried out using a thermometer to 1-out-of-2N encoder based on two-input
AND gates. This simple encoder will operate correctly only if there is no
bubble error in the thermometer code.
In general, the occurrence likelihood of bubbles becomes less important
as their number becomes greater. Because the bubbles are mainly introduced
near the one-to-zero transition point in the thermometer code, the encoder
can be designed to correct only certain single bubbles. Figure 4.24 shows
the block diagram of the 3-bit flash ADC with the bubble error correction
based on three-input AND gates [11]. The correction is limited to bubble
errors, which do not affect the 1-to-00 transition in the thermometer code.
The possible states of the different signals in response to a given input are
shown in Table 4.5 for the 3-bit flash ADC. The appropriate word line in
the Gray ROM encoder is activated by the signals ti , which are given by the
120 Data Converters, Phase-Locked Loops, and Their Applications
T 7 (OR) V DD
+ − D Q 1−out−of−8 encoder CK
3
VREF /2 − + D Q
t7
R T6
+ − D Q ML

7 − + D Q
t6

R T5
+ − D Q ML

6 − + D Q t5

R T4
+ − D Q ML

5 − + D Q t4

R T3
+ − D Q ML
In T/H
Vi 4 − + D Q t3

CK1 T2
R + − D Q ML

t2
3 − + D Q

R T1
+ − D Q ML
t1
2 − + D Q

R T0
+ − D Q ML
t0
1 − + D Q V DD

R V DD
CK2
g1 g2 g3
−VREF /2

FIGURE 4.23
Block diagram of a 3-bit flash ADC with the bubble error correction based on
a majority logic (OR: over-range).

following Boolean equation,



T 6 · T 7 for i=7
ti = Ti−1 · Ti · Ti+1 for i = 1, 2, · · · , 6 (4.54)


T0 · T1 for i=0

where Ti denotes a bit of the thermometer code. Note that T7 represents the
over-range signal generated as a result of the comparison between the input
signal and VREF /2.
The fundamental difference between the ML and three-input AND en-
coders can be illustrated by comparing the ideal thermometer code and error-
correction results of the examples included in Table 4.6, where the first Ti
column represents the ideal case and bold characters are used to show the
bits affected by bubble errors. The ML encoder relies on the best-expectation
principle and the detection of the 1-to-0 transition, while the three-input AND
Nyquist Analog-to-Digital Converters 121
T7 V DD
+ − D Q
1−out−of−8 encoder CK3
VREF /2 − + D Q
t7
R T6
+ − D Q

7 − + D Q
t6
R T5
+ − D Q

6 − + D Q
t5
R T4
+ − D Q

5 − + D Q
t4
R T3
+ − D Q
In T/H
Vi 4 − + D Q
t3
CK1 T2
R + − D Q

3 − + D Q
t2
R T1
+ − D Q

2 − + D Q
t1
R T0
+ − D Q

1 − + D Q
t0
R CK2

−VREF /2
g1 g2 g3

FIGURE 4.24
Block diagram of a 3-bit flash ADC with the bubble error correction based on
three-input AND gates.

encoder is based on the detection of the 1-to-00 transition. In both cases, the
error correction cannot be ensured for all bubble types.
An N -bit flash ADC generally requires at least 2N − 1 comparators, whose
reference voltages are set by a resistor string. The value of each comparator
output depends on whether or not the input voltage exceeds the corresponding
reference voltage. A set of all comparator outputs, which form the so-called
thermometer code, is first scaled to the appropriate logic levels by latches
in order to mitigate the metastability problem and then converted into a
form of binary data. The resulting data with N -bit resolution are applied to
the output buffer, which can be implemented using D latches. Note that an
additional comparator is often used to indicate the presence of a signal over-
range. Because the metastability, which is characterized by an output state
between the logic level high and logic level low, is due to the violation of
setup and hold time, it can be reduced by allowing more time for comparator
122 Data Converters, Phase-Locked Loops, and Their Applications

TABLE 4.5
Truth Table of the 3-Bit Bipolar Flash ADC with a Three-Input AND Encoder

Thermometer Code 1-out-of-8 Code Gray Code

Input Range T 6 T 5 T 4 T 3 T 2 T 1 T 0 t7 t6 t5 t4 t3 t2 t1 t0 g 1 g 2 g 3
3△ < Vi < 4△ 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0
2△ < Vi < 3△ 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1
△ < Vi < 2△ 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1
0 < Vi < △ 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 0
−△ < Vi < 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0
−2△ < Vi < −△ 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1
−3△ < Vi < −2△ 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1
−4∆ < Vi < −3△ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

TABLE 4.6
Illustration of Three Correction Examples of Bubbles in the ML and Three-
Input AND Encoders

ML Encoder Three-input AND Encoder

Case 1 Case 2 Case 3 Case 1 Case 2 Case 3
i Ti Ti Ti∗ ti Ti Ti∗ ti Ti Ti∗ ti T i ti T i ti T i ti
7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
4 0 1 0 1 0 0 0 0 0 0 1 0 0 1 0 1
3 1 0 1 0 1 0 1 1 0 0 0 0 1 0 1 0
2 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0
1 1 1 1 0 1 1 0 0 0 1 1 0 1 0 0 1
0 1 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0

regeneration. The speed of the overall structure depends on the comparator

speed and the propagation delay of the digital section. But with the use of
pipeline latches, the comparison and code conversion can ideally be achieved
in a single clock phase allowing the flash ADC to operate at higher frequencies.
The block diagram of a flash ADC based on the above principle is shown
in Figure 4.25. For a given analog input voltage, the thermometer code should
ideally exhibit only a single 1-to-0 transition. But in practice, the converter
components may be subject to nonidealities such as finite bandwidth, noise,
and mismatches, leading to the introduction of bubbles in the thermometer
code. This problem can be alleviated by using an intermediate Gray encoding
stage instead of converting directly from the thermometer code to the binary
Nyquist Analog-to-Digital Converters 123
T2 N−1
+ − D Q Over−range

VREF/2 − + D Q

R T2 N−2
+ − D Q

− + D Q

Gray−to−two´s complement encoder

Thermometer−to−Gray encoder
R T2 N−3
+ − D Q

− + D Q

Pipeline latch

Output latch
R T2 N−4 Digital
+ − D Q
Output
− + D Q

R T2 N−5
+ − D Q
In T/H
Vi − + D Q

CK1 R

T0
+ − D Q

− + D Q
CK3 CK4
R CK2

−VREF/2

FIGURE 4.25
Block diagram of a flash ADC.

code. Furthermore, the robustness to bubbles can be enhanced by inserting

an adequate error correction stage before the digital encoder.
T6
T5

T4 X Ci S X Ci S b3 Ci
FA FA
T3 Y C0 Y C0
1
T2 S
0

T1 X Ci S X Ci S b2 1
FA FA X
0
T0 Y C0 Y C0 b1
Y 1
C0
0

FIGURE 4.26
Tree encoder based on ones-counter for a 3-bit flash ADC.

Note that the output generated by a thermometer-to-binary encoder is a

binary representation of the number of 1s in the thermometer code. Hence,
a ones-counter based on full adders can also be used as a digital encoder.
Figure 4.26 shows the block diagram of a tree encoder for a 3-bit flash ADC.
This approach is insensitive to bubbles, which maintain constant the overall
number of 1s in the thermometer code. However, the propagation delay of the
tree encoder increases linearly with the converter resolution. Bit-level pipelin-
ing, which consists of inserting a register between logic blocks, can then be
124 Data Converters, Phase-Locked Loops, and Their Applications

used to reduce the critical path. This will incur an increase in the hardware
overhead and power consumption.
VDD VDD VDD VDD

RL RL RL RL RL RL RL RL

Cgs Cgs Cgs Cgs Cgs Cgs Cgs Cgs

In

−VREF /2 VREF /2
R R R R
CD CD

FIGURE 4.27
Equivalent circuit model of the flash ADC input stage.

High-resolution flash ADCs generally require a large number of compara-

tors. This can result in a large input capacitor, considerable chip area and very
high power consumption. Figure 4.27 shows the equivalent circuit model of the
flash ADC input stage, where CD is used to decouple the reference voltages.
The gate-source capacitors, Cgs , of the transistors in the comparator input
stage form a parasitic capacitor between the comparator inputs. The input
signal is then capacitively coupled to the resistive reference network, thereby
leading to a variation in the reference voltages. The total resistance of the
resistive reference network should be kept low enough to maintain the maxi-
mum feedthrough error lower than 1 LSB. This requirement can be relaxed by
dividing the resistive reference network into subsections with an adequate size
using decoupling capacitors, especially in cases where there is an important
increase in the power consumption.

Vi+
+ − V0−
Cp
− + V0+
Vi−

FIGURE 4.28
Comparator with a parasitic capacitor between the inputs.

At high frequencies, the input parasitic capacitor of the comparator, as

illustrated in Figure 4.28, couples the input signal with the resistive net-
work used for the generation of the reference voltages. To avoid a variation
in reference voltages, which can affect the comparator threshold levels, the
maximum resistance of the resistive network must be estimated using the
equivalent circuit model shown in Figure 4.29, where it is assumed that
Nyquist Analog-to-Digital Converters 125
R R R R R R Vm R R R R R R

Cp Cp Cp Cp Cp Cp Cp Cp Cp Cp Cp

+ V
− i

FIGURE 4.29
Equivalent circuit model for the maximum resistance derivation in the flash
ADC.
R R R R R R Vm R R R R R R

Cp Cp Cp Cp Cp Cp Cp Cp Cp Cp Cp

+ V
C’D − i C’D

(a)

R Vx R Vm R Vx R

Cp Cp Cp

+ V
− i

(b)

FIGURE 4.30
(a) Equivalent circuit model with decoupling capacitors; (b) equivalent circuit
model of a subsection of the resistive reference network.

the high and low reference voltages are fully decoupled. For a flash ADC
with a resolution of N bits, we have

R = RT /2N (4.55)

and
Cp = CT /2N (4.56)
where RT denotes the total resistance of the resistive network and CT is
the total parasitic capacitance. Generally, the resulting resistance is low for
high-speed ADCs, and the power consumption of the reference network,
2
which is of the form VREF /RT , is increased. With the use of decoupling ca-
′
pacitors as shown in Figure 4.30(a), where CD is the decoupling capacitor,
the total resistance of the resistive network can be increased without dete-
riorating the level of the feedthrough error. The effect of the decoupling is
to split the equivalent circuit model required for the worst-case estimation
of RT into q almost identical subcircuits. Simulations of the equivalent
subcircuit depicted in Figure 4.30(b) show that the voltage at the middle
126 Data Converters, Phase-Locked Loops, and Their Applications

node, Vm , is most affected by the input signal feedthrough error. Using

Kirchhoff’s current law, the next node equations can be obtained,

Vm − Vx
(Vi − Vm )sCp = 2 (4.57)
R
Vx Vx − Vm
(Vi − Vx )sCp = + (4.58)
R R
Combining Equations (4.57) and (4.58), we get

Vm (sRCp )2 + 4sRCp (sRT CT )2 + 22N +2 sRT CT

= =
Vi (sRCp )2 + 4sRCp + 2 (sRT CT )2 + 22N +2 sRT CT + 24N +1
(4.59)
Let f be the frequency of the input voltage Vi . With the assumption that
s = j2πf and πf RT CT ≪ 1, we can find the following expression:

Vm π
≃ f RT CT (4.60)
Vi 4

In the worst case, the voltages Vm and Vi can be expressed in LSB units,
leading to
Vm k
=q N (4.61)
Vi 2

where k represents the feedthrough level and q is the decoupling period.

The maximum resistance is then defined by

4k
RT ≤ q (4.62)
πf CT 2N

Because q is greater than 1, the decoupling capacitors will increase the

total resistance by a factor of q.

Furthermore, the attainable resolution is limited by the accuracy of the

reference voltages and comparator offset voltage. Typically, for a 10-bit con-
verter with 2 Vp−p input signal, the comparator should resolve less than about
2 mV. This requirement is difficult to meet in CMOS technology, and various
techniques for reducing the offset-voltage effects such as chopper stabilization
and auto-zeroing result in an increase in the power consumption and a re-
duction in the conversion speed. Therefore, a good compromise may be to
design a flash ADC for applications requiring less than 8 bits for the data
representation.
Note that flash ADCs can also be implemented without the input T/H cir-
cuit, which is generally based on open-loop structures in high-speed applica-
tions. In this case, a higher dynamic performance is required for comparators.
Nyquist Analog-to-Digital Converters 127

4.1.4 Averaging ADC

Device mismatches often limit the differential and integral nonlinearity char-
acteristics and the resolution of classical flash ADC architectures. Averaging
techniques can be used to minimize the mismatch effect.

+
+ − +− +− D Q

− + −+ −+ D Q
+
VREF −
R1 R1 R1 R1

R +
+ − +− +− D Q

− + −+ −+ D Q
−
R1 R1 R1 R1

R +
+ − +− +− D Q

Bubble correction & Digital encoder

− + −+
− −+ D Q

R1 R1 R1 R1

R +
+ − +− +− D Q Digital
− + −+ −+ D Q
Output
−
R1 R1 R1 R1

R +
+ − +− +− D Q

− + −+ −+ D Q
−

R R1 R1 R1 R1

+
+ − +− +− D Q
In T/H
− + −+ −+ D Q
−
R1 R1 R1 R1
CK1
R +
+ − +− +− D Q

− + −+ −+ D Q
V−
REF
−
R1 R1 R1 R1
CK 2

Reference First Averaging Second Averaging Comparators Latches

ladder preamplifier resistors preamplifier resistors
stage stage

FIGURE 4.31
Circuit diagram of a flash ADC with averaging stages.

Figure 4.31 shows the circuit diagram of a flash ADC with two averaging
stages. The inherent symmetry of differential circuits is exploited to use the
same number of reference nodes as in single-ended structures. The mirror-
image preamplifiers with respect to the reference midpoint can then be con-
nected oppositely to reference voltage nodes. The requirement of maintaining
the gain high enough in order to reduce the effect of the input-referred offset
on the subsequent stages can be met by cascading two stages of preampli-
fication and averaging. By inserting lateral resistors between the outputs of
neighboring preamplifier stages, the random component of currents is reduced
and the effect of offsets on the ADC performance is attenuated [12]. The offset
reduction is dependent on the value of the preamplifier output resistance, R0 ,
128 Data Converters, Phase-Locked Loops, and Their Applications

and the averaging resistors, R1 . Using the superposition principle with the
consideration that the signal and reference voltage sources are disconnected,
the inputs of the first stage of preamplifiers are reduced to the offset voltages.
Req Req
R1 R1 R1 R1 R1

R0 R0 R0 R0

+ V + V Vk+1 + Vk+2 +
− k−1 − k − −

FIGURE 4.32
Equivalent circuit of the preamplifier array with an averaging resistor network.

Figure 4.32 shows the equivalent circuit of a preamplifier array with an

averaging resistor network supposed to be infinite. The equivalent resistance,
Req , seen to the right and to the left of each output node is given by
r
1 1 2
Req = R1 + R0 k Req ⇒ Req = R1 + R + R1 R0 (4.63)
2 4 1
In practice, the length of the averaging resistive network is limited and the
equivalent resistance, especially at the termination nodes, may differ from the
above value.
The preamplifier transfer characteristics are illustrated in Figure 4.33(a).
The zero-crossing points of the preamplifiers at the array edges are shifted in-
ward. This leads to undesirable variations in the INL mean value near the two
edges of the preamplifier array, as illustrated in Figure 4.33(b). Furthermore,
the standard deviation of the offset voltage is larger for preamplifiers at the
boundaries than the one at the center.
To avoid any discontinuity at the edges of the averaging network, over-
range dummy preamplifiers, whose outputs remain unused, are often added at
each edge of the array. The complementary outputs of the first and last over-
range preamplifiers are cross-connected through a pair of resistors to ensure
that every preamplifier in the array sees the same effective load resistance and
has a balanced number of preamplifiers contributing to its output [13]. A 6-bit
ADC, for instance, includes an array of 63 preamplifiers, and about 9 dummy
preamplifiers are required at each array end to create a linear behavior at the
edges of the input full scale. However, the addition of dummy preamplifiers
results in a reduction in the available headroom for the input voltage, and an
increase in the input capacitance and power dissipation.
In the specific case of resistor-loaded preamplifiers, the number of dummy
preamplifiers can be reduced by resizing the resistors at either edge of the
averaging network, as shown in Figure 4.34 [14], where the index k is used
for the lowermost or uppermost in-range preamplifier. Provided R1 > R0 ,
the electrical load symmetry at the averaging network edges can be restored
without resorting to the use of dummy preamplifiers by changing the first and
Nyquist Analog-to-Digital Converters 129
∆1 ∆ 2 N−1

∆2 ∆ 2 N−2

Preamplifier output
V max
0 Input
−Vmax

V V V V V V V V V
R1 R2 R3 R N−1 R N−1 R N−1 R N R N R N
2 −1 2 2 +1 2 −3 2 −2 2 −1
(a)

INL (LSB)

∆ INL Ideal
Output
0 code

−∆ INL

(b) Full−scale range

FIGURE 4.33
(a) Preamplifier transfer characteristics; (b) effect of the asymmetrical pream-
plifier boundaries on the converter linearity.
R1 R1 R1−R0 R1 R1 RT

R0 R0 R0 R0 R0 R0 R0

+ V + V + V + V + V + V + V
− k−1 − k − k+1 − k−1 − k − k+1 − k+2

(a) (b)

FIGURE 4.34
Equivalent circuits of one edge of the averaging network with a resized termi-
nation resistor: (a) Case R1 > R0 , (b) case R1 < R0 .

last resistances to R1 − R0 . In the cases where R1 < R0 , the first and last
averaging resistors will be short-circuited and the value of the next resistors
will be modified as follows:

 3R − R0
 1 if R1 < 3R0
RT = 2 (4.64)
2R − R0 if R < 6R

1 1 0
3
Otherwise, additional preamplifiers with short-circuited averaging resistors
will be connected at the network edges to reduce the equivalent load resistance
so that a positive value can be found for RT .
For a given preamplifier, the magnitude of offset reduction provided by
the averaging network depends on the ratio R0 /R1 and the number of neigh-
boring preamplifiers operating in the nonsaturated region. By increasing the
130 Data Converters, Phase-Locked Loops, and Their Applications

ratio R0 /R1 to improve the offset reduction, the overall output resistance
seen by the preamplifiers can be reduced, leading to a decrease in the gain
and an increase in the input-referred offset for the subsequent stages (ampli-
fiers, or comparators). On the other hand, an augmentation in the number
of nonsaturated preamplifiers can also improve the offset reduction and can
contribute to a substantial increase in the preamplifier gain. Because this can
be achieved by stepping up the overdrive voltage, there is a great repercussion
on the power consumption. In practice, it is necessary to use a high number
of nonsaturated preamplifiers and a low value of the ratio R0 /R1 to maintain
the effects of resistor mismatches to an acceptable level. At least a two times
reduction in the offset voltage of a flash converter can be achieved by choosing
the ratio R0 /R1 between 0.5 and 1. The use of edge termination resistors does
not significantly increase the power consumption and area of the converter.
However, it can effectively mitigate the effect of preamplifier offset voltages
only when the averaging window is narrow and the specification of matching
termination resistors is less stringent.

Over−range In−range preamplifier array Over−range

preamplifier preamplifier
In
V R VR R VR R VR R VR R
R1
− 2 3 2 N−2 2 N−1 +
VREF VREF
−+

+−

−+

+−

−+

+−

−+

+−

−+

+−

−+

+−

−+

+−
R1 R1 R1 R1 R1 R1 R1

R1 R1 R1 R1 R1 R1 R1

To the next stage

FIGURE 4.35
Preamplifier array with the averaging resistor network based on the triple
cross-connection.

An alternative low-power and low-area design solution is to use an aver-

aging resistor network based on the triple cross-connection [15], as shown in
Figure 4.35. The effect of zero-crossing shifts can be compensated by intro-
ducing a cross-connection and an over-range preamplifier at each boundary.
A proper termination can be realized due to the symmetry provided by the
cross-connection at the center. To counteract the reduction in the effective
transconductance at the boundary due to the negative transconductance of
the over-range preamplifier, the over-range preamplifier should be designed
such that its input linear region extends along that of the adjacent in-range
preamplifier. Furthermore, it is desirable that the over-range preamplifier op-
erate with the same reference voltage as the penultimate preamplifier.
Nyquist Analog-to-Digital Converters 131
VREF CK

R T j+1 V
j+1
+ − D Q
Vj+1 0
j+1 − + D Q Vi
VR
j+1
R Tj Vj
+ − D Q
Vi Vj 0
j − + D Q Vi
VR
j
R T j−1 V
j−1
+ − D Q
Vj−1 0
j−1 − + D Q Vi
VR
j−1
R

FIGURE 4.36
A section of the processing path in a flash ADC.
CK

C j+1 V
j+1
Folding + − D Q
Vj+1 0
block − + D Q Vi
VR VR VR
7 8 9
VR VR VR
7 8 9 Cj Vj
Folding + − D Q
Vi Vj 0
block − + D Q Vi
VR VR VR
4 5 6
VR VR VR
4 5 6 C j−1 V
j−1
Folding + − D Q
Vj−1 0
block − + D Q Vi
VR VR VR
1 2 3
VR VR VR
1 2 3

FIGURE 4.37
A section of the processing path in a folding ADC.

4.1.5 Folding and interpolating ADC

An analog preprocessing structure, which performs the folding and interpola-
tion operations, can be used to reduce, respectively, the number of compara-
tors and preamplifiers needed in the flash ADC [16–19]. Figure 4.36 shows
a section of the processing path in a flash ADC. For N -bit conversion, the
input signal should be compared with at least 2N − 1 voltage reference levels
and a different comparator is used for each possible digital code. By introduc-
ing folding stages, as shown in Figure 4.37 for three reference voltages, the
locations of the zero-crossings in the signals now determine the cyclic code
transitions to be identified by comparators. The folding factor F (here F = 3)
indicates the number of zero-crossings included in the transfer characteristic.
132 Data Converters, Phase-Locked Loops, and Their Applications

One comparator detects F reference voltages rather than one, as is the case in
the full flash architecture, and the reference voltages of the folding amplifier
should be sufficiently far apart to ensure a proper operation of comparators.

TABLE 4.7
Thermometer and Circular Codes of Numbers from 0 to 3

Circular Thermometer
Code Code
C3 C2 C1 C0 T2 T1 T0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 1
0 0 1 1 0 1 1 2
0 1 1 1 1 1 1 3
1 1 1 1 0 0 0 0
1 1 1 0 0 0 1 1
1 1 0 0 0 1 1 2
1 0 0 0 1 1 1 3

Let us consider a folding ADC including four folding amplifiers, whose

reference voltages are chosen as follows:
F1 : (1/16)VREF (5/16)VREF (9/16)VREF (13/16)VREF
F2 : (2/16)VREF (6/16)VREF (10/16)VREF (14/16)VREF
F3 : (3/16)VREF (7/16)VREF (11/16)VREF (15/16)VREF
F4 : (4/16)VREF (8/16)VREF (12/16)VREF (16/16)VREF

The first cycle of the circular code, which is produced at the comparator
outputs, is shown in Table 4.7. The equivalent thermometer code can be de-
rived using a circular-to-thermometer encoder based on the following Boolean
equations:

T2 = C2 ⊕ C3 T1 = C1 ⊕ C3 and T0 = C0 ⊕ C3 (4.65)

and implemented using XOR gates. There are two folds in one cycle. With a
folding factor of 4 as in this example, the input full range is divided into two
cycles or four folds. Because the folding characteristic is redundant, a cycle
pointer is generally necessary to resolve the ambiguity in the output code.
A high degree of folding can result in a decrease in the signal bandwidth,
which is caused by the presence of parasitic capacitors at the folder output
nodes. In practice, F is then limited to eight and more quantization levels can
be obtained using a parallel configuration of folding blocks. The necessary
number of folding amplifiers or folders can still be high. The amplifier number
is reduced using an interpolator with the factor I between two consecutive
folding blocks. The interpolation is based on the signal division and can be
Nyquist Analog-to-Digital Converters 133

realized by a resistor ladder, as illustrated in Figure 4.38, where we have

VR4 = (VR1 + VR7 )/2, VR4 = (VR2 + VR8 )/2, and VR6 = (VR3 + VR9 )/2.
CK

C j+1 V
j+1
Folding + − D Q
Vj+1 0
block − + D Q Vi
VR VR VR
7 8 9
VR VR VR R R
7 8 9 Cj Vj
+ − D Q
Vi Vj 0
− + D Q Vi
VR VR VR
4 5 6
R R
Cj−1 Vj−1
Folding + − D Q
Vj−1 0
block − + D Q Vi
VR VR VR
1 2 3
VR VR VR
1 2 3

FIGURE 4.38
A section of the processing path in a folding and interpolating ADC.

The folding operation relies on mapping the input waveform into a repet-
itive signal, whose frequency is multiplied by the folding factor. Here, the
amplitude quantization is transformed into the detection of zero-crossings of
the folding signal. Figure 4.39 shows the circuit diagram of the j-th folding
stage, where F is the folding factor. The output of the odd- and even-numbered
differential transistor pairs are cross-coupled. The input reference voltages are
defined by a resistive network. The polarity of the signal changes each time
the input voltage attains a reference level.
V
DD

R1 R2

V−
Fj

V+
Fj

In
− +
VREF VREF
VR VR VR VR
R 1 R 2 R F−1 R F R

FIGURE 4.39
Implementation of a folding amplifier.

The interpolation can be realized using passive elements, and active ele-
ments and components. The circuit diagram of an interpolation circuit with
a differential structure is shown in Figure 4.40(a). The voltage division is
134 Data Converters, Phase-Locked Loops, and Their Applications

realized by a resistor ladder driven by nMOS source followers [19]. The in-
terpolated signals are denoted by Vik , where k = 1, 2, · · · , I + 1, and I is the
interpolation factor. The output signals of two neighboring folding stages can
also be interpolated as shown in Figure 4.40(b). Due to the fact that only the
zero-crossings contain useful information, an accurate gain is not required for
any amplifier of the interpolation circuit. The interpolation amplifiers can sim-
ply consist of differential transistor pairs, which can operate with a low supply
voltage. Here, the interpolation by a factor of the form I = 2p is achieved by
cascading p amplifier sections and 2q + 1 amplifiers are required in the q-th
section.

VF− − + − +
VDD VDD j VI
T1 T2 1
VF+ VF+ +− +−
j j
VF−
j
Vi − +
1
IB R R IB
+−
Vi
2

R R − + − +
VI
2
Vi +− +−
3

Vi − +
VDD I VDD
VF+ T3 R R T4 +−
j+1
Vi
VF− I+1
j+1 VF− − + − +
j+1 VI
IB IB 3
VF+ +− +−
j+1
1
2 +1 22+1 2N+1
(a) (b) Amplifiers

FIGURE 4.40
Implementations of interpolating circuits using (a) resistors and (b) differential
amplifiers.

Note that current-division techniques can also be exploited in order to

implement the interpolation stage. This approach relies on the use of current
comparators or I-to-V converters and can have the drawback of reducing the
bandwidth of the folder circuit due to the extra node, which can be introduced
in the signal path.
In the case of interpolations by a factor higher than 2, a systematic error
is introduced in the position of zero-crossings due to the effect of the non-
linear transfer characteristic of folding amplifiers on the signal values near
the boundaries of the input range. Figure 4.41 shows signals obtained as a
result of the interpolation by a factor of 4. Because of the symmetry of the
transfer characteristic, the zero-crossing location of the interpolated signal
in the middle remains unaffected. In comparison with the ideal case, where
the zero-crossings should be uniformly distributed, the other two interpolated
Nyquist Analog-to-Digital Converters 135
Vi
k

0 Ideal

Primary folding
Vi signals

FIGURE 4.41
Illustration of the input stage nonlinearity effects on interpolated signals.

zero-crossings tend to move outward. This can be attributed to the amplitude

mismatch between the folding signals and the interpolated signals. One way
to restore the ideal zero-crossing points can be to extend the operation range
of the folding amplifier.

V
0

N
2 levels

N
2 /F levels

V V FSR
i
0 Fold 1 Fold 2 Fold 3 Fold 4 Fold F−1 Fold F 1

FIGURE 4.42
Transfer characteristic of an ideal folding ADC.

Ideally, the input-output characteristic of the folding amplifier is periodic

and consists of piece-wise linear segments, or folds, whose number is related to
the folding factor. As this leads to a repetitive code at the comparator output,
a cycle pointer or coarse converter is needed in addition to a fine converter. The
coarse converter ascertains in which period of the folding amplifier transfer
characteristic the input signal lies. The transfer characteristic of a converter
based on the folding principle is illustrated in Figure 4.42, where the input
range is assumed to be divided into F regions or folds. Note that two folds
constitute a folding cycle. An N -bit full flash ADC requires 2N quantization
levels, while a folding ADC needs 2N /F levels, allowing the use of the folding
signal signs for the determination of the LSBs and F levels for the generation
of the MSBs of the output code.
136 Data Converters, Phase-Locked Loops, and Their Applications

MSB
x−bit coarse ADC Digital encoder
input stage & synchronizer
MSB−x

Folding
Comparator
amplifier 1

Comparator

Interpolator
In T/H

Decoding & Error correction

Comparator

Folding
Comparator MSB−(x+1)
amplifier 2

LSB

Folding
Comparator
amplifier N F

Comparator
Interpolator

−1

Comparator

Pre−processing Fine conversion

FIGURE 4.43
Block diagram of a folding and interpolating ADC.

The folding and interpolating converter, as shown in Figure 4.43, con-

sists of two ADCs operating in parallel. The coarse ADC quantizes the input
signal and provides the MSBs, while the fine ADC, which includes an ana-
log preprocessing stage, is used for the generation of the LSBs. The outputs
at the boundaries of the resistor interpolation structure are generally cross-
connected to alleviate the effects caused by the asymmetrical nature of the
network edges. As a result, the translational symmetry of the impulse response
of the resistor network is preserved. The mitigation of the delay effect intro-
duced by the analog preprocessing between the MSBs and the other bits is
achieved by a bit-synchronization block. Otherwise, a misalignment of the dif-
ferent bits can be observed for high-frequency inputs. The decoder transforms
the comparator output signals into a binary code.
The total resolution of the folding ADC is given by

N = NMSB + NLSB (4.66)

where NMSB and NLSB are the numbers of bits resolved in the coarse and fine
converters, respectively. Let F be the folding factor, I denote the interpolation
factor, NF represent the number of primary folding signals, and NI be the
Nyquist Analog-to-Digital Converters 137

MSB
SET
2−bit coarse ADC Digital encoder
input stage & synchronizer MSB−1
RST

C0
Folding +− D Q

amplifier 1 −+ D Q
R1 R1
C1
+− D Q

−+ D Q
R1 R1 b1
C2
+− D Q
In T/H
−+ D Q
b2

Output buffer
R1 R1

Gray−to−binary encoder
CK1 C3 g1 b3
+− D Q

−+ D Q
g2
b4
R1 R1
C4 g3
Folding +− D Q b5
amplifier 2 −+ D Q
R1 R1
C5
+− D Q D SET Q
−+ D Q CK 3 RST Q
R1 R1
C6
+− D Q

−+ D Q Circular−to−Gray encoder

R1 R1
C7
+− D Q

−+ D Q
R1 R1
CK 2

FIGURE 4.44
Block diagram of a 5-bit folding and interpolating ADC.

total number of interpolated signals [20]. We have

F = 2NM SB (4.67)

and
NI = 2NLSB (4.68)
while the total number of folding amplifier is computed as the ratio between
the total number of primary folds and the interpolation factor,

NF = NI /I (4.69)

It can be shown that NF F = 2N /I. In practice, F and I are assumed to

be a power of two. For a given resolution, the choice of F , I, and NF is
determined by the trade-off to be made between the bandwidth, speed, and
power consumption of the converter.
138 Data Converters, Phase-Locked Loops, and Their Applications
T3
+ − D Q

VREF − + D Q Digital encoder & synchronizer

3R/2 T2
+ − D Q
MSB
3 − + D Q

R T1
+ − D Q
Vi
2 − + D Q
MSB−1

R T0
+ − D Q

1 − + D Q RST

R/2 CK2

SET

C0 C0

FIGURE 4.45
Block diagram of the coarse ADC.

V
0

11 T
0
Coarse ADC

10 T
1
01 T
2
00 T
3
V V FSR
0 1/4 1/2 3/4 1 i

V C VF1
0 0

111
110
101
Fine ADC

100 MSB
011
010 MSB−1
001
000 MSB−2
V V FSR
0 1/4 1/2 3/4 1 i 0 1/8 1/4 3/8 1/2 5/8 3/4 7/8 1
(a) (b) V V FSR
i

FIGURE 4.46
(a) Transfer characteristic of a 5-bit folding and interpolating ADC; (b) illus-
tration of the synchronization between the coarse ADC bits and MSB-2.

The numbers of comparators in flash and folding ADCs are summarized in

Table 4.8. For the same resolution, the flash ADC requires more comparators
than the folding ADC. The use of the folding technique then results in an
important reduction in the comparator number as the converter resolution is
increased.
A 5-bit full flash ADC includes at least thirty-one comparators. Using a
folding and interpolating architecture based on a 2-bit coarse ADC and a 3-bit
fine ADC, as shown in Figure 4.44, the number of comparators can be reduced,
leading to a decrease in chip area and power consumption [21]. In this case,
Nyquist Analog-to-Digital Converters 139

TABLE 4.8
Number of Comparators in Flash ADC and Folding ADC versus the Converter
Resolution

Number of Comparators
5 bits 6 bits 7 bits 8 bits
Flash ADC 31 63 127 255
Folding ADC with a 2-bit coarse ADC 11 19 35 67
Folding ADC with a 3-bit coarse ADC 11 15 23 39

the reference voltages for the folding amplifier F1 and F2 are, respectively, as
follows:
F1 : (1/32)VREF (9/32)VREF (17/32)VREF (25/32)VREF
F2 : (5/32)VREF (13/32)VREF (21/32)VREF (29/32)VREF
Only two primary folded signals are generated and the remaining ones are
recovered by interpolation. By using two interpolators with a factor of 4, the
fine ADC required eight comparators. The output code provided by these
comparators is repeated for every sixteen quantization levels and the overall
input range of the converter involves two folding cycles. Taking into account
the four comparators required in the coarse ADC, which is based on the flash
architecture, as shown in Figure 4.45, the total comparator count for the
folding and interpolating converter is twelve.
The transfer characteristic of the 5-bit folding and interpolating ADC is
shown in Figure 4.46(a). Due to the finite slew rate of the folding amplifier,
the triangular characteristic is approximated by a sinusoidal-like waveform.
The comparator outputs of the fine ADC form a circular code, which can be
converted into Gray representation using XOR gates. The circular-to-Gray
encoder is based on the next Boolean expressions:
g1 = C3 (4.70)
g2 = C5 ⊕ C1 (4.71)
g3 = (C6 ⊕ C4 ) ⊕ (C2 ⊕ C0 ) (4.72)
Note that the bit C7 , which is not actually connected to the encoder, can be
useful in the case where the circular code must be represented as a thermome-
ter code.
Note that the transition between a group of 1s and a group of 0s in the
circular code can also be detected using two-input XOR gates, whose Boolean
equations are expressed as follows:
(
C0 ⊕ C7 , if j = 0
cj = (4.73)
Cj ⊕ Cj−1 , if j = 1, 2, · · · , 7.
140 Data Converters, Phase-Locked Loops, and Their Applications

The XOR gate outputs, cj , are then to be applied to a ROM structure for the
conversion to Gray or binary representation.
For the coarse ADC, which is based on the flash architecture, the compara-
tor outputs constitute a thermometer code to be converted into the binary
representation. In addition to the minimum of three comparators required by
a 3-bit flash converter, the coarse ADC also includes a comparator for the
generation of the over-range signal. Ideally, the bit transitions of the coarse
and fine ADCs should be exactly synchronized, as illustrated in Figure 4.46(b)
for the 3 MSBs. However, this is not the case in practice because the coarse
and fine ADCs operate independently and exhibit different delays. A bit-
synchronization section is associated with the digital encoder of the coarse
ADC to prevent errors from occurring in the output code, as shown in Fig-
ure 4.47. It should be noted that the critical regions are located near the MSB
transitions. The coarse ADC bits can then be expressed as
M SB = C0 · T1 + T2 (4.74)
M SB − 1 = C0 · T0 + T3 (4.75)
where C0 is obtained from the fine ADC and is used as a bit-synchronization
signal.
Digital output

error

Input voltage

MSB

MSB−1

MSB−2

0 1/8 1/4 3/8 1/2 5/8 3/4 7/8 1

V V FSR
i

FIGURE 4.47
Effect of the misalignment between the coarse ADC bits and MSB-2.

For proper operation of the folding and interpolating ADC, the output
code should be set to the maximum or minimum value, respectively, provided
the input voltage is greater than the highest reference voltage or lower than the
lowest reference voltage. However, the MSBs saturate at the end of the input
range while the LSBs wrap around due to the circular nature of the folding
signals. For instance, the code 00000 is changed to 00111 as the input voltage
decreases; and with the input voltage increasing, the code 00111 becomes
Nyquist Analog-to-Digital Converters 141

TABLE 4.9
Circular and Binary Codes for the 5-Bit Folding and Interpolating ADC

Circular Code Binary Code

C7 C6 C5 C4 C3 C2 C1 C0 MSB MSB-1 MSB-2 MSB-3 LSB
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 1 1 0 0 0 1 0
0 0 0 0 0 1 1 1 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0 1 0 0
0 0 0 1 1 1 1 1 0 0 1 0 1
0 0 1 1 1 1 1 1 0 0 1 1 0
0 1 1 1 1 1 1 1 0 0 1 1 1
1 1 1 1 1 1 1 1 0 1 0 0 0
1 1 1 1 1 1 1 0 0 1 0 0 1
1 1 1 1 1 1 0 0 0 1 0 1 0
1 1 1 1 1 0 0 0 0 1 0 1 1
1 1 1 1 0 0 0 0 0 1 1 0 0
1 1 1 0 0 0 0 0 0 1 1 0 1
1 1 0 0 0 0 0 0 0 1 1 1 0
1 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 1 1 0 0 0 1
0 0 0 0 0 0 1 1 1 0 0 1 0
0 0 0 0 0 1 1 1 1 0 0 1 1
0 0 0 0 1 1 1 1 1 0 1 0 0
0 0 0 1 1 1 1 1 1 0 1 0 1
0 0 1 1 1 1 1 1 1 0 1 1 0
0 1 1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 0 1 1 0 0 1
1 1 1 1 1 1 0 0 1 1 0 1 0
1 1 1 1 1 0 0 0 1 1 0 1 1
1 1 1 1 0 0 0 0 1 1 1 0 0
1 1 1 0 0 0 0 0 1 1 1 0 1
1 1 0 0 0 0 0 0 1 1 1 1 0
1 0 0 0 0 0 0 0 1 1 1 1 1

00000. An over-range and under-range detection mechanism is required to set

or reset the output latches. The signals to detect the over-range and under-
range conditions are given by

RST = M SB · IR (4.76)
142 Data Converters, Phase-Locked Loops, and Their Applications

and

SET = M SB · IR (4.77)

where
IR = (C0 + T0 ) · (C0 + T3 ) (4.78)
The logic state of IR can be used to flag out-of-range signals. Table 4.9 summa-
rizes the output codes of the 5-bit folding and interpolating ADC. The MSB
and MSB-1 delivered by the coarse ADC are necessary for the identification
of each fold, and the MSB-2, MSB-3, and LSB are derived from the circular
code available at the comparator outputs of the fine ADC.
CMOS folding and interpolating converters can achieve resolutions of 8 to
10 bits at sampling frequencies comparable to that of a flash ADC and are
suitable for low-power applications. However, the converter operation can be
affected by nonideal effects, such as offsets in the comparators required for
the zero-crossing detection. Furthermore, without a front-end track-and-hold
circuit, the converter performance can be limited by distortions due to the
nonlinear transfer characteristic of folders.

4.1.6 Sub-ranging ADC

A solution for the reduction of the hardware growth with the number of bits
resolved can consist of achieving the analog-to-digital conversion in two steps
as shown in Figure 4.48 [22]. The input is first tracked and held and then
digitized by the L-bit ADC to produce the MSBs, which are applied to the
DAC and the result is subtracted from the T/H output signal. This difference
denotes the residue of the first step and is extended to the full scale by a 2L
amplification before being processed by the (N-L)-bit ADC, which determines
the LSBs. A summer can then combine a delayed version of the MSBs and
the LSBs to yield the final N-bit word.

L−bit L−bit (N−L)−bit

In T/H Σ 2L
ADC DAC ADC

L−bit Out
Σ
Latch (N bits)

FIGURE 4.48
Block diagram of a sub-ranging ADC.

Sub-ranging ADCs can reach an accuracy of 10 to 12 bits and possess the

latency of two clock cycles. This latter is the delay between the instant of the
conversion initiation of an input sample and the instant at which the corre-
sponding digital data are being made available. With a speed comparable to
Nyquist Analog-to-Digital Converters 143

the one of a flash ADC, a sub-ranging ADC uses far less hardware for the same
resolution. For example, an N -bit flash converter requires 2N −1 comparators,
while a two-stage sub-ranging structure needs only 2(2N/2 − 1) comparators.
However, the design of high-resolution sub-ranging ADCs remains limited by
practical circuit nonidealities such as component mismatches, charge injection,
offset, noise, and finite amplifier gain and bandwidth.

4.1.7 Pipelined ADC

A pipelined ADC is another type of sub-ranging ADC, derived by break-
ing a high-resolution conversion into multiple steps. Pipelined converters are
attractive for applications, such as image and video processing, digital com-
munication, and instrumentation, that require a resolution from 10 to 16 bits
and data throughput greater than 5 Ms/s.
The pipelined ADC architecture shown in Figure 4.49 includes a T/H
circuit, a cascade of M − 1 coarse conversion stages, followed by a fine con-
verter. The cascaded stages are structurally similar, consisting of a sub-ADC
(SADC), a DAC, and an amplifier with a gain factor of 2nk . Each of these
stages, for instance, performs a coarse conversion of the incoming full-scale
ramp signal and generates a residue signal that corresponds to an amplified
version of the quantization error. The parameter nk (k = 1, 2, · · · , M − 1)
represents the number of bits resolved by the k-th stage of the converter, and
the fine converter exhibits a resolution of nM bits.
Vi Vres

t Vi Σ n
2 k V res Vi
Gain
stage
Vi
n k−bit coarse n k−bit
ADC DAC

Digital code
n k bits

Vi

Vi

Analog Stage 1 Stage k Stage M−1 Fine ADC

input T/H
n 1 bits n k bits n M−1 bits n M bits

N−bit digital
Correction & decoding section output

FIGURE 4.49
Block diagram of a pipelined ADC.
144 Data Converters, Phase-Locked Loops, and Their Applications

The first processing step is performed by the T/H circuit and amounts
to acquiring a sample of the input signal. The resulting output is digitized
by the SADC to provide the first n1 MSBs, which are also transformed into
the corresponding analog voltage by the n1 -bit DAC. The residue obtained
by subtracting the n1 -bit DAC output from the sampled-and-held input is
amplified by a factor of 2n1 so that its maximum swing is readjusted to the
ADC full scale. This amplified residue is passed to the subsequent stages,
where identical operations are performed. Finally, the different digital codes
are appropriately synchronized to eliminate the clock delay and combined to
produce the required N -bit full ADC resolution. Thus,
M−1
X
N= nk + nM (4.79)
k=1

Note that the amplification of the residue signal helps keep the signal level
constant, allowing the use of the same reference source for all sub-ADCs and
yielding a reduced sensibility of the last stages to circuit imperfections such as
noise, offset voltages, switch charge injection, and parasitic-loading capacitors.
Furthermore, the insertion of a track-and-hold circuit between the
pipelined stages to allow a concurrent operation of all stages can result in a
high conversion throughput. However, this is achieved at the cost of increased
latency and power consumption.
Vres /V REF Vres /V REF

1 1
00 01 10 11 00 01 10 11

0 V i /VREF V i /VREF
−1 1

−1 −1
−1 −1/2 0 1/2 1

(a) (b)

FIGURE 4.50
(a) Ideal and (b) practical residue-input signal transfer characteristics.

Let us consider a 2-bit pipelined stage for the analysis of the circuit
imperfection effects on the residue waveform for a full-scale ramp input
signal [23, 24]. The ideal relationship between the amplified residue signal,
Vres , and the input signal is shown in Figure 4.50(a). The reference levels
(0, ±VREF /2) of the flash SADC set the position of transitions, whose mag-
nitude at the code boundary is determined by the DAC and the gain of the
interstage amplifier. The different output voltage contributions of the DAC
are ±VREF /4 and ±3VREF /4. The signal Vres is a linearly increasing function
of the input, the magnitude of which is between two adjacent thresholds of
the SADC comparator. Once the input signal reaches a threshold level, the
Nyquist Analog-to-Digital Converters 145

signal Vres abruptly changes in the opposite direction while remaining within
the full scale. Note that the residue is multiplied by the interstage gain of 4
to exactly fit the full-scale of the next stage.
Practical converters can exhibit some linearity errors (see Figure 4.50(b))
such as missing codes. This can be the result of a missing decision level or
the loss of a digital code at a DAC input caused by a residual voltage, which
exceeds the actual conversion range due to the gain error of the interstage
amplifier and offset voltages.
The over-range errors of the residual voltage can be corrected by reducing
the interstage gain to 2 (see Figure 4.51(a)) [23]. For a full-scale input, the
signal Vres of the pipelined stage k should remain between −VREF /2 and
VREF /2. Any excursion of Vres outside this range is considered an error, which
can be detected by adding extra quantization levels to the stage k + 1. The
SADC outputs representing these quantization levels are used by the digital
correction to either increment or decrement the output code of the stage k for
a residue signal greater than VREF /2 or less than −VREF /2, respectively. This
correction approach works successfully for decision errors as large as ±VREF /4
or ±1/2 LSB.
Vres /V REF Vres /V REF

1 1
00 01 10 11 00 01 10 11
1/2 1/2

0 V i /VREF 0 V i /VREF

−1/2 −1/2

−1 −1
−1 1/2 0 1/2 1 −1 −1/4 0 1/4 3/4 1

(a) (b)

FIGURE 4.51
Residue-input signal transfer characteristics (a) with a gain of 2 and (b) with
VREF /4 offset voltage.

Vi Σ 2 V res
Gain
stage
Σ VREF /4 VREF /4 Σ

2−bit 2−bit
coarse ADC DAC

2−bit
digital code

FIGURE 4.52
An equivalent model of the 2-bit stage with offset adjustments.
146 Data Converters, Phase-Locked Loops, and Their Applications
Vres /V REF

1
00 01 10
Vi Σ 2 Vres 1/2
− Gain
stage 0 V i /VREF
1.5−bit 1.5−bit
coarse ADC DAC
−1/2

3−Level digital −1
−1 −1/4 0 1/4 1
code
(a) (b)

FIGURE 4.53
(a) A 1.5-bit stage of the pipelined ADC; (b) residue-input signal transfer
characteristic.

The arithmetic of the correction section can be reduced to an addition op-

eration using the stage architecture of Figure 4.52. By appending a −VREF /4
offset voltage to the SADC and DAC, the signal Vres now varies from −VREF
to VREF /2. Because the locations of the SADC decision levels and the DAC
reference voltages are uniformly shifted by the offset value, a negative over-
range condition is prevented for errors up to ±VREF /4. This eliminates the
requirement for the subtraction function in the correction logic.
As shown in Figure 4.51(b), the top decision level can be fixed at VREF /4
for each stage except the last one. The comparator with the threshold at
3VREF /4 is not required because the amplified residue signal falling above the
expected range can be detected by the next stage. The MSB of each pipelined
stage can then be resolved by an SADC with only 1.5-bit resolution. In this
case, the comparator reference voltages of the SADC are at ±VREF /4 and the
output levels of the DAC include ±VREF /2 and 0. Table 4.10 summarizes the
characteristics of the 2-bit and 1.5-bit pipelined stages.

TABLE 4.10
Characteristics of 2-Bit and 1.5-Bit Pipelined Stages

2-Bit/stage 1.5-Bit/stage
Input range From −VREF to VREF From −VREF to VREF
SADC threshold levels −VREF /2, 0, VREF /2 −VREF /4, VREF /4
Number of comparators 3 2
−3VREF /4, −VREF /4,
DAC reference levels VREF /4, 3VREF /4 −VREF /2, 0, VREF /2
Output digital code 00, 01, 10, 11 00, 01, 10
Inter-stage gain 4 2

Here, the nonideal effect of the component is reduced by introducing a

redundancy in the pipelined ADC. That is, the resolution of the converter
Nyquist Analog-to-Digital Converters 147

should be less than the sum of the ones provided by single stages. The extra
bits are eliminated at the output by the digital correction.

Vi Σ 2 Vres Vi 2 Σ Vres
− −

1.5−bit 1.5−bit 1.5−bit 1.5−bit

ADC DAC ADC DAC

−
+V
− − −
REF /4 Digital +V REF /2 + V REF /4 Digital + V REF
code code

FIGURE 4.54
Scaling of the 1.5-bit pipelined stage for the switched-capacitor implementa-
tion.

φ
2

φ C2 φ’
1 1

V φ
i C1
1
−
+VREF V0
+
3R/2
+ −

+VREF /4 − +
+VREF
φ
2
R
+ −
φ
1
−VREF /4 − + t
b k,MSB b k,LSB −VREF φ
3R/2 2
MSB t
φ φ’
−VREF 2 DAC & 2x Amplification 1
t
(a) Sub−ADC (b)

FIGURE 4.55
(a) A switched-capacitor implementation of the 1.5-bit stage circuit; (b) timing
diagram.

For the switched-capacitor (SC) implementation, the block diagram of the

1.5-bit pipelined stage can be scaled as shown in Figure 4.54. This allows the
use of an adequate clocking scheme to maintain a synchronization between
the signal paths. Let Vi be the input voltage and VREF denote the reference
voltage. Ideally, the amplified residue signal generated by the k-th stage can
then be written as
Vres(k+1) = 2Vres(k) − Dk VREF k = 1, 2, · · · , M − 1 (4.80)
where 

−1 if Vres(k) < −VREF /4
Dk = 0 if − VREF /4 < Vres(k) < VREF /4 (4.81)


1 if Vres(k) > VREF /4
148 Data Converters, Phase-Locked Loops, and Their Applications

and Vres(1) = Vi . A single-ended SC implementation of the 1.5-bit pipelined

stage is depicted in Figure 4.55. This circuit includes a flash SADC and a mul-

DAC & 2x Amplification φ

2

φ C2 φ’
1 1

Vi− φ C1
1
− + V0+

+− V0−
φ
Vi+ 1 C1

φ φ’
1 C2 1

φ
2

+VREF

− +
3R/2 −
+
+VREF /4 +−
+VREF −VREF
φ
R 2

−VREF /4 − +
−
3R/2 +
+−
−VREF
Sub−ADC
−VREF +VREF

b k,MSB b k,LSB

FIGURE 4.56
Differential version of the switched-capacitor implementation of the 1.5-bit
stage circuit.

tiplying DAC (MDAC), which performs the multiplication by two followed by

the digital-to-analog conversion of the SADC output, the track-and-hold func-
tion and the two times amplification of the input signal, and the subtraction.
It operates with two-phase nonoverlapping clock signals. To reduce the effect
of the difference in propagation delay between the signal paths, the charges
due to the held and reconverted versions of the input signal are transferred
toward the output during the same clock phase, φ2 . The comparators used
in the SADC can be designed using an input-sensing preamplifier followed by
a regenerative latch, and the control signals of the MDAC are derived from
the outputs of a thermometer-to-binary encoder. The amplifier should be de-
signed with a dc gain and bandwidth such that it can settle within ±1/2 LSB
accuracy in one-half of the clock signal period. The output signal, V0 , is given
Nyquist Analog-to-Digital Converters 149

by
 
 C1

 1+ Vi − VREF if Vi > VREF /4

 C2


 C1

V0 = 1+ Vi if − VREF /4 ≤ Vi ≤ VREF /4 (4.82)

 C2

 

 C1

 1+ Vi + VREF if Vi < −VREF /4
C2

The stage gain of 2 is realized for C1 = C2 . By requiring only two capacitors,

the amplifier loading requirement of the resulting 1.5-bit pipelined stage is re-
laxed, yielding a reduced sensibility to noise and an improved operation speed.

1.5 bit 1.5 bit 1.5 bit 1.5 bit 1.5 bit 1.5 bit
In T/H
MDAC MDAC MDAC MDAC MDAC MDAC

1.5 bit 1.5 bit 1.5 bit 1.5 bit 1.5 bit 1.5 bit 2 bit
ADC ADC ADC ADC ADC ADC ADC

2 2 2 2 2 2 2
D
Q
CK

D D
Q Q
CK CK

D D D
Q Q Q
CK CK CK

D D D D
Q Q Q Q
CK CK CK CK

D D D D D
Q Q Q Q Q
CK CK CK CK CK

D D D D D D
Q Q Q Q Q Q
CK CK CK CK CK CK

D D D D D D D
Q Q Q Q Q Q Q
CK CK CK CK CK CK CK

CK

Digital adder

Out (8 bits)

FIGURE 4.57
Block diagram of an 8-bit pipelined ADC including a digital correction stage.

A differential version of the 1.5-bit pipelined stage is shown in Fig-

ure 4.56 [25]. The zero reference is implemented by shorting the DAC output
together. It should be noted that differential circuits have the advantage of
increasing the signal dynamic range. In a pipelined ADC, the first stage gen-
erates the MSB of the resulting digital code, while subsequent stages increase
150 Data Converters, Phase-Locked Loops, and Their Applications
+VREF
V
i

R + −

+VREF /2 − +

R + −
MSB
0 − +

R
+ − LSB

−VREF /2 − + V
DD

R
φ
2
−VREF

FIGURE 4.58
Circuit diagram of a 2-bit flash ADC.

the resolution of the input signal conversion by delivering additional bits in less
significant positions of the output code. Figure 4.57 shows the block diagram
of an 8-bit pipelined ADC, which is based on 1.5-bit stage with an inter-stage
amplifier gain of 2. The amplified residue of each pipelined stage, except the
last one, is quantized by the following stage. Because the last stage does not
need to generate a residue, it can be implemented as the 2-bit flash ADC
shown in Figure 4.58. A resistor network is used to set the reference levels of
the three latched comparators to −VREF /2, 0, and VREF /2, respectively, and
the thermometer-to-binary encoder is based on few logic gates.
Adjacent stages of the pipelined ADC should be driven by the clock signals
with opposite phases to ensure a concurrent operation. There is a delay of a
half clock cycle between the instants at which the outputs of two consecutive
stages are available. One input signal sample then requires several clock cycles
to be processed by the overall pipelined ADC. The output codes (bk,MSB and
bk,LSB , k = 1, 2, · · · , M ) of the different pipelined stages are synchronized
using an array of D latches, and then summed to produce the converter output
code with B1 being the MSB.
By exploiting the 0.5-bit redundancy on each stage to correct any decision
error in the previous adjacent stage, the concept of the error correction circuit
can be illustrated as follows:

b1,MSB b1,LSB
b2,MSB b2,LSB
··· ···
··· ···
bM−2,MSB bM−2,LSB
bM−1,MSB bM−1,LSB
+ bM,MSB bM,LSB
B1 B2 ··· ··· ··· BN −2 BN −1 BN
Nyquist Analog-to-Digital Converters 151

This correction scheme works well as long as the comparator offset magnitudes
are not so high (i.e., less than VREF /4) as to cause missing codes. In this
example, the digital correction should remove the redundancy and deliver an
8-bit output data. It can simply be based on addition. Thus, the correction
consists of summing the MSB of a given stage with the LSB of the previous
stage. Here, the digital correction cannot be extended to the LSB of the last
stage. This implies that either the last stage should be implemented as a 2-bit
full flash ADC or using two 1.5-bit stages with the LSB of the final stage being
excluded from the converter output code. Figure 4.59 shows the block diagram
of a digital adder that may be used in the 1.5-bit/stage pipelined ADC. The
propagation of the carry bit is achieved in the direction of the output code
MSB. Each 1.5-bit pipelined stage effectively provides 1 bit to the overall
resolution. The resulting output data is coded in offset binary format, which
is identical with the two’s complement representation except that the MSB
must be inverted.

Y X

HA
Ci
Y X
C0 HA

C S

b 1,MSB b 1,LSB b 2,MSB b M−2,LSB b M−1,MSB b M−1,LSB b M,MSB b M,LSB

Y X Y X Y X

C0 FA M−2 Ci C0 FA 1 Ci C0 HA
S S S

B1 B2 BN−2 BN−1 BN

FIGURE 4.59
Block diagram for the digital correction stage (HA: half adder; FA: full adder).

For the 1.5-bit/stage pipelined ADC, the sequence of output digits does not
form a conventional binary number representation because the bits are signed.
The 1.5-bit stage generates three digits and exhibits a radix of 2. Because
the number of digits is greater than the radix, there is a redundancy in the
sequence of output digits. Hence, more than one combination of digits can be
used to represent the same magnitude of a signal sample. The 1.5-bit/stage
pipelined ADC is then equivalent to a redundant signed digit system.
It should be noted that, from the input to the output of the converter, the
input-referred noise contribution of the pipelined stages is reduced after each
stage due to the cumulative scaling effect of the interstage gain on the signal
152 Data Converters, Phase-Locked Loops, and Their Applications

level. Hence, capacitors can be scaled down toward the later stages to reduce
the power consumption [26].

Consider both circuit diagrams of Figure 4.60, which represent

the different versions of the MDAC generally used in the imple-
mentation of the 1.5-bit-per-stage pipelined ADC architecture.
φ φ
2 2

φ C2 φ φ C2
1 1 1

V φ V φ
i C1 i C1
1 1
φ φ
− 2 − 2
V0 V0
φ + φ φ +
2 2 1

D kVREF D kV
REF
(a) (b)

FIGURE 4.60
Two configurations of the SC MDAC for the 1.5-bit stage.

During the clock phase φ1 , (n − 1 < t ≤ n − 1/2), according

to the MDAC circuit depicted in Figure 4.60(a), the input volt-
age is sampled onto capacitors C1 and C2 , and the amplifier
is configured as a unity-gain follower. Assuming that A0 is the
amplifier dc gain, it can be shown that

V0 (n − 1/2) = A0 [V + (n − 1/2) − V − (n − 1/2)] (4.83)

where V + (n − 1/2) = Vof f and V − (n − 1/2) = V0 (n − 1/2).

During the clock phase φ2 , (n − 1/2 < t ≤ n), the capacitor C1
is connected to Dk VREF , while C2 acts as a feedback capacitor.
The application of the charge conservation law at the negative
input terminal of the amplifier yields

C1 [Dk VREF − V − (n)] − [Vi (n − 1/2) − V − (n − 1/2)]
 (4.84)
= C2 [V − (n) − V0 (n)] − [V − (n − 1/2)) − Vi (n − 1/2)]
and
V0 (n) = A0 [V + (n) − V − (n)] (4.85)
+
where V (n) = Vof f . Because

µ
V − (n − 1/2) = V0 (n − 1/2) = Vof f (4.86)
1+µ
and
V − (n) = Vof f − µV0 (n) (4.87)
Nyquist Analog-to-Digital Converters 153

where µ = 1/A0 , it can be shown that

" !#
C1
1+µ 1+ V0 (n)
C2
! ! (4.88)
C1 C1 µ C1
= 1+ Vi (n − 1/2) − Dk VREF + 1+ Vof f
C2 C2 1+µ C2

Finally, the output-input relationship in the z-domain can be

derived as
! !
C1 C1 µ C1
1+ z −1/2 Vi (z) − Dk VREF + 1+ Vof f
C2 C2 1+µ C2
V0 (z) = !
C1
1+µ 1+
C2
(4.89)
An alternative MDAC structure is shown in Figure 4.60(b). Its
operation is similar to the first one, except during the phase φ2 ,
where the amplifier is now used in the open-loop configuration
and V − (n − 1/2) = 0. The output-input relationship in the z-
domain is then of the form
! !
C1 −1/2
C1 C1
1+ z Vi (z) − Dk VREF + 1 + Vof f
C2 C2 C2
V0 (z) = ! (4.90)
C1
1+µ 1+
C2

For a sufficiently high dc gain, µ tends to zero and it appears

that the second MDAC exhibits an increased sensibility to the
effect of the offset voltage. Ideally, the input signal is multiplied
by a factor of 2 for C1 = C2 .
Assuming that the effects of the amplifier imperfections are neg-
ligible, the linearity of the converter can still be limited by the
capacitor mismatch. With αk being the ratio mismatch between
C1 and C2 , that is, C1 = (1 + αk )C2 , the output voltage of the
MDAC can be expressed as

V0 (z) = 2(1 + αk /2)z −1/2 Vi (z) − Dk (1 + αk )VREF (4.91)

In order to fulfill the N -bit resolution requirement, any deviation

error due to a component imperfection should be no larger than
LSB/2, or 1/2N −k−1 for the k-th pipelined stage.
154 Data Converters, Phase-Locked Loops, and Their Applications

The correction logic in the 1.5-bit/stage pipelined ADC is implemented

as an addition with the carry propagation of the overlapping correction bits.
Although this technique is very simple, it can only correct the offset voltage
effect of SADC comparators. The resulting resolution is then limited to 10
bits due to the effect of errors introduced by the finite gain and bandwidth of
the amplifier, capacitor mismatches, and noise on the accuracy of the digital-
to-analog conversion and interstage amplifier gain.
The use of laser wafer trimming to adjust the values of circuit components
during the IC test results in the enhancement of the converter resolution. But
this approach can be limited by aging and temperature variations, which can
affect the matching accuracy, and by the extra production cost.
To enable a high resolution, various other circuit techniques (digital
calibration, capacitor averaging, dithering, gain-boosting method) can be
used [27–30], generally at the price of an increased circuit complexity and
power consumption, and a reduced conversion speed.
With a uniform per-stage resolution, the design is modular, but the use of
a multi-bit stage at the converter input can greatly relax the matching and
noise requirements for the following stages. In [31], a converter resolution of
14 bits is achieved using a 4-bit pipelined stage followed by eight 1.5-bit stages
and a 3-bit flash ADC. Note that the stage resolution is generally not greater
than 4 bits to maintain the converter power consumption at an acceptable
level.

The principle of the redundant sign digit coding can also be ex-
ploited in the design of pipelined stages with a resolution greater
than 1.5 bits.
φ
2

φ C2 φ
1 1

V φ
i C1
1
φ
− 2
φ V0
2 +
D V
1k REF
φ C1
1

φ
2
D V
2k REF
φ C1
1

φ
2
D 3kVREF

FIGURE 4.61
Circuit diagram of the 2.5-bit SC MDAC.
Nyquist Analog-to-Digital Converters 155

In the specific case of a 2.5-bit stage, the SADC has six reference
levels of the forms, ±VREF /8, ±3VREF /8, and ±5VREF /8. In
the ideal case, the amplified residue signal generated by the k-th
stage can be obtained as

Vres(k+1) = 4Vres(k) − Dk VREF k = 1, 2, · · · , M − 1 (4.92)

where


 −3 if Vres(k) < −5VREF /8



 −2 if − 5VREF /8 < Vres(k) < −3VREF /8



 if
−1 − 3VREF /8 < Vres(k) < −VREF /8
Dk = 0 if − VREF /8 < Vres(k) < VREF /8 (4.93)


1
 if VREF /8 < Vres(k) < 3VREF /8



 2 if 3VREF /8 < Vres(k) < 5VREF /8



3 if Vres(k) > 5VREF /8

and Vres(1) = Vi . To maintain the residue output voltage within

±VREF , the value of the comparator offset voltage should not
exceed ±VREF /8. The representation in the binary format of
the SADC comparator outputs can result in seven codes, which
are 000, 001, 010, 011, 100, 101, and 110.
The circuit diagram of a 2.5-bit MDAC is shown in Figure 4.61,
where C1 and C2 should have the same value. During the first
phase of the clock signal, the capacitors C1 are connected to
the input voltage. In the second clock phase, the capacitor C2
is included in the amplifier feedback loop, while the capacitors
C1 are set to the appropriate values of the reference voltage.
Ideally, the output voltage is given by
 
3C1 −1/2 C1
V0 (z) = 1 + z Vi (z) − (D1k + D2k + D3k )VREF (4.94)
C2 C2

where D1k , D2k , and D3k are equal to −1, 0, or 1, depending on

the output of the SADC. The MDAC output signal correspond-
ing to a given SADC digital code is generated by appropriately
switching each of the three capacitors C1 to one of the reference
levels, −VREF , 0, or VREF .

4.1.8 Algorithmic ADC

Algorithmic or cyclic analog-to-digital converters (ADCs) [32–35], which are
based on the binary division principle, are useful in applications requiring low
power consumption and chip area. The core of an algorithmic ADC, as shown
156 Data Converters, Phase-Locked Loops, and Their Applications

Start
Vi
Vx CK Shift
T/H + Digital
register output

2 −
Gain
stage Comparator

V REF

Σ
−VREF

FIGURE 4.62
Block diagram of an algorithmic ADC.

in Figure 4.62, consists of a T/H circuit, precision multiply-by-two amplifier,

comparator, and summer.
Let k be the number of conversion cycles and bk the bit to be determined.
The residue signal, Vx , which is considered the partial remainder of a division,
can be expressed as
(
2Vi for k = 1
Vx(k) = bk−1
(4.95)
2Vx(k−1) + (−1) VREF otherwise,

where (
1 if Vx(k−1) ≥ VREF
bk = (4.96)
0 if Vx(k−1) < VREF
and k = 1, 2, 3, · · · , N . The iterative execution of this algorithm produces a
digital output code in the offset binary representation. At each conversion
step, the operation of the algorithmic ADC involves a magnitude comparison,
a bit selection, and a decision-dependent summation.
The input signal is first selected using the input switch before being sam-
pled by the T/H circuit. The resulting signal, Vx , is applied at the input of
the comparator. If Vx is greater than zero, the selected bit will be set to the
high logic state and VREF will be subtracted from 2Vx ; otherwise, this bit
will take the low logic state and VREF will be added to 2Vx . By closing the
feedback loop through the operation of the input switch, the residue is sent
back to the input of the T/H circuit and the determination of the remaining
LSB bits proceeds in the same manner. It should be emphasized that each bit
of the digital output code is kept in the shift register after its determination.
Starting with the MSB, each bit bk is determined sequentially, depending
on the polarity of Vx(k) . By iterating up to k = N , we can obtain
" N −1
! #
X
N −1 bk −k
Vx(N ) = 2 Vi + (−1) 2 VREF (4.97)
k=1

The signal Vx can be considered the residue generated after the determination
of each bit. Hence, the set of bits bk (k = 1, 2, · · · N ) is a binary representation
Nyquist Analog-to-Digital Converters 157
S5

C2 φ φ
2 2

C5 φ
S4 2

φ −
2
S1 φ
1 +
Vi φ
S2 C1 φ 3 Shift Digital
3
− φ register output
VREF
2
C4
S3 +
−
φ
3
C3 S4 +
Reset φ
1
CK Switch control logic φ
φ 2
φ 1 φ φ
2 S 3

S1 S2 S3 S4 S5

FIGURE 4.63
Circuit diagram of an algorithmic ADC.

b b b
1 2 N

φ
S

φ
1

φ
2

φ
3

FIGURE 4.64
Clock signals for the algorithmic ADC.

of a fractional number equal to Vi /VREF , where Vi is a bipolar signal with a

range from −VREF to VREF .
To achieve a high resolution, the algorithmic ADC circuit should be de-
signed such that its sensitivity to component imperfections is minimized [36,
37]. For a given resolution, the deviation of the converter characteristic due
to these nonidealities should be maintained well below 1/2 LSB. Figure 4.63
shows the circuit diagram of a ratio-independent algorithmic ADC, which
requires a three-phase clock signal to overcome the effects of capacitor mis-
matches and offset voltages. To perform the voltage multiplication by a factor
of 2 independently of the capacitor ratio, the charge of the input capacitor
C3 due to the residue voltage, Vx , is transferred onto the feedback capacitor,
C2 , initially charged to Vx . The operation of the ratio-independent algorithmic
158 Data Converters, Phase-Locked Loops, and Their Applications

ADC is better understood by analyzing the charge transfer between capacitors

during the three phases of the clock signal.
During the first phase, a sample of the input signal is connected to the
converter and the charge due to the input voltage is stored on the capacitor
C1 .
In the second phase, C2 is connected to the amplifier output, a charge
transfer takes place between C1 and C2 , and the output of the input amplifier
is set to the voltage Vx , which is used to charge the capacitors C4 and C5 of
the next stages.
During the third phase, the charge on C2 is transferred onto C3 , while the
charge on C5 is maintained and the MSB is resolved by the comparator. Note
that the charge transfer is not affected by C1 because one of its input nodes
is floating.
For the first phase of the determination of the next bit, the capacitor C1
is charged to VREF and the charge produced by Vx on C5 is transferred onto
C2 .
In the second phase, C2 acts as a feedback capacitor and its initial charge is
combined with the ones on C1 and C3 to update the value of the residue signal,
thereby resulting in the summation of the two charge contributions associated
with the input voltage and due to the reference voltage. The derived residue
is used to charge the capacitors C4 and C5 connected to the output of the
input amplifier.
During the third phase, the state of the output bit is determined by the
comparator and the charge on C2 is transferred onto C3 .
These last three phases are then repeated for each of remaining bits to be
resolved. The ratio-independent algorithmic ADC requires three clock phases
for the determination of each bit; therefore an N -bit conversion is performed
in 3N clock phases.

TABLE 4.11
Switch Control Signals for a Bipolar Conversion

MSB Bit bk (k > 1) Bit bk

S1 φS · φ1 φS · φ1
S2 φS (bk−1 φ1 + bk−1 · φ2 ) φS (bk−1 φ1 + bk−1 · φ2 )
S3 φS · φ2 φS (bk−1 φ2 + bk−1 · φ1 ) φS · φ2 + φS (bk−1 φ2 + bk−1 · φ1 )
S4 φS (φ1 + φ3 ) φS · φ3 φS (φ1 + φ3 ) + φS · φ3
S5 φS · φ1 φS · φ1

The clock signals for a bipolar conversion can be generated according to

the Boolean logic equations of Table 4.11. In the case of a unipolar conversion
with the input signal varying between 0 and VREF , the converter switching
scheme should be slightly modified. It is necessary to exchange the control
Nyquist Analog-to-Digital Converters 159

signals for switches S2 and S3 during the determination of the MSB. As a

result, the first residue will be of the form Vx(1) = Vi − VREF .
The accuracy of the algorithmic ADC is affected by the nonlinearities
due to charge injections of switches, and offset voltages of the amplifier and
comparator. The amplifier can be designed to have enough gain and speed
such that the deviations due to the finite gain and settling time are greatly
reduced. But, the remaining uncompensated component imperfections limit
the achievable resolution to about 10 bits.

4.1.9 Time-interleaved ADC

A solution for the design of data converters operating with a speed beyond
the fundamental technological limit can consist of interleaving, in time, more
than one ADC.

In S/H ADC Σ Out In S/H ADC Σ Out

φ φ φ φ
0 0 0

S/H ADC ADC

φ φ φ
1 1 1

S/H ADC ADC

φ φ φ
M−1 M−1 M−1

φ
φ φ
0 0

φ φ
1 1

φ φ
M−1 M−1

FIGURE 4.65 FIGURE 4.66

Time-interleaved ADC with identi- Time-interleaved ADC with a
cal parallel channels. single-input S/H circuit.

One approach to control the sampling operation in time-interleaved struc-

tures is to use several clock signals, as shown in Figure 4.65, where M is the
number of parallel channels. Ideally, the effective sampling rate of the result-
ing structure is increased by M times in comparison to the one of a single
ADC. However, due to the difference in the delays between successive sam-
pling instants, dynamic distortions can be observed in the spectrum of the
output signal. This results in a degradation of the overall ADC performance.
A way to reduce the timing mismatches is to use the structure of Figure 4.66,
160 Data Converters, Phase-Locked Loops, and Their Applications

where the input signal is sampled at a high rate and then multiplexed over M
parallel channels to be processed by ADCs. The drawback of this approach
is the limited input bandwidth due to the increased capacitive loading of the
input sampling stage.
Let vi (tn ) denote the sequences obtained by sampling the band-limited
input signal at the instants tn given by

tn = (n + αm )T (4.98)

where T = 1/fs is the sampling period, αm (m = 0, 1, · · · , M −1) is the timing

offset measured in percentage of the sampling period T , and n = kM + m.

By relying on the definition

+∞
X
ci (ω) =
V vi (tn )e−jωnT (4.99)
n=−∞

to compute the signal spectrum as if the signal has been sampled uni-
formly, the digital output spectrum of the converter processing a sine
wave will exhibit line spectra whose magnitudes are frequency depen-
dent.

The spectrum of the nonuniformly sampled signal [38] can be computed

as
+∞
X
ci (ω) =
V vi (tn )e−jωtn (4.100)
n=−∞

That is,
+∞  
c 1 X 2π
Vi (ω) = A(k)Vi ω − k (4.101)
T MT
k=−∞

where
M−1
1 X −jkαm (2π/M) −jkm(2π/M)
A(k) = e e (4.102)
M m=0
and Vi (ω) is the Fourier transform of vi (t).

For αm = 0, the signal spectrum is reduced to

+∞  
c 1 X 2π
Vi (ω) = Vi ω − k (4.103)
T MT
k=−∞

which corresponds to a uniformly sampled signal.

Nyquist Analog-to-Digital Converters 161

ci (ω), can be derived as follows:

The signal spectrum, V
+∞
X
ci (ω) =
V vi (tn )e−jωtn (4.104)
n=−∞
+∞ M−1
X X
= vi ((kM + m + αm )T )e−jω(kM+m+αm )T (4.105)
k=−∞ m=0

Using
Z +∞
1
vi ((kM + m + αm )T ) = Vi (Ω)e−jΩ(kM+m+αm )T dΩ (4.106)
2π −∞

and permuting the order of the first summation and integration,

we obtain
X 1 Z +∞
M−1  X+∞ 
ci (ω) =
V Vi (Ω) e−j(Ω−ω)kMT e−j(Ω−ω)(m+αm )T dΩ
m=0
2π −∞
k=−∞
(4.107)
Because
+∞
X +∞
X  
−j(Ω−ω)kMT 2π 2π
e = δ Ω−ω+k (4.108)
MT MT
k=−∞ k=−∞

it can be shown that

X 1 Z +∞
+∞ M−1
X  
ci (ω) = 2π
V Vi (Ω)δ Ω − ω + k e−j(Ω−ω)(m+αm )T dΩ
m=0
M T −∞ M T
k=−∞
(4.109)
Hence,
+∞ M−1  
ci (ω) = 1 X X 2π
V Vi ω − k e−jk(2π/MT )(m+αm )T (4.110)
MT m=0
M T
k=−∞

and finally,
+∞
X  
ci (ω) = 1
V A(k)Vi ω − k
2π
(4.111)
T MT
k=−∞

where
M−1
1 X −jkαm (2π/M) −jkm(2π/M)
A(k) = e e (4.112)
M m=0
162 Data Converters, Phase-Locked Loops, and Their Applications

Classical time-interleaved ADC structures can be affected by the following

sources of error.

• Timing skew errors

Let us consider a sinusoidal input signal of the following form:

vi (t) = sin(ωi t) (4.113)

The Fourier transform of vi (t) is given by

Vi (ω) = jπ[δ(ω + ωi ) − δ(ω − ωi )] (4.114)

With the assumption that ωi = 2πfi , where fi is the frequency, the substitu-
tion of Equation (4.114) into (4.101) leads to the next equation,
+∞     
c 2π X 2π 2π
Vi (ω) = A(k)δ ω + ωi − k + B(k)δ ω − ωi − k
T MT MT
k=−∞
(4.115)
where
M−1
1 X jαm (2πfi /fs ) −jkm(2π/M)
A(k) = − e e (4.116)
2jM m=0

and
M−1
1 X −jαm (2πfi /fs ) −jkm(2π/M)
B(k) = e e (4.117)
2jM m=0

Note that A(k) = B ∗ (M − k), where ∗ denotes the notation for the complex
conjugate. Due to timing errors between the ADC clock signals, pairs of line
spectra centered at ±fi + mfs /M (m = 1, 2, · · · , M − 1) appear in the out-
put spectrum. The corresponding magnitudes are given by |A(k)| and |B(k)|,
respectively.
Practical time-interleaved ADCs exhibit a clock skew error of a few picosec-
onds. That is, the value of αm computed from the discrete Fourier transform
of the converter output signal is used to control programmable delays with pi-
cosecond resolution or clock signal generators. However, the major drawback
of this approach is the high complexity of the digital hardware needed for the
algorithm implementation [39]. In order to address the problem of timing skew
mismatches, the generation of clock signals can be controlled by a delay-locked
loop. Another alternative can consist of using the structure of Figure 4.66. By
not resetting between samples, the full-speed single sample and hold (S/H)
at the front-end provides subsequent circuit sections the whole clock period
to operate on the held signal and eliminates in this way the timing skew errors.
Nyquist Analog-to-Digital Converters 163

• Gain and offset dispersions

The distortions due to the gain and offset dispersions can be modeled by
assuming an input sinusoidal input signal of the form

vi (t) = Am sin(ωi t) + Vm (4.118)

where m = 0, 1, · · · , M − 1. The corresponding Fourier transform is given by

Vi (ω) = jπAm [δ(ω + ωi ) − δ(ω − ωi )] + 2πVm δ(ω) (4.119)

Substituting Equation (4.119) into (4.101), the output spectrum can be writ-
ten as
+∞
X     
ci (ω) = 2π
V A(k) δ ω + ωi − k
2π
+ δ ω − ωi − k
2π
T MT MT
k=−∞
+∞  
2π X 2π
+ V (k)δ ω − k
T MT
k=−∞
(4.120)

where
M−1
1 X
A(k) = − Am e−jkm(2π/M) (4.121)
2jM m=0

and

M−1
1 X
V (k) = Vm e−jkm(2π/M) (4.122)
M m=0

The gain error results in sidebands centered at ±fi + mfs /M . However, the
components in each pair of line spectra have the same magnitude, |A(k)|, in
contrast to distortions caused by clock skew mismatches.
The dispersion of the offset among the channels gives rise to distortions
which can be observed in the frequency domain as tones at each path sampling
frequency, fs /M , and its integer multiples. The magnitude of these spectral
lines is determined by |V (k)|.
Because the distortion power of gain and offset errors is not frequency
dependent, it can then be compensated using appropriate circuit calibration
techniques [40, 41].
In high-resolution ADCs, the thermal noise appears to be the most im-
portant nonideality. Specifically, the increase in the number of bits implies a
reduction in the noise level, which can be achieved by augmenting the com-
ponent sizes and equivalently the power consumption.
164 Data Converters, Phase-Locked Loops, and Their Applications

4.2 Summary
In practice, ADCs operating at the Nyquist rate are difficult to implement
and may require a high power consumption, especially for high resolutions.
Nyquist ADCs exhibit a quantization noise, which is uniformly spread from
0 to approximately half the sampling rate or clock signal frequency, and in-
dividually convert each input signal sample into a digital output code. They
can be categorized into SAR, integrating, flash, sub-ranging, and pipelined
architectures. In general, the achievable resolution and speed are limited by
various noise contributions, and component and timing mismatches. For a
given application, the ADC design is determined by the trade-off that can be
achieved between the resolution, speed, chip area, and power consumption.
Flash ADCs can provide a resolution ranging from 5 to 9 bits at the sam-
pling rate, while counting ADCs can offer a resolution of 10 to 20 bits at a
speed 2N times smaller than the sampling rate and with a latency equal to
the product of 2N and the clock period, where N is the number of bits. On
the other hand, pipelined ADCs can achieve a resolution of 10 to 14 bits by
operating at the sampling rate, while SAR ADCs can provide a resolution of
8 to 16 bits at a frequency equal to the sampling rate divided by the resulting
number of bits. SAR and pipelined ADCs exhibit an identical latency equal
to the product of the resolution in bits and the clock period, but they can be
designed to meet the requirement of low power consumption.

4.3 Circuit design assessment

1. Buffer amplifier for data converter interfacing
− Consider a buffer amplifier with the response to a step input
given by
v0 (t) = Vm [1 − exp(−t/τ )] (4.123)
where Vm is the maximum amplitude of the output signal and τ
is the time constant. In an application requiring a resolution of
N bits, the amplifier should be designed such that the condition
[v0 (t) − Vm ]/Vm ≤ 1/2N +1 is satisfied for t = ts = 1/(2fs ), where
fs is the sampling frequency.
Determine the time constant τ .
− In the case where the input signal is a sinusoid of the form

vi (t) = VF S sin 2πfB t (4.124)

where VF S and fB represent the signal full-scale amplitude and

Nyquist Analog-to-Digital Converters 165

bandwidth frequency, respectively, find the maximum aperture tim-

ing error ta = △V /[(dvi (t)/dt)|t=0 ], assuming that the resulting am-
plitude error |△V | is to be less than a half of the least-significant
bit (LSB) and LSB = VF S /2N .
2. Quantizer model
In analog-to-digital converters, each sample of the input signal is
quantized to fit a finite resolution. This quantization process can
be modeled using a characteristic and error function, as illustrated
in Figures 4.67(a) and (b) in the case of midtread (a) and midrise
(b) quantizers, respectively.
Assuming that the quantization error, eQ = x̂ − x, is a stationary
process and uncorrelated with the input signal, x, it can be seen
that the probability density of the quantization error is uniformly
distributed between −△/2 and △/2.

^
x x^
7∆
2
3∆ 5∆
2
2∆ 3∆
2
−9∆ −7∆ −5∆ −3∆ −∆ ∆
2 2 2 2 2 −4∆ −3∆ −2∆ −∆ 2
∆ 3∆ 5∆ 7∆
x x
−∆ ∆ 2∆ 3∆ 4∆
2 2 2 2 2
−3∆
2
−2∆
−5∆
2
−3∆
−7∆
2
−4∆

eQ eQ

∆/2 ∆/2
x x
−∆/2 −∆/2
−9∆ −7∆ −5∆ −3∆ −∆ ∆ 3∆ 5∆ 7∆ −4∆ −3∆ −2∆ −∆ ∆ 2∆ 3∆ 4∆
(a) 2 2 2 2 2 2 2 2 2 (b)

FIGURE 4.67
Characteristics and errors of (a) midtread and (b) midrise quantizers.

For both quantizers, show that

Z ∆/2
E(eQ ) = eQ p(eQ )deQ = 0 (4.125)
−∆/2

and
Z ∆/2
2 △2
σQ = E(e2Q ) = e2Q p(eQ )deQ = (4.126)
−∆/2 12

where p(eQ ) is the probability density of the quantization error and

△ is the quantizer step size.
166 Data Converters, Phase-Locked Loops, and Their Applications

3. A model for the sampling jitter estimation

The output of an S/H circuit, yk , can be computed as

yk = x(kT + δk ) + nk k∈Z (4.127)

where x(t) is the input signal, T is the sampling period, nk is the ad-
ditive sampling noise, and δk denotes the error due to the deviation
in the sampling instant.
Let
x(t) = A cos(ω0 t + φ) (4.128)
be a sinusoid signal with the amplitude A, the initial phase φ, and
the angular frequency ω0 .
Using the assumption x(kT + δk ) ≃ x(kT ) + δk x′ (kT ), where x′
represents the first derivative of x, verify that:

yk ≃ A cos(ω0 kT + φ) + ǫk (4.129)

where ǫk = −Aω0 δk sin(ω0 kT + φ) + nk .

Show that the variance of the error term ǫk can be written as

E[ǫ2k ] = E[A2 ω02 δk2 sin2 (ω0 kT + φ) + n2k ] (4.130)

2
A ω02 A 2
ω02
= σδ2 − σδ2 cos(2ω0 kT + 2φ) + σn2 (4.131)
2 2
where σδ2 = E[δk2 ] and σn2 = E[n2k ].
Propose a procedure based on the Fourier transform for the com-
putation of the variances σδ2 and σn2 .
4. Switched-capacitor SAR ADC
The circuit architecture shown in Fig 4.68 [42] achieves the con-
version of bipolar signals into a digital code, the MSB of which
indicates the polarity. The control signals Sj (j = 1, 2, · · · , 14) are
defined in Table 4.12, C1 = C2 , and C5 = C6 . The clock signal
φS determines the sampling and conversion phases. The sign of the
input signal is detected during the on-state of φP . The bit b0 will
be set either to 1 if Vi ≥ 0 or to 0 if the input signal is negative.
Its value is maintained at the output of one latch during the next
conversion period fixed by φH .
Let k denote the conversion cycle. The sampled analog input signal,
Vi (k), which is stored on C1 , is compared to the DAC output, V (k),
available on C2 . The sign of the threshold voltage generated by the
DAC is similar to the one of the input signal. Show that the voltage
Vc (k) at the inverting input node of the comparator is given by
−C1 Vi (k) + C2 V (k)
Vc (k) = + Vof f (4.132)
C1 + C2 + Cp
Nyquist Analog-to-Digital Converters 167
S1
D Q b0
S1 C1
S Q
Vi − 3
bk
S1 +
D Q
Comparator
φ Q
3
C2 S2
DAC SAR

S2
Control
logic

φ
(a) x

S
12

S7 φ
S 1
11

S C3 φ S C5
4 3 8
−
V(k)
S
3 − S +
9
C6 S
+ VREF 13
S C4
5 S
S 10
6
S
14
(b)

φ
S

φ
P

φ
H

φ
1

φ
2

φ
3

bj b0 b1 b2 b3
(c)

FIGURE 4.68
(a) Block diagram of a SAR ADC, x = S, P, H, 1, 2, 3; (b) SC DAC; (c) clock
and digital signal waveforms.

where Cp is the parasitic capacitance at the comparator input node

and Vof f is the comparator dc offset voltage.

Propose a gate-level implementation of the control circuit.

The DAC is realized using an S/H and an amplifier circuit with the
168 Data Converters, Phase-Locked Loops, and Their Applications

TABLE 4.12
Digital Signals for the SAR ADC Switch Control

S1 : φS φ1 S2 : φS + φ1 φP S3 : φS φ3
S4 : bk φS φ3 S5 : φS φ3 + bk φS φ3 S6 : bk φ1 φH
S7 : bk φ1 φH S8 : φ1 φH S9 : φS φ2
S10 : φS φ1 + bk φ1 φP S11 : bk φS φ3 S12 : φS φ3 + φS (φ2 + φ3)
S13 : φS φ2 + bk φS φ3 + φS (φ2 + φ3) S14 : φS φ1 + bk φ1 φP

gain of 1/2. Its output signal can be written as

 
k−1
X
V (k) = −(−1)b0 VREF 2−k + bj 2−j  (4.133)
j=0

Depending on the value of b0 , the positive or negative charge due to

VREF and stored on C5 is transferred onto C4 . Compare the results
of the theoretical analysis of the DAC circuit to SPICE simulations.
Analyze the dependence of the converter resolution to the amplifier
finite gain and mismatching between C5 and C6 .
5. SAR ADC
Consider the 4-bit SAR ADC shown in Figure 4.69. A dummy ca-
pacitor C is used in addition to the binary weighted capacitor array,
so that the total capacitance of the SC DAC can be equal to 24 C,
allowing a binary division to be performed when the states of the
SAR output bits are successively changed.
S

S
−
2 3C 2 2C 2C C C SAR & Output
+ output buffer code
b1 b2 b3 b4 S Enable CK
VREF

Vi φ 4
S

FIGURE 4.69
Circuit diagram of a 4-bit SAR ADC.

Use the equivalent model of the SC DAC shown in Figure 4.70 and
verify the following statements:

(a) At the end of the sampling phase, the charge stored on the
lower plates of the capacitors is Q = −16CVi .
Nyquist Analog-to-Digital Converters 169
4C
VREF V−
If b 1 = 0
12C

16C 8C
Vi V− VREF V− 12C
8C VREF V−
If b 1 = 1
4C

(a) (b)
(c)

FIGURE 4.70
Equivalent model of the SC DAC: (a) sampling, (b) MSB or b1 , (c) b2 .
b1 b2 b3 b4

V
REF
1111
15 VREF /16
1110
14 VREF /16
V
i 1101
13 VREF /16
1100
12 VREF /16
1011
11 VREF /16
1010
10 VREF /16
1001
9V /16
REF
1000
8V /16
REF
0111
7V /16
REF
0110
6V /16
REF
0101
5V /16
REF
0100
4 VREF /16
0011
3 VREF /16
0010
2 VREF /16
0001
1 VREF /16
0000
0

φ Clock signal
Sampling Conversion

FIGURE 4.71
An example waveform of the 4-bit SAR ADC.

(b) During the determination of b1 (MSB),

Q = −16CVi = 8C(V − − VREF ) + 8CV −

and

V − = −Vi + VREF /2
170 Data Converters, Phase-Locked Loops, and Their Applications
S
Vi+

V+
REF
b1 b2 b3 b4 S

2 3C 2 2C 2C C C 4

S −
V SAR &
CM Output
+ output buffer
S code
Enable CK

2 3C 2 2C 2C C C φ

b1 b2 b3 b4 S 4
V−
REF

Vi−
S

FIGURE 4.72
Circuit diagram of a 4-bit SAR ADC with differential SC DACs.

If Vi > VREF /2, then V − < 0 and the comparator output

goes high, as a result b1 is set to 1. On the other hand, if
Vi < VREF /2, then V − > 0 and the comparator output goes
low, b1 is then set to 0.
(c) During the determination of b2 , the voltage at the comparator
input is given by
(
− −Vi + VREF /4 if b1 = 0
V =
−Vi + 3VREF /4 if b1 = 1

The conversion process then continues until all the remaining

bits are generated.

Verify that the input voltage of the comparator can generally be

written as
 
b1 b2 b3 b4
V − = −Vi + VREF + + + (4.134)
2 4 8 16

Verify that the 4-bit SAR ADC operation, as described by the wave-
forms of Figure 4.71, corresponds to the output code 1101.

A 4-bit SAR ADC can also be implemented using differential SC

DACs, as shown in Figure 4.72.
Analyze this circuit and show that the comparator input voltages
Nyquist Analog-to-Digital Converters 171

are given by
 
b1 b2 b3 b4
V + = −Vi− + VCM + VREF
−
+ + + (4.135)
2 4 8 16
 
b1 b2 b3 b4
V − = −Vi+ + VCM +
+ VREF + + + (4.136)
2 4 8 16

Deduce the expressions of the voltages V + and V − in the specific

+ −
case where VREF = VCM + VREF /2, VREF = VCM − VREF /2, and
VCM = VREF /2.
6. Nyquist data converter analysis
• Consider the DAC depicted in Figure 4.73, which consists of a
binary weighted capacitor array.
φ
1

N−1 N−2 N φ
2 C 2 C 2C C 2 C 2
b b b b
1 2 N−1 N

φ
1
b b b b
1 2 N−1 N
φ
− 2
b φ φ b V0
0 2 1 0
+

b b
0 0

V REF

FIGURE 4.73
Block diagram of a charge redistribution DAC.

In the ideal case, show that the output voltage is of the form
N
X
V0 = (−1)b0 VREF 2−k bk (4.137)
k=1

where b0 is the sign bit, bk (k = 1, 2, · · · , N ) represents the magni-

tude bit, and VREF is the reference voltage.
Verify that the total capacitance required to achieve a resolution of
N bits is CT = (2N +1 − 1)C.
Assuming that the saturation level of the amplifier output volt-
age is αVDD , where α = 0.8 and VDD = 2.5 V, solve the equation
|V0 | ≤ αVDD with C = 1 pF to determine the maximum value of N .

• For the flash ADC of Figure 4.74, verify that the numbers of
comparators and resistors required to achieve a resolution of N bits
are 2N + 1 and 2N , respectively.
172 Data Converters, Phase-Locked Loops, and Their Applications
T 2 N−1
+ − D Q Over−range

VREF /2 − + D Q

R T 2 N−2
+ − D Q

− + D Q

T 2 N−3

Thermometer−to−Gray Encoder
R
+ − D Q

Gray−to−binary Encoder
− + D Q

Pipeline Latch

Output Latch
R T 2 N−4 Digital
+ − D Q
Output
− + D Q

R T 2 N−5
+ − D Q
In T/H
Vi − + D Q

CK1 R

T0
+ − D Q

− + D Q
CK3 CK4
R
+ − D Q Under−range

−VREF /2 − + D Q

CK2

FIGURE 4.74
Block diagram of a flash ADC.

Let the differential nonlinearity (DNL) be defined as the difference

between an actual step width and the ideal value of 1 least signifi-
cant bit (LSB). For each code Tk (k = 0, 1, · · · , 2N − 1), the DNL
is given by
△k
DNLk = −1 (4.138)
VLSB
where VLSB = VREF /2N , and △k is the actual step size associated
with the code Tk .
Assuming that the differential input voltage of each comparator is
of the form V + − V − + Vof f , where Vof f is the offset voltage, and
V + and V − are the voltage levels applied to the noninverting and
inverting node, respectively, show that
(
Vof f if k = 2N − 1
DNLk = (4.139)
0 otherwise.

For Vof f = 10 mV and VREF = 2.5 V, determine the maxi-

mum achievable resolution, Nmax , by solving the equation DNLk ≤
VLSB /2, which guarantees an effective number of bits equal to
Nmax .
Nyquist Analog-to-Digital Converters 173

7. Flash ADC
A thermometer-to-binary encoder generates a binary output code
representing the number of ones on the inputs. Its implementation
can then be based on a ones-counter. This last approach has the
advantage of providing a global bubble error suppression.
T14
T13 T14 1
T12 0
T13
Ci S Ci S b4
T11 X X T12
FA FA 1
T10 Y C0 Y C0 0
(LSB) T11
X Ci S b4
T9
FA T10
Y C0 1
T8 X Ci S X Ci S
T9 0
FA FA
T7 Y C0 Y C0 T8
X Ci S b3 1
T6 T7 b3
FA 0
T5 Y C0 T6
T4 X Ci S X Ci S 1
T5 1
FA FA 0
T3 Y C0 Y C0 0
X Ci S b2 T4
FA
T2 Y C0 b1 T3 1
1 b2
(MSB) 0
T1 X Ci S X Ci S T2 0
FA FA
T0 Y C0 Y C0 1
T1 1 b1
1 0
0
(a) T0 0
(b)

FIGURE 4.75
Tree encoder based on ones-counter for a 4-bit flash ADC: implementations
using (a) full adders and (b) 2-to-1 multiplexers.

Analyze the circuits of Figure 4.75 to show that they realize a

thermometer-to-binary encoding.
8. Two-step ADC
A two-step ADC can be implemented without an interstage gain
stage, as shown in Figure 4.76. It is composed of an input stage that
performs a coarse conversion, and an output stage that realizes a
fine conversion.
VREF / 2 P

VREF
+
Q−bit Flash
Vi T/H Σ
− ADC

P−bit Flash P−bit

ADC DAC

P MSBs Q LSBs

FIGURE 4.76
Two-step ADC without an interstage gain stage.
174 Data Converters, Phase-Locked Loops, and Their Applications
VREF
2

VREF G=2 P
1
+
Q−bit Flash
Vi T/H Σ G
− ADC

P−bit Flash P−bit

ADC DAC

P MSBs Q LSBs

FIGURE 4.77
Two-step ADC with an interstage gain stage.
1111
1110
1101
1100
1011
Digital output code

1010
1001
1000
0111
0110
0101
0100
0011
2−bit ADC
0010
4−bit ADC
0001
0000
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 1

Vi / VREF

FIGURE 4.78
Transfer characteristic of the 4-bit two-step ADC.

Assuming that the 2-bit bipolar flash ADC is implemented using a

ladder of 4 identical resistors R, 3 comparators, and a thermometer-
to-binary decoder, complete the encoding table presented in Ta-
ble 4.13.

TABLE 4.13
Truth Table of the 2-Bit Bipolar Flash ADC

Comparator Binary
outputs code
Input voltage range T2 T1 T0 b1 b2
VREF /2 < Vi ≤ VREF 1 1 1 ... ...
0 < Vi ≤ VREF /2 0 1 1 ... ...
−VREF /2 < Vi ≤ 0 0 0 1 ... ...
−VREF < Vi ≤ −VREF /2 0 0 0 ... ...
Nyquist Analog-to-Digital Converters 175

To relax comparator specifications, a two-step ADC can also be

implemented with an interstage gain stage, as shown in Figure 4.77.
It is considered to generate a residue of the form:
P −1
!
X
Vr = (G ± △G) Vi − VREF bk+1 2−k−1 (4.140)
k=0

where G = 2P and △G represents the gain error.

Assuming that P = Q = 2 bits, determine the residue Vr when the
digital output code is 1000 and 0111.
Deduce that the difference between the residues when the digital
output code is 1000 and 0111 can be written as

VREF
△Vr = (G ± △G) (4.141)
4

Determine △G so that △Vr remains less than or equal to one LSB,

where
VREF2 VREF1 VREF
1 LSB = = = (4.142)
4 4×4 16
and VREF1 = VREF .
Verify that the characteristic of the two-step ADC can be repre-
sented as shown in Figure 4.78.
9. Pipeline ADC
A pipeline ADC of Figure 4.79(a) consists of a track-and-hold (T/H)
circuit, two 1.5-bit stages, a 2-bit stage, and a digital adder. For
k = 1, 2, the residues (or outputs of the first and second stages) can
be obtained as follows


2Vk−1 + VREF if Vk−1 < −VREF /4
Vk = 2Vk−1 if − VREF /4 < Vk−1 < VREF /4


2Vk−1 − VREF if Vk−1 > VREF /4
(4.143)
where V0 = Vi and VREF = 0.5 V, and the corresponding digital
output code is 00, 01, and 10, respectively.
Verify that the residues, V1 and V2 , can be represented, as shown
in Figure 4.79(b), where Vi /VREF is the ratio of the input voltage
to the reference voltage.
Verify that the diagram of Figure 4.80 effectively illustrates the op-
eration of the pipeline ADC when the input voltage, Vi , is assumed
to be equal to 0.1 V.
176 Data Converters, Phase-Locked Loops, and Their Applications

Stage 1 V1 Stage 2 V2 Stage 3

Vi T/H
1.5 bit 1.5 bit 2 bits

Output
Digital adder
code
(a)

Vk / VREF

−5/8 −3/8 −1/8 1/8 3/8 5/8

1

V2

Vi / VREF
−1 1

V1
−1
(b) −1/4 1/4

FIGURE 4.79
Pipeline ADC: (a) block diagram; (b) representation of residues V1 and V2 .

Stage 1 Stage 2 Stage 3

1.5 bit 1.5 bit 2 bits
V1 / VREF V2 / VREF V3 / VREF

1 1 1
11
10 10
0.4 1/2
1/8 1/8 10
Vi = 0.1 V
01 01
−0.2
−1/8 −1/8 01
−1/2
00 00
00
−1 −1 −1

0 1 1 0 0 1

1 0 0 1
MSB LSB

FIGURE 4.80
Illustration of the pipeline ADC operation.
Nyquist Analog-to-Digital Converters 177

10. SNR degradation due to clock skew errors

The analysis (see Subsection 4.1.9) of timing skew errors between
the ADC clock signals of time-interleaved converters shows that
pairs of line spectra centered around the frequencies ±fi + mfs /M
(m = 1, 2, · · · , M − 1) appear in the output spectrum. The corre-
sponding magnitudes are given by |A(k)| and |B(k)|, respectively,
and
M−1
1 X jαm (2πfi /fs ) −jkm(2π/M)
A(k) = − e e (4.144)
2jM m=0
M−1
1 X −jαm (2πfi /fs ) −jkm(2π/M)
B(k) = e e (4.145)
2jM m=0
where fi is the frequency of the input sine wave, fs is the sampling
frequency, and αm is the relative error in the sampling instants with
respect to the clock signal period.
Verify that the SNR due to clock skew errors is given by
 
Pi
SN R = 10 log10 (4.146)
Pη
where the noise power is provided by the formula
Pη = P − Pi (4.147)
Pi = |A(0)|2 + |B(0)|2 (4.148)
is the power of the input signal, and by using Parseval’s relation,2
the output signal power is estimated as
1
P = PA + PB = (4.149)
2
with
M−1
X 1
PA = |A(k)|2 = (4.150)
4
k=0
M−1
X 1
PB = |B(k)|2 = (4.151)
4
k=0

Note that A(k) and B(k) can be considered the discrete

Fourier transform of the sequences −(1/2jM )ejαm (2πfi /fs ) and
(1/2jM )e−jαm (2πfi /fs ) , respectively.

2 Let x(n) be an N -point sequence, and X(k) its discrete Fourier transform. The next

equation,
N−1
X N−1
1 X
|x(n)|2 = |X(k)|2
n=0
N k=0
is known as Parseval’s relation.
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5
Delta-Sigma Data Converters

CONTENTS
5.1 Delta-sigma analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.1.1 Time domain behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.1.2 Linear model of a discrete-time modulator . . . . . . . . . . . . . . . . . . . . . . . 188
5.1.3 Modulator dynamic range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
5.1.4 Continuous-time modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
5.1.5 Lowpass delta-sigma modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
5.1.5.1 Single-stage modulator with a 1-bit quantizer . . . . . . . . . . 197
5.1.5.2 Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.1.5.3 Design examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.1.5.4 Modulator architectures with a multi-bit quantizer . . . . . 210
5.1.5.5 Cascaded modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
5.1.5.6 Effect of the multi-bit DAC nonlinearity . . . . . . . . . . . . . . . . 222
5.1.5.7 Quantization noise-shaping and inter-stage coefficient
scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.1.6 Bandpass delta-sigma modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.1.6.1 Single-loop bandpass delta-sigma modulator . . . . . . . . . . . . 225
5.1.6.2 Cascaded bandpass delta-sigma modulator . . . . . . . . . . . . . 226
5.1.6.3 Design examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
5.1.7 DT modulator synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.1.8 CT modulator synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
5.1.9 Decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
5.2 Delta-sigma digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
5.2.1 Interpolation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
5.2.2 Digital modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.3 Nyquist DAC design issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
5.3.1 Vector-feedback DEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
5.3.2 Data-weighted averaging technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
5.3.2.1 Element selection logic based on a tree structure and but-
terfly shuffler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
5.3.2.2 Generalized DWA structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
5.4 Data converter testing and characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
5.4.1 Histogram-based testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
5.4.2 Spectral analysis method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
5.4.3 Walsh transform-based transfer function estimation . . . . . . . . . . . . . 286
5.4.4 Testing using sine-fit algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
5.5 Delta-sigma modulator-based oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
5.6 Digital signal processor interfacing with data converters . . . . . . . . . . . . . . . . . 290
5.6.1 Parallel interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
5.6.2 Serial interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
5.7 Built-in self-test structures for data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
5.8 Circuit design assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

183
184 Data Converters, Phase-Locked Loops, and Their Applications

In comparison with other analog-to-digital converters (ADCs) and digital-

to-analog converters (DACs), delta-sigma (∆Σ) data converters (or generally
oversampling data converters) exhibit a reduced sensitivity to analog com-
ponent matching. ∆Σ converters are usually the best choice for applications
requiring a resolution greater than 20 bits. In these converters, the input sig-
nal can be sampled at a rate much greater than the Nyquist frequency (i.e.,
twice the bandwidth or highest frequency of the signal being sampled), and
the quantization noise is shaped by the modulator to be low in the signal
band and high in the out-band spectrum. The specifications of either the ana-
log anti-aliasing filter for the analog-to-digital conversion or the smoothing
filter for the digital-to-analog conversion are then relaxed due to the signal
oversampling, and the remaining out-band noise is attenuated by a filter. The
actual reduction of in-band noise power level depends on the modulator struc-
ture and the oversampling ratio (OSR) and a high resolution is achieved with
a penalty in speed, as the modulator hardware has to operate at the oversam-
pling rate, and an increased complexity of the filter hardware. Oversampling
data converters then present a trade-off between speed and resolution.

∆Σ modulators can be exploited in the implementation of calibration

stages required to improve the linearity of Nyquist converters. Built-in self-
test is another application for analog signal synthesis where ∆Σ modulators
are ideally suited.

5.1 Delta-sigma analog-to-digital converter

∆Σ ADCs can be implemented using either continuous-time (CT) or discrete-

time (DT) filters, as shown in Figures 5.1 and 5.2. The signal sampling is
performed at the input node in the DT case by an S/H circuit, while it is
implemented after the filtering in the CT structure. In both types, the system
consists of a ∆Σ modulator followed by a digital decimator. A filter, a quan-
tizer, and a DAC are used as building blocks of the modulator, which is based
on an output-feedback structure. Note that even modulators based on a CT
filter possess an equivalent in the DT domain, where the converter design is
generally achieved.

During the data conversion, the modulator feedback forces the average
value of the quantized signal to follow one of the input signals and the quan-
tization noise in the signal band is attenuated. A decimation filter is required
to eliminate the out-of-band noise and to reduce the sampling rate of the
modulator output signal.
Delta-Sigma Data Converters 185
CK
Modulator

Analog Discrete−time Digital Digital

input S/H Σ Quantizer output
filter filter

DAC

FIGURE 5.1
Block diagram of a DT ∆Σ ADC.

Modulator CK
@ fS =1/T

Analog Continuous−time Digital Digital

input Σ Quantizer output
filter filter

DAC

FIGURE 5.2
Block diagram of a CT ∆Σ ADC.

5.1.1 Time domain behavior

At each processing step, a ∆Σ modulator generates a digital estimation of the
signal, which is subtracted from the actual sample of the input signal and the
digital conversion of the resulting sequence is achieved such that the output
and input signals tend to be equal on average.
In the general case, a single-stage modulator can be described in the time
domain using the following equations

JS JQ
X X
x(n) = hS (j)s(n − j) + hQ (j)eQ (n − j) (5.1)
j=0 j=1

eQ (n) = y(n) − x(n) (5.2)

y(n) = Q[x(n)] (5.3)

where hS and hQ are the impulse responses of the signal transfer function
(STF) and quantization noise transfer function (QNTF), respectively; x de-
notes the output state of the modulator filter, JS and JQ represent the
length of the STF and QNTF, respectively; and Q is the equivalent piecewise-
constant function of the quantizer. The modulator will be considered stable
for a given input and initial conditions if the signal samples x are bounded
and the quantizer is not overloaded.
186 Data Converters, Phase-Locked Loops, and Their Applications

Comparator

ε X
S Σ Integrator Y

~ 1−bit VREF
Y
DAC −VREF

FIGURE 5.3
Block diagram of a first-order ∆Σ modulator.

In the special case of the first-order ∆Σ modulator shown in

Figure 5.3, the sum ǫ of the input signal s and the output ỹ of a
1-bit feedback DAC is applied to an integrator, whose output x
is connected to the input of a comparator delivering the digital
sequence y available at the modulator output, which is then
used to drive the 1-bit feedback DAC. Assuming that the supply
voltages of the comparator are VDD and −VSS , and the DAC
reference voltages are ±VREF , the modulator can be described
using the next time-domain equations,

x(n) = x(n − 1) + ǫ(n − 1) (5.4)

y(n) = Q[x(n)] (5.5)
ǫ(n) = s(n) − ỹ(n) (5.6)

where (
H if x(n) ≥ 0
Q[x(n)] = (5.7)
L if x(n) < 0
and (
VREF if y(n) = 1
ỹ(n) = (5.8)
−VREF if y(n) = 0
At the modulator output, a logic high state, H, corresponds to a
voltage level of about VDD and a logic low state, L, is represented
by approximately −VSS .
Let a dc input signal of 0.25 V be applied to the modulator
and the reference voltages of the DAC be ±1 V. The state and
output sequences of the modulator are given in Table 5.1, where
the initial conditions are specified in the row associated with
n = 0. It can be observed that the state and output sequences
for n ∈ [2, 9] are periodically repeated starting from n = 10. For
the first-order modulator, the quantization noise is correlated
with the input signal and appears not to be entirely random.
The allowed input range is from VREF to −VREF , resulting in a
Delta-Sigma Data Converters 187

TABLE 5.1
State and Output Sequences of the First-Order Modulator

n s(n) x(n) y(n) ỹ(n) ǫ(n)

0 — 0.10 H 1 −1.00
1 0.25 −0.90 L −1 1.25
2 0.25 0.35 H 1 −0.75
3 0.25 −0.40 L −1 1.25
4 0.25 0.85 H 1 −0.75
5 0.25 0.10 H 1 −0.75
6 0.25 −0.65 L −1 1.25
7 0.25 0.60 H 1 −0.75
8 0.25 −0.15 L −1 1.25
9 0.25 1.10 H 1 −0.75
10 0.25 0.35 H 1 −0.75
11 0.25 −0.40 L −1 1.25
12 0.25 0.85 H 1 −0.75
13 0.25 0.10 H 1 −0.75
14 0.25 −0.65 L −1 1.25
15 0.25 0.60 H 1 −0.75

converter full-scale range (FSR) of 2VREF , or say 2 V. A 0.25-V

input signal is 1.25 V above the lower −1-V limit of the FSR,
that is, the input represents (1.25/2) × 100 = 62.5% of the FSR.
By averaging the first 8 samples of the output sequence, the
number of bits at the high state is 5, leading to the H-state
density given by (5/8) × 100 = 62.5%.
In practice, the modulator output is decoded using a digital low-
pass filter that averages every given number of samples, which
can be increased to improve the overall resolution. For input sig-
nals around the mid-scale, the H-state density is about 50% in
the modulator output sequence. An increase in the input signal
toward the higher limit of the FSR results in an augmentation of
the H-state density, while a decrease in the input signal toward
the lower limit of the FSR induces a reduction in the H-state
density.
Waveforms of a first-order modulator with a sine wave input
signal are illustrated in Figure 5.4. The oversampling ratio is
assumed to be 64. In general, it can be increased to improve the
conversion resolution.
188 Data Converters, Phase-Locked Loops, and Their Applications

Input
Output
Clock signal

Magnitude

Time

FIGURE 5.4
Waveforms of a first-order modulator with a sine wave input.

Due to oversampling, a ∆Σ modulator makes use of the available speed to

exchange the resolution in time for that in amplitude.

5.1.2 Linear model of a discrete-time modulator

A linear model of a discrete-time modulator can be obtained based on the
assumptions that different feed-ins to the filter are used by the input and
feedback signals, and the quantization is done with an additive error. With
reference to Figure 5.5, the output signal of the modulator can be computed
as
Y (z) = HS (z)S(z) + HQ (z)EQ (z) (5.9)
where
Y (z) qH(z)
HS (z) = = (5.10)
S(z) 1 + qH(z)
Y (z) 1
HQ (z) = = (5.11)
EQ (z) 1 + qH(z)
and H represents the z-domain transfer function of the loop filter, HS denotes
the signal transfer function (STF), HQ is the quantization noise transfer func-
tion (QNTF), EQ represents the quantization error, and q (q > 0) is the
quantizer gain. To simplify the analysis, the modulator is generally modeled
by replacing the quantizer with a unity-gain element followed by an additive
noise source. Hence,
HS (z) = 1 − HQ (z) (5.12)
and the QNTF determines the modulator performance and stability. It should
be emphasized that a modulator realized with real components is a nonlinear
system and the coupling between the signal and quantization noise is neglected
in the above description.
Delta-Sigma Data Converters 189

E Q(z) E Q(z)
H S (z)
S(z)
H Q (z)
X(z) X(z)
S(z) Σ H(z) q Y(z) q Y(z)
H Q (z) −1
H Q (z)

FIGURE 5.5
Block diagram of the DT ∆Σ modulator linear model.

∆Σ modulators are generally described by the order of the loop filter, the
characteristic of which determines the shape of the noise spectrum. Lowpass
filters are generally used to meet the desired resolution in audio applications,
while modulators based on a bandpass filter are preferred for the digitization
of high-frequency band-limited signals in telecommunication systems. In the
z-domain, an arbitrary L-th-order lowpass modulator can be transformed into
a bandpass modulator of order 2L using the transformation

z −1 → −z −2 (5.13)

In this way, the zeros of the QNTF are shifted from dc to fs /4, where fs is
the sampling frequency.
The resolution achievable with a single-bit ∆Σ ADC is limited and can
generally be improved using converters based on high-order filters [4] or multi-
bit quantizers [12].

5.1.3 Modulator dynamic range

Consider a ∆Σ modulator with order L operating with the oversampling ratio
OSR = fs /fN = fs /(2fmax ), where fs is the sampling frequency, fN is the
Nyquist frequency, and fmax is the highest spectral component present in the
input signal. The quantization noise is shaped by a transfer function of the
form
HQ (z) = (1 − z −1 )L (5.14)
In the frequency domain, we have
" !#L " ! !#L
f f f
HQ (jf ) = 1 − exp −j2π = 2j sin π exp −jπ
fs fs fs
(5.15)
and " !#L
f
|HQ (jf )| = 2 sin π (5.16)
fs
Figure 5.6 shows the plot of HQ magnitudes for L = 1, 2, 3, 4, 5. The quan-
tization noise suppression over the low-frequency signal band is improved as
190 Data Converters, Phase-Locked Loops, and Their Applications

the value of L, or equivalently the modulator order, is increased.

L=5
5

4
L=4
Magnitude (dB)

3
L=3

2 L=2

L=1

0
0 0.1 0.2 0.3 0.4 0.5
Normalized frequency

FIGURE 5.6
Plot of HQ magnitudes for L = 1, 2, 3, 4, 5.

Let △ be the quantizer step size. Assuming that the quantization error,
eQ , is evenly distributed between −△/2 and △/2, the mean value of eQ is
zero and the probability density of eQ can be expressed in the form

1
if eQ ∈ [−△/2, △/2]
p(eQ ) = △ (5.17)

0 otherwise.
2
The variance of the quantization noise, σQ , is then given by
Z ∞ Z △/2
2 1 △2
σQ = e2Q p(eQ )deQ = e2Q deQ = (5.18)
−∞ △ −△/2 12

Generally, the input signal is sampled at the frequency fs , and the spectral
density of the quantization noise to be filtered is supposed to remain constant
between 0 and fs /2. That is,
Z fs /2 Z fs /2
2
σQ = pi df = pi df = pi (fs /2) (5.19)
0 0

or, equivalently,
2 1 △2 2
pi = σQ = (5.20)
fs /2 12 fs
The spectral density of the quantization noise at the modulator output can
Delta-Sigma Data Converters 191

be written as !
2 22L △2 f
p0 = |HQ (jf )| pi = sin2L π (5.21)
6fs fs
The power of the quantization noise in the Nyquist frequency range is given
by
Z fN /2
PQ = p0 (f )df (5.22)
0
Because the value of the oversampling ratio OSR = fs /fN is generally high,
we have fN ≪ fs . As a consequence, we have 0 ≤ f ≤ fN /2 ≪ fs and
sin(πf /fs ) ≃ πf /fs . Hence,
Z !2L
22L △2 fN /2 f
PQ ≃ π df (5.23)
6fs 0 fs

Finally, we obtain
!2L+1
△2 π 2L 1
PQ ≃ (5.24)
12 2L + 1 OSR
In the case of a rounding quantizer, each input sample is assigned to the
nearest quantization level. The quantization error is then limited to the range
of −△/2 to △/2, and
FSR
△= B (5.25)
2 −1
where B is the number of bits of the quantizer. In the case of a sinusoidal
signal with a peak-to-peak amplitude equal to the quantizer full-scale range,
FSR, the average power is
FSR2
PS = σS2 = E[s2 (n)] = (5.26)
8
The dynamic range (DR) of the modulator can then be expressed as
PS
DR2 =
PQ
!2
FSR
√
2 2 3 2L + 1 B
= !2L+1 = (2 − 1)2 OSR2L+1
FSR2 π 2L 1 2 π 2L
12(2B − 1)2 2L + 1 OSR
(5.27)
or in decibels,
!
3 2L + 1 B
DR(in dB) = 10 log10 (2 − 1)2 + 10(2L + 1) log10 OSR (5.28)
2 π 2L
 192 Data Converters, Phase-Locked Loops, and Their Applications

Thus, the dynamic range, DR, is a function of the filter order and the over-
sampling ratio, OSR. The multiplication of the OSR by a factor of 2 results in
an increase in the DR on the order of 3(2L + 1) dB, or equivalently, (L + 1/2)
bits of resolution. Note that the dynamic range given by Equation (5.28) may
be considered an upper bound because it is based on a linear model of the
modulator. Furthermore, the stability requirements of modulators with an or-
der equal to or greater than 2 are only met by using design techniques or
structures that can constrain the modulator dynamic range well below this
upper bound.

Overload
SQNR (dB)

Ideal

DR
Practical
Overloading
level

Input level (dB or dBFS)

FIGURE 5.7
Curve of the signal-to-quantization noise ratio (SQNR) versus the input level.

90
80
1
70

0.5 60
SQNR (dB)
Imaginary axis

50

0 40
30
−0.5 20
10
−1 0
−1 −0.5 0 0.5 1 −100 −80 −60 −40 −20 0
Real axis Input level (dBFS)

FIGURE 5.8 FIGURE 5.9

Pole-zero plot of the NTF. SQNR curve of the ∆Σ modulator.

The curve of the signal-to-quantization noise ratio (SQNR) versus the

input level is depicted in Figure 5.7. A linear scaling effect is observed between
the modulator SQNRs obtained by relying on an ideal model or a practical
chip. Furthermore, a premature clipping occurs in the practical SQNR at high
input levels because the slew rate of active components appears to be limited.
Note that the input level can be evaluated in dB, or in dBFS (decibels relative
Delta-Sigma Data Converters 193

to full scale), provided the output spectrum is normalized so that a full-scale

sine wave can appear at 0 dB.

0 0

Output spectrum (dBFS/NBW)

Input signal tone Input signal tone
−20 −20
Output spectrum (dBFS)

−40 −40

−60 −60
−80 −80

−100 −100
−120 −120

−140 −140
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Normalized frequency Normalized frequency

FIGURE 5.10 FIGURE 5.11

Output power spectrum of a fourth- Output power spectrum of a fourth-
order lowpass ∆Σ modulator. order bandpass ∆Σ modulator.

A typical way to synthesize a ∆Σ modulator is to select the integrator type

and signal paths such that all zeros of the noise transfer function are located
on the unit circle, or equivalently at z = 1. This approach has the advantage
of reducing the complexity of the modulator architecture, but the achievable
SNR and DR may be limited.
Given a modulator order, the above performance characteristics can be
improved by selecting a noise transfer function with zeros on the unit circle
and poles inside the unit circle [5,6], as shown in Figure 5.8. The poles can be
chosen to be identical to the ones of a filter approximation function, such as
Butterworth or Chebyshev polynomial, while the zeros are optimally placed
on the unit circle. In this case, the noise transfer function is of the form
HQ (z) = N (z)/D(z), where N and D are two polynomials, and it is assumed
that the realizability constraint, limz→∞ HQ (z) = 1, and stability requirement
are met. The resulting SQNR curve is depicted in Figure 5.9. The fourth-order
lowpass modulator considered here exhibits a maximum signal-to-noise ratio
of about 80 dB at an oversampling ratio of 32.
The DR formula is still valid in the case of 2L-th bandpass modulators
obtained by applying the dc-to-fs /4 transformation to L-th lowpass modulator
prototypes. For lowpass modulators, the STF is designed as a lowpass filtering
function and the QNTF is chosen as a highpass function, while, for bandpass
modulators, the STF is a bandpass function and the QNTF is a band-reject
or notch function. The output spectra of fourth-order lowpass and bandpass
modulators are depicted in Figures 5.10 and 5.11, respectively. The output
spectrum of the bandpass modulator is determined relative to the noise power
bandwidth (NBW).
194 Data Converters, Phase-Locked Loops, and Their Applications

5.1.4 Continuous-time modulator

Continuous-time (CT) modulators are more suitable for high-frequency ap-
plications. However, they are more sensitive to clock jitter than their SC
counterparts.
p(t) p(t) p(t)
1 1 1

t/T t/T t/T

0 1 0 1/2 1 0 1/2 1
(a) (b) (c)

FIGURE 5.12
DAC waveforms: (a) NRZ, (b) RZ, (c) HRZ.

In CT modulators, the sampling of the signal takes place in the loop and
the stability must be analyzed in the DT domain. The design of the modulator
filter then results in the equivalent transfer function H(z). Note that the
unstable behavior will be observed when the poles are located far away from
the zeros even for input signals with a low amplitude, while the performance is
compromised by placing the poles very close to the zeros. Let us assume that
the operation of a 1-bit quantizer can be described by the following expression,
(
1 if p1 T ≤ t ≤ p2 T
p(t) = (5.29)
0 otherwise,

where p1 , p2 ∈ [0, 1] and T is the sampling period. In the s-domain, this

corresponds to the zero-order hold pulse transfer function given by

P (s) = (e−sp1 T − e−sp2 T )/s (5.30)

The type of the DAC pulse, which is determined by the values of p1 and p2 ,
is nonreturn-to-zero (NRZ) for p1 = 0 and p2 = 1, return-to-zero (RZ) for
p1 = 0 and p2 = 1/2, and half-clock-period delayed return-to-zero (HRZ) for
p1 = 1/2 and p2 = 1 (see Figure 5.12).
An NRZ DAC is characterized by an output signal that remains constant
throughout the whole period of the clock signal. It can easily be implemented.
However, the mismatch between the rise and fall times of the output waveform
causes inter-symbol interference that limits the linearity of the NRZ DAC.
When this data-dependent transient nonlinearity is translated into even-order
harmonic distortions, it can be canceled by fully differential circuits.
A RZ (or HRZ) DAC exhibits an output signal that is active only during
a half of the clock signal period. To deliver the same amount of charge per
clock signal period as an NRZ DAC, its output signal magnitude should be
two times greater than that of the NRZ DAC. It can still operate linearly
even in the presence of a mismatch between the rise and fall times of the
output waveform. However, the RZ (or HRZ) DAC is more sensitive to clock
Delta-Sigma Data Converters 195

jitter than the NRZ DAC because it requires twice as many output signal
transitions.
CT modulators are very sensitive to clock jitter because the amount of
feedback charge generated by the DAC is a function of the clock signal pulse
width. The use of various other (exponentially decaying, sine-shaped) DAC
pulses with a duty cycle shorter than the clock period is one of the approaches
to reduce the sensitivity of CT modulators to clock jitter. The clock jitter
effect can also be attenuated by increasing the DAC resolution or by lowering
the oversampling ratio. But, due to the inherent mismatch between the DAC
elements, multi-bit DACs generally require calibration.
The CT transfer function, H(s), can be obtained using the impulse invari-
ant transformation as follows,

Z −1 {H(z)} = L−1 {P (s)Ĥ(s)}|t=nT (5.31)

where Z −1 and L−1 denote the inverses of the z-transform and Laplace trans-
form, respectively; H(z) is the transfer function of the DT filter; and Ĥ(s)
represents the transfer function of the CT filter. This last equation can equiv-
alently be written in the time domain as
Z ∞ 
h(nT ) = [p(t) ∗ ĥ(t)] = p(τ ) ∗ ĥ(t − τ )dτ (5.32)
t=nT −∞ t=nT

where ∗ represents the time convolution, h(nT ) is the impulse response of

the DT filter, p(t) is the impulse response of the DAC, and ĥ(t) denotes the
impulse response of the CT filter.
The classical approach used for the design of a CT modulator consists
of first choosing the appropriate z-domain QNTF, HQ (z), that meets the
required specifications and converting it to the DT loop transfer function
H(z) = (HQ (z) − 1)/HQ (z). The CT filter transfer function, Ĥ(s), is then
obtained by solving the equation of the impulse invariant transformation with
a symbolic math program or numerical methods. Whenever possible, the DT
transfer function of the modulator can be decomposed into partial fractions
of the form Hi (z), i = 1, 2, and the equivalent CT function is derived using
the results of Table 5.2, where fs is the clock signal frequency [7]. Note that
l’Hopital’s rule was exploited to obtain the s-domain equivalent functions
in the specific case where zk = 1 (i.e., the poles are located at dc). The
impulse invariant method has the advantage of resulting in circuits with a low
complexity in comparison with other approaches.
In practice, the settling behavior of the DAC and quantizer are affected
by the excess loop delay due to the nonzero switching time of transistors in
the quantizer latch and DAC, and timing jitter.
It can be observed that in the CT structure, the clock jitter, which causes
a variation in the width of DAC pulses, disturbs the sum of the input signal
and quantization noise, because the sampling occurs at the quantizer rather
than the input. In the DT case, only the input signal is affected. As a result,
196 Data Converters, Phase-Locked Loops, and Their Applications

TABLE 5.2
Impulse-Invariant Transformation of Functions with Single, Double, and
Triple Poles

z-domain s-domain


 sk
z −1  , if zk 6= 1
H1 (z) = Ĥ1 (s) = q1 (s − sk )
1 − zk z −1 
 fs
 , if zk = 1
(p2 − p1 )s

 (q2 sk + q1 fs )s − q2 s2k

 ,

 zk q12 (s − sk )2



 if zk 6= 1
z −2   
H2 (z) = Ĥ2 (s) = p1 + p2
(1 − zk z −1 )2 
 − fs 1 − s + fs2

 2

 ,

 (p2 − p1 )s2


if zk = 1

 r2 fs s2 + r1 fs2 s + r0 fs3

 ,

 zk2 q13 (s − sk )3



 if zk 6= 1
z −3   
H3 (z) = Ĥ3 (s) = 3 p1 + p2
(1 − zk z −1 )3 
 rfs s2 − fs2 − s + fs3

 2 2

 ,

 (p2 − p1 )s3


if zk = 1

where
fs = 1/T
sk = ln(zk )/T
q1 = zk1−p1 − zk1−p2
q2 = (1 − p2 )zk1−p2 − (1 − p1 )zk1−p1
r0 = (q4 /2)s3k
r1 = −q4 s2k + q3 sk + q12
r2 = (q4 /2)sk − q3
r = 1 + [p1 (p1 − 9) + p2 (p2 − 9) + 4p1 p2 ]/12
q3 = (3/2 − p1 )(zk1−p1 )2 + (3/2 − p2 )(zk1−p2 )2 + (p1 + p2 − 3)zk1−p1 zk1−p2
and
q4 = (1 − p1 )(2 − p1 )(zk1−p1 )2 + (1 − p2 )(2 − p2 )(zk1−p2 )2
+[p1 (p1 + 3) + p2 (p2 + 3) − 4(1 + p1 p2 )]zk1−p1 zk1−p2

Adapted from [7], ©1999 IEEE.

Delta-Sigma Data Converters 197

the signal-to-noise ratio (SNR) of CT modulators is more severely affected

by the timing jitter in the quantizer clock than the SNR of the equivalent
DT versions. It should be noted that modulators with an NRZ DAC are less
sensitive to the clock jitter than the one with RZ or HRZ DACs.
Furthermore, the performance of CT ∆Σ modulators can be affected by
the so-called excess delay, which is required by the quantizer to update its
output. As a result, the DAC pulse can extend beyond T (or the clock period
end) and the order of the equivalent DT loop filter is now one unit higher
than the CT filter order. In general, solutions at the circuit level (appropriate
selection of the DAC pulse, feedback coefficient tuning, use of extra feedback
paths) can be used for the compensation.

5.1.5 Lowpass delta-sigma modulator

Lowpass ∆Σ modulators are based on discrete-time integrators with a delay,
and whose transfer function is
z −1
I(z) = (5.33)
1 − z −1
and a comparator. Note that the term 1/(1 − z −1 ) is generally realized by
a switched-capacitor integrator, but the delay z −1 introduced in the transfer
function numerator can be implemented using appropriate clock signals at
the integrator input and output, or at the integrator input and to drive the
quantizer.

5.1.5.1 Single-stage modulator with a 1-bit quantizer

In Σ α 1 I(z) Out

1−bit
DAC

FIGURE 5.13
Block diagram of a first-order modulator.

The block diagram of a first-order modulator is shown in Figure 5.13. It con-

sists of an integrator, a 1-bit quantizer or comparator, and a 1-bit DAC. With
the assumption that α1 = 1, the STF and QNTF are given by

HS (z) = z −1 and HQ (z) = 1 − z −1 (5.34)

This structure has a large dynamic range, and is simple and less sensitive
to the component nonidealities. However, the quantization noise can be sig-
nal dependent and not statistically uncorrelated with the input signal as it
is usually assumed. As a consequence, single-frequency tones appear in the
198 Data Converters, Phase-Locked Loops, and Their Applications

modulator output spectrum for slowly varying input signals. This effect can
be prevented by whitening the quantization noise through dithering. It consists
of adding a pseudo-random sequence, which is independent and uncorrelated
with the input signal, at the quantizer input. The transfer function from the
dither input to the modulator output must be proportional to the one of the
quantization noise. Furthermore, the magnitude of the dither signal should be
chosen so that the quantizer cannot overload. The increase of the number of
state variables (integrator input and output) can also help to reduce tones by
preventing the formation of a repeating bit pattern at the modulator output.

In Σ α 1 I(z) Σ α 2 I(z) Out

1−bit
DAC

FIGURE 5.14
Block diagram of a second-order modulator.

The modulator shown in Figure 5.14 achieves a second-order shaping of

the quantization noise. It uses two integrators in the filter loop. In comparison
to the first-order structure, the number of internal states is increased and the
occurrence likelihood of spectral tones is reduced. Here for α2 /2 = 2α1 = 1,
the STF and QNTF can be written in the form

HS (z) = z −2 and HQ (z) = (1 − z −1 )2 (5.35)

Here, the QNTF exhibits two zeros at dc and can provide an improved at-
tenuation of the noise in the baseband compared to the one of the first-order
modulator.

In Σ α 1 I(z) Σ α 2 I(z) Σ α 3 I(z) Out

1−bit
DAC

FIGURE 5.15
Block diagram of a third-order modulator.

The third-order modulator of Figure 5.15 is derived by adding an integrator

stage and a feedback path to the second-order structure. The STF and QNTF
Delta-Sigma Data Converters 199

can be, respectively, expressed as

3
Y
αi [I(z)]3
i=1
HS (z) = 3 Y
3
(5.36)
X
1+ αj [I(z)]3−i+1
i=1 j=i

α1 α2 α3 z −3
= (5.37)
D(z)
and
1
HQ (z) = 3 Y
3
(5.38)
X
3−i+1
1+ αj [I(z)]
i=1 j=i

(1 − z −1 )3
= (5.39)
D(z)
where

D(z) = 1+(α3 −3)z −1 +[α3 (α2 −2)+3]z −2 +[α3 (α2 α1 −α2 +1)−1]z −3 (5.40)

With the following set of coefficients, α1 = 0.2 and α2 = α3 = 0.5, the

expected SNR, DR, premature overloading are 80 dB, 86 dB, and 0.55 (with
reference to 1, ideally), respectively, at an OSR of 64.
Due to the nonlinear nature of ∆Σ modulators, the stability can depend on
characteristics such as the input signal level or initial conditions. Simulations
show that the use of a multi-bit quantizer, which can better accommodate
large signals than a single-bit quantizer, is necessary to stabilize a single-
loop modulator with the QNTF of the form HQ (z) = (1 − z −1 )L , where
L > 2. An L-th-order ∆Σ modulator will then be stable if the quantizer
possesses B ≥ L + 1 bits of resolution. However, higher-order single-loop
modulators with a single-bit quantizer can be made stable by matching the
QNTF to a more general highpass or band-reject transfer function. This is
generally achieved either using the Butterworth or inverse-Chebyshev filter
approximations to find the QNTF and then suitable zeros are added to the
numerator in order to improve the attenuation of the baseband quantization
noise or by numerically finding the poles and zeros of the QNTF, which can
provide a more effective shaping of the baseband quantization noise out of the
band of interest, with the help of computer-aided design tools. It may then
be necessary to increase the complexity of the loop filter structure, as shown
in Figures 5.16 and 5.17. These third-order modulator structures are based
on single-stage topologies with feedforward and feedback paths and can allow
the QNTF zeros to be spread over the signal bandwidth instead of being all
placed at dc.
200 Data Converters, Phase-Locked Loops, and Their Applications
γ

α1

In Σ I(z) Σ I(z) α2I(z)

β1 β2 β3

Σ Out

1−bit
DAC

FIGURE 5.16
Block diagram of the third-order modulator with a feedforward summation
and local resonator feedback.
In

δ1 δ2 −γ δ3

α1 α2

Σ I(z) Σ I(z) Σ I(z) Out

β1 β2 β3
1−bit
DAC

FIGURE 5.17
Block diagram of the third-order modulator with feedforward input paths,
distributed feedbacks, and a local resonator feedback.

Single-bit modulators with an order equal to or greater than three possess

a dynamic range lower than the one predicted by Equation (5.28) due to the
attenuation required in the signal path in order to meet the loop stability con-
dition. The design objective is to find the coefficient combination that provides
the maximal dynamic range, while maintaining the modulator stability.
Most of the methods for generating the loop coefficients from modulator
specifications focus on synthesizing a QNTF based on a filtering function.
Because a delay-free loop around a quantizer is not implementable, the asso-
ciated QNTF should have the property that limz→∞ HQ (z) = 1. Let the noise
power gain (NPG) be defined as
Z π
1
NPG = (|HQ (ejω )|)2 dω (5.41)
π 0

The modulator must be designed such that the NPG limitation is satisfied.
That is,
NPGmin ≤ NPG ≤ NPGmax (5.42)
where NPGmin is determined by the acceptable level of in-band tones, and
Delta-Sigma Data Converters 201

NPGmax depends on the stability requirement that is affected by the mod-

ulator order and the maximum power of the input dc signal. To take into
account the effect of coefficient variations due to component imperfections,
the upper bound of the NPG must be selected with a safety margin from the
instability border. The resulting NPG is generally a function of the in-band
noise suppression, the OSR, and the modulator order.
As a design example with a maximum stable input signal of −6 dB, a
bandwidth of 20 kHz, an OSR of 64, a SNR of 89 dB, and DR of 92 dB, the
coefficients of the third-order modulator shown in Figure 5.16 can be obtained
as: α1 = 0.598, α2 = 0.709, α3 = 0.196, β1 = 1.543, β2 = 0.895, β3 = 0.782,
and γ = 0.013.
In the case of the third-order modulator shown in Figure 5.17, an improved
DR of 95 dB is achieved with the following set of coefficients: α1 = 0.2273,
α2 = 0.2972, α3 = 0.7060, β1 = 1, β2 = 1.2915, β3 = 0.9332, δ1 = 1,
δ2 = δ3 = 0, and γ = 0.0086.
Note that γ is the most sensitive coefficient for SNR performance because
it determines the locations of the NTF zeros. The input frequency used for
SNR and DR calculations is fs /1024 and fs is the sampling frequency.

5.1.5.2 Dithering
In general, the time-domain output waveform of ∆Σ modulators can be af-
fected by idle tones or pattern noise, which appears as periodic impulses whose
peak levels are much greater than their rms values. This behavior, which is
due to the correlation between the quantizer error and the dc level of the input
signal, is undesirable, especially in audio applications. A solution consists of
using dithering, which can be realized by adding a pseudo-random sequence
to the quantizer input. As a result, the quantization noise is made almost
independent of the modulator input signal and asymptotically white in some
cases.
Comparator

Filter y(n)+q(n)
s(n) Σ Σ Σ y(n) y(n)
H(z) HQ

PN Generator H Q(z) q’(n) Adaptation

η (n) circuit

DAC
Programmable
η(n)
FIR filter q’(n)

(a) (b)

FIGURE 5.18
(a) Block diagram of a modulator with dithering; (b) adaptive filter-based
realization of HQ (z).

The block diagram of a modulator with dithering is shown in Fig-

ure 5.18(a). Here, the dithering signal, which is a digital sequence provided
202 Data Converters, Phase-Locked Loops, and Their Applications

by a pseudo-random number generator, can be added to the comparator out-

put [8], instead of the input. Because it is shaped by the modulator in the
same way as the quantization noise, its cancelation at the modulator output
is realized using a filter section with the transfer function, HQ , and a sub-
tractor. The noise transfer function, HQ , is determined by the specifications
of the loop filter, and is implemented using either a conventional digital filter
or an adaptive filter [9], as illustrated in Figure 5.18(b). This latter approach
can provide a better tracking of the modulator response.

5.1.5.3 Design examples

α 1z −1 α 2z −1
1 1
In Σ Σ Out
1− z−1 1− z−1

α 1z −1 α 2z −1 CK

1−bit
DAC

FIGURE 5.19
Block diagram of a second-order lowpass DT modulator.

−VREF C1 −VREF C2
+VREF +VREF
φ φ
2d 2d

φ C1 φ φ C2 φ
1d 2 C 1d 2 C
Vi+ V0+
φ φ φ φ
2d 1 2d 1
−+ −+ −+ D Q
CK φ
1
φ φ +− φ φ +− +− D Q
2d 1 2d 1 Enable
V0−
Vi−
φ φ C φ φ C
1d C1 2 1d C2 2
φ
1d
φ φ
2d 2d
C1 C2
−VREF −VREF
+VREF +VREF

FIGURE 5.20
Circuit diagram of a second-order lowpass DT modulator.

The block diagram of a second-order lowpass modulator is shown in Fig-

ure 5.19, where α1 = 1/2, α2 = 2. This modulator is implemented as a fully
differential circuit depicted in Figure 5.20, where the comparator is assumed
to have an enable (or comparison) phase and a reset phase. It is based on
a switched-capacitor (SC) integrator and operates with nonoverlapping two-
phase clock signals. Phase 1 includes φ1 and φ1d , while φ2 and φ2d constitute
Delta-Sigma Data Converters 203

phase 2. The comparator can provide erroneous decisions due to the fact that
its decision time generally increases for input signals with a low magnitude.
It is then followed by a flip-flop, which can reduce the bit error due to the
metastability. The switching of the reference voltages is controlled by a digital
circuit, which consists of NAND gates and inverters with a buffer function.
Simulation results show that the dynamic range of the modulator increases
by 15 dB for every doubling of the OSR.
α2 α1
ω2 ω1
In Σ s Σ s Out

β2 β1 CK

1−bit
DAC

FIGURE 5.21
Block diagram of a second-order lowpass CT modulator.

C C

Vi+ − + −+ − + −+ −+ D Q D Q V0+
gm2 g m1 CK CK
Vi− + − +− + − +− +− D Q D Q V0−
Enable

C C
1−bit NRZ 1−bit NRZ φ φ
DAC 2 DAC1

b
b

FIGURE 5.22
Circuit diagram of a second-order lowpass CT modulator.

The block diagram of a second-order lowpass modulator, which uses a

continuous-time filter, is shown in Figure 5.21, where α1 = α2 = 1, β1 = 1.5,
β2 = 1, and ω1 = ω2 = 1. The implementation of this modulator shown in
Figure 5.22 is based on gm -C operational amplifier integrators. The output
signal of the filter is quantized by the latched comparator and then processed
by the D flip-flops, which drive the two 1-bit switched-current DACs used in
the feedback path.
Figure 5.23 shows the principle, waveforms, and circuit diagram of a dif-
ferential 1-bit NRZ DAC. The DAC output current remains constant over a
full period of the clock signal.

Because Ĥ(s) cannot uniquely be determined by the impulse

invariant transformation, a suitable CT filter prototype is gen-
erally used to solve Equation (5.31). For the filter used in the
204 Data Converters, Phase-Locked Loops, and Their Applications
VDD
VDD
IB b
+ VB2
I DAC
b

b b b
+
I DAC
I−
b DAC

IB

−
I DAC
(a)
b b
φ

t/T
+
I DAC VB1

IB VSS
t/T
(b) 0 1 (c)

FIGURE 5.23
Differential 1-bit NRZ DAC: (a) principle, (b) waveforms, (c) circuit diagram.

modulator of Figure 5.22, it can be assumed that the DAC pulse

is of the NRZ type and the filter has the following transfer func-
tion:
β1 β2
Ĥ(s) = + 2 (5.43)
s s
Here, the equivalent DT transfer function can be obtained as
n h i o
H(z) = Z L−1 P (s)Ĥ(s) (5.44)
t=nT

Because the s-transform of the DAC pulse is given by

1 − e−sT
P (s) = (5.45)
s
we have
( " # )
−1 −1 Ĥ(s)
H(z) = (1 − z )Z L (5.46)
s
t=nT

Noting that
( " # )
1 T z −1
Z L−1 = (5.47)
s2 (1 − z −1 )2
t=nT
( " # )
−1 1 T 2 z −1 (1 + z −1 )
Z L = (5.48)
s3 (1 − z −1 )3
t=nT
Delta-Sigma Data Converters 205

and T = 1, the equivalent z-domain transfer function can be

expressed as

(2β1 + β2 )z −1 + (−2β1 + β2 )z −2
H(z) = (5.49)
2(1 − z −1 )2
In the case where β1 = 1.5 and β2 = 1, we can obtain

2z −1 − z −2
H(z) = (5.50)
(1 − z −1 )2
The CT modulator of Figure 5.21 is then equivalent to a second-
order DT modulator with the QNTF given by

1
HQ (z) = = (1 − z −1 )2 (5.51)
1 + H(z)
Note that the design of a CT modulator can be based on other
types of DAC pulses. In order to obtain the output at any time
between two consecutive sampling instants, the expression of the
equivalent DT transfer function should be rewritten as
n h i o
H(z) = Zm L−1 P (s)Ĥ(s) (5.52)
t=nT

where Zm denotes the modified z-transform.

In the analysis of the excess loop delay, the transfer function
provided by the modified z-transform, which is based on the
assumption that the delay occurs at the output of the CT filter,
is similar but not identical to the one obtained by solving the
impulse invariant transformation equation in the time domain,
where the fact that the delay occurs prior to the DAC pulse, as
it is the case in practical circuit, can be taken into account.
α2 α1 α0
ω2 ω1
In Σ s Σ s Σ Out

, , CK
β2 β1 β0
1−bit
DAC

FIGURE 5.24
Block diagram of a second-order lowpass CT modulator with an extra feedback
path.
α0 = α1 = α2 = 1, ω1 = ω2 = 1.

One approach to compensate for the excess loop delay consists

of adding extra feedback paths to the modulator. In the mod-
ulator block diagram shown in Figure 5.24, the additional path
206 Data Converters, Phase-Locked Loops, and Their Applications

connects the DAC output to the summer inserted between the

last integrator and the quantizer. The transfer function of the
CT filter now becomes
β1′ β′
Ĥ(s) = β0 + + 22 (5.53)
s s
Considering an excess loop delay equal to τ , the z-domain equiv-
alent transfer function of the filter can be obtained as
n h i o
Hτ (z) = Z L−1 Pτ (s)Ĥ(s) (5.54)
t=nT

where T is the clock signal period, and the Laplace transform

of the DAC pulse, Pτ (s), is given by
Z T +τ
Pτ (s) = e−st dt (5.55)
τ
e−sτ − e−s(T +τ )
= (5.56)
s
−sτ
e − e−sT 1 − e−sτ
= + e−sT (5.57)
s s
Using the following impulse invariant transformations
( " # )
−1 Pτ (s) (1 − τ )z −1 −1 τ z
−1
Z L = + z (5.58)
s 1 − z −1 1 − z −1
t=nT

and
( " # )
Pτ (s) (1 − τ )2 z −1 + (1 − τ 2 )z −2
Z L−1 =
s2 2(1 − z −1 )2
t=nT (5.59)
τ (2 − τ )z −1 + τ 2 z −2
+ z −1
2(1 − z −1 )2
it can be shown that
az −1 + bz −2 + cz −3
Hτ (z) = (5.60)
2(1 − z −1 )2
where

a = 2β0 + 2β1′ (1 − τ ) + β2′ (1 − τ )2 (5.61)

b = −4β0 − 2β1′ (1 − 2τ ) + β2′ (1 2
+ 2τ − 2τ ) (5.62)

and

c = 2β0 − 2β1′ τ + β2′ τ 2 (5.63)

Delta-Sigma Data Converters 207

The compensation for the excess loop delay is achieved pro-

vided the transfer functions H(z) and Hτ (z) are matched. Set-
ting Equation (5.49) equal to (5.60) yields
β0 = β1 τ + β2 τ 2 /2 (5.64)
β1′ = β1 + β2 τ (5.65)

and

β2′ = β2 (5.66)
The aforementioned method for the derivation of the feedback
coefficients may become cumbersome and impractical due the
nonideal characteristics (parasitic poles and zeros) of amplifiers
used in the integrator design. As a consequence, numerical tech-
niques and behavioral simulations are often used in practice.

R 2b C2 C1

R 2a
Vi+ −+ − + −+ −+ D Q D Q V0+
gm1 CK CK
V−
i +− + − +− +− D Q D Q V0−
R 2a Enable

R 2b C2 C1
φ φ
1−bit 1−bit
SC DAC RZ DAC
b

φk

FIGURE 5.25
Circuit diagram of a second-order lowpass CT modulator.

A CT modulator can also be implemented using RZ DACs. Let us consider

the following second-order DT signal transfer function,
z −1 (2 − z −1 )
H(z) = (5.67)
(1 − z −1 )2
= H2 (z) + H1 (z) (5.68)
where H1 (z) = 2/(z − 1) and H2 (z) = 1/(z − 1)2 . Using a switched-capacitor
with a series resistor (SCR) DAC [10, 11] and a switched-current RZ DAC,
the equivalent CT transfer function can be obtained by making the quantizer
inputs of DT and CT modulator prototypes equal at the sampling instants,
nT . In the z-domain, for j = 1, 2, this translates into the equation to be solved
for the CT transfer function,
Z −1 {Hj (z)} = L−1 {PHj (s)Ĥj (s)}|t=nT (5.69)
208 Data Converters, Phase-Locked Loops, and Their Applications
VCM −VREF

φ
k C

b. φk φ
R
+ t/T
b. φk I DAC
φ
φ φ k
d k
VCM b. φk t/T
φ
d
φ φ
d k b. φk I−
DAC t/T
R I+
DAC
C I B /( T/ τ )

φ t/T
k p p
0 1 2 1
VCM +VREF
(a) (b)

FIGURE 5.26
Circuit diagram and waveforms of a 1-bit SCR DAC.

VDD VDD
b. φ k
I B /( p2 − p1 ) VB2
+
b. φ k I DAC

b. φ k
b. φ k

I+
b. φ k I− DAC
DAC

I B /( p2 − p1 ) VCM

(a) I−
DAC

φ
b. φ k
t/T
φk
VB1
t/T
I+
DAC
(c) VSS

I B /( p2 − p1 )

t/T
0 p p 1
(b) 1 2

FIGURE 5.27
Principle, waveforms, and circuit diagram of a 1-bit RZ DAC.

where

e−sp1 T (1 − e−(s+1/τd )(p2 −p1 )T )

PH2 (s) = (5.70)
s + 1/τd
−sp1 T −sp2 T
e −e
PH1 (s) = (5.71)
s

and τd is the discharging time constant of the DAC. In the time domain, by
making the impulse responses identical at the sampling instants, the equivalent
Delta-Sigma Data Converters 209

equation is derived as,

Z +∞
h(nT ) = phj (t) ∗ hj (t)|t=nT = phj (τ )hj (t − τ )dτ (5.72)
−∞ t=nT

where
(
e−(t−p1 T )/τd p1 T ≤ t < p2 T
ph2 (t) = (5.73)
0 otherwise
(
1 p1 T ≤ t < p2 T
ph1 (t) = (5.74)
0 otherwise.

The CT transfer function of the loop filter can be obtained as

Ĥ(s) = Ĥ2 (s) + Ĥ1 (s) (5.75)

r21 s + r20 2r10
= + (5.76)
s2 s
where
1
r10 = (5.77)
(p2 − p1 )T
1
r20 = (5.78)
τd (1 − e−(p2 −p1 )T /τd )T
p1 + τd /T − 1 − (p2 + τd /T − 1)e−(p2 −p1 )T /τd
r21 = (5.79)
τd (1 − e−(p2 −p1 )T /τd )2
The resulting second-order CT modulator can be implemented as shown in
Figure 5.25. The loop filter consists of a feedback RC integrator followed by
a gm C-OA integrator.
The circuit diagram and waveforms of a 1-bit SCR DAC are represented
in Figure 5.26, where φ is the clock signal. During the phase φk , that lasts
for a quarter of the clock signal period, the capacitors C are charged to a
potential difference of 2VREF . Afterward, depending on the input data bit b
(comparator output), the capacitors C are discharged through the resistors R
that are switched on during the phase φd , whose duration is one-half of the
clock signal period.
Figure 5.27 shows the principle, waveforms, and circuit diagram of a dif-
ferential 1-bit RZ DAC. Here, φk lasts for a quarter of the clock signal period.
Depending on the input data bit, the DAC can deliver a current of the form,
+
IDAC = bIB /(p2 − p1 ), where b = ±1. During the return-to-zero phase, either
the transistor switch driven by the NAND gate or the one driven by the NOR
gate is closed so that the DAC current can be directed to the path connected
to the common-mode voltage, VCM . In this way, the current source transis-
tors are prevented from going into the non-linear region, hence relaxing the
settling requirements.
210 Data Converters, Phase-Locked Loops, and Their Applications

Note that by choosing the peak current equal to 2IB for the RZ DAC and
IB T /τ for the SCR DAC, each DAC can deliver the same total charge per
clock signal period if τ ≪ T /2.
In general, by operating with symmetric signals, differential architectures
have the advantage of reducing the inter-symbol interference effects caused by
unequal rise and fall times of the DAC pulses.

5.1.5.4 Modulator architectures with a multi-bit quantizer

A multi-bit ∆Σ modulator is realized by using a multi-bit quantizer (or say, a
B-bit ADC) and a DAC. The main advantage of multi-bit modulators is the
increase in the dynamic range by about 20 log10 (2B − 1) dB compared to that
of modulators with a single-bit quantizer. This is due to the fact that the power
of the quantization noise is proportional to the square of the quantizer step
size, which is reduced by increasing the number of quantization levels in the
converter range. The oversampling ratio required to achieve a given conversion
resolution can then be reduced. In the design of high-order (L > 2), single-
loop modulators, the use of a multi-bit quantizer helps prevent the instability
due to quantizer overload and observed in most single-bit structures. In the
case of low-order (L ≤ 2) modulators, an improved attenuation of tones can
be expected because the quantization noise is more randomly distributed as
the number of bits of the quantizer is increased.

B−bit
In Σ α 1 I(z) Σ α 2 I(z) Out
ADC

B−bit
DAC

FIGURE 5.28
Block diagram of a multi-bit second-order modulator.

The block diagram of a multi-bit second-order modulator is depicted in

Figure 5.28, where α1 = 1/2, α2 = 2, and I(z) = z −1 /(1 − z −1). The multi-bit
DAC used in the feedback loop can be implemented using either current-
steering circuits, wherein transistor matching is essential to obtain a high
linearity, or charge-redistribution circuits, in which capacitor matching is re-
quired. By modeling the quantizer as an additive source with the quantization
noise EQ and the multi-bit DAC as an additive source with the nonlinearity
error ED , the modulator output, Y , is given by

Y (z) = z −2 S(z) + (1 − z −1 )2 EQ (z) − ED (z) (5.80)

where S denotes the input signal. Hence, the performance of the multi-bit
modulator is limited by the nonlinearity of the B-bit internal DAC, which re-
sults in distortions directly added to the input signal. Modulator designs were
reported using digital correction techniques [12] or dynamic element matching
Delta-Sigma Data Converters 211

(DEM) methods such as data-weighted averaging (DWA) to reduce the effect

of the DAC mismatch errors that can be introduced in the signal baseband.

B−bit Digital
In Σ α 1 J(z) Σ α 2 I(z) Out
ADC correction

B−bit
DAC

FIGURE 5.29
Block diagram of a multi-bit second-order modulator with digital calibration.

The general architecture used for the digital calibration is illustrated by

the block diagram shown in Figure 5.29. During the calibration, the system is
configured to allow the estimation of DAC errors that are stored in memory
and subsequently used for correction.
The internal ADC is generally of the flash type and its hardware complexity
increases exponentially with the bit resolution. That is, a suitable choice for
the number of bits, B, is on the order of 4. The block diagram of the digital
calibration required to meet the accuracy of 16 bits using a second-order
modulator with an OSR of 128 is shown in Figure 5.30 [12]. It is based on
the length truncation of data stored in a random access memory (RAM).
In the worst case, the 4-bit internal DAC is assumed to exhibit a linearity
of 9 bits. The modulator output is transferred to the address lines for the
selection of the corresponding RAM word with the length of 10 bits (1 sign
bit + 9 bits). This latter is reduced to 3 bits by a first-order digital ∆Σ
modulator. The compressed RAM word, e, is then added to x, which is a 10-
bit delayed version of the modulator output. The modulator output sequences
form the four MSBs, the fifth MSB is set to 1 to assign the positive sign of
x to the addition result for any value of e, and the remaining bits are zero.
The 10-to-4 bit truncation of s is then achieved using the structure shown in
Figure 5.31. Note that the characteristic of the truncator is determined by the
signal resolution predicted by simulations to be at least 18 bits. The scheme
depicted in Figure 5.32 is used to store the conversion errors of the 4-bit DAC
in the RAM. The analog equivalent of the digital input code generated by
a 4-bit counter is applied to the initial multi-bit ∆Σ modulator operating
as a single-bit converter. The decimation stage is based on counters, which
can provide an 18-bit word for each digital input code, which is held for 218
clock periods. The error data to be stored in the RAM is computed as the
difference between the converted and the original input code. The overall
calibration requires 24 × 218 clock periods and is achieved off-line. However,
with a DAC structure that can operate with multiple inputs and outputs, such
as the resistor-string converter, the modulator can be duplicated to allow a
background calibration.
An alternative technique used to mitigate the effect of component mis-
match in multi-bit DACs is dynamic element matching (DEM), which con-
sists of using an algorithm to assign randomly the DAC unit elements to the
212 Data Converters, Phase-Locked Loops, and Their Applications
4 10 x 10 s 10−to−4 bit 4
In z −1 Out
Truncator

Address
e

Data out
10 11 3 (Sign bit + 2 MSBs)
RAM
Read/ Write
9 (Sign bit + 8 LSBs)
z −1

10−to−3 bit truncation

FIGURE 5.30
Block diagram of the digital calibration. (From [12], ©1993 IEEE.)

10 18 4
s Σ Σ z −1 Quantizer Out

z −1

FIGURE 5.31
Block diagram of the modulator used for the 10-to-4 bit truncation.

4−bit 4−bit 4−bit 4

Σ α 1 I(z) Σ α 2 I(z)
counter ADC ADC

1 (MSB)
4 1−bit
DAC
14
2
18 18 Decimation
stage
18−bit
adder Σ

10

Address Data in
RAM
Read/ Write

FIGURE 5.32
Scheme for the storage of the DAC error data in the RAM. (From [12], ©1993
IEEE.)

code being converted. In this way, the linearity error, which is generated in
the case where some mismatched elements are more frequently selected than
others over a given time period, is modulated at frequencies outside the signal
band. The DEM technique can be implemented using a shifter controlled by
a suitable selection logic. However, the clock frequency of the resulting mod-
ulator can be limited by the time delay introduced in the feedback path by
this additional logic.
In comparison with single-bit topologies, multi-bit modulators offer a bet-
ter performance (an increase of the dynamic range by 6 dB per additional bit
as a result of the reduced quantization noise, and an improved attenuation of
Delta-Sigma Data Converters 213

tones because the randomness assumption of the quantization noise is better

satisfied as the number of quantization levels is increased) without increasing
the OSR, but they can be limited by the stringent linearity requirement placed
on the feedback DAC.

5.1.5.5 Cascaded modulator

The use of a high-order filter structure or a multi-bit internal quantizer can
be adopted to improve the dynamic range of a modulator without increasing
the oversampling ratio. However, each of these design solutions is known to
be limited by potential shortcomings. High-order single-loop modulators may
become prone to instability due to quantizer overload caused by large signals
or the integrator initial conditions. The performance of modulators with a
multi-bit quantizer is affected by the nonlinearity of the internal DAC and
the increasing loading of amplifiers. A suitable design alternative can consist
of performing high-order filtering through a cascade of low-order structures
to ensure modulator stability and using a multi-bit quantizer only in the fi-
nal stage, whose noise cancelation logic also attenuates the nonlinearity of
the multi-bit DAC in the signal baseband [13]. The resulting implementation
is known as a multistage or cascaded modulator. Here, cascaded modulators
are realized using only first-order and second-order structures, which feature
relaxed stability criteria. In this way, the dynamic range of the cascaded modu-
lator can be larger than the one of single-loop structures, provided an adequate
matching is achieved between the loop coefficients.
The input signal of the first stage is S and the subsequent stages are fed
by a signal, which is either the inverted version of the quantization noise
generated by the previous stage or the output of the last integrator in the
previous stage, and which can be computed from the following equations:
Xi (z)
EQi (z) = Yi (z) − or Xi (z) = αi (Yi (z) − EQi (z)) i = 1, 2, 3
αi
(5.81)
for the first-order modulator, and
X2 (z)
EQ1 (z) = Y1 (z) − or X2 (z) = α1 α2 (Y1 (z) − EQ1 (z)) (5.82)
α1 α2
in the case of the second-order modulator. Here, EQ1 , EQ2 , and EQ3 are the
quantization noises; Y1 , Y2 , and Y3 denote the modulator outputs; X1 , X2 ,
and X3 represent the integrator outputs; and α1 , α2 , and α3 are scaling coeffi-
cients. The purpose of the scaling process is to maximize the overload level by
using all the available signal swing at the output of each integrator without
clipping. To keep the modulator output independent of the integrator coef-
ficients, the output of the last integrator in a given stage is multiplied by a
factor proportional to the inverse of the product of all the integrator coeffi-
cients of that stage before being summed at the input of the next stage.
214 Data Converters, Phase-Locked Loops, and Their Applications

Second-order modulator

In Σ α 1 I(z) H 1 (z) In Σ α 1 I(z) H 1 (z)

1/α 1 1/α 1
1−bit Σ Out 1−bit
DAC DAC Σ Out

b−bit b−bit
Σ α 2 I(z) H 2 (z) Σ α 2 I(z) Σ H 2 (z)
ADC ADC

b−bit b−bit

(a) DAC (b) DAC

FIGURE 5.33
Block diagrams of 1-1 cascaded lowpass modulators.

The second-order architectures depicted in Figure 5.33 require two first-order

modulator stages. It can be assumed that α1 = α2 = 1.

• Second-order, 1-1 cascaded lowpass modulator (a)

In the modulator structure of Figure 5.33(a), the quantization noise of the
first stage is estimated, inverted, and applied to the next stage. The linear
analysis in the z-domain of the modulator yields the following equations,

Y1 (z) = z −1 S(z) + (1 − z −1 )EQ1 (z) (5.83)

−1 −1
Y2 (z) = −z EQ1 (z) + (1 − z )EQ2 (z) (5.84)

and

Y (z) = H1 (z)Y1 (z) + H2 (z)Y2 (z) (5.85)

where Y1 and Y2 denote the outputs of the first and second stages, respec-
tively, and EQ1 and EQ2 represent the quantization noises of the first and
second stages, respectively.

• Second-order, 1-1 cascaded lowpass modulator (b)

For the implementation illustrated by the block diagram of Figure 5.33(b), the
output of the first integrator is connected to the input of the second modulator
stage. The following expressions can be derived:

Y1 (z) = z −1 S(z) + (1 − z −1 )EQ1 (z) (5.86)

−1 −1
Y2 (z) = z X1 (z) + (1 − z )EQ2 (z) (5.87)

and

Y (z) = H1 (z)Y1 (z) + H2 (z)[Y2 (z) − H1 (z)Y1 (z)] (5.88)

Delta-Sigma Data Converters 215

where Y1 and Y2 denote the outputs of the first and second stages, respectively,
and EQ1 and EQ2 represent the quantization noises of the first and second
stages, respectively. The output, X1 , of the integrator in the first stage can
be obtained as
X1 (z) = z −1 (S(z) − EQ1 (z)) (5.89)
and it can then be found that

Y2 (z) = z −2 (S(z) − EQ1 (z)) + (1 − z −1 )EQ2 (z) (5.90)

By choosing the transfer functions, H1 and H2 , of the digital cancelation

logics for the modulators of Figure 5.33 as

H1 (z) = z −1 and H2 (z) = 1 − z −1 (5.91)

the overall output should ideally exhibit only the quantization noise of the
last modulator stage. Hence,

Y (z) = HS (z)S(z) + HQ (z)EQ2 (z) (5.92)

where the STF and QNTF are, respectively, of the form

HS (z) = z −2 and HQ (z) = (1 − z −1 )2 (5.93)

Third-order modulator

A third-order lowpass modulator can be implemented by the 1-1-1 cascaded

or 2-1 cascaded structures as shown in Figure 5.34, where α1 = α2 = α3 = 1,
or Figure 5.35, where α1 = 1/2, α2 = 2, α3 = 1.

• Third-order, 1-1-1 cascaded lowpass modulator (a)

With reference to the modulator of Figure 5.34(a), we have

Y1 (z) = z −1 S(z) + (1 − z −1 )EQ1 (z) (5.94)

−1 −1
Y2 (z) = −z EQ1 (z) + (1 − z )EQ2 (z) (5.95)
−1 −1
Y3 (z) = −z EQ2 (z) + (1 − z )EQ3 (z) (5.96)

and

Y (z) = H1 (z)Y1 (z) + H2 (z)Y2 (z) + H3 (z)Y3 (z) (5.97)

where Y1 , Y2 , and Y3 are the outputs of the first, second, and third stages,
respectively; and EQ1 , EQ2 , and EQ3 represent the quantization noises of the
first, second, and third stages, respectively. To remove the quantization noises
216 Data Converters, Phase-Locked Loops, and Their Applications

In Σ α 1 I(z) H 1 (z) In Σ α 1 I(z) G1 (z)

1/α 1 1/α 1
1−bit 1−bit
DAC DAC

Σ α 2 I(z) H 2 (z) Σ Out Σ α 2 I(z) G2 (z) Σ Out

1/α 2 1/α 2
1−bit 1−bit
DAC DAC

b−bit b−bit
Σ α 3 I(z) H 3 (z) Σ α 3 I(z) G3 (z)
ADC ADC

b−bit b−bit

(a) DAC (b) DAC

FIGURE 5.34
Block diagrams of 1-1-1 cascaded lowpass modulators.

of the two first stages from the modulator output, it is necessary to use digital
circuit sections with the transfer functions
H1 (z) = z −2 H2 (z) = z −1 (1 − z −1 )
H3 (z) = (1 − z −1 )2
and
(5.98)
• Third-order, 1-1-1 cascaded lowpass modulator (b)
In the case of the structure depicted in Figure 5.34(b), the following expres-
sions can be derived:
Y1 (z) = z −1 S(z) + (1 − z −1 )EQ1 (z) (5.99)
−1 −1
Y2 (z) = z X1 (z) + (1 − z )EQ2 (z) (5.100)
−1 −1
Y3 (z) = z X2 (z) + (1 − z )EQ3 (z) (5.101)

and

Y (z) = G1 (z)Y1 (z) + G2 (z)Y2 (z) + G3 (z)Y3 (z) (5.102)

where Y1 , Y2 , and Y3 are the outputs of the first, second, and third stages,
respectively; and EQ1 , EQ2 , and EQ3 represent the quantization noises of the
first, second, and third stages, respectively. The output of the first integrator
can be computed as
X1 (z) = z −1 (S(z) − EQ1 (z)) (5.103)
and Y2 becomes
Y2 (z) = z −2 (S(z) − EQ1 (z)) + (1 − z −1 )EQ2 (z) (5.104)
while the output of the second integrator is obtained as
X2 (z) = z −2 (S(z) − EQ1 (z)) − z −1 EQ2 (5.105)
Delta-Sigma Data Converters 217

and Y3 can take the form

Y3 (z) = z −3 (S(z) − EQ1 (z)) − z −2 EQ2 (z) + (1 − z −1 )EQ3 (z) (5.106)

Here, the cancelation of the quantization noise of the first previous stages is
achieved with the following transfer functions:

G1 (z) = z −3 G2 (z) = z −2 (1 − z −1 ) and G3 (z) = (1 − z −1 )2

(5.107)

In Σ α 1 I(z) Σ α 2 I(z) H 1 (z)

2α 1 1/α 1 α 2

1−bit Σ Out
DAC

b−bit
Σ α 3 I(z) H 2 (z)
ADC

b−bit

(a) DAC

In Σ α 1 I(z) Σ α 2 I(z) H 1 (z)

2α 1 1/α 1 α 2

1−bit
DAC Σ Out

b−bit
Σ α 3 I(z) Σ H 2 (z)
ADC

b−bit

(b) DAC

FIGURE 5.35
Block diagrams of 2-1 cascaded lowpass modulators.

• Third-order, 2-1 cascaded lowpass modulator (a)

The modulator structure shown in Figure 5.35(a) can be described by

Y1 (z) = z −2 S(z) + (1 − z −1 )2 EQ1 (z) (5.108)

−1 −1
Y2 (z) = −z EQ1 (z) + (1 − z )EQ2 (z) (5.109)

and

Y (z) = H1 (z)Y1 (z) + H2 (z)Y2 (z) (5.110)

where Y1 and Y2 are the outputs of the first and second stages, respectively;
and EQ1 and EQ2 represent the quantization noises of the first and second
stages, respectively.
218 Data Converters, Phase-Locked Loops, and Their Applications

• Third-order, 2-1 cascaded lowpass modulator (b)

In the case of the modulator structure of Figure 5.35(b), we have

Y1 (z) = z −2 S(z) + (1 − z −1 )2 EQ1 (z) (5.111)

−1 −1
Y2 (z) = z X2 (z) + (1 − z )EQ2 (z) (5.112)

and

Y (z) = H1 (z)Y1 (z) + H2 (z)[Y2 (z) − H1 (z)Y1 (z)] (5.113)

where Y1 and Y2 are the outputs of the first and second stages, respectively;
and EQ1 and EQ2 represent the quantization noises of the first and second
stages, respectively. The output of the second integrator in the first stage, X2 ,
is given by
X2 (z) = z −2 S(z) + z −1 (z −1 − 2)EQ1 (z) (5.114)
and Y2 takes the form

Y2 (z) = z −3 S(z) + z −2 (z −1 − 2)EQ1 (z) + (1 − z −1 )EQ2 (z) (5.115)

In the cases of the 2-1 cascaded structures depicted in Figure 5.35, the
transfer functions of the cancelation logic are given by

H1 (z) = z −1 and H2 (z) = (1 − z −1 )2 (5.116)

and the overall output of the modulator can be written as

Y (z) = HS (z)S(z) + HQ (z)EQ3 (z) (5.117)

where the STF and QNTF are given by

HS (z) = z −3 and HQ (z) = (1 − z −1 )3 (5.118)

Ideally, the 2-1 and 1-1-1 cascaded modulators can be designed to realize
the same STF and QNTF. However, because the cancelation of the quanti-
zation noise generated by the first stage is achieved after the second-order
shaping in the 2-1 cascaded modulator, the required component matching is
more relaxed than in the 1-1-1 cascaded structure, which is based on first-
order stages.

Fourth-order modulator

The block diagrams of fourth-order lowpass modulators are depicted in Fig-

ure 5.36, where α1 = 1/2, α2 = 2, and α3 = α4 = 1, and Figure 5.37, where
α1 = α3 = 1/2 and α2 = α4 = 2.

• Fourth-order, 2-1-1 cascaded lowpass modulator (a)

Delta-Sigma Data Converters 219

In Σ α 1 I(z) Σ α 2 I(z) H 1 (z)

2α 1 1/α 1 α 2

1−bit
DAC

Σ α 3 I(z) H 2 (z) Σ

1/α 3
1−bit H’3 (z)
DAC

b−bit
Σ α 4 I(z) H 3 (z) Σ Out
ADC

b−bit
(a) DAC

In Σ α 1 I(z) Σ α 2 I(z) H 1 (z)

2α 1 1/α 1 α 2

1−bit
DAC

Σ α 3 I(z) Σ H 2 (z) Σ

1/α 3
H’3 (z)
1−bit
DAC

b−bit
Σ α 4 I(z) Σ H 3 (z) Σ Out
ADC

b−bit
(b) DAC

FIGURE 5.36
Block diagrams of 2-1-1 cascaded lowpass modulators.

With reference to the 2-1-1 cascaded modulator structure shown in Fig-

ure 5.36(a), we can obtain
Y1 (z) = z −2 S(z) + (1 − z −1 )2 EQ1 (z) (5.119)
−1 −1
Y2 (z) = −z EQ1 (z) + (1 − z )EQ2 (z) (5.120)
−1 −1
Y3 (z) = −z EQ2 (z) + (1 − z )EQ3 (z) (5.121)

and

Y (z) = H3′ (z)[H1 (z)Y1 (z) + H2 (z)Y2 (z)] + H3 (z)Y3 (z) (5.122)
where Y1 , Y2 , and Y3 are the outputs of the first, second, and third stages,
respectively; and EQ1 , EQ2 , and EQ3 represent the quantization noises of the
first, second, and third stages, respectively.
220 Data Converters, Phase-Locked Loops, and Their Applications

• Fourth-order, 2-1-1 cascaded lowpass modulator (b)

For the 2-1-1 cascaded modulator structure depicted in Figure 5.36(b), it can
be shown that
Y1 (z) = z −2 S(z) + (1 − z −1 )2 EQ1 (z) (5.123)
−1 −1
Y2 (z) = z X2 (z) + (1 − z )EQ2 (z) (5.124)
−1 −1
Y3 (z) = z X3 (z) + (1 − z )EQ3 (z) (5.125)

and

Y (z) = H3 (z)[Y3 (z) − Y ′ (z)] + Y ′ (z) (5.126)

where
Y ′ (z) = H3′ (z){H1 (z)Y1 (z) + H2 (z)[Y2 (z) − H1 (z)Y1 (z)]} (5.127)
Here, Y1 , Y2 , and Y3 are the outputs of the first, second, and third stages,
respectively; and E1 , E2 , and E3 represent the quantization noises of the first,
second, and third stages, respectively. The output, X2 , of the second integrator
in the first stage is
X2 (z) = z −2 S(z) + z −1 (z −1 − 2)EQ1 (z) (5.128)
and Y2 can be written as
Y2 (z) = z −3 S(z) + z −2 (z −1 − 2)EQ1 (z) + (1 − z −1 )EQ2 (z) (5.129)
For the output, X3 , of the integrator in the second stage, the following ex-
pression is obtained
X3 (z) = z −3 S(z) + z −2 (z −1 − 2)EQ1 (z) − z −1 EQ2 (z) (5.130)
and
Y3 (z) = z −4 S(z)+z −3(z −1 −2)EQ1 (z)−z −2EQ2 (z)+(1−z −1)EQ3 (z) (5.131)
The transfer functions of the cancelation logic for the 2-1-1 cascaded struc-
tures shown in Figure 5.36 are derived such that the quantization noises of the
first two stages should be removed from the overall output of the modulator.
That is,
H1 (z) = H3′ (z) = z −1 , H2 (z) = (1 − z −1 )2
and H3 (z) = (1 − z −1 )3
(5.132)
• Fourth-order, 2-2 cascaded lowpass modulator (a)
The analysis of the 2-2 cascaded modulator structure shown in Figure 5.37(a)
yields
Y1 (z) = z −2 S(z) + (1 − z −1 )2 EQ1 (z) (5.133)
Y2 (z) = z −2 EQ1 (z) + (1 − z −1 )2 EQ2 (z) (5.134)
Delta-Sigma Data Converters 221

In Σ α 1 I(z) Σ α 2 I(z) H 1 (z)

2α 1 1/α 1 α 2

1−bit Σ Out
DAC

b−bit
Σ α 3 I(z) Σ α 4 I(z) H 2 (z)
ADC

2α 3

b−bit

(a) DAC

In Σ α 1 I(z) Σ α 2 I(z) H 1 (z)

2α 1 1/α 1 α 2

1−bit
DAC Σ Out

b−bit
Σ α 3 I(z) Σ α 4 I(z) Σ H 2 (z)
ADC

2α 3

b−bit

(b) DAC

FIGURE 5.37
Block diagrams of 2-2 cascaded lowpass modulators.

and

Y (z) = H1 (z)Y1 (z) + H2 (z)Y2 (z) (5.135)

where Y1 and Y2 are the outputs of the first and second stages, respectively;
and EQ1 and EQ2 represent the quantization noises of the first and second
stages, respectively.

• Fourth-order, 2-2 cascaded lowpass modulator (b)

The 2-2 cascaded modulator structure of Figure 5.37(b) can be characterized
by equations of the form

Y1 (z) = z −2 S(z) + (1 − z −1 )2 EQ1 (z) (5.136)

−2 −1 2
Y2 (z) = z X2 (z) + (1 − z ) EQ2 (z) (5.137)

and

Y (z) = H2 (z)[Y2 (z) − H1 (z)Y1 (z)] + H1 (z)Y1 (z) (5.138)

where Y1 and Y2 are the outputs of the first and second stages, respectively;
222 Data Converters, Phase-Locked Loops, and Their Applications

and EQ1 and EQ2 represent the quantization noises of the first and second
stages, respectively. By expressing the output, X2 , of the second integrator in
the first stage as
X2 (z) = z −2 S(z) + z −1 (z −1 − 2)EQ1 (z) (5.139)
we obtain
Y2 (z) = z −4 S(z) + z −3 (z −1 − 2)EQ1 (z) + (1 − z −1 )2 EQ2 (z) (5.140)
For the 2-2 cascaded modulators of Figure 5.37, the digital cancelation
logic suppresses the quantization noise of the first stage, provided that
H1 (z) = z −2 and H2 (z) = (1 − z −1 )2 (5.141)
The output of the above fourth-order modulator is of the form
Y (z) = HS (z)S(z) + HQ (z)EQ3 (z) (5.142)
where the STF and QNTF are given by
HS (z) = z −4 and HQ (z) = (1 − z −1 )4 (5.143)
In practice, the cancelation of the quantization noise due to the first mod-
ulator stages is limited by the matching level achievable between the loop
gains.

5.1.5.6 Effect of the multi-bit DAC nonlinearity

Given an L-th-order cascaded modulator with k stages, the nonlinearity of
the multi-bit DAC used in the last stage can be modeled as an additive noise
characterized by the z-domain function, ED . The linear analysis yields a more
general equation of the modulator output, Y , as follows,
Y (z) = HS (z)S(z) + HQ (z)EQk (z) + HD (z)ED (z) (5.144)
where S denotes the input signal, EQk is the quantization noise of the last
stage, and STF and QNTF are, respectively, given by
HS (z) = z −L and HQ (z) = (1 − z −1 )L (5.145)
Here, the DAC nonlinearity is attenuated in the signal baseband by the trans-
fer function
HD (z) = Hk (z) = (1 − z −1 )η (5.146)
where η represents the number of integrators used in the stages 1 to k − 1.
This can be understood by observing that the output of the multi-bit DAC
is actually fed back to the input of the last stage, but it can be considered a
signal shaped by an η-th-order transfer function from the perspective of the
overall modulator. Note that the 2-1-1 and 2-2 cascaded modulators realize
the same STF and QNTF, but the errors due to the feedback multi-bit DAC
are shaped by third- and second-order transfer functions, respectively. As a
result, the 2-1-1 cascaded modulator features better attenuation of the DAC
nonlinearities in the baseband than does the 2-2 cascaded structure.
Delta-Sigma Data Converters 223

5.1.5.7 Quantization noise-shaping and inter-stage coefficient scal-

ing

In Σ α 1 I(z) Σ α 2 I(z)

2α 1 κ1 α α
1 2

1−bit
D
DAC

κ 1κ 2
1 κ1 κ2−1

Σ α 3 I(z) Σ

D D
κ3 α
3
1−bit
Σ Σ Σ D
DAC

κ3κ4
1 κ1κ3 κ4−1
b−bit
Σ α 4 I(z) Σ
ADC

D D D Σ Out

b−bit
Σ Σ Σ
DAC

FIGURE 5.38
Block diagram of a 2-1-1 cascaded lowpass modulator with scaling coefficients.

In Σ α 1 I(z) Σ α 2 I(z)

2α 1 κ1 α α
1 2

1−bit
D D
DAC

κ1κ2
1 κ1 κ2−1
b−bit
Σ α 3 I(z) Σ α 4 I(z) Σ Σ Out
ADC

2α 3 D D

b−bit
Σ Σ
DAC

FIGURE 5.39
Block diagram of a 2-2 cascaded lowpass modulator with scaling coefficients.

To avoid clipping at high levels of the quantization noise, it may be neces-

sary to use additional inter-stage scaling coefficients in cascaded modulators
as shown in the block diagram of Figures 5.38 and 5.39. The 2-1-1 cascaded
modulator uses two inter-stage gains, κ1 and κ3 , and the DAC feedback signal
is scaled by κ2 and κ4 ; while for the 2-2 cascaded structure, κ1 denotes the
inter-stage gain and κ2 is the scaling coefficient of the DAC feedback signal.
224 Data Converters, Phase-Locked Loops, and Their Applications

The QNTF can be obtained as

(1 − z −1 )4
HQ (z) = (5.147)
κ
where κ is, respectively, equal to κ1 κ3 and κ1 for the 2-1-1 and 2-2 cascaded
modulators. The design objective is to find the modulator coefficients that
yield the maximum dynamic range. The level of the signal transferred from
one stage to the next is set to avoid a premature overload by appropriately
selecting the values of the coefficients κ1 , κ2 , κ3 , and κ4 . The multiplication of
the last stage output with a factor 1/κ that is greater than 1 leads to a decrease
in the modulator resolution by log2 (1/κ) bits. Thus, a trade-off must be made
between the minimization of the quantization noise in the baseband and the
achievable improvement of the overload condition due to the 1/κ scaling effect.
To simplify the implementation of the digital circuit for the noise cancelation,
the factor 1/κ is generally chosen as a power of 2. Note that a feedback path
is added to the cancelation logics for each of the coefficients κ2 and κ4 , that
is different from unity.

5.1.6 Bandpass delta-sigma modulator

For a given technology, bandpass ∆Σ modulators are generally dedicated for
the analog-to-digital conversion of signals with a higher frequency than the one
supported by lowpass modulators. This is due to the fact that the bandwidth
frequency of a bandpass modulator is limited to fs /(2 OSR), where OSR is
the oversampling ratio and fs is the sampling frequency, instead of the signal
frequency as is the case for a lowpass modulator, thus making possible the
conversion of signals with frequencies up to fs /2. Bandpass modulators can
then find applications in the digitalization of intermediate frequency signals
in wireless receivers.
The key parameters in the design of ∆Σ modulators for a specified signal-
to-noise ratio (SNR) and dynamic range (DR) are the OSR, the order or
structure of the loop filter, and the quantizer resolution. A bandpass modula-
tor can be designed to have the passband center frequency located anywhere
between 0 and fs /2. However, the class of bandpass modulators with the pass-
band centered around fs /4 seems to exhibit some advantages. It can easily be
derived from lowpass prototypes using the z −1 to −z −2 transformation. The
resulting bandpass modulator can be implemented using building blocks with
a reduced complexity because it is based on second-order resonators with the
transfer function given by

ẑ −1 z −2
R(z) = I(ẑ)|ẑ−1 =−z−2 = =− (5.148)
1 − ẑ −1 1 + z −2
ẑ −1 =−z −2

The function R is characterized by a resonance occurring at the frequency

fs /4 due to the pair of complex poles located at z = ±j.
Delta-Sigma Data Converters 225

In the general case, the transformation of the lowpass prototype into a

bandpass modulator can be achieved using the following z-variable substitu-
tion,
z −1 − α
z −1 → −z −1 (5.149)
1 − αz −1
where α = cos 2π(f0 /fs ) and f0 represents the desired center frequency. As-
suming that f0 = fs /4, the above expression is reduced to the transformation,
z −1 → −z −2. However, this general approach has the inconvenience of not pre-
serving the dynamic properties of the lowpass prototype and may result in a
circuit implementation with increased complexity.

5.1.6.1 Single-loop bandpass delta-sigma modulator

In Σ α 1R(z) Out

1−bit
DAC

FIGURE 5.40
Block diagram of a second-order bandpass modulator.

The second-order bandpass modulator shown in Figure 5.40 is derived by

performing the dc-to-fs /4 transformation on a first-order lowpass prototype.
Assuming that α1 = 1, the STF and QNTF of the bandpass modulator are,
respectively, given by

HS (z) = −z −2 and HQ (z) = 1 + z −2 (5.150)

In Σ α 1 R(z) Σ α 2 R(z) Out

1−bit
DAC

FIGURE 5.41
Block diagram of a fourth-order bandpass modulator.

The fourth-order bandpass modulator depicted in Figure 5.41 is obtained

from the single-loop second-order lowpass modulator. In the case where we
have α1 = 1/2 and α2 = 2, the STF and QNTF can be expressed as

HS (z) = z −4 and HQ (z) = (1 + z −2 )2 (5.151)

226 Data Converters, Phase-Locked Loops, and Their Applications

5.1.6.2 Cascaded bandpass delta-sigma modulator

The SNR can be increased using a higher OSR or higher-order filter. However,
the power consumption due to the settling requirements of amplifiers becomes
a constraint in modulators with a high value of OSR. Because higher-order
modulators based on a single loop may be prone to instability, an alternative
is to use cascaded structures, provided that the mismatch between the analog
and digital transfer functions is maintained at an acceptable level.

In Σ α 1 R(z) Σ α 2 R(z) H 1 (z)

2α 1 1/α 1α 2

1−bit Σ Out
DAC

b−bit
Σ α 3 R(z) H 2 (z)
ADC

b−bit

(a) DAC

In Σ α 1 R(z) Σ α 2 R(z) H 1 (z)

2α 1 1/α 1 α 2

1−bit
DAC Σ Out

b−bit
Σ α 3 R(z) Σ H 2 (z)
ADC

b−bit
DAC
(b)

FIGURE 5.42
Block diagrams of 4-2 cascaded bandpass modulators.

The block diagrams of 4-2 cascaded bandpass modulators, as shown in

Figure 5.42, are derived from the 2-1 cascaded lowpass modulators. To proceed
further, it can be assumed that α1 = 1/2, α2 = 2, and α3 = 1. With the
transfer functions of the cancelation logic being given by

H1 (z) = z −2 and H3 (z) = (1 + z −2 )2 (5.152)

the overall output of the bandpass modulators can be expressed as

Y (z) = HS (z)S(z) + HQ (z)E2 (z) (5.153)

where S is the input signal, E2 is the quantization noise of the second stage,
and the STF and QNTF are given by

HS (z) = −z −6 and HQ (z) = (1 + z −2 )3 (5.154)

Delta-Sigma Data Converters 227

For the design of a bandpass modulator based on the z −1 to −z −2 trans-

formation, the zeros (z = ±j) of the QNTF are located at fs /4 instead of
dc (or say, z = 1), as is the case for lowpass modulators. In addition, this
transformation has the advantage of preserving the stability property of the
lowpass prototype.

5.1.6.3 Design examples

1−bit
DAC
α1 φ
1
φ α1
1
−z−1
Σ
α1 1+ z−1 1
−z−2
In Σ Out In φ
Out
1+ z−2 α1 0
2
−z−1
Σ
α1 CK 1+ z−1 2−1 MUX

1−bit α1 φ
2
DAC
1−bit
(a) (b) DAC

FIGURE 5.43
Block diagram of a second-order bandpass DT modulator.

z−1 −1
In Σ Out
1− z−1

−z−1 2 z −1
In Out (b)
1+ z −1
(a)
−z−1/2
In Σ z−1/2 Out

(c) −z−1/2

FIGURE 5.44
Block diagrams of alternative realizations of the transfer function, H(z) =
−z −1 /(1 + z −1 ).

The block diagram of a DT, second-order bandpass modulator is illustrated

in Figure 5.43(a). It is derived from a first-order lowpass filter prototype using
the z −1 to −z −2 transformation. As a result, the integrator is replaced by a res-
onator with the transfer function −z −2 /(1 + z −2 ), which can be implemented
using various SC topologies. The resonator implementation using a loop of
two undamped SC integrators is generally plagued by transfer function errors
due to the finite dc gain and bandwidth of the amplifier. The bandpass mod-
ulator is then preferably realized using a two-path structure, as depicted in
228 Data Converters, Phase-Locked Loops, and Their Applications

φ
+VREF 1d
C1 C3
−VREF φ
2d
φ
2d φ C2
1

φ C1 φ
1d 2 φ
V+
2
i
+
V01
φ φ
2d 1
−+ −+ D Q
φ
1
φ φ +− +− D Q
2d 1 V−
01 Enable
V− φ
i φ φ 2
1d C1 2
φ
1d
φ
φ
1 C2
2d
C1
φ
−VREF 2d
C3 1
+VREF φ V0+
1d 0
φ
1
φ
+VREF 2d 1
C1 C3 V0−
0
−VREF φ
1d
φ
1d φ C2
2
φ
2d
φ C1 φ
2d 1 φ
Vi+
1
+
V02
φ φ Enable
1d 2
−+ −+ D Q
CK φ
2
φ φ +− +− D Q
1d 2 V−
02
V− φ
i φ φ 1
2d C1 1

φ
φ
2 C2
1d
C1
φ
−VREF 1d
C3
+VREF φ
2d

FIGURE 5.45
Circuit diagram of the second-order bandpass DT modulator based on a first-
order highpass filter.

Figure 5.43(b), where φ1 and φ2 represent both nonoverlapping clock phases,

and each path is clocked in a time-interleaved fashion. The z-domain transfer
function of the filter is obtained as

z −1
H(z) = R(z 2 ) = − (5.155)
1 + z −1

It should be noted that the effective sampling frequency of the overall mod-
ulator is two times the one of a single path, as implied by the variable z 2 .
However, without a careful circuit and layout technique, the modulator dy-
Delta-Sigma Data Converters 229

−+ D Q
CK φ
1
+VREF C1
+− D Q
−VREF Enable

φ
1d
φ
1d

φ φ φ
2d C1 1d 1d

+VREF φ φ C3 φ
1 2d 1
−VREF
φ C1 φ
2d 2d C2 φ φ
2 2

φ φ φ
1d 2d 2d

Vi+ φ φ C3 φ
2 1d 2
φ
φ 2d C1 φ 1
1d 1d C2 φ φ +
V02 V0+
1 + 1 0
−+ V01 −+
φ C1 φ
1
1d −
φ +− V01 φ +− − 1
C2 1 1 V02 V0−
φ
φ 1d 0
2d
φ φ φ
Vi− 2 1d C3 2

φ φ φ
φ 1d C1 2d 2d
2d
φ φ
φ C2 2 2
2d
−VREF C1
φ φ φ
+VREF 1 1d C3 1

φ φ φ
2d 1d 1d

φ −+ D Q
1d C1 φ
CK 2
−VREF +− D Q
+VREF Enable

φ
2d

FIGURE 5.46
Circuit diagram of the second-order bandpass DT modulator based on a half-
delay cell.

namic range may be limited by path mismatches, which appear as spurious

frequency components in the output spectrum.
Depending on the filter topologies, the accuracy of the transfer function
pole location can be limited by capacitor mismatches. Figure 5.44 shows the
block diagram of various structures that can be used to precisely realize the
highpass transfer function, H(z).
Based on the filter block diagram of Figure 5.44(b), the circuit diagram
of the modulator was realized as shown in Figure 5.45. During the sampling
phase, the capacitors C1 are connected to the input and reference voltages,
respectively; the charge stored on capacitors C2 and C3 are proportional to
the output voltage and the inverse of the output voltage, respectively; and the
capacitors C2 are included in the feedback path around the amplifier. During
230 Data Converters, Phase-Locked Loops, and Their Applications

the integrating phase, the capacitors C3 are switched to the amplifier feedback
path and a charge transfer takes place between the capacitors C1 and C3 ; the
capacitors C2 become a load connected to the output voltage. That is,

C3 V0j (n) = C1 [Vi (n − 1) + VREF (n − 1)] − C3 V0j (n − 1) j = 1, 2 (5.156)

and
V0j (z) = H(z)[Vi (z) + VREF (z)] (5.157)
where
C1 z −1
H(z) = ± (5.158)
C3 1 + z −1
The transfer function H(z) was derived with the assumption that the clock
phasing at the filter input and at the level of the comparator latch is such
that a delay of one clock period exists from the input to output (leading to
the term z −1 in the numerator). Note that the sign of the transfer function
can be modified by simply reversing the positive and negative input nodes of
the differential implementation. Furthermore, the signal is sampled during the
first clock signal and the charge transfer occurs during the second clock phase
for one path; whereas for the other path, we have the signal sampling on the
second phase and the charge transfer on the first phase. Because the capacitors
C3 are used in the amplifier feedback path and to invert the polarity of the
output voltage, the numerator of the filter transfer function is not affected by
capacitor mismatches and the pole location can remain on the unit circle. The
value of C2 is not critical for the z-domain design, but it must be chosen so
that a low level of the thermal noise and an adequate settling of the amplifier
during the sampling phase can be achieved.
The discrete-time filter in the double-sampling bandpass modulator can
also be implemented using two half-delay cells, as depicted in Figure 5.44(c).
This approach is selected for the SC implementation of the modulator shown
in Figure 5.46. The sampling of the signal during one clock phase and the
charge transfer during the next clock phase required for the realization of the
half delay are performed by the same capacitor, or say C2 and C3 for the
first and second stages, respectively. As a result, the pole of the filter transfer
function remains insensitive to capacitor mismatches. Then, we can write

C1 [Vi (n − 1/2) + VREF (n − 1/2)] = C2 [V01 (n) + V02 (n − 1/2)] (5.159)

C3 [V02 (n − 1/2) − V01 (n − 1)] = 0 (5.160)

and
V02 (z) = H(z)[Vi (z) + VREF (z)] (5.161)
where
C1 z −1
H(z) = ± (5.162)
C2 1 + z −1
The term z −1 included in the numerator of the H(z) transfer function is due
Delta-Sigma Data Converters 231

to the fact that there is a delay of one clock period between the sampling
instants at the filter input and at the level of the comparator latch. The size
of capacitors C1 is determined by the dc gain of the filter, while C2 and C3
can be unit size capacitors.
−γ
−γ

α1 β2
ω1 ω2
In Σ s s
ω1 ω2
In Σ s s β1 Σ Out

α2
β1 β2 CK

1−bit
Σ Out
DAC
(a) (b)

FIGURE 5.47
Block diagrams of (a) a CT resonator and (b) a second-order bandpass CT
modulator.

+ −
gm1
− +
C C

Vi+ − + −+ − + −+ − + − + −+ D Q D Q V0+
gm1 gm1 gm1 gm2 CK CK
V−
i
+ − +− + − +− + − + − +− D Q D Q V0−
Enable

C C
φ
− + φ
1−bit gm1
NRZ DAC
+ −

FIGURE 5.48
Circuit diagram of a second-order bandpass CT modulator.

The CT bandpass modulator to be designed is based on a second-order res-

onator. Let X be the input signal of the CT resonator shown in Figure 5.47(a),
and X1 and X2 the output variables of the first and second integrators, re-
spectively. With the resonator output signal given by

Y (s) = β1 X1 (s) + β2 X2 (s) (5.163)

where

sω1
X1 (s) = X(s) (5.164)
s2 + γω1 ω2
232 Data Converters, Phase-Locked Loops, and Their Applications

and

ω1 ω2
X2 (s) = X(s) (5.165)
s2 + γω1 ω2

the transfer function is obtained as

Y (s) β1 ω 1 s + β2 ω 1 ω 2
Ĥ(s) = = (5.166)
X(s) s2 + γω1 ω2

where β1 , β2 , ω1 , ω2 , and γ are real coefficients.

For a second-order CT modulator designed with the loop coef-

ficients β1 = −1/2, β2 = −1/2, γ = 1, and ω1 = ω2 = ω0 , the
transfer function of the resonator is given by

(ω0 /2)s + ω02 /2

Ĥ(s) = − (5.167)
s2 + ω02

In the case of an NRZ DAC pulse, the equivalent z-domain trans-

fer function can be derived as
( " # )
−1 −1 Ĥ(s)
H(z) = (1 − z )Z L (5.168)
s
t=nT

The partial-fraction expansion of the function Ĥ(s)/s takes the

form
Ĥ(s) 1/2 − (1/2)s + ω0 /2
=− − (5.169)
s s s2 + ω02
Because
( " # )
1
−1 1
Z L = (5.170)
s 1 − z −1
( " #t=nT )
s 1 − z −1 cos ω0 T
Z L−1 2 2 = (5.171)
s + ω0 1 − 2z −1 cos ω0 T + z −2
t=nT
( " # )
−1 ω0 z −1 sin ω0 T
Z L = (5.172)
s2 + ω02 1 − 2z −1 cos ω0 T + z −2
t=nT

and the center frequency of the modulator is located at fs /4,

that is,
π
ω0 T = (5.173)
2
Delta-Sigma Data Converters 233

where T is the period of the clock signal, the transfer function

H(z) is reduced to
!
1 − z −1 1 1 z −1
H(z) = − − + (5.174)
2 1 − z −1 1 + z −2 1 + z −2

Finally, the DT version of the filter transfer function is obtained

as
z −1
H(z) = − (5.175)
1 + z −2
Note that different CT filters can be derived, depending on the
numerator implementation of the DT transfer function due to
the occurrence of the signal sampling inside the modulator loop.
For the function H(z) given by Equation (5.175), it is assumed
that the digital section of the modulator exhibits a delay of one
clock period, or equivalently z −1 . However, it is also possible to
consider that the digital stage between the comparator and the
DAC has no delay, and the DT transfer function of the filter is

z −2
H(z) = − (5.176)
1 + z −2
Especially, we need to have the set of coefficients, β1 = 1/2,
β2 = −1/2, γ = 1, and ω1 = ω2 = ω0 , yielding the CT resonator
transfer function
− (ω0 /2)s + ω02 /2
Ĥ(s) = − (5.177)
s2 + ω02

The resonator can be implemented with gm -C operational am-

plifier integrators, a local feedback, and two feedforward gain
stages. In this way, the coefficients of the transfer function can
be related to the values of capacitances and transconductances.

The modulator design can start by choosing a second-order z-domain

QNTF given by
HQ (z) = 1 + z −2 (5.178)
The loop transfer function is derived as

1 − HQ (z) z −2
H(z) = =− (5.179)
HQ (z) 1 + z −2

To remove the delay introduced by the digital section, here z −1 , the loop
transfer function is multiplied by 1/z −1. This results in the transfer function
234 Data Converters, Phase-Locked Loops, and Their Applications

of the DT filter, which is then converted to the equivalent CT filter of the

form
(ω0 /2)s + ω02 /2
Ĥ(s) = − (5.180)
s2 + ω02
where ω0 = π/(2T ) and T is the period of the clock signal. This conversion
is achieved using the impulse invariant transform and assuming a DAC pulse
of the NRZ type. Figure 5.47(b) shows the block diagram of the bandpass
modulator. The same value is assigned to the coefficients α1 , α2 , and γ, which
can be used to scale the signal level at the input of the first integrator, while
β1 = −1/2, β2 = −1/2, γ = 1, and ω1 = ω2 = ω0 . The modulator implemen-
tation with gm -C operational amplifier circuits is illustrated by the circuit
diagram shown in Figure 5.48, where gm2 = 2gm1 and ω0 = gm1 /C.
Unlike DT modulators using an SC filter, whose coefficients are related to
capacitor ratios, CT modulators based on a gm -C operational amplifier filter
have coefficients that are determined by the absolute values of transconduc-
tances and capacitors. A matching on the order of 1% is achievable between
gm /C values. However, the absolute gm /C value can be subject to fluctuations
of about 20% due to CMOS IC process variations. A solution may consist of
using an on-chip tuning circuit or a calibration stage based on a programmable
transconductor or capacitor array.

5.1.7 DT modulator synthesis

Given the specifications (OSR, signal-to-noise ratio, SNR, dynamic range, DR)
of a DT (lowpass) modulator, the (high-pass) QNTF, HQ (z), can be derived
by relying on traditional filter approximation functions, such as Butterworth
and Chebyshev frequency responses, or using numerical methods. Then, the
loop filter transfer function is computed using H(z) = −1 + 1/HQ (z), and
simulations are used to estimate the corresponding peak SNR and DR. If the
specifications are not met, the synthesis procedure should be repeated with
a higher order or cutoff frequency for the QNTF. For the transfer function
realizability, it is necessary that HQ (∞) must be equal to one.
In general, conventional synthesis approaches result in the optimal design
only for certain performance criteria.
Numerical methods are used to first determine the optimized QNTF zeroes
as solutions of the equations obtained by setting the first derivative of the in-
band power spectral density to zero, and then to iteratively find the best
placement, but not necessarily optimal, for the QNTF poles. QNTFs of the
Butterworth type have a very high dc loop gain or noise suppression at lower
frequencies, but less noise suppression at higher frequencies. QNTFs based
on the Chebyshev filter response feature a steeper roll-off. But they can also
exhibit ripples either in the stopband or in the passband.
For the modulator stability, the closed-loop poles should be located inside
the unit circle. But the modulator can also become unstable if the level of
the quantizer input signal exceeds the quantizer range. This is due to the fact
Delta-Sigma Data Converters 235

that the poles can move out of the unit circle as a result of a quantizer gain
reduction caused by the increase of the input signal level.
Note that when the out-of-band gain of a QNTF is too high, the quantizer
can saturate even for small input levels. For instance, a QNTF of the form,
(1 − z −1 )N , exhibits a high out-of-band gain,1 ||HQ ||∞ , that is given by 2N
at z = −1. In this case, the stability condition can be satisfied by increasing
the quantizer resolution or by adding poles to the QNTF. As a rule-of-thumb,
the modulator stability requires that ||HQ ||∞ < 1.6 (or 4.08 dB).

5.1.8 CT modulator synthesis

To reduce the number and complexity of feedback DACs, reconfigurable CT
∆Σ modulators, that find applications in multi-mode receivers, are generally
designed using architectures with multiple feedforward paths and only one
feedback path.
However, such architectures generally provide less attenuation of aliased
signal components than architectures with multiple feedback paths. They also
exhibit an undesirable out-of-band peaking in the STF. As a result, the dy-
namic range can be reduced due to the presence of strong out-of-band blockers,
especially in wireless receivers. On the other hand, the use of multiple feed-
back paths can have the inconvenience of leading to an increase of integrator
output swings. That is, low-gain integrators with large integration capacitors
must be used to avoid signal clipping.
CK EQ
@ f s = 1/T
US (s) Σ H(s) Σ Y(z)

DAC

Pτ (s)
UF (s)

FIGURE 5.49
Equivalent linear model of a CT modulator.

Methods that are generally adopted to design CT modulators based on

a loop filter with a single input path rely on the linear model shown in Fig-
ure 5.49.
Let HQ (z) be the QNTF obtained from the modulator specification. The
transfer function of the corresponding DT loop filter can be obtained as:
1 − HQ (z)
H(z) = (5.181)
HQ (z)

1 For a system characterized by the z-domain transfer function HQ (z), we have:

||HQ ||∞ = max |HQ (ejθ )|. The ||HQ ||∞ norm is infinite if the system has poles that
θ∈[0,π]
are located on the unit circle.
236 Data Converters, Phase-Locked Loops, and Their Applications

Given the transfer function, Ĥ(s), of the CT loop filter derived from the
selected modulator architecture, the impulse-invariant transformation is then
used to map Ĥ(s) to Hτ (z), as follows:

Hτ (z) = Z{L−1 [Ĥ(s)Pτ (s)]t=nT } (5.182)

where T denotes the period of the clock signal, Z is the z-transform, L−1
is the inverse Laplace transform, τ is the excess-loop delay, and Pτ (s) is the
Laplace transform of the DAC pulse. In practice, this can be achieved using
pre-computed mapping tables for NRZ, RZ, and HRZ DAC pulses or numerical
methods.
Finally, the modulator coefficients are determined by matching Hτ (z) and
H(z).
In the aforementioned design method, all modulator coefficients are
uniquely determined to achieve a target QNTF, and the STF is not directly
taken into account.

CK EQ
@ f s = 1/T
US (s) G(s) Σ Σ Y(z)

DAC

F(s) Pτ (s)
UF (s)
(a)

CK EQ
@ f s = 1/T
US (s) G(s) Σ Σ Y(z)

F(z)
(b)

FIGURE 5.50
Equivalent linear models of a CT modulator.

The design of CT modulators with a peaking-free STF is achieved using

alternative methods [14, 15] that can allow the simultaneous synthesis of the
QNTF and the transfer function of the feedforward signal path. To this end,
the linear models of the CT modulator can be derived as illustrated in Fig-
ure 5.50, where G(s) denotes the feedforward transfer function, F (s) denotes
the feedback transfer function, Pτ (s) is the transfer function of the DAC pulse,
and τ represents the excess-loop delay. In the z-domain, the QNTF can be
obtained as,
Y (z) 1
HQ (z) = = (5.183)
EQ (z) 1 − F (z)
Delta-Sigma Data Converters 237

Or equivalently, the DT feedback transfer function is given by

HQ (z) − 1
F (z) = (5.184)
HQ (z)

Considering the CT modulator as a linear system with two input vari-

ables and one output variable, the following state-space representation can be
obtained:

sX(s) = AX(s) + BU(s) (5.185)

Y (s) = CX(s) + DU(s) (5.186)

where A is the state matrix, B is the input matrix, C is the output matrix,
D is the feedforward matrix, and U(s) = [UF (s) US (s)]T , with US (s) being
the modulator input and UF (s) the DAC output. The transfer functions can
be derived as:
T(s) = C(sI − A)−1 B + D (5.187)
where  T
Y (s) Y (s)
T(s) = (5.188)
UF (s) US (s)
with F (s) = Y (s)/UF (s) and G(s) = Y (s)/US (s).
The transfer functions, F (s) and G(s), have an identical denominator be-
cause the eigenvalues of the modulator state matrix are unique. Furthermore,
the synthesis of a peaking-free STF with a monotonic roll-off frequency re-
sponse requires that G(s) be an all-pole transfer function.
Hence,
N
X −1
ai si
Y (s)
F (s) = = − i= 0 (5.189)
UF (s) D(s)
Y (s) d0
G(s) = = (5.190)
US (s) D(s)

where
N
X
D(s) = b i si (5.191)
i= 0

with ai , bi , and d0 being constants that can be related to the modulator

coefficients.
At dc, the signal gain should be equal to 1 (or 0 dB). Due to the fact that
F (z)|z=1 = F (s)|s= 0 , the analysis of the linear model leads to

Y (z)|z=1 G(s)|s= 0 d0 /b0

= = =1 (5.192)
US (s)|s= 0 1 − F (s)|s= 0 1 + a0 /b0
 238 Data Converters, Phase-Locked Loops, and Their Applications

and
d0 = a0 + b0 (5.193)

Using numerical methods, the DT QNTF can be obtained from the mod-
ulator specifications. Based on (5.184), it is used to compute the DT feedback
transfer function, F (z), that can then be transformed into the CT transfer
function F̂ (s). Finally, the modulator coefficients are determined by matching
F (s) and F̂ (s) and using (5.193).

5.1.9 Decimation filter

Once the modulator has transformed the analog samples into a low-resolution
code with the frequency OSR · fs much greater than two times the highest
spectral component of the input signal, a digital filter is used to attenuate the
out-of-band quantization noise, and high-frequency interferences that can be
aliased into the passband. The decimation of the modulator output bit stream
at the Nyquist rate is achieved by a lowpass filter followed by a down-sampler
with the factor D equal to the OSR. The aliasing in the decimation process is
avoided by pre-filtering the signal samples to eliminate the components above
the frequency fs /(2D).
The SNR is simply increased when the resolution changes from the low
resolution to B bits as a result of the down-sampling and filtering. However, it
should be noted that there is no one-to-one correspondence between the input
and output samples as is the case for some ADCs and each input sample value
contributes to the whole train of output samples.

π
Magnitude response H(ω)

H(ω)

DN
Baseband
droop
Phase response

−π
0
0 1/(2D) 1/D 2/D 3/D 0 1/D 2/D 3/D

(a) Normalized frequency ω2πT (b) Normalized frequency ω2πT

FIGURE 5.51
(a) Magnitude and (b) phase responses of a decimation filter with N sections.

The filter architecture should be chosen to have a linear-phase frequency

response2 and minimize the hardware complexity. These requirements can be
2A filter is assumed to have a linear phase if its transfer function can be written as
Delta-Sigma Data Converters 239

met by a moving-average filter [16], the transfer function of which is given by


D−1
X D if z = 1
G(z) = z −i = 1 − z −D (5.194)
 otherwise,
i=0
1 − z −1
where D = fs /fD is the decimation ratio and fD is the decimation frequency.
In the frequency domain, that is, for z = ejωT , we have
!
ejωDT /2 − e−jωDT /2 e−jωDT /2
G(ω) = (5.195)
ejωT /2 − e−jωT /2 e−jωT /2

and
sin(ωDT /2) −jω(D−1)T /2
G(ω) = e (5.196)
sin(ωT /2)
where T = 1/fs and fs is the sampling frequency. It was assumed that
ˆ jx − e−jx )/2j. The filter zeroes are located uniformly at multiples of
sin(x)=(e
the decimation frequency, fs /D. The magnitude response is obtained as


D if ω = 0
|G(ω)| = sin(ωDT /2) (5.197)

 sin(ωT /2) otherwise;

and the phase response is given by


 ωT
−(D − 1) if G(ω) ≥ 0
∠G(ω) = 2 (5.198)
−(D − 1) ωT ± π

if G(ω) < 0
2
Note that the phase response changes linearly with the frequency. The stop-
band attenuation of a single filter section with the transfer function G(z) is
limited. Given a modulator with the order L, the required decimation filter
should have a transfer function of the form [17]

H(ω) = [G(ω)]N (5.199)

where N = L + 1, in order to reduce the effect of an aliasing of the out-of

band noise on the baseband signal. Figure 5.51 shows the frequency responses
of a decimation filter with N sections. Generally, they will have D − 1 spectral
zeros, ⌊D/2⌋ of which are located between 0 and fs /2, where ⌊x⌋ denotes the
largest integer not greater than x. By sampling a signal at a rate of fs /D,
the baseband of interest should be restricted to the frequency range from 0

G(ω) = αe−jτ ω GR (ω), where α and τ are complex and real constants, respectively, and
GR (ω) is a real-valued function of ω.
240 Data Converters, Phase-Locked Loops, and Their Applications

to fb = fs /(2D). The worst-case distortion occurs at the edge frequency of

the baseband, which is characterized by ωb = π(fs /D) and where the transfer
function magnitude of the decimation filter is

−N
|H(ωb )| = [sin(π/D)] (5.200)

Within the signal bandwidth, a decimation filter with N sections then exhibits
a maximum attenuation of

Droop = −20N log10 [sin(π/D)] dB (5.201)

Generally, the signal components in the frequency range from k(fs /D) − fb to
k(fs /D) + fb , k = 1, 2, . . . , ⌊D/2⌋ can alias back into the signal baseband. In
practical applications, the useful signal bandwidth is then selected such that
fb ≪ fs /(2D) to improve the filter attenuation in aliasing bands centered
around multiples of the decimation frequency.

N N
1− z −D 1
In D Out In D (1−z −1 ) N Out
1− z −1 1− z −1

(a)

N sections with N sections with

registers clocked at f S registers clocked at f S /D

In Σ Σ Σ D Σ Σ Σ Out

z −1 z −1 z −1 z −1 z −1 z −1
Register
(b) clocked at f S /D

FIGURE 5.52
(a) Single-stage decimation filter and (b) its CIC filter-based implementation.

By moving the numerator of the filter transfer function after the rate
change stage where the sampling rate can be reduced to fs /D (see Fig-
ure 5.52(a)), the power consumption of the resulting structure is minimized.
Figure 5.52(b) shows an implementation of the decimation filter, which con-
sists of N integrators using shift registers clocked at the sampling rate fs , a
rate change stage that can be realized using a shift register operating at the
decimation rate, fs /D, and N differentiators based on shift registers with a
clock signal of fs /D. Such an implementation, known as a cascaded integrator-
Delta-Sigma Data Converters 241

comb (CIC) filter,3 has the advantage of requiring only registers and adders.

A simplistic analysis of a first-order modulator shows that the average

value of the input signal is contained in the serial output bitstream.
The decimation filter following the modulator reduces the sampling rate
of the signal sequence and increases the signal resolution by averaging
the input bitstream. In the case of a decimation by a factor D, this is
achieved by transferring one out of every D signal samples to the output.
Let us assume that the modulator delivers a 1-bit output bitstream
of the form
HLHLHHLH
where H and L denote the high and low logic states, respectively, to be
downsampled by a factor 8. The output of the decimation filter is related
to the H-state density, given by 5/8 = 0.625, that is, the signal sequence
with an overall of 8 states has 5 states at the logic high level. Because
0.625 = 1 × 2−1 + 0 × 2−2 + 1 × 2−3, the input signal can be interpreted as
a 3-bit number with the binary representation, 101. Here, the decimation
process results in a reduction of the sampling rate by a factor of 8 and
the conversion of the 1-bit serial input into a 3-bit number.

Data loss due to arithmetic overflow is avoided in the decimation filter

by using a two’s complement representation and registers with a sufficiently
large length. If the input data of the decimation filter are encoded using a
two’s complement binary format with Bin bits, the magnitude of the output
samples will be bounded by Hmax satisfying the following equation,
D−1
X
Hmax = 2Bin −1 |h(n)| (5.202)
n=0

Next, the transfer function of the decimation filter can be expressed as

D−1
"D−1 #N
X X
−n −n
H(z) = h(n)z = z (5.203)
n=0 n=0

The decimation stage can be considered a finite-impulse response (FIR) filter

producing an output word, which represents a weighted average of its most
recent input samples.
Because the product of positive coefficient polynomials is a polynomial
3 The decimation CIC filter is also called a sinc filter. This is due to the fact that the

frequency magnitude response can be expressed in terms of sinc functions, where sinc(x)
is defined as sin(x)/x.
242 Data Converters, Phase-Locked Loops, and Their Applications

with positive coefficients, all the coefficients h(n) are positive, and
D−1
X D−1
X
|h(n)| = h(n) = H(1) = DN (5.204)
n=0 n=0

Assuming that Bout is the number of bits of the output data, we have

Hmax ≤ 2Bout (5.205)

and
Bout = ⌈N log2 (D) + Bin ⌉ (5.206)
where ⌈x⌉ is the smallest integer not less than x. By considering the least
significant bit (LSB) to be the bit number zero, the most significant bit (MSB)
number Bmax in the output is given by

Bmax = ⌈N log2 (D) + Bin − 1⌉ (5.207)

Although the overall dc gain of a CIC decimation filter with N sections is

finite, individual integrators, whose gain is infinite at dc, can be subjected to
numerical overflows. If two’s complement arithmetic is used, and if the sum
of more than two numbers is guaranteed not to overflow, then overflows in
partial sums will be interpreted as either the most positive or most negative
representable number, depending on its sign. The difference between any two
successive samples computed by the following differentiator cancels out the
overflow provided the data in all filter sections are represented with the same
MSB position as the one of the output samples, as set by the word length,
Bmax .
MSB

Bmax
1

LSB

Output
register

In SEU
Σ Σ Σ Σ Σ Σ Out

0 Ci 0 Ci 0 Ci 1 Ci 1 Ci 1 Ci

CK ÷D
@ fS

FIGURE 5.53
Circuit diagram of a CIC decimation filter with three sections.

The circuit diagram of a CIC decimation filter with three sections is illus-
trated in Figure 5.53. This structure can be used as a decimation stage for a
Delta-Sigma Data Converters 243

single-bit second-order modulator. The sign extension unit (SEU) increases the
resolution and converts the binary input data stream into the two’s comple-
ment representation with Bmax bits. This is achieved by converting a sample
with a high logic level to 1 in two’s complement and a sample with a low
logic level to −1 in two’s complement. The subtraction in the differentiator
is realized using the adder carry-in node to add one to the sum of one input
sequence and the complement obtained by inverting the bits of the other input
sequence. A hard-wired logic realization of the CIC decimation filter only re-
quires registers, adders, and a clock divider. However, other implementations
may use a digital signal processor, which relies on multiply and accumulate,
and address increment and decrement (or data shifting) operations.
The word length of registers and adders are related to the overall dc gain
of the decimation filter and the input data word length. In applications with
a decimation factor greater than 64, the number of bits required for the data
representation can become excessively high as the number of filter sections
increases, leading to a structure that is prohibitively difficult to implement.
Because registers and adders are sized to have the same MSB, the word length
can be scaled down by discarding the least significant bits (LSBs) to the bit
position in any section that cannot grow beyond the LSB of the output word.
The number of LSBs to be truncated or rounded from one filter section to
another can be determined by assuming that the truncation error at the filter’s
output uniformly bounds the error incurred at the intermediate sections.

The use of truncation to reduce the word length in the N sec-

tions of a CIC decimation filter can result in a total of 2N + 1
error sources. The errors associated with the truncation at inte-
grator and differentiator inputs are labeled with j running from
1 to N and from N +1 to 2N , respectively. The truncation of the
data available at the output of the decimation filter produces an
error source specified by 2N + 1. If Bj represents the number
of bits truncated at the j-th section, the truncation or rounding
error has a uniform distribution with a width of
(
0 when using the full precision
Ej = Bj
(5.208)
2 otherwise.

The corresponding mean is Ej /2 in the case of truncation; oth-

erwise it is zero, and the variance is, respectively, given by
Ej2
σj2 = (5.209)
12
The noise error introduced at the j-th section propagates
through the filter. It can be verified that the overall mean at
the filter output is a function of only the contributions of the
244 Data Converters, Phase-Locked Loops, and Their Applications

first and last error sources. The statistical dispersion of all er-
rors is better tracked by the variance, which is then used for the
derivation of the design criteria. Assuming that the noise sources
are mutually uncorrelated, the variance at the filter output due
to the truncation at the j-th stage is

σT2 j = σj2 Fj2 (5.210)

where

 (D−1)N +j−1

 X


 h2j (n) j = 1, 2, . . . , N

 n=0
Fj2 = 2NX +1−j (5.211)

 h2j (n) j = N + 1, N + 2, . . . , 2N



 n=0

1, j = 2N + 1

and hj (n) is the impulse response from the j-th error source
to the output. The overall variance at the filter output can be
written as
2N
X +1
σT2 = σT2 j (5.212)
j=1

In practice, it can be assumed that the variance from the first

2N error sources is at least as small as the variance of the last
error source and the overall error is evenly spread out between
these 2N sources. Hence,

1 2
σT2 j ≤ σ , j = 1, 2, 3, . . . , 2N, (5.213)
2N T2N +1
where
1 2Bj 2
σT2 j =2 Fj (5.214)
12
For each filter section, the number of LSBs that can be thrown
aside is then
$ %
1 6
Bj = log + log2 σT2N +1 − log2 Fj (5.215)
2 2N

for j = 1, 2, 3, . . . , 2N . With the length of the output data being

Bout , we can get the number of LSBs discarded at the output
as follows,
B2N +1 = Bmax − Bout + 1 (5.216)
Note that the truncation of B2N +1 bits at the filter output (or
rounding the filter output) will produce an output noise with
Delta-Sigma Data Converters 245

Integrator section Differentiator section Output

Decimator register
MSB

Bout

Bmax B2N B2N+1

BN+1 BN+2
BN
Bin

LSB B2
B1

FIGURE 5.54
Register word lengths in a CIC decimation filter.

variance 22B2N +1 /12. Figure 5.54 shows the distribution of the

register word length in a CIC decimation filter.

Note that alternate decompositions of the transfer function, H(z), can be

exploited to arrive at other implementation structures of the CIC decimation
filter.

In H(z) D Out

(a)

In H1 (z) D1 H2 (z) D2 HK (z) DK Out

(b)

FIGURE 5.55
(a) Single-stage and (b) multistage decimation filters.

The decimation filter can be realized using a single-stage architecture as

shown in Figure 5.55(a). With the FIR filter commonly used for the decima-
tion, the required order (or length) is generally proportional to the sampling
frequency and inversely proportional to the width of the transition band.
Because the decimation filter should provide a narrow transition band, a
hardware-efficient design then relies on a multistage architecture [18] as shown
in Figure 5.55(b), where the earlier sections have a lower order than the latter
ones. In this way, the input signal with a high sampling rate is processed by a
filter that exhibits a large transition width, and therefore possesses a low or-
der. For the following sections, both sampling frequency and transition width
are reduced and an acceptable filter length can still be achieved.
246 Data Converters, Phase-Locked Loops, and Their Applications

1+δ p
1
1−δ p

Gain
Passband Transition Stopband
band

δs

0 Fp Fs fs /2
Frequency

FIGURE 5.56
Lowpass filter specifications.

Let the lowpass filter required by a single-stage decimation be charac-

terized by the specifications shown in Figure 5.56, where δp and δs are the
passband and stopband ripples, respectively, and Fp and Fs denote the edge
frequencies of the passband and stopband, respectively. Conventional design
methods such as the Parks-McClellan algorithm and linear programming can
be used to find the FIR filter length and coefficients such that the magnitude
frequency response, |H(ω)|, meets the following requirements:

||H(ω)| − 1| ≤ δp for 0 ≤ ω ≤ Ωp (5.217)

and
|H(ω)| ≤ δs for Ωs ≤ ω ≤ ωs /2 (5.218)
where Ωp = 2πFp and Ωs = 2πFs .

With a multistage decimation filter [20], the overall decimation ratio D is

factored into the product,
YK
D= Dk (5.219)
k=1

where K is the number of stages, and each independent section within the
structure decimates the signal by Dk , which is a positive integer. The k-th
stage must have a ripple less than δp /K in the passband defined by

0 ≤ f ≤ Fp (5.220)

where Fp is supposed to be the highest frequency in the original signal, and a

ripple less than δs in the stopband specified by

FK Fk−1
Fk − ≤f ≤ , k = 1, 2, . . . , K (5.221)
2 2
Delta-Sigma Data Converters 247

where Fk is the sampling frequency of the k-th stage. Hence,

Fk−1
Fk = (5.222)
Dk
and FK = F0 /D, where F0 represents the input sampling frequency, Dfs , of
the first stage. The passband ripple of the individual filters is selected with the
aim of maintaining the overall passband ripple within the bounds set by δp .
For each stage, the stopband ripple, and the edge frequencies of the passband
and stopband are determined such that the effects of aliasing on the baseband
spanning from 0 to F0 /2D can be eliminated. Note that the transition band
of the last stage is the same as the one of the single-stage architecture, but
the sampling frequency is somewhat reduced.

In z −1 z −1 z −1 z −1

Σ Σ Σ Σ Σ z −1

z −1 z −1 z −1 z −1

N−4 N−2
h(0) h(1) h(2) h h
2 2

Out Σ Σ Σ Σ

FIGURE 5.57
Direct form structure of a linear-phase FIR filter with N even.

In z −1 z −1 z −1 z −1

Σ Σ Σ Σ

z −1 z −1 z −1 z −1

N−3 N−1
h(0) h(1) h(2) h h
2 2

Out Σ Σ Σ Σ

FIGURE 5.58
Direct form structure of a linear-phase FIR filter with N odd.

The decimation filter should be designed to provide sufficient attenuation

of unwanted high-frequency signals that can be aliased into the baseband, and
to feature a hardware-efficient structure. By increasing the stopband atten-
uation using more CIC filter sections, the passband droop is also increased.
To compensate for the limitations of the CIC structure, a typical multistage
decimation filter will then consist of a CIC filter, followed by half-band FIR
filters and a FIR compensation filter.
248 Data Converters, Phase-Locked Loops, and Their Applications

An FIR filter can be described by the transfer function

N
X −1
H(z) = h(n)z −n (5.223)
n=0

where N is the length of the filter and h(n) denotes the filter coefficients. In
the case of a lowpass FIR filter constrained to be a linear phase system, the
coefficients must satisfy the condition

h(n) = h(N − 1 − n) (5.224)

For N even, the filter transfer function can be decomposed as

N
−1 N −1
X
2 X
H(z) = h(n)z −n + h(n)z −n (5.225)
n=0 n=N/2
N −2 N −2
X2 X 2
−n
= h(n)z + h(N − 1 − n)z −(N −1−n) (5.226)
n=0 n=0
N −2
X2 h i
= h(n) z −n + z −(N −1−n) (5.227)
n=0

and for N odd, we have

N −1
2 −1
X   N
X −1
N −1
H(z) = h(n)z −n + h z −(N −1)/2 + h(n)z −n
n=0
2
n= N 2−1 +1
(5.228)
N −3
X2
  N −3
X2
N −1
= h(n)z −n + h z −(N −1)/2 + h(N − 1 − n)z −(N −1−n)
n=0
2 n=0
(5.229)
N −3
X2 h i  
−n −(N −1−n) N −1
= h(n) z + z +h z −(N −1)/2 (5.230)
n=0
2

As a result, the filter exhibits a symmetric h(n) and the number of coefficients
is reduced to either N/2 for N even or (N + 1)/2 for N odd. Figures 5.57
and 5.58 show the direct form structures of a linear-phase FIR filter, where N
is even and odd, respectively. By reversing the signal flow-graph of the direct
form FIR filters while maintaining the same transfer function, the transpose
form structures of Figures 5.59 and 5.60 can be derived in the cases, where N
is even and odd, respectively. The main advantage of transpose architectures
is that adders are naturally pipelined without introducing additional latency.
Delta-Sigma Data Converters 249
In

N−2 N−4
h h h(1) h(0)
2 2

Σ z −1 Σ z −1 Σ z −1

z −1

Σ z −1 Σ z −1 Σ z −1 Σ z −1 Out

FIGURE 5.59
Transpose form structure of a linear-phase FIR filter with N even.
In

N−1 N−3
h h h(1) h(0)
2 2

Σ z −1 Σ z −1 Σ z −1

z −1 Σ z −1 Σ z −1 Σ z −1 Out

FIGURE 5.60
Transpose form structure of a linear-phase FIR filter with N odd.

Note that pipelining consists of adding latches or flip-flops between logic sec-
tions to reduce the critical path and increase the throughput of a system.

The block diagram of a two-fold decimation filter based on the direct

form structure is depicted in Figure 5.61(a). This implementation features the
computational complexity of the FIR filter and is not hardware efficient. An
improvement can be obtained using a polyphase structure and then swapping
the position of the filter and down-sampler, as shown in Figure 5.61(b). In
general, for an FIR filter of length N , the next polyphase decomposition can
be obtained [21]:
 N −2 N −2

X
 X
2 2

 h(2n)z −2n
+ z −1
h(2n + 1)z −2n if N even

H(z) = n=0 N −1
n=0
N −3 (5.231)

 X2 X2



 h(2n)z −2n + z −1 h(2n + 1)z −2n if N odd.
n=0 n=0

Let
hi (n) = h(2n + i) i = 0, 1 (5.232)
denote the n-th filter coefficient of the i-th polyphase component. The transfer
250 Data Converters, Phase-Locked Loops, and Their Applications

DMUX
In H(z) 2 Out
1 D Q
(a)
CK CK

x(n) H 0 (z 2 ) 2 x(n) 2 H 0 (z)

z −1 z −1

H 1 (z 2 ) 2 y(n) 2 H 1 (z) y(n)

(b)

FIGURE 5.61
Block diagrams of two-fold decimation filters based on (a) direct form and (b)
polyphase structures.

function of the FIR filter can be written as

H(z) = H0 (z 2 ) + z −1 H1 (z 2 ) (5.233)

where  N −2

 X2



 h0 (n)z −n if N even
H0 (z) = n=0 (5.234)
N −1

 X2



 h0 (n)z −n if N odd
n=0

and  N −2

 X2



 h1 (n)z −n if N even
H1 (z) = n=0 (5.235)
N −3

 X2



 h1 (n)z −n if N odd.
n=0

Basically, the filter coefficients h(n) were grouped into even- and odd-
numbered samples.
For N even, the number of multipliers and delay units is reduced by making
use of the fact that the filter coefficients of polyphase components exist in
mirror image pairs. This leads to the block diagrams of a linear-phase FIR
filter with a decimation factor of 2, as illustrated in Figures 5.62 and 5.63,
where ⌈x⌉ denotes the smallest integer not less than x.
For N odd, the implementation of the decimation filter is made hardware
efficient by exploiting the coefficient symmetry. With ⌊x⌋ being the largest
integer less than or equal to x, Figures 5.64 and 5.65 show the resulting block
diagrams of a linear-phase FIR filter with a decimation factor of 2.
Delta-Sigma Data Converters 251

In 2

N −1 N −2
h0 h0 h 0(1) h 0(0)
4 4

Σ z −1 Σ z −1 Σ z −1 Σ

z −1 z −1

Σ z −1 Σ z −1 Σ z −1 Σ z −1 Out

N −1 N −2
h1 h1 h 1(1) h 1(0)
4 4

FIGURE 5.62
Block diagram of a linear-phase FIR filter with a decimation factor of 2 (N
even and N/2 even).

In 2

N −1 N −2
h0 h0 h 0(1) h 0(0)
4 4

Σ z −1 Σ z −1 Σ z −1 Σ

z −1

z −1 Σ z −1 Σ z −1 Σ z −1 Out

N −1 N −2
h1 h1 h 1(1) h 1(0)
4 4

FIGURE 5.63
Block diagram of a linear-phase FIR filter with a decimation factor of 2 (N
even and N/2 odd).

The impulse response of a half-band FIR filter [22, 23] is characterized by



α if n = (N − 1)/2
h(n) = 0 if n = 2k − 1, k 6= (N + 1)/4 k = 1, 2, . . . , (N − 1)/2


h(2k) if n = 2k, k = 0, 1, 2, . . . , (N − 1)/2
(5.236)

where α is usually 1/2 and the filter length is of the form, N = 4L − 1, with
L being an integer. All coefficients with n odd, except for n = (N − 1)/2, are
252 Data Converters, Phase-Locked Loops, and Their Applications

In 2

N−1 N−1 −1
h0 h0 h 0(1) h 0(0)
4 4

Σ z −1 Σ z −1 Σ z −1

z −1

z −1 Σ z −1 Σ z −1 Σ z −1 Out

N−1 −1
h1 h 1(1) h 1(0)
4

FIGURE 5.64
Block diagram of a linear-phase FIR filter with a decimation factor of 2 (N
odd and (N − 1)/2 even).

In 2

N−1 N−1 −1
h0 h0 h 0(1) h 0(0)
4 4

Σ z −1 Σ z −1 Σ z −1

z −1 z −1

Σ z −1 Σ z −1 Σ z −1 Σ z −1 Out

N−1 N−1 −1
h1 h1 h 1(1) h 1(0)
4 4

FIGURE 5.65
Block diagram of a linear-phase FIR filter with a decimation factor of 2 (N
odd and (N − 1)/2 odd).

then zero. As a result, the z-domain transfer function can be expressed as

H(z) + H(−z) = 2α (5.237)

Assuming that z = ejωT , we have H(z) ↔ H(ω) and H(−z) ↔ H(ω − π), so
that
H(ω) + H(ω − π) = 2α (5.238)
Hence, the frequency response is symmetric with respect to one-quarter of the
sampling frequency, or fs /4. That is,

Fp + Fs = fs /2 (5.239)
Delta-Sigma Data Converters 253

where Fp and Fs are the edge frequencies of the passband and stopband, re-
spectively, and the passband and stopband ripples should be identical, namely,
δp = δs .

In 2

N−2 N−4
h0 h0 h 0(1) h 0(0)
2 2

Σ z −1 Σ z −1 Σ z −1

z −1 z −1

Σ z −1 Σ z −1 Σ z −1 Σ z −1 Out

N−1
h1
2

FIGURE 5.66
Block diagram of a half-band FIR filter with a decimation factor of 2.

Because a half-band filter is required to have a magnitude response with

the value of 1/2 at fs /4, it is only suitable for a decimation by a factor of 2.
Figure 5.66 shows the block diagram of a half-band FIR filter with a two-fold
decimation. The realization of a higher decimation ratio can then be addressed
by cascading a series of such filters.
In practice, the decimation filter should have a flat passband response and
narrow transition band in order to avoid the signal distortion. These features
are not generally offered by the CIC and half-band filters. A solution can then
consist of using a compensation FIR filter to cancel the passband droop intro-
duced by the CIC filter and to narrow the overall passband. This FIR filter is
designed to have the inverted version of the CIC filter passband response and
can achieve a decimation by a factor 2. To prevent the amplification of signal
components near the stopband edge frequency of the CIC filter, a good rule
of thumb is to limit the upper passband frequency of the compensation FIR
filter to about 1/4 the frequency of the first null in the frequency response of
the CIC filter.
An approach for overcoming the threat of runtime overflow in FIR filters is
to estimate the maximum value of the signal at the output of the k-th stage,
ymax,k , and to find the worst-case word length of each adder and the size of
the corresponding output register using to the following equation,
k−1
X
ymax,k = xmax |h(n)| ≤ 2Bk (5.240)
n=0

where xmax is the maximum value of the input signal, h(n) denotes the filter
coefficients, and Bk is the required number of bits. To minimize the hardware
254 Data Converters, Phase-Locked Loops, and Their Applications

complexity, rounding to lower word length or bit truncation can be performed

at each filter stage if the additional noise generated will not affect the target
accuracy.
By representing filter coefficients in the canonic signed digit (CSD)
form [24, 25], multiplications by a constant value can be transformed into a
sequence of shift operations, additions and subtractions. An important reduc-
tion in the power consumption, area, and latency in FIR circuits can then be
achieved, especially when shift operations are simply carried out at the wiring
level, and dedicated shifters are not required. The radix-2 CSD expression of
a fractional filter coefficient h is given by
L−1
X
h= ak 2pk (5.241)
k=P

where ak ∈ {−1, 0, 1}, P ≤ pk ≤ M − 1 and M − P denotes the number of

ternary digits. Note that a CSD code contains no adjacent nonzero digits, and
the −1 value is represented by 1̄.
Starting from the LSB and proceeding toward the MSB, the bits bk of
a two’s complement number can be converted into CSD digits ak for the
indexes k = 0, 1, 2, · · · , N − 1. It is assumed that c0 = 0 and bN = bN −1 , and
the conversion is realized according to the following equation,

ck+1 = ⌊(ck + bk + bk+1 )/2⌋ (5.242)

ak = bk + ck − 2ck+1 (5.243)

where ck is the input auxiliary carry, ck+1 represents the output auxiliary
carry, and ⌊x⌋ denotes the largest integer less than or equal to x.

>>3 >>2 >>8 >>5 >>3 >>2 >>3

Σ Σ Σ Σ Σ Σ
h(1) h(0)
>>1 >>6
y(1) y(0) >>6 >>1 >>5
Σ Σ
Σ z −1 Σ Σ Σ

h(1) y(1) h(0) y(0) y(1) y(0)

Σ z −1
(a) (b) (c)

FIGURE 5.67
(a) Section of a transpose filter; filter coefficient implementations (b) without
and (c) with sub-expression sharing.

The CSD representation of a number is unique and it has the advantage

of containing the fewest number of nonzero digits, which represent additions
or subtractions. A substantial hardware saving can then be realized in the
implementation of the multiplication with a CSD coefficient.
Delta-Sigma Data Converters 255

A section of a linear-phase filter with the coefficients h(0) = 0.90234 and

h(1) = 0.45703 is shown in Figure 5.67(a). The coefficient values in the 10-bit
two’s complement representation are given by

h(0) = 2−1 + 2−2 + 2−3 + 2−6 + 2−7 + 2−8 = 0.111001110 (5.244)

−2 −3 −4 −6
h(1) = 2 +2 +2 +2 = 0.011101001 (5.245)

whereas in the 10-digit radix-2 CSD representation, we have

h(0) = 20 − 2−3 + 2−5 − 2−8 = 1.001̄01001̄0 (5.246)

−1 −4 −6 −8
h(1) = 2 −2 +2 +2 = 0.1001̄01010 (5.247)

By exhibiting a reduced number of nonzero ternary digits, the CSD code

appears to be suitable for the implementation of the filter coefficients, as shown
in Figure 5.67(b). Note that the symbol >> i indicates the right shift by i bit
positions due to the term 2−i and the symbol << i represents the left shift by
i bit positions related to the term 2i . Provided that the transposed direct-form
structure is used for the FIR filter realization, common sub-expressions can
be shared between the coefficients to reduce the overall number of operations.
The filter coefficient implementation shown in Figure 5.67(b) is based on the
identities

h(0) = (−2−3 + 1)(2−5 + 1) and h(1) = 2−1 (−2−3 + 1) + 2−6 (2−2 + 1)

(5.248)

For high-order filters, the design of hardware efficient structures is performed

using algorithms [26–28] to combine sub-expressions occurring often in coeffi-
cients.
cos(2π kn0 )
Bin Lowpass Bout
decimation I out
filter
Bandpass B
In
modulator
Bin Lowpass Bout
decimation Q out
filter
−sin(2πkn0 )

FIGURE 5.68
Architecture of a bandpass modulator with a decimation filter.

The decimation stage for a bandpass modulator can consist of bandpass

filters and sample rate down-converters. Because bandpass modulators are
generally used to digitize signals at an intermediate-frequency stage of a wire-
less receiver based on the direct-conversion scheme, where in-phase (I) and
quadrature-phase (Q) signals are required to track any changes in magnitude
and phase of the incoming message, the decimation filter can be realized, as
256 Data Converters, Phase-Locked Loops, and Their Applications

shown in Figure 5.68. The two mixers, respectively, perform digital sine and
cosine multiplications at the same sample rate as the one of the bandpass
modulator. The center frequency of the input signal is then shifted to base-
band or dc, and I/Q versions of the modulator output are generated. This
allows the use of the lowpass decimation filter, which is easier to implement
and more hardware efficient than the bandpass decimation filter. However,
the word length of the input signal can still be long enough to significantly
increase the filter hardware resource.
cos(kπ/2)
2 Lowpass Bout
decimation I out
filter
Bandpass 1
In
modulator
2 Lowpass Bout
decimation Q out
filter
−sin(kπ /2)

FIGURE 5.69
Architecture of a bandpass fs /4-modulator with a decimation filter.

When the sampling frequency, fs , is four times the center frequency, f0 ,

of the modulator, the ratio n0 = f0 /fs is reduced to 1/4 and the coefficients
in the multiplications are given by

cos(kπ/2) = 1, 0, −1, 0, 1, 0, −1, 0, · · · for k = 0, 1, 2, 3, 4, 5, 6, 7, · · ·

(5.249)
− sin(kπ/2) = 0, −1, 0, 1, 0, −1, 0, 1, · · · for k = 0, 1, 2, 3, 4, 5, 6, 7, · · ·
(5.250)
Because the multiplication operations are reduced to selectively not change,
nullify, or invert the input signal, they can be implemented using a few logic
gates in the case of a single-bit modulator. Figure 5.69 shows a bandpass fs /4-
modulator with the decimation filter.

Remark
In special cases, the CIC decimation filter can be implemented using polyphase
structures [18].

Consider a CIC decimation filter consisting of N cascaded sec-

tions. Its transfer function is
!N
1 − z −D
H(z) = (5.251)
1 − z −1

By choosing the decimation factor to be a power of 2, we have

Delta-Sigma Data Converters 257

D = 2M , where M is an integer. The transfer function H(z) can

be written as
D−1
!N 2M −1 N
M−1
X X Y i
H(z) = z −i = z −i  = (1 + z −2 )N (5.252)
i=0 i=0 i=0

The commutative rule for multirate systems can be used to

N
1− z −D
In D Out
1− z −1

(a)
M sections

In (1+z −1 ) N 2 (1+z −1 ) N 2 (1+z −1 ) N 2 (1+z −1 ) N 2 Out

x(n) 2 H 0 (z)

z −1

2 H 1 (z) y(n)
(b)

FIGURE 5.70
(a) Single-stage CIC decimation filter and (b) its polyphase FIR implementa-
tion for D = 2M .

transform the block diagram of the CIC decimation filter shown

in Figure 5.70(a) into the polyphase structure of Figure 5.70(b),
which is realized by cascading M identical sections with a deci-
mation factor of 2. The transfer function of each section can be
decomposed as follows:
N
X
(1 + z −1 )N = h(j)z −j = H0 (z 2 ) + z −1 H1 (z 2 ) (5.253)
j=0

where H0 and H1 denote the polyphase components. This imple-

mentation is based on FIR filters. The data path size increases
by N bits for each section and the overflow is prevented by set-
ting the minimum word length for the k-th section to Bin + kN
bits, where Bin is the number of bits at the filter input and
k = 1, 2, · · · , M . Because the sampling frequency is successively
decreased by a factor of 2, the power consumption component,
which is proportional to the sampling frequency, can be reduced
in comparison with the one of decimation structures where this
is not the case.
258 Data Converters, Phase-Locked Loops, and Their Applications

5.2 Delta-sigma digital-to-analog converter

Delta-sigma (∆Σ) digital-to-analog converters (DACs) are typically used in
applications where a high linearity is preferred over a high bandwidth.

N Digital N <N Low Analog

Digital Digital Analog
input interpolation resolution lowpass output
fs filter OSR.fs modulator OSR.fs DAC filter

FIGURE 5.71
Block diagram of a delta-sigma DAC.

The block diagram of a delta-sigma DAC is depicted in Figure 5.71. It

comprises a digital interpolation filter, a digital delta-sigma modulator, a low-
resolution DAC, and an analog lowpass filter. The input signal is assumed to be
a stream of digital words with N bits. It is processed by a digital interpolation
filter, which raises the data rate to OSR · fs , where OSR is the oversampling
ratio and fs is the sampling rate, by inserting OSR − 1 equidistant zero-
valued samples between two consecutive samples of the input sequence. The
oversampled signal is then supplied to a digital modulator or noise shaper,
which reduces the word length, generally to 1 bit. An analog version of the
modulator output is provided by the reconstruction stage, which includes a
low-resolution DAC and a lowpass (smoothing) filter.

5.2.1 Interpolation filter

The interpolation by an integer factor of I, which results in an increase in the
output sampling rate, is the process of inserting I − 1 zeros between successive
samples of the input signal, followed by the filtering of the undesired spectral
images. For large values of I, the hardware-efficient implementation of the
interpolation filter is generally based on a multistage structure [20].

In I H(z) Out

(a)

In IK HK (z) I2 H2 (z) I1 H1 (z) Out

(b)

FIGURE 5.72
(a) Single-stage and (b) multistage interpolation filters.

Figure 5.72(a) shows the block diagram of a single-stage interpolation fil-

ter. The overall interpolation ratio I, which is equal to the oversampling ratio
of the modulator, OSR, can also be realized by a cascade of K stages, each
Delta-Sigma Data Converters 259

achieving a sampling rate increase of Ik (see Figure 5.72(b)). It can then be

factored as
K
Y
I= Ik (5.254)
k=1

where K is the number of stages. The sampling frequency, Fk , at the output

of the k-th stage is given by

Fk−1 = Ik Fk k = K, K − 1, · · · , 1 (5.255)

where it is assumed that the output sampling frequency is F0 = Ifs with fs

being the sampling frequency of the signal to be interpolated. Here, the stages
are numbered backward from K to 1 to show that, for a given rate change and
number of stages, an interpolation filter is the dual of a decimation filter, and
the input signal is applied to the K-th filter stage. The up-sampling process
also creates images of the original spectrum centered at multiples of the origi-
nal sampling frequency. For the k-th stage, lowpass filters characterized by the
transfer functions Hk (z) are used to remove the images of the baseband signal
at frequencies above ω = π(fs /Ik ). This requirement can be met by a filter
designed to have a passband ripple δp /K, a stopband ripple δs , a passband
specified by
0 ≤ f ≤ Fp (5.256)
and a stopband of the form

FK Fk−1
Fk − ≤f ≤ (5.257)
2 2
where FK is the input sampling rate, fs . It should be noted that the K-th
filter stage has the smaller transition band.
Generally, multistage structures can exhibit reduced filter lengths and com-
putational complexity as compared to single-stage designs. This is due to
the fact that the specifications of individual interpolation filters are relaxed
and low-order filters can provide a sufficient attenuation of unwanted high-
frequency signals that can be aliased into the baseband. A hardware-efficient
implementation of the interpolation filter will then consist of a compensation
FIR filter, followed by half-band FIR filters and a CIC interpolation filter. The
role of the compensation filter, which is designed to have the inverse frequency
response of the CIC filter, is to pre-equalize the passband droop of the CIC
structure.
The block diagram of a twofold interpolation filter based on the direct form
structure, as shown in Figure 5.73(a), features the computational complexity
of the FIR filter and is not hardware efficient. The number of operations
required for the signal processing in interpolation filters can be reduced using
a polyphase structure and then swapping the position of the filter and down-
sampler as shown in Figure 5.73(b).
260 Data Converters, Phase-Locked Loops, and Their Applications

MUX
In 2 H(z) Out
D Q 1
(a)
CK
CK

x(n) 2 H 0 (z 2 ) y(n) x(n) H 0 (z) 2 y(n)

z −1 z −1

2 H 1 (z 2 ) H 1 (z) 2

(b)

FIGURE 5.73
Block diagram of twofold interpolation filters based on (a) direct form and (b)
polyphase structures.
Σ Σ Σ

N −2 N −1
h’0 (0) h’0 (1) h’0
4
h’0
4
Σ 2 Σ Out

z −1 z −1 z −1

Σ Σ Σ Σ Σ Σ Σ Σ z −1 z −1

In z −1 z −1 z −1

N −2 N −1
h’1 (0) h’1 (1) h’1 h’1 Σ 2
4 4

Σ Σ Σ

FIGURE 5.74
Block diagram of a linear-phase FIR filter with an interpolation factor of 2
(N even and N/2 even).
Σ Σ Σ

N −2 N −1
h’0 (0) h’0 (1) h’0
4
h’0
4
Σ 2 Σ Out

z −1 z −1 z −1

Σ Σ Σ Σ Σ Σ z −1

In z −1 z −1 z −1

N −2 N −1
h’1 (0) h’1 (1) h’1 h’1 Σ 2
4 4

Σ Σ Σ

FIGURE 5.75
Block diagram of a linear-phase FIR filter with an interpolation factor of 2
(N even and N/2 odd).
Delta-Sigma Data Converters 261

By grouping the filter coefficients h(n) into even- and odd-numbered sam-
ples, the transfer function of an FIR filter can be expressed as

H(z) = H0 (z 2 ) + z −1 H1 (z 2 ) (5.258)

where  N −2

X 2



 h0 (n)z −n if N even
H0 (z) = n=0 (5.259)
N −1

 X2



 h0 (n)z −n if N odd
n=0

and  N −2

X
 2

 h1 (n)z −n if N even

H1 (z) = n=0 (5.260)
N −3

 X2



 h1 (n)z −n if N odd.
n=0

In the case of linear-phase FIR filters, the coefficients are symmetric because
h(n) = h(N − 1 − n).
When N is even, we have h0 (n) = h1 (N/2−1−n). Hence, the coefficients of
the polyphase components are not symmetric and exist in time-reversed pairs
that can be realized using filter structures with symmetric and anti-symmetric
impulse responses [30].
For N/2 even, a new set of filter coefficients is defined as

1
h′0 (n) = [h0 (n) + h0 (N/2 − 1 − n)] (5.261)
2
1
h′1 (n) = [h0 (n) − h0 (N/2 − 1 − n)] (5.262)
2
where n = 0, 1, 2, · · · , N/4 − 1. The transfer functions of the polyphase com-
ponents can then be given by
N/4−1 N/4−1
X X
H0 (z) = h′0 (n)(z −n + z −(N/2−1−n) ) + h′1 (n)(z −n − z −(N/2−1−n) )
n=0 n=0
(5.263)
N/4−1 N/4−1
X X
H1 (z) = h′0 (n)(z −n + z −(N/2−1−n) ) − h′0 (n)(z −n − z −(N/2−1−n) )
n=0 n=0
(5.264)

The block diagram of the resulting linear-phase FIR filter with an interpola-
tion factor of 2 is depicted in Figure 5.74.
262 Data Converters, Phase-Locked Loops, and Their Applications

For N/2 odd, we have

1
h′0 (n) = [h0 (n) + h0 (N/2 − 1 − n)] (5.265)
2
1
h′1 (n) = [h0 (n) − h0 (N/2 − 1 − n)] (5.266)
2
where n = 0, 1, 2, · · · , ⌈N/4⌉ − 2, and

1
h′0 (⌈N/4⌉ − 1) = h0 (⌈N/4⌉ − 1) (5.267)
2
′ 1
h1 (⌈N/4⌉ − 1) = − h0 (⌈N/4⌉ − 1) (5.268)
2
where ⌈x⌉ denotes the function that returns the smallest integer not less than
x. The following expressions can then be derived:
⌈N/4⌉−2
X
H0 (z) = h′0 (n)(z −n + z −(N/2−1−n)) + h′0 (⌈N/4⌉ − 1)z −(⌈N/4⌉−1)
n=0
⌈N/4⌉−2
X
+ h′1 (n)(z −n − z −(N/2−1−n) ) + h′1 (⌈N/4⌉ − 1)z −(⌈N/4⌉−1)
n=0
(5.269)

⌈N/4⌉−2
X
H1 (z) = h′0 (n)(z −n + z −(N/2−1−n)) + h′0 (⌈N/4⌉ − 1)z −(⌈N/4⌉−1)
n=0
 
⌈N/4⌉−2
X
− h′0 (n)(z −n − z −(N/2−1−n) ) + h′1 (⌈N/4⌉ − 1)z −(⌈N/4⌉−1) 
n=0
(5.270)
The block diagram of the resulting linear-phase FIR filter with an interpola-
tion factor of 2 is shown in Figure 5.75.
In the case of FIR filters with N odd and half-band FIR filters, the coeffi-
cients of the polyphase components are also symmetric, and the interpolation
structures can be obtained by transposing the polyphase structures of the
corresponding decimation filter. The block diagrams of linear-phase two-fold
FIR filters with N odd are shown in Figures 5.76 and 5.77, for (N − 1)/2 even
and (N − 1)/2 odd, respectively. Note that ⌊x⌋ is the largest integer less than
or equal to the number x. Figure 5.78 shows the block diagram of a half-band
FIR filter with the interpolation factor of 2.
The polyphase structure offers increased efficiency in both size and speed.
This is due to the fact that the filtering operation occurs at the lower sampling-
rate side of the system, and the coefficient symmetry is exploited to derive an
optimal form of the filter using resource sharing.
Delta-Sigma Data Converters 263

Σ Σ Σ 2 Σ Out

N−1 −1 N−1
h 0(0) h 0(1) h0 h0
4 4

z −1 z −1 z −1

Σ Σ Σ Σ Σ Σ z −1

In z −1 z −1 z −1

N−1 −1
h 1(0) h 1(1) h1
4

Σ Σ 2

FIGURE 5.76
Block diagram of a linear-phase FIR filter with an interpolation factor of 2
(N odd and (N − 1)/2 even).

Σ Σ Σ 2 Σ Out

N−1 −1 N−1
h 0(0) h 0(1) h0 h0
4 4

z −1 z −1 z −1

Σ Σ Σ Σ Σ Σ Σ z −1 z −1

In z −1 z −1 z −1

N−1 −1 N−1
h 1(0) h 1(1) h1 h1
4 4

Σ Σ Σ 2

FIGURE 5.77
Block diagram of a linear-phase FIR filter with an interpolation factor of 2
(N odd and (N − 1)/2 odd).

For large rate changes, a cascaded integrator-comb (CIC) filter [16] has
an advantage over an FIR structure with respect to hardware efficiency in
the context of a high-speed operation. The higher interpolation factor in a
multistage architecture can then be achieved in the CIC filter following the
polyphase FIR systems. Two equivalent block diagrams based on a noble iden-
tity for multi-rate structures are shown in Figure 5.79(a). A CIC interpolation
filter, as illustrated in Figure 5.79(b), includes a differentiator section, an up-
sampler or zero-stuff circuit, and an integrator section. The differentiator
consists of a register and a subtractor. The zero-stuff circuit is realized using
a 2-to-1 multiplexer controlled by a binary counter. The integrator is com-
posed of a register and adder. The differentiator register is clocked at the input
sampling frequency while the counter and integrator register are clocked at
the output sampling frequency.
264 Data Converters, Phase-Locked Loops, and Their Applications

Σ Σ Σ 2 Σ Out

N−4 N−2
h 0(0) h 0(1) h0 h0
2 2

z −1 z −1 z −1

Σ Σ Σ Σ z −1 z −1

In z −1 z −1 z −1

N−1
h1
2
2

FIGURE 5.78
Block diagram of a half-band FIR filter with an interpolation factor of 2.

N N
1− z −I 1 1
In I1 Out In (1−z −1 ) N I1 Out
1− z −1 1− z −1

(a)

N sections with N sections with

registers clocked at F 1 registers clocked at I 1 F 1

In Σ Σ Σ I1 Σ Σ Σ Out

z −1 z −1 z −1 z −1 z −1 z −1
Zero−stuff circuit

1
MUX

0 0

1 0 0 0 . . . 0 1 0 0 0. . . 0 1 . . .

CK Counter I1 −1 zeros
@ I 1 F1
(b)

FIGURE 5.79
(a) Single-stage CIC interpolation filter and (b) its implementation.

Because the effect of finite word lengths may be critical in the integrator
section, where overflows can cause very large errors and lead to instability due
to the unity feedback, rounding is not allowed for integrators. Furthermore,
the data widths in the CIC interpolation filter should be set by the worst-case
gain at the output of each section to accommodate the maximum value of the
signal.

Consider the realization of the interpolation by a factor I1 using a CIC

structure. The transfer function of the interpolation filter can be shown to
be !N
1 − z −I1
H1 (z) = (5.271)
1 − z −1
where N is the number of sections. The CIC interpolation filter [16] is
Delta-Sigma Data Converters 265

realized by cascading N differentiators, an up-sampler, and N integrators.

Each differentiator exhibits the transfer function

HD (z) = 1 − z −1 (5.272)

With z = e−jωT , the frequency response is given by

HD (ω) = 2j sin(ωT /2)e−jωT /2 (5.273)

The magnitude, which is then of the form

|HD (ω)| = 2| sin(ωT /2)| (5.274)

has a maximum value of 2 because the absolute value of a sine function is

bounded by one. Hence, the maximum gain from the input to the output
of the k-th section of the interpolation filter can be written as
(
2j j = 1, 2, · · · , N
Gj = 2N −j j−N −1
(5.275)
2 I1 j = N + 1, · · · , 2N

where, for j > N , we have

!j−N
−I1 2N −j 1 − z −I1
H1 (z) = (1 − z ) (5.276)
1 − z −1

and the factor 1/I1 is introduced to account for the I1 − 1 zeros inserted
by the up-sampler between the input samples. For an input data stream
with Bin bits, the minimum data width at the j-th section is

Bj = ⌈Bin + log2 Gj ⌉ (5.277)

However, as GN > GN +1 , the data width of the last differentiator is larger

than the one of the first integrator. Consequently, either the data width
of the last differentiator must be reduced to

BN = Bin + N − 1 (5.278)

when the two’s complement arithmetic is employed, or the data width

at each integrator should be increased by one to ensure filter stability.
To obtain an output data with Bout bits, the number of LSBs discarded
should be
BT = B2N − Bout (5.279)

Note that some LSBs will be truncated only if the effect of arithmetic
errors at the filter output is maintained at an acceptable level.
266 Data Converters, Phase-Locked Loops, and Their Applications

Digital
In Σ Quantizer Out
filter

FIGURE 5.80
Block diagram of an output-feedback modulator.

5.2.2 Digital modulator

Generally, the digital modulator is based on a noise-shaping loop, where ei-
ther the output signal or the quantizer error signal is fed back. This leads
to two possible structures, known as the output-feedback and error-feedback
modulators.
The block diagram of the output-feedback modulator is shown in Fig-
ure 5.80. It consists of a digital filter and quantizer, which has a truncation
function. In this case, the quantizer should provide an output data of B-bit
length consisting of the input signal MSBs. Let H be the transfer function of
the filter. Assuming that the quantizer can be modeled as an additive noise
source, the modulator output, V0 , can be related to the input voltage, Vi , in
the z-domain by
V0 (z) = HS (z)Vi (z) + HQ (z)EQ (z) (5.280)
where
H(z)
HS (z) = (5.281)
1 + H(z)
1
HQ (z) = (5.282)
1 + H(z)

and EQ is the quantization error signal. Ideally, the quantization noise has to
be suppressed at the frequency band allocated to the signal. The quantizer
and the loop filter must be designed to ensure the stability of the modulator.
Another architecture of the digital modulator, referred to as the error-
feedback scheme [29], is depicted in Figure 5.81. Here, the feedback signal
involves the quantizer error. Assuming that H is the filter transfer function,

b MSBs
In Σ Quantizer Out

Digital EQ
Σ
filter

FIGURE 5.81
Block diagram of an error-feedback modulator.
Delta-Sigma Data Converters 267

the output of this structure can be expressed in the z-domain as

V0 (z) = Vi (z) + HQ (z)EQ (z) (5.283)

where the QNTF is given by

HQ (z) = 1 − H(z) (5.284)

and EQ is the error signal introduced by the quantizer. Note that the STF
is reduced to 1. Due to the high sensitivity to component nonidealities, the
error feedback scheme is only suitable for digital implementations.
One way to improve the attenuation of the quantization noise in the base-
band is to increase the order of the digital modulator, which is similar to the
one of the loop filter. There are various structures for the realization of digital
modulators based on QNTFs with a highpass frequency response.
N N+k B MSBs
In Σ Out

Σ N+k−B

z −1 z −1

FIGURE 5.82
Block diagram of a second-order error-feedback modulator with a B-bit quan-
tizer.

The block diagram of a second-order error-feedback modulator with a B-

bit quantizer, which extracts the MSBs of its input signal, is shown in Fig-
ure 5.82. The remaining LSBs are accumulated in the feedback path until they
overflow into MSBs and thus contribute to the output. The quantization error
is shaped by a second-order transfer function of the form

HQ (z) = (1 − z −1 )2 (5.285)

and the transfer function of the filter is given by

H(z) = 2z −1 − z −2 (5.286)

The modulator implementation is greatly simplified because all multiplier co-

efficients are powers of 2 and the multiplication can be reduced to shift and
add operations.

The block diagram of a third-order error-feedback modulator is depicted

in Figure 5.83. By placing the zeros of the QNTF on the unit circle, we have

HQ (z) = (1 − z −1 )3 (5.287)
268 Data Converters, Phase-Locked Loops, and Their Applications
N N+k B MSBs
In Σ Out

Σ N+k−B

−3 3

z −1 z −1 z −1

FIGURE 5.83
Block diagram of a third-order error-feedback modulator with a B-bit quan-
tizer.

and the transfer function of the filter is given by

H(z) = 3z −1 − 3z −2 + z −3 (5.288)

Hence, the filter used in the modulator has an FIR frequency response. The
modulator implementation may not be hardware efficient due to the circuit
complexity required for multiplications by non-power-of-2 coefficients.

N N+k b MSBs (B+2−b)−bit

In Σ
shifter

Σ N+k−b

z −1 z −1

N+k+1−b B MSBs B+2 B+3

Σ (1−z −1) 2 Σ Out

N+k+1−(b+B)
z −1

FIGURE 5.84
Block diagram of a third-order, 2-1 cascaded error-feedback modulator.

A third-order error-feedback modulator can also be implemented by the

2-1 cascaded structure shown in Figure 5.84, where it is assumed that B ≥ b.
The first stage is a second-order b-bit modulator, and the inverted version
of its quantization noise is applied to the second stage, which is based on a
first-order B-bit modulator. Let S be the modulator input signal. The linear
analysis yields the equations

Y1 (z) = S(z) + (1 − z −1 )2 EQ1 (z) (5.289)

Y2 (z) = −EQ1 (z) + (1 − z −1 )EQ2 (z) (5.290)
Delta-Sigma Data Converters 269

and

Y (z) = Y1 (z) + (1 − z −1 )2 Y2 (z) (5.291)

where Y1 and Y2 denote the outputs of the first and second stage, respectively;
EQ1 and EQ2 represent the quantization noises of the first and second stage,
respectively; and the transfer function of the cancelation section is chosen in
the form, (1 − z −1 )2 . In order to correctly combine the output signals, Y1 and
Y2 , the output of the first stage must be shifted left to ensure the alignment
of both MSBs. The output of the digital modulator can then be written as

Y (z) = S(z) + (1 − z −1 )3 EQ2 (z) (5.292)

The realization of the differentiator at the output of the second stage using
digital circuits has the advantage of being more accurate than the implemen-
tation in the analog domain. However, the bit growth introduced in the error-
cancelation path has the effect of imposing stringent matching requirements
on the unit elements used in the implementation of the output DAC.
The single-bit quantization is generally preferred, because the two-level
DAC is inherently linear. However, the use of a multi-bit quantizer results
in an increase of the modulator resolution due to the reduction of the noise
effect both inside and outside the signal band and the elimination of the spec-
tral tones that can be problematic in single-bit structures. Note that a B-bit
quantizer can be implemented in modulators based on the two’s complement
arithmetic by simply truncating the multi-bit input code to its B MSBs. Aside
from this advantage, multi-bit converters require calibration schemes for the
cancelation of the distortion caused by element mismatches in the DAC.
A high resolution can also be obtained using high-order modulators. This
approach is limited by the stability constraint set by the nonoverload require-
ment of the quantizer. A digital modulator with a QNTF of the form (1−z −1 )L
will remain stable if the number of bits, B, in the quantizer output is such
that B ≥ L + 1 and the input signal does not exceed the midpoint of the last
quantization interval [31]. This is a sufficient but not necessary criterion for
the modulator stability, which depends on the input signal. To ensure stabil-
ity in special cases, simulations can be carried out to determine the allowed
maximum magnitude of the input signal.
The representation of the modulator output in the analog domain is
achieved by a DAC. The latter produces a signal containing the replica of
the digital input and the additive quantization noise. An analog lowpass filter
is then designed to eliminate the noisy signal, which lies outside the bandwidth
of interest.
270 Data Converters, Phase-Locked Loops, and Their Applications

5.3 Nyquist DAC design issues

In DAC implementations using an array of unit elements, the output signal is
the sum of all contributions due to the unit elements, which are selected based
on the input code. Any element mismatch may then affect DAC operation
and linearity. Dynamic element-matching (DEM) calibrations can be used to
convert mismatch errors into a zero-mean white noise, or to remove the noise
caused by mismatches out of the frequency band of interest [1–3, 51]. The
objective is to randomize the switching of DAC unit elements such that the
mismatch errors are averaged out. This is achieved taking into account the
fact that the bit weights are equal, and the unit element switching associated
with each digital code conversion can be performed in an arbitrary way.

Element
#1
Element selection logic

Digital Analog
input Σ
input
Element
#2 N−1

Element
#2 N

FIGURE 5.85
Block diagram of a DAC with dynamic element-matching calibration.

The general architecture of a DEM DAC is depicted in Figure 5.85. In

mismatch-scrambling DEM DACs, mismatch errors are turned into white
noise, while for mismatch-shaping DEM DACs, mismatch errors are spectrally
shaped by an appropriate filtering function. A straightforward implementation
of the digital circuit section, which is needed in DEM DACs, may substantially
increase the hardware complexity. Various vector-feedback and data-weighted
averaging (tree-structured, butterfly shuffler, barrel shifter) approaches are
often adopted to trade the hardware complexity for a lower degree of random-
ization. In contrast to data-weighted averaging structures, vector-feedback
DEM DACs have the advantage of allowing the implementation of any high-
order mismatch-shaping transfer functions, but can be limited by hardware
complexity.

5.3.1 Vector-feedback DEM

An alternative element selection approach with the advantage of providing
a high-order spectral shaping of the DAC noise can be based on the vector
feedback structure [3, 33], which uses a sorting mechanism to determine the
DAC unit elements to be selected for each conversion.
Delta-Sigma Data Converters 271
From modulator
output
v

2 B −1

Σ H(z)−1 Σ sy
1 sv1

To DAC unit elements

Vector quantizer
sv2
Σ H(z)−1 Σ sy
2

sv2 B
Σ H(z)−1 Σ sy B
2

Min

FIGURE 5.86
Vector-feedback ESL.

The block diagram of a vector-feedback ESL is depicted in Figure 5.86.

It consists of a vector quantizer, a min block (or a smallest-element sorter),
two adders, and a filter. The vector-feedback ESL processes a signal vector,
whose length is equal to the number of DAC unit elements, that is, 2B − 1
for a resolution of B bits. The signal vector, sy, is sorted and quantized in
such a way that the DAC elements associated to the v largest sy components
are enabled by the corresponding sv bits, while the remaining elements are
deactivated. For each conversion, the number of bits set to 1 in sv must be
equal to the number of 1s in the thermometer code of v. To keep the signal
values within the range, which is fixed by the finite precision arithmetic, the
smallest of all filter output signals is subtracted from the signal available at
each filter output.
The noise contribution due to element mismatch is shaped in the z-domain
by H(z), where H(z) − 1 is the filter transfer function. For applications with
lowpass or bandpass signals, the mismatch noise is efficiently removed from
the band of interest by highpass and band-reject filters, respectively.
A conventional 4-bit thermometer-coded DAC consists of 16 unit elements.
Ideally, all unit elements should be matched. However, in practice, they can
be slightly different due to IC process variations. Assuming that the DAC unit
elements exhibit random errors with a standard deviation of 1%, a first-order
noise-shaping scheme with the transfer function of the form H(z) = 1 − z −1
is used to improve the SNR of the DAC. Figure 5.87 shows the unit-element
usage for the thermometer coding and first-order noise shaping, respectively.
The number of unit elements that are in the on state (boxes filled in gray)
corresponds to the decimal equivalent of the input digital code. Figure 5.88
272 Data Converters, Phase-Locked Loops, and Their Applications
15 15
14 14
13 13
12 12
11 11
Unit element number

Unit element number

10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
8 8 10 9 10 10 11 11 12 11 14 11 14 13 12 15 13 13 14 14 8 8 10 9 10 10 11 11 12 11 14 11 14 13 12 15 13 13 14 14
(a) Input code (b) Input code

FIGURE 5.87
DAC unit-element usage: (a) Thermometer coding, (b) first-order shaping.

0
No shaping
First−order shaping
Ideal
−50
Output spectrum (dB)

−100

−150

−200 −3 −2 −1
10 10 10
Normalized frequency

FIGURE 5.88
Output power spectrum of third-order lowpass modulators.

illustrates the output power spectrum of third-order lowpass modulators using

thermometer-coded and first-order noise-shaped DACs. The correction scheme
improves the SNR for low frequencies by first-order shaping the mismatch-
induced noise. In order to whiten the noise generated by the selection algo-
rithm itself, a dither signal can be included in the correction scheme.

Let us consider a vector, x, with four different elements, x0 , x1 ,

x2 , and x3 . To design the Min block and vector quantizer, six
digital multi-bit comparators are necessary. They are configured,
Delta-Sigma Data Converters 273

+
C5
−
+ x0 00
C4 x1 01
− Cx0 Cx3 Min( x 0 , x 1, x 2 , x 3)
x2 10
+ x3 11
C3
−

Encoder
C x3
X3 +
C2 C x2
−
X2 + C1a C1x C x1
C1
−
C x0
X1 +
C0
X0 −
(a) (b)

FIGURE 5.89
(a) Generation of the signals Cx0 -Cx3 and C1a -C1x ; (b) implementation of the
Min block for an input vector with four elements.

TABLE 5.3
Boolean Expressions for the Min Block Design

Min(x0 , x1 , x2 , x3 ) = x0
Cx0 = C0 · C1 · C2 · C 3 · C 4 + C0 · C1 · C2 · C3 · C 5 + C0 · C1 · C2 · C4 · C5
Min(x0 , x1 , x2 , x3 ) = x1
Cx1 = C 0 · C 1 · C 2 · C3 · C4 + C 0 · C1 · C3 · C4 · C 5 + C 0 · C2 · C3 · C4 · C5
Min(x0 , x1 , x2 , x3 ) = x2
Cx2 = C 0 · C 1 · C 2 · C 3 · C5 + C0 · C 1 · C 3 · C 4 · C5 + C 1 · C2 · C 3 · C4 · C5
Min(x0 , x1 , x2 , x3 ) = x3
Cx3 = C 0 · C 1 · C 2 · C 4 · C 5 + C0 · C 2 · C 3 · C 4 · C 5 + C1 · C 2 · C3 · C 4 · C 5

as shown in Figure 5.89(a), to perform the following operations:

C0 : x1 > x0 C1 : x2 > x0 C2 : x3 > x0 C3 : x2 > x1
C4 : x3 > x1 C5 : x3 > x2 C 0 : x0 > x1 C 1 : x0 > x2
C 2 : x0 > x3 C 3 : x1 > x2 C 4 : x1 > x3 C 5 : x2 > x3
The output signal of a comparator is set to either the logic
high state or the logic low state, depending on the comparison
result. A dichotomy technique can be used to sort a given set
of elements. This is achieved by iteratively defining mutually
exclusive subsets such that a tree hierarchy can emerge. Here,
the sorting process provides six ordered combinations with a
274 Data Converters, Phase-Locked Loops, and Their Applications

TABLE 5.4
Boolean Functions Useful for the Sorting Procedure Implementation

x3 > x2 > x1 > x0 x3 > x2 > x0 > x1

C1a = C0 · C1 · C2 · C3 · C4 · C5 C1b = C 0 · C1 · C2 · C3 · C4 · C5
x3 > x1 > x2 > x0 x3 > x1 > x0 > x2
C1c = C0 · C1 · C2 C 3 · C4 · C5 C1d = C0 · C 1 · C2 C 3 · C4 · C5
x3 > x0 > x2 > x1 x3 > x0 > x1 > x2
C1e = C 0 · C 1 · C2 · C3 · C4 · C5 C1f = C 0 · C 1 · C2 C 3 · C4 · C5
x2 > x3 > x1 > x0 x2 > x3 > x0 > x1
C1g = C0 · C1 · C2 · C3 · C4 · C 5 C1h = C 0 · C1 · C2 · C3 · C4 · C 5
x2 > x1 > x3 > x0 x2 > x1 > x0 > x3
C1i = C0 · C1 · C2 · C3 · C 4 · C 5 C1j = C0 · C1 · C 2 · C3 · C 4 · C 5
x2 > x0 > x3 > x1 x2 > x0 > x1 > x3
C1k = C 0 · C1 · C 2 · C3 · C4 · C 5 C1l = C 0 · C1 · C 2 · C3 · C 4 · C 5
x1 > x3 > x2 > x0 x1 > x3 > x0 > x2
C1m = C0 · C1 · C2 · C 3 · C 4 · C5 C1n = C0 · C 1 · C2 · C 3 · C 4 · C5
x1 > x2 > x3 > x0 x1 > x2 > x0 > x3
C1o = C0 · C1 · C2 · C 3 · C 4 · C 5 C1p = C0 · C1 · C 2 · C 3 · C 4 · C 5
x1 > x0 > x3 > x2 x1 > x0 > x2 > x3
C1q = C0 · C 1 · C 2 · C 3 · C 4 · C5 C1r = C0 · C 1 · C 2 · C 3 · C 4 · C 5
x0 > x3 > x2 > x1 x0 > x3 > x1 > x2
C1s = C 0 · C 1 · C 2 · C3 · C4 · C5 C1t = C 0 · C 1 · C 2 · C 3 · C4 · C5
x0 > x2 > x3 > x1 x0 > x2 > x1 > x3
C1u = C 0 · C 1 · C 2 · C3 · C4 · C 5 C1v = C 0 · C 1 · C 2 · C3 · C 4 · C 5
x0 > x1 > x3 > x2 x0 > x1 > x2 > x3
C1w = C 0 · C 1 · C 2 · C 3 · C 4 · C5 C1x = C 0 · C 1 · C 2 · C 3 · C 4 · C 5

given element being the minimum. The total number of possible

combinations is then 6 × 4, or 24.
The circuit diagram of the Min block is depicted in Fig-
ure 5.89(b). There is no connection between the Cx0 input and
any of the encoder gates because all inputs are in the logic low
state when the 00 code is selected. It is assumed that only one
of the Boolean functions, Cx0 , Cx1 , Cx2 , or Cx3 , can be set to
the logic high state at a time. Following the design process of
combinational logic circuits, each of the Boolean expressions,
Cx0 , Cx1 , Cx2 , and Cx3 , whose logic state can be related to the
Delta-Sigma Data Converters 275

1 1
sv
0 0 3

1 1
sv 2
0 0

1 1
sv
0 0 1

1 1
sv
0 0 0

C 1a v0 v1 v2 v3 C 1b v1 v0 v2 v3 C 1x v3 v2 v1 v0

FIGURE 5.90
Implementation of the vector quantizer for a DAC with four unit elements.

fact that the corresponding element is minimum or not, can be

derived as shown in Table 5.3.
To design the vector quantizer, the occurrence condition for each
of the possible combinations of the vector elements to be sorted
is translated into a Boolean expression. The block diagram of
the vector quantizer is shown in Figure 5.90. It consists of four
2-to-1 multiplexers and 24 decoders followed by tri-state buffers.
The use of tri-state buffers allows all decoders to share the same
output line. Table 5.4 summarizes the Boolean functions used
as control signals in the vector quantizer.

In practice, the implementation of DACs based on the vector-feedback ESL

can be affected by the stability problems of high-order modulator loops and
is limited to resolutions less than 4 bits due to the high number of logic gates
(e.g., (B − 1)! digital comparators and (B − 1)! × B decoders for a resolution
of B bits) required by the vector quantizer.

5.3.2 Data-weighted averaging technique

Data-weighted averaging (DWA) algorithms equally select the DAC elements
taking part in the data conversion, such that matching errors average to zero
over a given time period. The re-selection of a given element is possible only
276 Data Converters, Phase-Locked Loops, and Their Applications

after the choice of all the others. As a consequence, the processing of consec-
utive input codes should require different DAC units.
Assuming that the deviation from the nominal value of the i-th unit ele-
ments of the DAC is denoted by ǫi , we have
I
X
ǫi = 0 (5.293)
i=1

where I is the number of elements. A given input code, which can be written
as
X = qI + r, 0 ≤ r < I (5.294)
where q and r are two integers, is converted with the mismatch error
I
X J
X
∆X = q ǫi + bi ǫi (5.295)
i=1 i=1
J
X
= bi ǫi (5.296)
i=1
PJ
Here, i=1 bi = r and bi is either 0 or 1. To reduce the effect of the residual
error term on the converter performance, it is advisable to choose bi randomly.
The result of the conversion is obtained by adding the DAC codes at
successive time instants, k (k = 0, 1, · · · , K). That is, ∆X is written in the
z-domain as the product of the error associated with the initial DAC code
and the function 1 + z −1 + · · · + z −K , which can be approximated by 1 − z −1
for large K. The error caused by mismatch is then first-order shaped.
The block diagram of the N -bit ∆Σ modulator depicted in Figure 5.91 in-
cludes a DWA circuit [34], which can reject the tones caused by mismatches of
the DAC unit elements out of the baseband. The DWA implementation of Fig-
ure 5.92 consists of an adder, a shift register, binary-to-thermometer encoders,
AND and exclusive-OR gates, inverters, and multiplexers. The number of unit
elements actually required is N = K +L, where K and L are the number of el-
ements assuming an ideal DAC and the number of additional elements due to
the DWA, respectively. Note that the value of L determines the noise-shaping
performance of the DWA technique. For a 4-bit modulator, N can be chosen
to be 15 + 1. The binary-to-thermometer decoder should have 16 outputs and
the last one can be maintained at the low state.

5.3.2.1 Element selection logic based on a tree structure and but-

terfly shuffler
Assuming a 3-bit (or eight-element) DAC, Figures 5.93 and 5.94 show the
block diagrams of the element selection logic (ESL) or encoder based on a tree
structure and butterfly shuffler, respectively. In both schemes, the number of
unit elements is given by 2N , and the switching section comprises log2 (N )
layers, where N is the number of bits.
Delta-Sigma Data Converters 277
CK

Analog Discrete−time N−bit Digital Digital

input T/H Σ output
filter quantizer filter

N−bit DWA
DAC circuit

FIGURE 5.91
Block diagram of an N -bit delta-sigma modulator including a DWA circuit.

N Load
Sum N
From Σ Register
N CK
modulator Carry
output Clear

Binary−to Binary−to
thermometer thermometer
encoder encoder
CK
Select

0 1 0 1 0 1
MUX

Y1 Y2 Y2N

To DAC unit elements

FIGURE 5.92
A digital implementation of the data-weighted averaging technique.
C 31 C 21 C 11
1
1
2
C 11
Thermometer encoder

2 1
3 C 21 1
C 32 C 22 C 12
3 C 12
In Out In Out
1 C 33 C 23 C 13
1
0 C 31 3 1
2
C 13

2 1
C 22 1

C 14 C 34 C 24 C 14

Layer 3 Layer 2 Layer 1 Layer 3 Layer 2 Layer 1

FIGURE 5.93 FIGURE 5.94

Tree-structured ESL. Butterfly shuffler ESL.

• For the approach based on a tree structure, a combination of the N -bit

binary code to be converted and a zero, which represents the first bit (LSB)
278 Data Converters, Phase-Locked Loops, and Their Applications
k−1

0 LSB
1 k
1 Out1 SL
k+1
In 1 s
q D Q
0 LSB 1
SL
k CK E Q
CK q 1 Out2
r s
(a)
E Q q
r 1 2
0 1 D Q q
1 Out1 0
In1 1
In2
1 s
(c)
q 0
SL 1
Out2
CK q 1

(b) r

FIGURE 5.95
Circuit diagram of a switching block with (a) (k + 1)-bit and (b) 2-bit input
words; (c) implementation of the selection logic (SL).
E
E
E DI 1
DI D Q D Q
0
CK Q CK Q

FIGURE 5.96
Circuit diagram of D flip-flops with enable.

of the input data, is applied to the encoder. This latter consists of 2N − 1

switching blocks, the operation of which is equivalent to signal processing
functions of the form
xij + Cij
y1ij = (5.297)
2
xij − Cij
y2ij = (5.298)
2

where xij and ykij (k = 1, 2) are the input and output signals, respectively,
and Cij denotes the difference between the top and bottom outputs of the
switching block j on the layer i. To simplify the hardware implementa-
tion, other definitions, which satisfy the number conservation rule, may be
adopted for switching function. It can be assumed, for instance, that
(
0 if xij is even
Cij = (5.299)
±1 if xij is odd.

The operation of the encoder is equivalent to an N -to-2N transformation

Delta-Sigma Data Converters 279

followed by a scrambling. By processing an input with (k + 1)-bits, the

switching block provides two k-bit outputs.
• The butterfly shuffler ESL can only operate with an even number of DAC
unit elements. It can be composed of a thermometer encoder, which achieves
the N -to-2N conversion, and a selection stage consisting of N 2N −1 cells
called swappers or switching blocks, which can be described as follows:
xij ij
1 + x2 xij − xij
y1ij = + Cij 1 2
(5.300)
2 2
x + xij
ij
xij − xij
y2ij = 1 2
− Cij 1 2
(5.301)
2 2
where xij ij
k and yk (k = 1, 2) are the input and output signals, respectively;
i denotes the layer number; and j represents the position of the swapper in
the layer. Depending on the level of the signal Cij , the switching block may
either pass the inputs directly to the corresponding outputs or assign the
inputs in reverse of the outputs on each clock cycle. The butterfly shuffler
ESL (see Figure 5.94) can perform efficiently even if it allows only a selected
set of connections. It should be noted that the association of each of the
N inputs to all possible N outputs, would require a digital encoder with N
factorial paths, or a large die area.
The resulting noise of the DAC is a linear combination of the data, Cij ,
with weighting factors, which are linearly related to the unit element errors.
As long as each selection logic shapes Cij by a specific transfer function, the
static errors introduced by the element mismatch in the DAC will also be
modeled in the same way.
For a (k + 1)-bit input word, the switching block can be implemented, as
shown in Figure 5.95(a). The (k + 1)-bit input word is split into the upper
k − 1 bits and the lower 2 bits, which are used to appropriately assign the least
significant bit (LSB) of the output data. When the length of the input word
becomes equal to 2 bits, the switching block can be realized using the structure
of Figure 5.95(b). For a first-order mismatch shaping, the selection logic (SL)
can be designed, as illustrated in Figure 5.95(c) [35–37]. The D flip-flops are
enabled by the parity signal, s, provided by the XOR gate connected to the
2 LSBs of the input code, and the clock frequency is fixed at the data rate.
The dither signal, r, which is delivered by a pseudo-random noise generator
(or linear feedback shift register) whose output assumes the values 0 or 1 with
the same likelihood and is used to eliminate spurious tones in the DAC output
spectrum, should be uncorrelated with the input code. The selection sequence
is determined by the output signals (Q and Q) of the second D flip-flop. The
circuit diagram of D flip-flops with enable is shown in Figure 5.96. A logical 1
at the enable node E allows the transfer of the data D to the flip-flop, and the
truth table of the overall structure is then similar to the one of a conventional
D-flip-flop. The previous state of the flip-flop is maintained in the cases where
E = 0.
280 Data Converters, Phase-Locked Loops, and Their Applications

It should be noted that a tree-structured DEM DAC seems to offer a more

efficient hardware implementation in the case of high-order mismatch shaping
functions than a butterfly shuffler DEM DAC.

5.3.2.2 Generalized DWA structure

In comparison with other DEM approaches, the DWA technique [38, 39] is
mainly used because it offers a suitable trade-off between hardware complexity
and mismatch noise attenuation performance. The reduction of the hardware
complexity, and therefore the delay that can be introduced in the delta-sigma
modulator feedback path by the DWA circuit, proves essential in meeting
high-frequency specifications.

Σ z −D

Rseq
1 N
Element
Dir
Shift

#1
Thermometer encoder

Barrel shifter

N
Digital N 2 Analog
input Σ
input
Element
#2 N−1

Element
#2 N

FIGURE 5.97
Generalized structure for DWA implementations.

A generalized structure that can be used for the implementation of var-

ious DWA algorithms is shown in Figure 5.97, where N denotes the DAC
bit resolution, and the sequence Rseq can follow any arbitrary repeating ±1
pattern of length D. It must use modulo-N arithmetic in order to satisfy the
requirement to limit the selection data range from 0 to N − 1.
In particular for a 3-bit DAC, the barrel shifter can be realized as depicted
in Figure 5.98. It operates as a reversible rotator and should involve CMOS
switches with dual supply voltages (VDD and VSS ).
By configuring the generalized DWA structure to realize a mismatch shap-
ing transfer function, H(z), of the form

H(z) = 1 + z −D (5.302)

where D is a positive integer, the term of the required Rseq sequence can, for
instance, be defined by the formula, Rseq(k) = (−1)⌈k/D⌉ , where ⌈x⌉ is the
smallest integer not less than x. For the implementation of

H(z) = 1 − z −D (5.303)
Delta-Sigma Data Converters 281
Dir Shift 2 Shift1 Shift 0

1
1 RT0
1 0
1 0
1 0
0 1
T0 0 1 RT1
1 0
1 0
1 0
0 1
T1 0 1 RT
2
1 0
1 0
1 0
0 1
T2 0 1 RT
3
1 0
1 0
1 0
0 1
T3 0 1 RT
4
1 0
1 0
1 0
0 1
T4 0 1 RT
5
1 0
1 0
1 0
0 1
T5 0 1 RT
6
1 0
1 0
1 0
0 1
T6 0 1 RT
7
1 0
1 0
1 0
0
T7 0

FIGURE 5.98
Circuit diagram of an 8-input barrel shifter.

the term of the Rseq sequence can be chosen as Rseq(k) = 1, for k > 0.

Known implementations of DWA algorithms use various values of D. For

lowpass delta-sigma modulators, a conventional DWA circuit based on the
transfer function given by, H(z) = 1−z −1, provides a high-pass shaping of the
DAC mismatch noise. However, its performance may be limited by spurious
tones. A method to reduce the effect of these spurious tones consists of using
DWA algorithms with bi-directional rotation of unit elements.
On the other hand, DWA algorithms can also be used to improve the linear-
ity of bandpass delta-sigma modulators with a multi-bit DAC. In a bandpass
modulator that has center frequency at fs /4, the shaping transfer function
can be chosen as, H(z) = 1 − z −4 , and has notch frequencies at dc, ±fs /4,
and ±fs /2, where fs is the sampling frequency. The extra notch frequencies
(at dc and fs /2) due to the term 1 − z −2 in the shaping transfer function help
de-correlate the mismatch error from the input code, thereby leading to an
attenuation of spurious tones, but at a price of an increased mismatch noise
floor.
By selecting the shaping transfer function as H(z) = 1 + z −2 , the notch
frequencies are only located at ±fs /4, and the resulting DWA circuit for the
282 Data Converters, Phase-Locked Loops, and Their Applications

bandpass delta-sigma modulator can suppress the mismatch noise in the band
of interest. A DAC with the 1+z −2 shaping transfer function does not substan-
tially contribute to spurious tones in the output frequency spectrum, especially
in the implementation of quadrature bandpass modulators.

5.4 Data converter testing and characterization

Power
supply
Pattern Logic−state
generator analyzer
Data Converter
under test
Frequency Spectrum
synthesizer analyzer
Clock
generator

FIGURE 5.99
Block diagram of a test setup.

The performance of data converters can be characterized by static and

dynamic parameters. Static linearity, which can be obtained by comparing the
ideal and real transfer characteristics of the converter, is generally specified
through DNL and INL errors. The analysis of the converter output samples
can also provide dynamic measures such as signal-to-noise ratio (SNR), signal-
to-noise and distortion (SINAD), effective number of bits (ENOB), spurious-
free dynamic range (SFDR), and harmonic distortions. The data converter
testing [40–42] is achieved by means of microprocessor-based instrumentation
due to the complexity of the required signal processing algorithms. A typical
test setup for a data converter is shown in Figure 5.99. The following analysis
methods can be used for the converter characterization.

5.4.1 Histogram-based testing

As shown in Figure 5.100, the histogram of an ideal ADC processing a dc
signal consists of equal-sized bins for all output codes. When the converter
transfer characteristic exhibits a nonlinearity, the bins will not have the same
size due to the fact that some output codes occur more frequently than others.
Generally, a periodic input sequence is applied to the ADC. The output data
are collected as a series of records, each of which contains a given number of
samples. They are represented in the form of a normalized histogram or code
density showing the occurrence frequency of each converter code. The con-
Delta-Sigma Data Converters 283

verter characteristics can then be determined by comparing the code density

data to the ideal distribution density function. In the absence of offset errors,
for instance, the histogram should be symmetrical. Gain deviations affect the
histogram width. A zero occurrence is the result of a missing code. Note that
a large spike generally corresponds to a high DNL.
Let Λi be the number of occurrences of code i, ΛT be the total number
of samples, and P (i) be the occurrence probability of code i or the bin width
of the ideal converter. The next definitions can be adopted for the DNL and
INL expressed in LSBs:
Λi
DN L(i) = −1 (5.304)
ΛT P (i)
DN L = max|DN L(i)| (5.305)

i
X
IN L(i) = DNL(j) (5.306)
j=1

IN L = max|IN L(i)| (5.307)

where i = 0, 1, · · · , 2B+1 − 2. Note that the definition of the DNL cannot be

applied to the last code and Λi /ΛT is the histogram bin width of the converter
under test (Λi is the number of occurrences of each code i and ΛT denotes
the total number of acquired codes). If the signal applied to the converter is
assumed to be a sinusoid of the form

x = A sin(2πf t) (5.308)

the probability density function is given by4

1
pX (x) = √ (5.309)
π A2 − x2
where A denotes the amplitude. The parameter P for a given input sample is
defined as Z Vi+1
P (i) = pX (x)dx (5.310)
Vi

4 Let X = Φ(Θ) = A sin(Θ). With θ = Φ−1 (x), the probability density function (pdf) is
derived from the following expression,
dθ
pX (x) = pΘ (θ)
dx
where the phase, Θ, of the sine wave is assumed to be a random variable uniformly dis-
tributed between −π/2 and +π/2 with the pdf given by
(
1
if θ ∈ (− π2 , + π2 )
pΘ (θ) = π
0 otherwise.
284 Data Converters, Phase-Locked Loops, and Their Applications
Output
code

LSB

Occurrence j−1 j j+1 V j−1 Vj V j+1

Output code Input voltage
(a)
Output
code

LSB
Occurrence

Sj

j−1 j j+1 V j−1 V j V j+1

Output code Input voltage
(b)

FIGURE 5.100
Correspondence between the histogram and ADC transfer characteristic: (a)
Ideal case, (b) nonideal case.

where Vi and Vi+1 are the lower and higher transition levels, respectively. That
is,     
1 Vi+1 Vi
P (i) = arcsin − arcsin (5.311)
π A A
Taking the cosine of both sides of the above relation and using trigonometric
relations,5 we can obtain
2
 
Vi+1 − [2Vi cos(πP (i))] Vi+1 + Vi2 − A2 1 − cos2 (πP (i)) = 0 (5.312)
This quadratic equation can be solved for Vi+1 . As a result,
q
Vi+1 = Vi cos(πP (i)) + sin(πP (i)) A2 − Vi2 (5.313)

where only the positive square root was retained so that Vi+1 can be greater
than Vi . With the assumption that the first decision level is fixed at −A, the
other decision levels can be computed as
 
πΣΛi
Vi+1 = −A cos (5.314)
ΛT
5 Given two numbers x and y,
cos(x − y) = cos(x) cos(y) + sin(x) sin(y)
and p
cos(arcsin(x)) = 1 − x2
Delta-Sigma Data Converters 285

where P is replaced by the measured frequency of occurrence, ΣΛi /ΛT , and

ΣΛi denotes the total number of codes included in the bins 1 through i. A
missing code corresponds to a DNL equal to −1. The record length and ratio
of the sampling rate to the signal frequency are chosen so that dynamic errors
(in-phase distortion, information redundancy, etc.) are negligible.

5.4.2 Spectral analysis method

Fast Fourier transform data are used to characterize linearity and noise prop-
erties of the ADC in the frequency domain. The output provided by an ADC,
which processes a sine-wave signal, comprises a tone at the input frequency,
harmonics, spurious components, dc offset, and a broadband term character-
izing the different kinds of noise. The power estimation of each narrowband
component can be affected by the energy leaking from neighboring tones. A
solution can then consist of using a suitable window function prior to the
Fourier transform. The next parameters can be deduced from the spectrum
data.

• The SNR is a measure of the broadband noise introduced by the converting

and sampling process into the signal band. It is the ratio of the root-mean
square (rms) value or power of the output signal to the one of the sum
of all other frequency components below the Nyquist rate, except those
representing dc and harmonics of the fundamental.

• The dynamic range (DR) is the ratio of the rms value of a full-scale sinusoidal
input signal to the rms noise delivered by the converter with inputs shorted
together. It is limited by the Nyquist frequency.

• The total harmonic distortion (THD) is the ratio of the fundamental to the
sum of the harmonics, which can be identified from the noise floor. It can
also be expressed as a percentage.

• The SINAD6 is the ratio of the power in the fundamental frequency bin
to that in all other bins, including harmonics. It can also be computed as
(SNR2 + THD2 )1/2 .

• The SFDR is the difference in rms magnitudes of the fundamental and the
highest spur, which is not due to dc offset.

In another approach to performing a spectral analysis of the converter, the

input signal is assumed to be the sum of two sine waves with the same am-
plitude, and frequencies equal to f1 and f2 , respectively. The intermodulation
distortion (IMD) provides the ratio of the rms sum of intermodulation com-
ponents at frequencies if1 ± jf2 in the spectrum to the rms value of the input
signal, where i and j are integers different from zero. The intermodulation
6 The SINAD is also known as signal-to-noise and distortion ratio (SNDR).
286 Data Converters, Phase-Locked Loops, and Their Applications

order is given by i + j. In a practical implementation, the spectral leakage is

eliminated either by assuming a coherent relationship between the sampling
frequency, fs , and input frequencies, that is, m/fs = m1 /f1 = m2 /f2 , where
the integers m1 and m, and m2 and m are, respectively, prime of each other,
or by applying a filtering window such as the Blackmann Harris function to
the data.
The noise power test, as shown in Figure 5.101, consists of analyzing the
output samples delivered by a converter, which processes a limited band of
white noise provided by a generator. The Fourier transform is used to evaluate
the noise power ratio (NPR), which is the measure of all contributed errors in
the frequency domain. However, the fundamental frequency and dc offset are
discarded in the computation. The ENOB can be written as

1 NPR
ENOB = N − log2 2 (5.315)
2 σQ

2
where N is the number of bits of the converter and σQ denotes the theoretical
quantization noise.

Noise Lowpass Spectrum

ADC
generator filter analyzer
Notch
filter

(a)

A0 A0
Amplitude

Amplitude

NPR

0 fB 0 fB
Frequency Frequency
(b) (c)

FIGURE 5.101
(a) NPR test setup; (b) signal spectrum at the output of the notch filter; (c)
output signal spectrum of the ADC.

Dynamic specifications are generally expressed in decibels (dB). However,

they can be referenced to the converter FSR, which is constant, before being
transformed into decibels. This results in parameters, whose unit is dBFS, or
decibels relative to full-scale.

5.4.3 Walsh transform-based transfer function estimation

The transfer function of an N -bit converter can be represented as the sum of
a given number of Walsh functions adequately weighted by the Walsh coeffi-
cients. These latter can be obtained by reconstructing the ADC output data
Delta-Sigma Data Converters 287

using the Walsh transform. To achieve a good resolution, the number of points
considered for the computation should be a power of 2 multiple of 2N . The
comparison of the ideal and real transfer functions can then provide the ADC
error parameters.

5.4.4 Testing using sine-fit algorithms

The ENOB characterization of an ADC, which processes a sampled sine wave,
is carried out by reconstructing the input signal based on the four parameters
(amplitude, frequency, phase, and dc offset) computed from the output data.
The signal samples of the original input are then subtracted from the ones of
the synthesized sine wave to estimate the average noise power. The ENOB at
a given input frequency can then be computed as
 
F SR
ENOB = log2 √ (5.316)
12 · RM SE
where F SR is the full-scale range of the ADC and RM SE is the root-mean
square of the digitized signal or the noise power provided by the test proce-
dure. The achievable accuracy is limited by the convergence performance of
the estimation algorithm, and the validity of the stochastic model is guar-
anteed only for a restricted range of the ratio between the number of ADC
quantization levels and the one of the acquired samples.
Note that a pattern generator instead of a frequency synthesizer is required
for the DAC testing. The ADC, which can be used to deliver a digital version
of the analog output necessary for the different computations, can limit the
speed and precision of the evaluation. To test DAC in the frequency-domain,
the solution can consist of using analog spectrum analysis techniques. The
level of harmonic distortions can then be related to the transfer characteristic
deviations.
Generally, the power consumption of data converters increases with perfor-
mance characteristics such as the dynamic range and bandwidth. The figure-
of-merit (FOM) measures the efficiency with respect to the dissipated power.
It is defined as
DR × BW
FOM = (5.317)
P
where DR and P are the dynamic range and the total power dissipation of
the converter, respectively, and BW is the signal bandwidth.

5.5 Delta-sigma modulator-based oscillator

Generally, the on-chip generation of high-quality signals is required in built-
in self-test structures for mixed-signal circuits. An approach to resolve this
288 Data Converters, Phase-Locked Loops, and Their Applications

problem is to use ∆Σ modulator-based oscillators, which can deliver signals

with a spurious-free dynamic range of about 90 dB.
A ∆Σ modulator-based oscillator consists of a loop including a digital
resonator with poles on the unit circle and an N × N -bit multiplier, which
is implemented by the combination of a ∆Σ modulator with a multiplexer to
reduce the silicon area and timing delay. The 1-bit pattern used to control the
multiplexer switching is available at the output of the ∆Σ modulator, which
should have a unity signal transfer function. It contains the sinusoidal signal
generated by the resonator and the out-of-band quantization noise, which can
be suppressed by a filter. An analog signal can be obtained by cascading a
1-bit DAC with the oscillator.
x1 LP ∆Σ LP
z −1 Out
modulator filter
+

M 0 −k
x2 + U
X
1 +k
z −1

FIGURE 5.102
Lowpass ∆Σ modulator-based oscillator.

Comparator

In Σ + Σ + z −1 Out
− −
z −1

FIGURE 5.103
Block diagram of a second-order lowpass ∆Σ modulator.

The block diagram of a lowpass ∆Σ oscillator [43] is shown in Figure 5.102.

It includes two integrators, a lowpass ∆Σ modulator, and a 2-to-1 multiplexer.
The delay of one clock period introduced on the signal path by the second-
order lowpass ∆Σ modulator shown in Figure 5.103 is compensated for by
using one nondelayed integrator. Let x1 and x2 be the state variables associ-
ated with the output of the first and second integrators, respectively. We can
write

x1 (n) = x1 (n − 1) + x2 (n − 1) (5.318)
x2 (n) = −kx1 (n) + x2 (n − 1) (5.319)

Using the z-transform, X1 and X2 can be eliminated and the next character-
istic equation is derived,

z −2 − (2 − k)z −1 + 1 = 0 (5.320)
Delta-Sigma Data Converters 289

To ensure the oscillation, the roots of the above equation should be conjugate
complex and located on the unit circle. This is the case for 0 < k < 4, and
p
−1 2−k±j k(4 − k)
z1,2 = (5.321)
2
The angular frequency of oscillation, ω0 , can then be related to the coefficient,
k, and the period of the clock signal, T , according to
p
k(4 − k)
tan(ω0 T ) = ± (5.322)
2−k

x2

z −1
l
− x1 BP ∆Σ LP
Σ Out
modulator filter

z −1

M 0 −k
+ U
X
1 +k

FIGURE 5.104
Bandpass ∆Σ modulator-based oscillator.

Comparator

In + Out

+
Σ

−2 −1

z −1 z −1 z −1 z −1 +

−2 −1 2 −8 −1

FIGURE 5.105
Block diagram of a fourth-order bandpass ∆Σ modulator.

A bandpass ∆Σ oscillator [44], as shown in Figure 5.104, offers the ad-

vantage of possessing a greater usable bandwidth while operating at a sample
rate comparable to that of a lowpass structure. It uses two registers (blocks
denoted by z −1 ) included in a loop with a multiplier (coefficient l), a band-
pass ∆Σ modulator, and a 2-to-1 multiplexer. Figure 5.105 shows the block
290 Data Converters, Phase-Locked Loops, and Their Applications

diagram of a fourth-order bandpass ∆Σ modulator with a signal transfer func-

tion equal to 1, such that the signal level is not modified. By inspection of the
oscillator, we can derive

x1 (n) = −x2 (n − 1) + lx1 (n − 1) − kx1 (n − 1) (5.323)

x2 (n) = x1 (n − 1) (5.324)

where x1 and x2 denote the state variables of the register outputs. These last
equations can be transformed to the z-domain as

z −2 + (k − l)z −1 + 1 = 0 (5.325)

Solving for z −1 , the roots of the characteristic equation (5.325) are given by
p
−1 l − k ± j 4 − (k − l)2
z1,2 = (5.326)
2
where |k − l| < 2. Hence, the oscillation frequency can be obtained from the
next expression, p
4 − (k − l)2
tan(ω0 T ) = ± (5.327)
l−k
The multiplication coefficient l can be chosen to be a power of 2 to reduce the
hardware complexity. Further reduction is achieved for l = 0.
For both oscillator structures, a discrete-time sinusoidal signal of the form

x(n) = A sin(ω0 T n + φ) (5.328)

can be obtained at the node labeled x1 . The amplitude A and the phase φ are
dependent on the coefficient k (and l), and the initial conditions, I1 and I2 ,
of the first and second registers.

Principles of time division multiplexing [45] can be exploited for the gen-
eration of two-tone signals. This is realized by replacing the 2-to-1 multiplexer
with a 4-to-1 multiplexer and each register with a pair of registers. As a result,
the effective clock frequency is divided by a factor of two.

5.6 Digital signal processor interfacing with data con-

verters
Due to the difference of processing speed and electrical characteristics ex-
isting between input/output (I/O) devices, such as data converters, and the
computer processing unit (CPU) of a microprocessor (digital signal proces-
sor (DSP), micro-controller), interface chips are required to synchronize data
Delta-Sigma Data Converters 291

transfer between the CPU and I/O devices. Generally, an interface chip is
composed of control registers, data registers, status registers, data direction
registers, and control circuit [46]. Control registers include data bits, whose
states determine the parameters of the I/O operation. The data transfer di-
rection for each I/O pin is set by the corresponding bit of the data direction
registers. The data register is used as a buffer to temporarily store the data
being transferred to or from the CPU. The status registers store bits provid-
ing information on the progression of the I/O operation. Because access to
the data bus is allowed to only one I/O device at a time, an address decoder
is used to generate chip-select or chip-enable signals for each device at the
request of the microprocessor.
The data transfer between the microprocessor and I/O devices can be ei-
ther parallel or serial. Parallel communications are based on the use of several
wires to simultaneously transmit data. Serial communications involve trans-
mitting digital data, sequentially, over only one wire. To achieve a high trans-
fer speed, parallel data transmissions are preferred, while serial links are the
better option when the interconnection hardware overhead should be kept
minimal.
Due to the typical speed difference between the microprocessor and I/O
devices, a synchronization mechanism is required for proper data transmission.
Various types of synchronization can be used to interface I/O devices.
A simple synchronization technique is to design the software such that it
can initiate the communication and then wait a fixed amount of time for the
I/O operation to complete. This method is known as blind cycle counting
because it provides no information about the outcome of the I/O operation
back to the microprocessor.
In the gadfly or busy waiting approach, the software routine includes loops
that can check the I/O status until the completion of data transfer. This
approach is suitable only for I/O operations with a small wait time.
The periodic polling is based on the principle of continually checking the
status of the I/O operation to detect whether it is complete. By continuously
monitoring the status register, the microprocessor can notice the end of the
data transfer. It can then retrieve data and proceed further according to the
programmed instructions.
The interrupt technique requires more complex hardware and software, but
has the advantage of efficiently using the microprocessor CPU. An interrupt
request is generated either when the I/O device is ready or to acknowledge
a successful data transfer. As a result, the CPU forces a branch-out of the
current program sequence to the appropriate interrupt service routine (ISR).
Prior to the transfer of the control to the ISR, the CPU state must be saved
on the stack. This is necessary because the program execution should resume
after returning from the ISR. However, the achievable response time may be
limited due to the microprocessor latency time (the time elapsed between the
generation of an interrupt request and the servicing of the corresponding I/O
device).
292 Data Converters, Phase-Locked Loops, and Their Applications

Another I/O synchronization technique is based on direct memory access

(DMA). DMA controllers can transfer data from I/O devices directly to the
main memory, and vice versa, without the intervention of the CPU. They
can generate an address sequence to access blocks of data and manage access
priorities. Here, the load of the CPU is reduced and a higher data throughput
can be achieved by manipulating data blocks.
Data in
(parallel)

bN b2 b1

M M M
U D Q U D Q U D Q Data out
X X X (serial)
Q Q Q

CK
Load
(a)

Data out
(parallel)

bN b2 b
1

Data in D Q D Q D Q
(serial)
Q Q Q

CK
(b)

FIGURE 5.106
(a) Parallel-to-serial converter; (b) serial-to-parallel converter.

CK

RESET

WR

ID[0:N]

SCK

SD D0 D1 D2 DN

BUSY

FIGURE 5.107
Timing waveforms for the parallel-to-serial converter.

Interfacing a DSP with data converters involves both physical connections

and software routines that steer the transmission of data. Data converters used
in the interface implementation should exhibit more flexibility. This is achieved
using a set of on-chip registers to achieve programmability and control the data
flow. The write (WR) and read (RD) operation of each register is determined
Delta-Sigma Data Converters 293

by a given signal. The communication between a digital signal processor (DSP)

and data converters can be done either in parallel or serially [47]. A DSP with
only one type (parallel or serial) of port can still communicate with any I/O
device, provided data can be converted from parallel to serial form, and vice
versa. Figures 5.106(a) and (b) show the circuit diagrams, which realize the
parallel-to-serial and serial-to-parallel transformation, respectively. The first
structure uses time-division multiplexing for the placement of N -bit input data
in a single channel, while the second structure relies on the delay, which can be
introduced on a data stream by shift registers. Note that various architectures
are available for the same interface type, which is efficiently implemented as
a combination of hardware and software.
It should be noted that the above converters include additional input and
output nodes in a data acquisition environment. The timing waveforms are
shown in Figure 5.107 for the specific case of the parallel-to-serial converter.
After the initialization step steered by the RESET signal, the input data
ID[0 : N ] are applied to the circuit and the write (WR) pulse is enabled. The
signal BUSY changes to the high level and data are transferred one bit after
the other to the serial output (SD) under control of the clock signal (CK).
The initiation and end of the transmission are detected from the information
in SCK, which is an inverted version of CK.

5.6.1 Parallel interfacing

Address
Decoder
A[0:13]
Logic
IOMS RD WR

IOMS
RD RD CS
DSP WR WR

ADC
D[0:15] B[0:11]

IRQ0 EOC SOC

IRQ1

WR CS
Timer

LD
RD CS
WR
DAC
B[0:11]

FIGURE 5.108
Parallel interfacing of a DSP.
294 Data Converters, Phase-Locked Loops, and Their Applications

The block diagram of a parallel interface implementation for a fixed-point

DSP is depicted in Figure 5.108. Data are transferred between the DSP mem-
ory and ADC outputs (WR operation) or DAC inputs (RD operation) in one
clock period. Due to the short memory access time of high-speed processors,
the data transfer flow must be regulated by programming the DSP to insert
wait-states in the converter access cycle. Alternatively, the DSP can include a
different external input/output memory space (IOMS) for converters or other
nonmemory peripherals. Each data bit requires a pin, as well as the control
signals (WR, RD, and chip select (CS)). The timer must generate an inter-
rupt request (IRQ), which determines the start of the conversion (SOC) of the
ADC or the load of data (LD) into the DAC. The end-of-conversion (EOC)
goes high to indicate that the conversion is complete and ADC output data
are ready to be read.
The converter resolution can be lower than the one of the DSP data bus.
The appropriate connection is then determined by the number representation
system. For instance, the right justification of buses is needed for binary cod-
ing, while the left justification provides an adequate transfer in the case of
two’s complement representations. This latter situation can be applied to the
interface structure of Figure 5.108, where a 12-bit ADC and 14-bit DAC are
used. The MSB (B11) of the ADC should be joined to D15 down to the LSB
(B0) wired to D4. The DAC inputs must be connected to the data bus starting
from B13 to D15 through B0 to D2.
Parallel interfacing has the advantage of higher transfer speed, but it re-
sults in a chip package with a high number of pins.

5.6.2 Serial interfacing

By serially interfacing a DSP, the number of pins can be reduced. This ap-
proach is constrained by the requirement that the transfer rate must be greater
than the required data bandwidth. Various serial protocols based on different
bit encoding and basic packet structure are available for the communication
between the DSP and data converters. Serial ports (SPORTs) can be used
to transmit or receive data words of length 4 to 16 bits. A DSP is able to
communicate in both directions simultaneously, that is, in full duplex mode.
In contrast to microcontrollers, DSPs use a frame sync (FS) signal to indicate
the beginning of the data stream and can operate with a continuous serial
clock (SCK) signal together with FS pulses. For a microcontroller, the data
transfer takes place with respect to the SCK signal, which must be active. The
data synchronization can be conducted either by the DSP or data converters,
but it is often convenient to have the sample timing being determined by the
ADC and DAC.
The block diagram of a serial interface is shown in Figure 5.109. The DSP
features pins corresponding to the data receive (DR), data transmit (DT),
receive frame sync (RFS), and transmit frame sync (RFS) operations. Before
the start of the transfer, synchronization pulses must be generated on the
Delta-Sigma Data Converters 295

Address
Decoder
A[0:13] Logic
IOMS WR RD

IOMS
WR
DSP RD
WR CS
Timer
D[0:15]

IRQ0

IRQ1

RFS DR SCK TFS DT

EOC CS LD
SCK SCK

SDO ADC SDI DAC

SDOFS SDOFS

FIGURE 5.109
Serial interfacing of a DSP.

corresponding pin. When the SPORT is enabled, the digital data from the
ADC are sent out on the serial data output (SDO) pin, and the ones from
the serial data input (SDI) pin are transmitted to the DAC. The EOC flag
is raised at the end of the analog-to-digital conversion and can be reset to
account for the DSP interrupt signal. The timer is used to generate the chip
select (CS) and DAC load (LD) inputs.

5.7 Built-in self-test structures for data converters

Due to the increase in circuit complexity, testing is becoming an integral part
of the integrated circuit design. Built-in self-test (BIST) structures provide
the advantage of reducing the test cost and improving the testing accuracy in
high-density circuits.
BIST structures based on code density test principles can be used to de-
termine low-frequency spectral characteristics of data converters [48, 49]. The
generation of the test signal can rely on the use of pattern memory and a DAC.
To reduce the required chip area, the digital version of the signal, which is
available at the memory output, is transformed into an analog waveform by
a 1-bit DAC, whose linearity is generally excellent. Thus, the quality of the
signal is primarily determined by the number of samples, which is bounded
by the memory size. By using a linear ramp as a test stimulus, the code width
associated with the converter output signal can be computed. The number of
296 Data Converters, Phase-Locked Loops, and Their Applications

occurrences in each bin should be equal in the ideal case, and any deviation can
be related to the imperfection of a practical converter. The DNL for a given
input sample is derived by subtracting the ideal code width from the measured
code width. The sum of the DNL from the first up to the current code is equal
to the INL. The accuracy of the DNL and INL determination is limited by
the noise and quantization errors to about 0.05 LSB. For data converters em-
bedded in a mixed-signal circuit, including a digital signal processor (DSP),
the self-test program and test data can be stored in the read-only memory
(ROM) and random access memory (RAM). However, BIST structures using
logic gates can feature a low area and a high speed.

In D 0 Out
M
ADC U
X 1
Input test pattern generator
DSP
1−bit pattern 1−bit Control
LPF RAM TDO
memory DAC CK logic
R0M

FIGURE 5.110
BIST structure for ADCs.

Input test pattern generator

1−bit pattern 1−bit

LPF
memory DAC
DSP
+ Index
Comparator V RAM TDO
− counter
R0M

In 0 M
U DAC
1 X
Out

CK Counter

Control
logic Inc

FIGURE 5.111
BIST structure for DACs.

The block diagram of the BIST structure for the ADC is shown in Fig-
ure 5.110, where CK is the clock signal and TDO is the test data output. It
consists of an input test generator including a pattern memory, a 1-bit DAC
and a lowpass filter (LPF), a control logic, a DSP, and the ADC to be tested.
Let the test pattern be a linear ramp, the magnitude of which is greater than
the full-scale range of the ADC. The output code of the converter can be
written as b2N −1 , b2N −2 , · · · , b0 , where N denotes the number of bits, and
b2N −1 and b0 are the MSB and LSB, respectively. The DNL and INL can
be estimated from the array of 2N − 2 elements obtained by excluding the
MSB and LSB, which correspond to non-doubly bounded input ranges, and
Delta-Sigma Data Converters 297

the occurrence number, Λi , of each code bi . That is,

Λi
DNLi = −1 (5.329)
Λ
and 
 0 if i = 0
INLi = DNLi + DNLi−1 (5.330)
 INLi−1 + otherwise,
2
where
N
2X −2
Λi
i=1
Λ= (5.331)
2N − 2
The above static parameters can be expressed as a fraction of the LSB.

V N
2 −1

V2
V1

V0

Inc

t0
t1
t 2N −1

FIGURE 5.112
Operation principle of a DAC BIST structure.

The BIST architecture for the DAC, as shown in Figure 5.111, includes a
test pattern generator, a counter for digital code generation, an analog com-
parator, an index counter, a DSP, a control logic, and the circuit under test,
which is a DAC. An analog version of the encoded sawtooth signal stored in
the memory of the pattern generator and the DAC output signal are applied,
respectively, to the positive and negative input nodes of the analog compara-
tor. During the test, the output signal, V , delivered by the analog comparator,
gives an estimation of the magnitude levels associated with the different input
codes of the DAC. It will assume the high or low state if the signal level at V +
is greater or lower than the one at V − . By detecting the rising edge of V , the
control logic can increment the index counter, the content of which represents
298 Data Converters, Phase-Locked Loops, and Their Applications

the different indexes, ti , to be stored in the DSP memory. The DNL and INL
(in fraction of the LSB) of the DAC can be derived as
ti − ti−1
DNLi = −1 (5.332)
Λ
and 
0 if i = 0
INLi = (5.333)
INLi−1 + DNLi otherwise,
where
t2N −1 − t0
Λ= (5.334)
2N − 1
and N is the number of bits of the DAC. Note that i = 1, · · · , 2N − 2 and
INL2N −1 = 0 because the determination of the DAC parameters relies on the
use of a linearized output line, whose support points are located in the first
and last levels of the transfer characteristic.
The BIST performance depends on the quality of the test signal generated
on-chip. Figure 5.112 illustrates the testing principle when the DAC transfer
characteristic is a monotonically increasing function and the levels of the adja-
cent codes are sufficiently separated to be detected by the analog comparator.
In cases where these last requirements are not fulfilled for the codes i and
i + 1, after the estimation of ti , the determination process of the next index
ti+1 should be restarted with the code i + 1 held constant at the DAC input.

5.8 Circuit design assessment

1. Truncation quantizer model

Delta-sigma digital modulators rely on a truncation quantizer to

reduce the number of bits of digital code. The conversion of digital
code x into a truncated version x̂ incurs a quantization error defined
as eQ = x̂ − x.
− Considering the characteristic and quantization error of the trun-
cation quantizer shown in Figure 5.113(a) in the case of the two’s
complement representation, the probability density function is given
by 
1
if − △ < eQ ≤ 0
p(eQ ) = △ (5.335)

0 otherwise.
Show that
Z +∞ Z 0
△
E(eQ ) = eQ p(eQ )deQ = eQ p(eQ )deQ = − (5.336)
−∞ −△ 2
Delta-Sigma Data Converters 299
x^ x^

3∆ 3∆

2∆ 2∆

∆ ∆
−4∆ −3∆ −2∆ −∆ −3∆ −2∆ −∆
x x
∆ 2∆ 3∆ ∆ 2∆ 3∆
−∆ −∆

−2∆ −2∆

−3∆ −3∆

−4∆ −4∆

eQ eQ
∆ ∆

3∆ 3∆
x x
−4∆ −3∆

−∆ −∆
(a) (b)

FIGURE 5.113
Characteristics and errors of a truncation quantizer: (a) Two’s complement
and (b) sign-magnitude representations.

and
Z +∞ Z 0
△2
E(e2Q ) = e2Q p(eQ )deQ = eQ p(eQ )deQ = (5.337)
−∞ −△ 3

Deduce that the variance or power of the quantization noise is of

the form
2 △2
σQ = E(e2Q ) − [E(eQ )]2 = (5.338)
12
where △ is the quantizer step size.
− Suppose now that a sign-magnitude representation is adopted.
The characteristic and quantization error of the truncation quan-
tizer are depicted in Figure 5.113(b) and the probability density
function can be obtained as

 1

 0 ≤ eQ < △ if x < 0

 2△
p(eQ ) = 1 (5.339)

 −△ < eQ ≤ 0 if x ≥ 0

 2△

0 otherwise.

Show that
E(eQ ) = E(eQ )|x<0 + E(eQ )|x≥0 = 0 (5.340)
and
△2
E(e2Q ) = E(e2Q )|x<0 + E(e2Q )|x≥0 = (5.341)
3
300 Data Converters, Phase-Locked Loops, and Their Applications

Deduce that the variance of the quantization noise is of the form

2 5 △2
σQ = {E(e2Q ) − [E(eQ )]2 }|x<0 + {E(e2Q ) − [E(eQ )]2 }|x≥0 =
2 12
(5.342)
where △ is the quantizer step size.
2. Analysis of a second-order DT ∆Σ modulator
Consider the block diagram of the second-order ∆Σ modulator de-
picted in Figure 5.114. The integrator can be implemented such that
I(z) = z −1 /(1 − z −1 ).
Assuming a linear model for the comparator, or in other words,
α1 α2

In Σ I(z) Σ I(z) Out

β1 β2

1−bit
DAC

FIGURE 5.114
Block diagram of a second-order ∆Σ modulator.

Y (z) = qX(z) + EQ (z), where Y is the comparator output, X is

the comparator input, EQ is the quantization noise, and q is the
comparator gain, show that

Y (z) = HS (z)S(z) + HQ (z)EQ (z) (5.343)

where
qα1 α1 z −2
HS (z) = (5.344)
1 + (qβ2 − 2)z −1 + [1 + q(α2 β1 − β2 )]z −2
and
(1 − z −1 )2
HQ (z) = (5.345)
1 + (qβ2 − 2)z −1 + [1 + q(α2 β1 − β2 )]z −2
Let z = ejωT , where T is the clock signal period. Evaluate the
coefficients α1 , α2 , β1 , and β2 in terms of q so that the stability
criterion, |HQ (ω)| < 1.5 for 0 ≤ ωT ≤ π, is fulfilled.
3. State-space representation of a second-order DT modula-
tor
A second-order DT modulator, as shown in Figure 5.115, can be im-
plemented using two switched-capacitor integrators, a comparator,
and a 1-bit DAC. To proceed further, let X(z) = [X1 (z) X2 (z)]T
be the state vector and use a linear quantizer model, that is,
Y (z) = X2 (z) + EQ (z), where EQ (z) is the quantization error.
Delta-Sigma Data Converters 301
EQ

z −1 X1 z −1 X2
US (z) Σ Σ Y(z)
1 − z −1 1 − z −1
Comparator
β2 β1
1−bit
DAC

FIGURE 5.115
Second-order DT modulator.

Assuming that EQ (z) = 0, show that the second-order DT modu-

lator can be described by a state-space representation of the form:

zX(z) = AX(z) + BUS (z) (5.346)

Y (z) = CX(z) + DUS (z) (5.347)

where
   
1 −β2 1
A= B=
1 1 − β1 0 (5.348)
 
C= 0 1 D=0

Verify that tne STF can written as follows:

Y (z)
ST T (z) = = C(zI − A)−1 B + D (5.349)
US (z)
z −2
= (5.350)
1 − (2 − β1 )z −1 + (1 + β2 − β1 )z −2

Assuming that US (z) = 0, show that the state-space representation

of the second-order DT modulator is given by:

zX(z) = AX(z) + BEQ (z) (5.351)

Y (z) = CX(z) + DEQ (z) (5.352)

where
   
1 −β2 −β2
A= B=
1 1 − β1 −β1 (5.353)
 
C= 0 1 D=1
302 Data Converters, Phase-Locked Loops, and Their Applications

Verify that the QNTF can be obtained as follows:

Y (z)
QN T F (z) = = C(zI − A)−1 B + D (5.354)
EQ (z)
(1 − z −1 )2
=
1 − (2 − β1 )z −1 + (1 + β2 − β1 )z −2
(5.355)

Show that the modulator poles are given by

  r
β1 β2
p1 , p2 = 1 − ± j β2 − 1 (5.356)
2 4

Deduce that the modulator poles are exactly located on the unit
circle if the coefficients are chosen as β2 = β1 = 1 or β2 = β1 = 1/2.
An all-pole Butterworth STF with cutoff frequency at 1/4 of the
sampling frequency exhibits the poles: p1 , p2 = 0.375±j0.320. Verify
that the modulator coefficients should be chosen as: β2 = 0.493 and
β1 = 1.250.
4. Second-order modulator with complex poles
Consider the second-order modulators described by the block dia-
grams shown in Figures 5.116 and 5.117.
γ

EQ
β2

1 z −1
S(z) Σ Σ Y(z)
1 − z −1 1 − z −1
β1 Comparator

1−bit
DAC

FIGURE 5.116
Second-order modulator with a feedforward summation.

Assuming that the comparator can be modeled with an additive

quantization noise source and the feedback DAC exhibits a propa-
gation delay of one clock period, show that
Y (z) = HS (z)S(z) + HQ (z)EQ (z) (5.357)
where
Ni (z)
HS (z) = (5.358)
1 − (2 − β1 )z −1 + (1 + γ + β2 − β1 )z −2
Delta-Sigma Data Converters 303
γ

EQ

z −1 1
S(z) Σ Σ Y(z)
1 − z −1 1 − z −1
Comparator
β2 β1

1−bit
DAC

FIGURE 5.117
Second-order modulator with a two feedback paths.

and

(1 − z −1 )2 + γz −2
HQ (z) = (5.359)
1 − (2 − β1 )z −1 + (1 + γ + β2 − β1 )z −2

where HS (z) and HQ (z) are the signal and quantization noise trans-
fer functions, respectively. For the first modulator (i = 1) and we
have N1 (z) = (β2 − β1 )z −1 + β1 , while for the second modulator
(i = 2) and N1 (z) = z −1 .
A second-order transfer function, N (z)/D(z), with a denominator
of the form, D(z) = 1 + a1 z −1 + a2 z −2 , is stable provided that
|a2 | < 1 and −(1 + a2 ) < a1 < 1 + a2 .
Deduce the constraints to be set on the modulator coefficients to
satisfy the stability conditions based on the linear model.
For less in-band noise, the quantization noise transfer function
should have complex zeros.
Determine the range of γ values for which the zeros of the quanti-
zation noise transfer function are complex.
5. Second-order modulator with one-bit and multi-bit quan-
tizers
The second-order delta-sigma modulator of Figure 5.118 is com-
posed of two stages and requires a single-bit and multi-bit quantiz-
ers (comparator and B-bit ADC). Ideally, it can help attenuate the
level of the quantization noise at the output by a factor 2B−1 , where
B is the number of bits, because the output contribution associated
to the quantization error of the comparator is replaced by that of
the B-bit ADC.
The combined latency of the quantizer and the feedback DAC is
modeled as a unit delay in the feedback path. By modeling the
quantization effect due to the comparator and the B-bit ADC as
304 Data Converters, Phase-Locked Loops, and Their Applications
EQ
2

Y2
H 2 (z)

B−bit ADC
EQ
1

1 1 Y1
S(z) z −1 Σ Σ H1 (z) Σ Y(z)
1 − z −1 1 − z −1
Comparator

1−bit
z −1
DAC

FIGURE 5.118
Second-order modulator with one-bit and multi-bit quantizers.

additive noises, EQ1 and EQ2 , that are uniformly distributed and
uncorrelated with the input signal, show that

Y1 (z) = z −1 S(z) + (1 − z −1 )2 EQ1 (z) (5.360)

and

Y2 (z) = Y1 (z) − EQ1 (z) + EQ2 (z)

= z −1 S(z) + EQ2 (z) − (2z −1 − z −2 )EQ1 (z) (5.361)

Verify that the output signal, Y , can be written as

Y (z) = z −1 (H1 (z) + H2 (z))S(z) + H2 (z)EQ2 (z)

(5.362)
+ [(1 − z −1 )2 H1 (z) − (2z −1 − z −2 )H2 (z)]EQ1 (z)

For H1 (z) = 2z −1 − z −2 and H2 (z) = (1 − z −1 )2 show that

Y (z) = z −1 S(z) + (1 − z −1 )2 EQ2 (z) (5.363)

For a 1-kHz sinewave input sampled at 1024 kHz with an oversam-

pling ratio of 64, use simulations to verify that a 1% error in the
pole location of each integrator of the single-bit loop can degrade
the SNR by more than 30 dB if the amplifier dc gain is not greater
than 75 dB and the number of bits, B, exceeds 4.
6. Low-distortion third-order DT modulator
For the feedforward third-order modulator shown in Figure 5.119,
the loop filter transfer function can be expressed as,
3
X X 3
ai z −i
H(z) = −1 i
= ai I i (z) (5.364)
i=1
(1 − z ) i=1
Delta-Sigma Data Converters 305

where
z −1
I(z) = (5.365)
1 − z −1
Verify that the signal and quantization noise transfer functions are,
respectively, given by
Y (z) 1 + H(z)
HS (z) = = =1 (5.366)
S(z) 1 + H(z)

and

Y (z) 1
HQ (z) = = (5.367)
EQ (z) 1 + H(z)

EQ
a3

z −1 z −1 z −1
Y(z) Σ Σ Y(z)
1 − z −1 1 − z −1 1 − z −1
a2 B−bit
ADC

a1

B−bit
DAC

FIGURE 5.119
Feedforward third-order modulator.

EQ
b2

1 z −1 1
S(z) z −1 Σ Σ Y(z)
1 − z −1 1 − z −1 1 − z −1
b1 B−bit
ADC

b0

B−bit
z −1
DAC

FIGURE 5.120
Low-distortion third-order modulator.
Consider the low-distortion third-order modulator of Figure 5.119.
Verify that the signal and quantization noise transfer functions can,
respectively, be expressed as

Y (z) 1 h 1 X2 i
i
HS (z) = = 1+ b i I (z) (5.368)
S(z) 1 + G(z) 1 − z −1 i=1
306 Data Converters, Phase-Locked Loops, and Their Applications

and

Y (z) 1
HQ (z) = = (5.369)
EQ (z) 1 + G(z)

where
1 h X2 i
−1 i
G(z) = b 0 z + b i I (z) (5.370)
1 − z −1 i=1

Using H(z) = G(z), show that

    
a1 1 1 0 b0
a2  = 0 1 1 b1  (5.371)
a3 0 0 1 b2

or, equivalently,

bi = ai − bi−1 for i = 1, 2 (5.372)

b 2 = a3 (5.373)

where
3
X 1
b0 = ai (−1)i+1 = −H(0) = 1 − =1 (5.374)
i=1
HQ (0)

7. Discrete-time to continuous-time transformation

A ∆Σ modulator can be designed to process either a continuous-
time or discrete-time signal, as shown in Figures 5.121(a) and
(b), respectively. The feedback digital-to-analog converter (DAC)
is characterized by the transfer function HDAC (s) = (1 − esT )/s,
where T = 1/fs is the sampling period, and fs is the sampling
frequency.
@ fS
x
s(t) Σ H(s)
x
y(n) s(n) Σ H(z) y(n)

1−bit 1−bit
DAC DAC
(a) (b)

FIGURE 5.121
Block diagram of first-order ∆Σ modulators.

Suppose that
1
H(s) = (5.375)
sT
Delta-Sigma Data Converters 307

and use s-transform tables to show that

  t t−T
h(t) = L−1 H(s)HDAC (s) = u(t) − u(t − T ) (5.376)
T T

With reference to z-transform tables, show that

  z −1
H(z) = Z h(t)|t=nT = (5.377)
1 − z −1

Now consider that

sk
H(s) = (5.378)
sT + sk
where ωc = sk /T is the 3-dB bandwidth frequency of the analog
lowpass filter, and use s-transform tables to show that
 
 
h(t) = L−1 H(s)HDAC (s) = 1−e−sk t u(t)− 1−e−sk (t−T ) u(t−T )
(5.379)
Show that the equivalent transfer function in the z-domain can be
put into the form

  (1 − zk )z −1
H(z) = Z h(t)|t=nT = (5.380)
1 − zk z −1

where zk = e−sk T .
8. First-order CT lowpass modulator
Consider the circuit diagram of a first-order modulator shown in
Figure 5.122(a). The input stage is an active RC integrator and
C1

R1
V − +
i
D Q D Q V0
+ −
CK Q CK Q φ
1
φ φ t/T
1 2
φ
2

I DAC R2 φ C2 φ t/T
2 1
I
DAC
IB
φ φ
1−bit 1 2

SCR DAC t/T

(a) (b) 0 1/2 1

FIGURE 5.122
(a) Circuit diagram of a first-order CT modulator; (b) waveforms of a 1-bit
SCR DAC (p2 = 1 and p1 = 1/2).
308 Data Converters, Phase-Locked Loops, and Their Applications

the quantizer output is assumed to be held for a full clock period.

Figure 5.122(b) shows waveforms of the switched-capacitor with a
series resistor (SCR) DAC, with φ1 and φ2 being non-overlapping
clock phases.
Assuming that the clock signal period is T and the desired DT
transfer function of the quantization noise is HQ (z) = 1 − z −1 , use
the following DT-to-CT transform
1 r0
→ (5.381)
z−1 s
where
1
r0 = (5.382)
τd (1 − e−(p2 −p1 )T /τd )
and τd = R2 C2 , to show that R1 C1 = 1/r0 .
9. Analysis of a second-order CT ∆Σ modulator
Consider the second-order CT ∆Σ modulator shown in Figure 5.21.
k3

k0 @ fS
b−bit
s(t) Σ I(s) Σ I(s) y(n)
x ADC

k1 k2
b−bit
DAC

FIGURE 5.123
Block diagram of a second-order CT ∆Σ modulator.

Assuming that I(s) = 1/(sT ), where T denotes the clock signal

period, show that

X(s) k2 sT + k1
H(s) = =− 2 2 (5.383)
Y (s) s T + k3

In the case where the digital-to-analog converter (DAC) is of the

half-return-to-zero (HRZ) type, or HDAC (s) = (e−sT /2 − e−sT )/s,
find the equivalent discrete-time (DT) transfer function H(z).
Generate the pole-zero plot of the DT modulator noise transfer
function based on the following coefficient values: k0 = 1, k1 = 2,
k2 = 3.5, and k3 = 0.015.
10. Second-order bandpass CT modulator
A second-order bandpass CT modulator [32] can be implemented
as shown in Figure 5.124. It consists of transconductors, a LC res-
onator, a 1-bit return-to-zero (RZ) DAC, and a 1-bit half-clock-
period delayed return-to-zero (HZ) DAC. The output voltage of the
Delta-Sigma Data Converters 309
Unit delay

Vi+ − + − + −+ D Q D Q V0+
gm2 C g m1 CK CK
Vi− + − + − +− D Q D Q V0−
Enable
L L

1−bit 1−bit φ φ
HZ DAC RZ DAC

Q D
CK
Q D

FIGURE 5.124
Circuit diagram of a second-order LC bandpass CT modulator.

CT filter is given by

V0 (s) = Ii ZLC (s) (5.384)

where Ii = gm Vi and ZLC (s) = 1/[Cs + (1/Ls)].

Verify that the filter transfer function can be put into the form,

V0 (s) kω0 s
Ĥ(s) = = 2 (5.385)
Vi (s) s + ω02

√ p
where ω0 = 1/ LC and k = gm L/C.

Assuming that the desired loop transfer function of the DT modu-

lator prototype is z −2 /(1 + z −2 ), and the transfer functions of the
DAC pulses are given by,

1 − e−sT /2
Prz (s) = (5.386)
s
e−sT /2 − e−sT e−sT /2 (1 − e−sT /2 )
Phz (s) = = (5.387)
s s

the feedback coefficients implemented by each of the DACs can be

310 Data Converters, Phase-Locked Loops, and Their Applications

determined by solving the next equation

   
−1 −1 ω0 s
z H(z) = krz Z L Prz (s) 2 +
s + ω02 t=nT
   
−1 ω0 s
khz Z L Phz (s) 2
s + ω02 t=nT
(5.388)
[sin(ω0 T ) − sin(ω0 T /2)]z −1 − sin(ω0 T /2)]z −2
= krz +
1 − 2 cos(ω0 T )z −1 + z −2
sin(ω0 T /2)z −1 + [sin(ω0 T /2) − sin(ω0 T )]z −2
khz
1 − 2 cos(ω0 T )z −1 + z −2
(5.389)
√ √ √ √
2 −1
(1 − 2 )z − 22 z −2 2 −1
2 z − (1 − 2 −2
2 )z
= krz + khz
1 + z −2 1 + z −2
(5.390)

where ω0 T = π/2 and H(z) = z −1 /(1 + z −2 ).

Deduce that
√ √
2 2
krz =− and khz =1+ (5.391)
2 2

A practical CT modulator can be affected by the excess loop delay

caused by the imperfection of the feedback components. Taking into
account the excess loop delay, the sampling period can be modeled
as (1+δ)T , where 0 < δ ≤ 1, and the loop transfer function becomes
 
−1 z −2 (1 − δ)π δπ
z H(z, δ) = sin + z −1 sin (5.392)
1 + z −2 2 2

To study the modulator stability, plot the pole-zero locus of the

resulting noise transfer in the z domain and verify that both poles
can move out of the unit circle for an excess loop delay of about
58% of the clock signal period, T .
11. DT and CT 2-1 cascaded ∆Σ modulators
For the 2-1 discrete-time (DT) cascaded ∆Σ modulator depicted in
Figure 5.125(a), verify that

X2 (z) α1 α2 z −2 2α1 α2 z −1
H1 (z) = =− − (5.393)
Y1 (z) (1 − z −1 )2 1 − z −1
−1
X3 (z) α3 z
H2 (z) = =− (5.394)
Y2 (z) 1 − z −1
Delta-Sigma Data Converters 311

and
 
X3 (z) κ2 α3 z −1
H3 (z) = = H1 (z) − κ1 κ2 (5.395)
Y1 (z) α1 α2 1 − z −1
κ2 α3 z −3 2κ2 α3 z −2 κ1 κ2 α3 z −1
=− − −
(1 − z −1 )3 (1 − z −1 )2 1 − z −1
(5.396)

x1 x2
s(n) Σ α 1 I(z) Σ α 2 I(z)

2α 1 κ2 α α
1 2
1−bit
y1 H 1 (z)
DAC
κ 1κ 2

x3 b−bit
Σ α 3 I(z) Σ y(n)
ADC

b−bit
y2 H 2 (z)
(a) DAC

k0 @ fS
x1 x2
s(t) Σ I(s) Σ I(s)

k1 g1 k2 g2
1−bit
y1 H 1 (z)
DAC
g0 @ fS
b−bit
Σ I(s) Σ y(n)
x3 ADC

g3
b−bit
H 2 (z)
DAC y2
(b)

FIGURE 5.125
Block diagrams of 2-1 cascaded ∆Σ modulators.

TABLE 5.5
Equivalent CT Transfer Functions of Some DT Transfer Functions

z −1 1 z −2 1 1 1
−1
→ −1 2
→ 2 2−
1−z sT (1 − z ) s T 2 sT
z −3 1 1 1 1
→ 3 3− 2 2+
(1 − z −1 )3 s T s T 3 sT

Use the impulse invariant transform relations of Table 5.5, where it

was assumed that the digital-to-analog converter (DAC) is modeled
by a transfer function of the form HDAC (s) = (1 − e−sT )/s, where
312 Data Converters, Phase-Locked Loops, and Their Applications

T is the period of the clock signal, to show that the equivalent s-

domain transfer functions of the z-domain transfer functions, Hp ,
(p = 1, 2, 3), are given by
α1 α2 3α1 α2 /2
H1 (s) = − − (5.397)
s2 T 2 sT
α3
H2 (s) = − (5.398)
sT
and
κ2 α3 κ2 α3 (2κ2 α3 /3)(1 − 3κ1 /2)
H3 (s) = − − + (5.399)
s3 T 3 s2 T 2 sT
With reference to the continuous-time (CT) 2-1 cascaded ∆Σ mod-
ulator shown in Figure 5.125(b), where k0 = k1 , determine the
transfer functions H1 (s) = X2 (s)/Y1 (s), H2 (s) = X3 (s)/Y2 (s), and
H3 (s) = X3 (s)/Y1 (s).
Find ki , (i = 0, 1, 2) and gj , (j = 0, 1, 2, 3) in terms of αp (p = 1, 2, 3)
and κq (q = 1, 2).
With the assumption that α1 = 1/2, α2 = 1/2, α3 = 1, κ1 κ2 = 1,
and κ2 = 1/2, generate the pole-zero plot of each of the modulator
noise transfer functions.
12. Third-order CT modulator with a PDWA DAC
MATLAB® (Delta Sigma or Control) toolboxes can be used to
design a third-order CT ∆Σ lowpass modulator with an SQNR of
89 dB at an oversampling rate of 16.
Assuming a 4-bit quantizer and choosing the inverse Chebyshev
filter response, the following quantization noise transfer function
can be derived:
(z − 1)(z 2 − 1.977z + 1)
HQ (z) = (5.400)
(z − 0.3474)(z 2 − 0.6295z + 0.2935)

Next, the transfer function of the corresponding DT loop filter is

obtained as,
HQ (z) − 1 2(z 2 − 1.232z + 0.449)
H(z) = = (5.401)
HQ (z) (z − 1)(z 2 − 1.977z + 1)
Assuming an NRZ DAC waveform and a total excess-loop delay of
τ = T /2, where T denotes the period of the clock signal, the DT
transfer function H(z) is transformed into a CT loop-filter transfer
function of the form:
0.8374s3 + 1.984s2 + 1.321s + 0.4342
F̂ (s) = − (5.402)
s(s2 + 0.0231)
Delta-Sigma Data Converters 313

In the special case of an NRZ DAC pulse, this can performed using
the d2c function of MATLAB Control toolbox.
γ δ3

EQ
δ1 α1 α2 α3
ω1 ω2 ω3
US (s) Σ s Σ s Σ s Σ z −1/2 Y(z)

δ2 4−bit ADC

β1 β2 β0
4−bit
UF (s) DAC

FIGURE 5.126
Block diagram of a third-order CT lowpass modulator.

γ δ 3 s/ ω 3’

EQ
δ1 α1 α2
ω1 ω2 ω 3’
US (s) Σ s Σ s Σ s z −1/2 Y(z)

δ2 4−bit ADC

4−bit
β ’0 z −1/2
DAC

β1 β2 Σ
4−bit
UF (s) DAC

FIGURE 5.127
Block diagram of the third-order CT lowpass modulator after scaling.

Consider the block diagram of a third-order CT lowpass modulator

shown in Figure 5.126, where the feedback coefficient β0 is employed
to compensate the excess-loop delay that is generally associated to
CT modulators with an NRZ DAC pulse. However, DACs using
NRZ pulses are less sensitive to clock jitter. Assuming that ωi = 1
for i = 1, 2, 3, it can be shown that
sX(s) = AX(s) + BU(s) (5.403)
Y (s) = CX(s) + DU(s) (5.404)
where

  
0 −γ 0 −β1 δ1
A =  α1 0 0 B = −β2 0 
−δ2 α2 0 0 0 (5.405)
   
C = 0 δ3 α3 D = −β0 0

and U(s) = [UF (s) US (s)]T , with US (s) being the modulator input
314 Data Converters, Phase-Locked Loops, and Their Applications
R 1a
R 3a

C1 C2 C 3a C3

R1 R2 R3
Latches
Vi+ −+ −+ −+ 4−bit
ADC D Q V0
V− +− +− +−
i CK
R1 R2 R3

φ
C1 C2 C 3a C3

R 3a

R 1a

+ + + +
4−bit 4−bit 4−bit 4−bit
DAC 1 DAC 2 DAC 0 DAC 0
Latches

DWA Q D

CK φ

FIGURE 5.128
Circuit diagram of the third-order CT lowpass modulator.
DAC
element
1

LSB Σ Out

Binary 7
3 7 Switch
MSBs to Di D0
thermometer array

7
φ
1
3 S
Register A Decoder
Σ

FIGURE 5.129
DAC with PDWA circuit.

and UF (s) the DAC output. The transfer functions can be obtained
as:
T (s) = C(sI − A)−1 B + D (5.406)
where  T
Y (s) Y (s)
T (s) = (5.407)
UF (s) US (s)
The feedback and feedforward transfer functions are, respectively,
given by

Y (s) a3 s3 + a2 s2 + a1 s + a0
F (s) = =− (5.408)
US (s) s(s2 + α2 γ)
Delta-Sigma Data Converters 315
Di [7:1]
φ

S1
VDD
D D [7:1]
0 S2
CK Q

D
CK Q S3

D
CK Q S4
D
CK Q S5
D
CK Q
S6
D
CK Q
S7
D
CK Q
S1 S2 S3 S4 S5 S6 S7
A[2:0]
Decoder A2 A1 A0 0
(a) (b)

FIGURE 5.130
Circuit diagram of the switch array (a) and the decoder (b).

4−bit code DAC elements

MSBs LSB 1 2 3 4 5 6 7 LSB 7 6 5 4 3 2 1
1 0
3 0
4 0
7 1
4 1
2 0
0 1
1 0
Usage 4 3 3 3 3 3 3 3 3 3 3 3 3 3 4

FIGURE 5.131
Illustration of the PDWA DAC operation.

and

Y (s) d1 s + d0
G(s) = = (5.409)
UF (s) s(s2 + α2 γ)
where

a 3 = β0 (5.410)
a 2 = β2 δ 3 (5.411)
a1 = (α1 δ3 − α3 δ2 )β1 + α2 α3 β2 + α1 β0 γ (5.412)
a0 = α1 α2 α3 β1 + α3 β2 γδ2 (5.413)
d1 = (α1 δ3 − α3 δ2 )δ1 (5.414)
316 Data Converters, Phase-Locked Loops, and Their Applications

and

d0 = α1 α2 α3 δ1 (5.415)

By matching F (s) and F̂ (s), modulator coefficients are obtained as

follows:
α1 = 0.5 α2 = 1 α3 = 2 β1 = 0.39 β2 = 0.65
(5.416)
β0 = 0.84 γ = 0.05 δ1 = 0.43 δ2 = 0.76 δ3 = 3.04

For a power-efficient design, the block diagram of the third-order

CT lowpass modulator is scaled to eliminate the output summer, as
illustrated in Figure 5.127, where ω3′ = ω3 α3 . To differentiate the
feedforward and feedback signals that are now applied at the input
of the last integrator, the gains δ3′ and β0′ of the corresponding paths
are scaled by s. The feedforward gain is of the form, δ3′ = δ3 /ω3′ .
For the feedback path, the differentiator is implemented in the dig-
ital domain, by mapping s as (1 − z −1/2 )/τ . Hence, β0′ = β0 /(ω3′ τ ),
where τ = T /2.

Assuming that T = 1, modulator coefficients can be obtained as

follows:
α1 = 0.5 α2 = 1 α3 = 2 β1 = 0.39 β2 = 0.65
′ (5.417)
β0 = 0.84 γ = 0.05 δ1 = 0.43 δ2 = 0.76 δ3′ = 1.5

Due to the fact the coefficient α3 is equal to a power of 2, it can be

implemented by decreasing the voltage reference level of the quan-
tizer (4-bit flash ADC) by a factor of 2.
The circuit diagram of the third-order CT lowpass modulator is
shown in Figure 5.128. It is based on RC circuits that are known to
feature a high linearity and signal swing.
A data-weighted averaging (DWA) circuit can be associated only
to the first DAC, that has the most stringent noise and linearity
requirements. It can provide a first-order shaping of errors due to
DAC element mismatches.
To reduce the hardware size by almost a factor of 4, the first DAC
is implemented with a partial DWA (PDWA) circuit, as shown in
Figure 5.129. Elements of the current steering DAC are laid out
symmetrically around the central unit element that is directly con-
trolled by the LSB bit. The other three MSBs of the codeword are
applied at the input of the accumulator, whose output is decoded
and then used as the selection code for the switch array. This en-
sures that the DAC elements are chosen equally and cyclically so
that the random mismatch error is averaged out.
Delta-Sigma Data Converters 317

Figure 5.130 shows the circuit diagrams of the switch array and
the decoder. The operation of the PDWA DAC circuit is illustrated
in Figure 5.131. The use of the PDWA DAC leads to an SNDR
degradation of less than 3 dB assuming a standard deviation of
σ = 1.5% for the DAC element mismatch.
Use simulation tools to verify that the designed third-order CT
modulator exhibit an SQNR of 87.7 dB at the OSR of 16, and a
DR of 76 dB over of the signal bandwidth of 5 MHz.
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Delta-Sigma Data Converters 323

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6
Circuits for Signal Generation and
Synchronization

CONTENTS
6.1 Generation of clock signals with nonoverlapping phases . . . . . . . . . . . . . . . . . 327
6.2 Phase-locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
6.2.1 PLL linear model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
6.2.2 Charge-pump PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
6.3 Charge-pump PLL building blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
6.3.1 Phase and frequency detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
6.3.2 Phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.3.2.1 Linear phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
6.3.2.2 Binary phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
6.3.2.3 Half-rate phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
6.3.3 Charge-pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
6.3.4 Loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
6.3.5 Voltage-controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
6.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
6.4.1 Frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
6.4.2 Clock and data recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
6.4.2.1 Dual-loop CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
6.4.2.2 Phase interpolator-based CDR circuit . . . . . . . . . . . . . . . . . . . 374
6.4.2.3 CDR circuit based on a gated VCO . . . . . . . . . . . . . . . . . . . . . 377
6.4.2.4 Reference-less dual-loop CDR circuit . . . . . . . . . . . . . . . . . . . . 381
6.4.2.5 Reference-less single-loop CDR circuit using a linear
phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
6.5 Delay-locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
6.6 PLL with a built-in self-test structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
6.6.1 Gain, capture and lock range, and lock time . . . . . . . . . . . . . . . . . . . . . 394
6.6.2 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
6.7 PLL specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
6.8 VCO-based analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
6.9 PLL based on time-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
6.9.1 Flash TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
6.9.2 Vernier TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
6.9.3 Switched ring oscillator TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
6.10 High-speed input/output link transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
6.11 Relaxation oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
6.12 Class D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
6.13 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
6.14 Circuit design assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

325
326 Data Converters, Phase-Locked Loops, and Their Applications

A circuit for the clock signal generation or recovery is often required to achieve
accurate data transfer between the different building blocks (see Figure 6.1)
of very large-scale ICs operating at high speed. In the case of transmission
systems, as shown in Figure 6.2, the multiplexer converts the input data into
a serial stream of non-return-to-zero data, which then drives a high-speed
buffer. At the receiver, the signal level is determined by an amplifier and the
clock signal is recovered from the transmitted data and used to control the
demultiplexer. The resulting data synchronization determines the accuracy
of the information regeneration. The rising edges of the clock signal, whose
frequency is set equal to the data rate, should coincide with the midpoint of
each data bit, such that the sampling occurs farthest from the preceding and
following transitions, yielding a maximum tolerance margin for the jitter and
other timing uncertainties.

Data converter 1
I/O Interface

Digital signal
Data converter 1 processor

Data converter 1

Clock generation circuit (PLL, DLL)

FIGURE 6.1
A typical integrated-circuit floorplan.

Data bus
Demultiplexer
Multiplexer

Input Output
data data
Buffer Buffer

Reference Clock Clock

clock generation recovery Clock

FIGURE 6.2
Transmission system.

Precision timing circuits are generally based on a phase-locked loop (PLL)

or delay-locked loop (DLL). They should typically feature a low sensitivity to
process and temperature variations, and generate a clock signal with very low
skew and jitter. However, achieving these requirements can be difficult due to
a number of design trade-offs to be made between the circuit characteristics.
Circuits for Signal Generation and Synchronization 327

Furthermore, a high level of integration will only be achieved if the objectives

of reducing the area and power consumption are met.

6.1 Generation of clock signals with nonoverlapping

phases
To keep negligible the charge leakage, the duration of the sampling phase and
hold phase required in the operation of switched-capacitor circuits is controlled
by nonoverlapping clock signals.

φ φ φ
1 t
φ
1 t
φ φ
2 2
(a) (b) t

FIGURE 6.3
(a) Circuit diagram of a two-phase nonoverlapping clock signal generator; (b)
clock signals.

φ
3

φ
1
φ
∆

φ
2

φ
(a) 4

φ
t
φ
1 t
φ
2 t
φ =φ
3 1d t
φ =φ
(b) 4 2d t

FIGURE 6.4
(a) Circuit diagram of a four-phase nonoverlapping clock signal generator; (b)
plot of output signals.
328 Data Converters, Phase-Locked Loops, and Their Applications

The circuit diagram of a two-phase nonoverlapping clock signal generator

is shown in Figure 6.3(a). It consists of NAND gates and inverters. Here, the
generator is designed to provide two outputs, which are not allowed to be in
the high state during the same time. The nonoverlapping time can be increased
by augmenting the number of inverters included between each output and the
NAND gate. Each output node is buffered with an inverter sized to drive the
on-chip clock bus. Figure 6.3(b) shows the plot of input and output signals. By
applying a 50% duty-cycle reference clock signal at the input, the rising edge
occurs at one output after the falling edge is produced at the other output.
The main advantage of the aforementioned signal generator is its simplicity.
However, the propagation delay introduced by the input inverter and changes
in clock waveforms due to variations in load conditions can become critical in
high-speed applications.

φ
1
CLR
D Q
φ
φ Q ∆1 ∆2 3

PR

Set/Reset

CLR
Q ∆1 ∆2 φ
4
D Q
PR
φ
2
(a)

φ
t
φ
1 t

φ
2 t

φ
3
t

φ
(b) 4 t

FIGURE 6.5
(a) Circuit diagram of a four-phase nonoverlapping clock signal generator with
equal pulse-width complementary signals; (b) plot of output signals.

Charge injection errors can be minimized using a four-phase clock signal

generator [4]. In the case of the structure shown in Figure 6.4(a), the delay ∆
blocks, which can be implemented by an even number of inverters connected in
series, are purposely introduced to increase the nonoverlap time between the
clock phases φ1 and φ2 . The plot of the input and output signals is depicted
in Figure 6.4(b), where φ3 and φ4 represent the delayed versions of φ1 and φ2 ,
respectively. The propagation delay of the NAND gate and inverters, which
determines the nonoverlap time, is a critical design parameter. If it is chosen
with a very small value, clock skew may affect the accuracy of the clock timing.
Conversely, if it is sized to be excessively large, the effective time period of
the clock signals will be considerably reduced. Under these conditions, the
clock speed may be reduced. Furthermore, the inverter required at the input
Circuits for Signal Generation and Synchronization 329

of the clock generator delivering nonoverlapping clock signals with the same
periodicity as the reference clock introduces a difference in the duty cycle of
complementary clock signals.
A solution to improve the performance of the clock generator can rely
on forcing the rising edges of a clock phase and its delayed version to occur
simultaneously. The circuit diagram of the four-phase nonoverlapping clock
signal generator [5] with equal pulse-width complementary signals is shown
in Figure 6.5(a). To make the pulse widths of complementary clock signals
equal, the input reference clock is applied to two divide-by-2 circuits based
on D flip-flops initialized to the high state and low state, respectively. The
resulting signals are then applied to a cross-coupled section including a NAND
gate, a delay block △1 , and two signal-edge synchronization structures, each
of which is composed of a series connection of two inverters, a delay block
∆2 , a NAND gate, and an inverter. The synchronization is achieved within a
specified maximum amount of time equal to the propagation delay introduced
by the series of two inverters and the delay block ∆2 . Each of the delay blocks,
∆1 and ∆2 , should be realized by an even number of inverters connected in
series. Figure 6.4(b) shows the plot of the input and output signals. The rising
edges of φ1 and φ2 are aligned to the ones of φ3 and φ4 , respectively, while
the falling edges of φ3 and φ4 occur after the ones of φ1 and φ2 , respectively.
In this approach, the clock generator has the advantage of not introducing
a difference of pulse width between both complementary clock phases and is
then suitable for the control of double-sampled or time-interleaved switched-
capacitor circuits.

6.2 Phase-locked loop

The block diagram of the PLL is shown in Figure 6.6. The PLL is a feedback

Phase Loop
In detector filter VCO Out

FIGURE 6.6
Phase-locked loop.

system, that operates by generating an oscillation signal, whose frequency has

to match the one of the input signal. It consists of a phase detector (PD),
loop filter, and voltage-controlled oscillator (VCO). The PD output waveform
is proportional to the phase difference between the input and VCO output
signals. It is then smoothed by the loop filter and the resulting dc signal is
330 Data Converters, Phase-Locked Loops, and Their Applications

applied to the VCO control node. The VCO can then be driven to minimize
the phase difference.
During the initial transient, the PLL operates in the nonlinear region as
the VCO tries to find the correct frequency. The PLL linear model is valid
when the locked condition is obtained. In this case, the phases of the input
and VCO output signals are relatively equal.
Note that the choice of PD architecture has an impact on the overall PLL
performance, such as the lock-in range and static phase error. The linear range
of a PD detector, which can consist of a simple XOR gate, spreads from −π to
π. On the other hand, an alternative structure known as a phase and frequency
detector (PFD), which generally exhibits the advantage of indicating the lead
or lag relation between input waveforms, can handle differences between the
clock signals in the range of −2π to 2π.

6.2.1 PLL linear model

Phase detector Filter VCO

Θ e Kp
Θi Σ H(s) Kv s Θ0
Vp Vf

FIGURE 6.7
PLL linear model.

Even if the PLL exhibits a nonlinear behavior, its design often starts with
the linear model. Figure 6.7 shows the linear model of the PLL. Let Θi and Θ0
be the phase angles associated with the input and output signals, respectively;
the output of the phase detector has the form

Vp (s) = Kp (Θi (s) − Θ0 (s)) (6.1)

where Kp is the PD conversion gain in units of volts per radian. The transfer
function of the filter is denoted by H(s) and that of the VCO is Kv /s, where
Kv is the VCO gain in units of radians per volt·second, because the frequency
is related to the time derivative of the phase. The phase and error transfer
functions can be, respectively, computed as
Θ0 (s) Kv Kp H(s)
T (s) = = (6.2)
Θi (s) s + Kv Kp H(s)

and
Θe (s) s
Te (s) = = (6.3)
Θi (s) s + Kv Kp H(s)
The frequency and transient responses of the loop appear to be affected by the
choice of filter characteristic. Due to the contribution of the VCO first-order
Circuits for Signal Generation and Synchronization 331

transfer function, the order of the PLL is equal to that of the filter plus 1.
In the special case of a second-order loop, the PLL transfer function contains
two poles at the origin due to the VCO and the loop filter implemented by an
integrator. To counteract the effect of these poles, the loop transfer function
must include a stabilizing zero, which is implemented by connecting a resistor
in series with the integrating capacitor.

A simple second-order PLL, as illustrated in Figure 6.8, consists

of a phase detector (PD), a loop filter, and a voltage-controlled
oscillator (VCO).

PD Loop filter
VCO
R VC
Di
Kv s RCK
VP
C

FIGURE 6.8
Second-order PLL with XOR PD.

Di
0 t1 t2 t3

RCK
t’1 t’2 t’3

VP

FIGURE 6.9
XOR PD waveforms.

An XOR logic gate is used to implement the PD. The XOR

PD output takes the high logic level when the inputs are set
to different logic levels, otherwise, it is at the low logic level.
Figure 6.9 shows a representation of XOR PD waveforms.
The PD characteristic can be obtained by plotting the average
output voltage, V̄P , as a function of the phase difference, θ. For
a given integer k, the phase difference between the PD inputs
can be defined as,
t′ − tk
θ = ± 2π k (6.4)
T
where T is the signal period.
The XOR PD with a single-ended output has a sawtooth char-
acteristic, as shown in Figure 6.10(a), that is periodic and non-
monotonic, while the XOR PD with differential outputs possess
332 Data Converters, Phase-Locked Loops, and Their Applications
VP

VH

θ
2π π 0 π 2π
(a)

VP

VH

θ
2π π 0 π 2π

VL
(b)

FIGURE 6.10
XOR PD characteristics: (a) single-ended output, (b) differential outputs.

a triangular characteristic, as illustrated in Figure 6.10(b). In

general, the PD gain is Kp = (VH − VL )/π, where VL ≤ 0.
The PD characteristic is linear over a range of π radians and is
sensitive to the duty cycle of the input signals.
Let θ0 and θi be the output and input phase angles, respectively.
The phase transfer function is of the form,
θ0 (s) Kv Kp H(s)
T (s) = = (6.5)
θi (s) s + Kv Kp H(s)
where the filter transfer function is given by
Vc (s) 1
H(s) = = (6.6)
Vp (s) 1 + s/ωc
and ωc = 1/RC represents the −3 dB cutoff angular frequency.
Hence,
θ0 (s) ωn2
T (s) = = 2 (6.7)
θi (s) s + 2ξωn s + ωn2
where
p
ωn = K p K v ωc (6.8)

and
r
1 ωc 1 ωc
ξ= = (6.9)
2 Kp Kv 2 ωn
with ωn and ξ being the natural frequency and damping ratio,
respectively. The −3 dB bandwidth of the PLL can be obtained
as p
BW = ωn (1 − 2ξ 2 + 2 − 4ξ 2 + 4ξ 4 )1/2 (6.10)
Circuits for Signal Generation and Synchronization 333

The phase error transfer function is given by

θe (s)
Te (s) = = 1 − T (s) (6.11)
θi (s)
s(s + 2ξωn ) s(s + ωc )
= 2 = 2 (6.12)
s + 2ξωn s + ωn2 s + 2ξωn s + ωn2

In the time domain, the PLL phase error in response to a unit

phase step at the input can be obtained by taking the inverse
Laplace transform of (1/s)Te (s). It depends on the damping
ratio ξ and can exhibit damped oscillations or overshoots before
reaching the
√ steady state. The settling time, ts , is minimum
when ξ = 2/2, and the steady-state value of the phase error is
then reached to within a tolerance of 10% for ωn ts ≃ 2.5.
Given a settling
√ time ts of 10 µs, VH = VDD = 2.5 V, and
choosing ξ = 2/2, the loop characteristics can be obtained as
follows:

ωn ≃ 2.5/ts = 2.5 × 105 rad (6.13)

5
ωc = 2ξωn = 3.5 × 10 rad (6.14)

and
√
Kv = ωn2 /(ωc Kp ) = ωn /( 2Kp ) = 2.2 × 105 Hz/V (6.15)

where Kp = VDD /π in V/rad. By selecting C = 1 nF, we can

obtain R = 1/(ωcC) = 2.8 kΩ.

The hold-in range, that is the range over which the PLL will
remain in the phase-locked state, but not necessarily acquire
that state, is given by △ωH = ±Kp Kv π/2 for the PD with a
triangular characteristic and △ωH = ±Kp Kv π for the PD with
a sawtooth characteristic. Thus, the VCO can be tuned by △ωH
without loss of lock.
A PLL with XOR PD can be limited by the fact that it can
lock to fractional harmonics of the input signal frequency, fi , or
M fi /N , with M and N being odd integers.

6.2.2 Charge-pump PLL

To achieve an extended tracking range, the PLL can be implemented as shown
in Figure 6.11. This structure includes a PFD, a charge-pump circuit, a loop
filter, and a VCO. The PFD has the advantage of also being sensitive to
334 Data Converters, Phase-Locked Loops, and Their Applications

Charge Loop
In PFD pump filter VCO Out

FIGURE 6.11
Charge-pump phase-locked loop.

frequency error. It acts as an extended-range phase detector and generates

a signal, which is indicative of the difference between its input signals. The
purpose of the charge-pump circuit is to convert the logic states of the PFD
into analog signals, which are appropriate for the VCO control.

6.3 Charge-pump PLL building blocks

A charge-pump PLL system generally consists of a phase and frequency de-
tector (PFD) or phase detector (PD), a charge-pump circuit, a lowpass filter,
and a VCO. The PFD or PD compares the phase of the input data and that
of the recovered clock signal generated by the VCO, and produces an error
signal, typically consisting of Up and Dn signals used to drive a charge-pump
circuit differentially. The output signal delivered by the charge-pump circuit
is dependent on the phase difference between the data and clock signals. The
resulting average signal, which is provided by the loop filter operating as an in-
tegrator, is applied to the VCO control input in order to appropriately change
the frequency of the clock signal.

6.3.1 Phase and frequency detector

The ideal characteristic of a three-state PFD, as shown in Figure 6.12, is linear
for the range of input phase differences from −2π to 2π. The gain of the PFD
can be defined as KP = (VH − VL )/2π, where VH and VL denote the highest
and lowest output levels, respectively.
When the PFD is followed by a charge-pump circuit, the threshold levels
VH and VL are used to control the value of the charge-pump current, IP , and
the combination of the PFD and charge-pump circuit then exhibits a gain of
the form, KP = IP /2π. For the absolute value of the phase difference not
exceeding 2π, the PFD is said to be in the lock state.
In the case of a comparison of two input signals with the same period
and amplitude, the PFD operation principle can be illustrated by the timing
diagrams shown in Figure 6.13.
If both input signals are of the same frequency and in phase, both outputs
will be set at zero. If CK leads RCK, pulses will be generated at the output
Circuits for Signal Generation and Synchronization 335

VH

CK Up
−4π −2π

Up−Dn
PFD
0 2π 4π
RCK Dn

VL

Phase difference ∆φ
(a) (b)

FIGURE 6.12
(a) Phase and frequency detector symbol; (b) ideal characteristic of a three-
state PFD.

CK CK CK

RCK RCK RCK

Up Up Up

Dn Dn Dn

(a) (b) (c)

FIGURE 6.13
(a)–(c) Timing diagrams illustrating the three states of a PFD.

RCK CK
RCK CK

Up=0 Up=0 Up=1

Dn=1 Dn=0 Dn=0

Discharge CK Initial RCK Charge

state state state

FIGURE 6.14
State graph of the three-state PFD.

Up while the Dn signal will remain at zero. On the other hand, if CK lags
RCK, the Dn signal will be pulsed while the Up signal level will remain low.
By applying input signals with different frequencies to the PFD, one output
signal is more often set to the high level than the other. As a result, the
average value of the output will be positive or negative, depending on the sign
of the frequency and phase difference.
The PFD operation can be described using finite-state machine, as shown
in Figure 6.14, where CK and RCK represent the two periodic input signals.
There are only three allowed combinations for the outputs Up and Dn. From
the initial state, Up = 0 and Dn = 0, a rising edge of CK causes a transition
to the charge state, Up = 1 and Dn = 0, while a rising edge of RCK causes
a transition to the discharge state, Up = 0 and Dn = 1. If the PFD is in the
336 Data Converters, Phase-Locked Loops, and Their Applications

charge state, a rising edge of CK will cause no state change, but a rising edge
of RCK will cause a change to the initial state. From the discharge state, the
PFD can change state only in response to a rising edge of CK. The charge,
initial, and discharge states can be, respectively, associated with the three dif-
ferent values, IP , 0, and −IP , of the current to be generated by a charge-pump
circuit.

Up

RCK Up
S1 Q1

Q1

Reset
Q2

S2 Q2
CK Dn

Dn

FIGURE 6.15
Gate implementation of the phase and frequency detector.

At the gate level, a PFD can be realized as shown in Figure 6.15 [6]. Each
of the logic states Q1 and Q2 are generated by an S R latch, including a pair
of cross-coupled two-input NAND gates. From the initial state where both
outputs are in the low state, the PFD can move to either the state Up (high
at the output Up and low at the output Dn) or state Dn (high at the output
Dn and low at the output Up) after the detection of the rising edge of one
of the input signals. It remains in this last state until the second input goes
high, causing the generation of a reset signal, which enables the return to the
initial state.
VDD

D Q Up
1
CK R Q

RCK R Q
2
D Q Dn

FIGURE 6.16
Circuit diagram of a D flip-flop-based PFD.

An implementation of the PFD based on two resettable D flip-flops, which

Circuits for Signal Generation and Synchronization 337

are clocked by the input signals, is depicted in Figure 6.16. The input terminal
D is connected to the positive supply voltage, VDD , and the CK terminals
serve, respectively, as inputs for the signals to be compared. The Dn and Up
output pulses are applied to the AND gate, which generates the flip-flop reset
signal. When both output signals are high, the AND gate output is set to the
high level and this in turn resets both D flip-flops. The reset time is about
several gate delays and determines the circuit speed.
Latch PFD
D flip−flop PFD

VH

2π
Up−Dn

−2π 0

VL

Phase difference ∆φ

FIGURE 6.17
Characteristics of PFD circuits based, respectively, on the R S latch and D
flip-flop.

In practice, due to the nonzero gate delays in the reset path and violations
of the setup and hold time, the PFD characteristic, as shown in Figure 6.17 [7],
may exhibit a reduced linear range and a dead zone, where small changes in
the input signals are not detected. The dead zone effect can be significantly
reduced by introducing an extra delay in the reset path to increase the over-
lapping time between the Up and Dn output signals. However, the efficiency of
this approach appears to be limited by the fact that the delay size is generally
dependent on variations in the IC process. For instance, the power consump-
tion will increase in the lock state if the predicted value of the delay time is
somewhat high. For a given PFD architecture, the dead zone, the operation
frequency range, the power dissipation, and the phase noise are dependent
on the design technique (standard logic gates, true single-phase clock logic
circuits, differential logic circuits). To extend the operating frequency range,
it may be necessary to use a PFD with more than three logic states.

6.3.2 Phase detector

A PD circuit, which can exhibit either a linear or binary transfer character-
istic [3], is required for the generation of the phase error signal. Linear PDs,
such as the Hogge phase detector, deliver a continuous error signal that is
responsible for a linear behavior in the tracking characteristic of the acquisi-
338 Data Converters, Phase-Locked Loops, and Their Applications

tion loop, while binary PDs, also known as Alexander (or bang-bang) phase
detectors, generate a quantized phase error signal that contributes to a non-
linear tracking characteristic. The input dynamic range of a phase detector is
smaller than that of a PFD.

RCK lags Di RCK leads Di

Di Di Di

RCK RCK RCK

Up Up Up

Dn Dn Dn
(a) (b)

FIGURE 6.18
Timing diagram of a (a) linear and (b) binary phase detectors.

Figures 6.18(a) and (b) show the timing diagram of a linear and binary
phase detectors, respectively. A linear PD generates an Up pulse whose width
is proportional to the phase difference between the input data Di and the
reference clock RCK and a Dn pulse that can be used to eliminate the de-
pendency on data pattern. A binary PD delivers Up and Dn pulses with two
possible levels that can be combined into a tri-state binary sequence indicating
whether the input data Di lags or leads the reference clock RCK.

6.3.2.1 Linear phase detector

VH
Up

−π
Up−Dn

Dn
Di D Q D Q 0 π
1 2
RCK Q Q
VL

(a) (b) Phase difference ∆φ

FIGURE 6.19
(a) Circuit diagram and (b) characteristic of a linear (Hogge) PD.

The circuit diagram of a Hogge PD [8] and its transfer characteristic are
depicted in Figure 6.19. The Hogge PD consists of two flip-flops, which are,
respectively, enabled at the rising and falling edge of the clock signal, and two
XOR gates. The input data, Di , and the output signal of the first flip-flop are
processed by the first XOR gate to generate an Up phase error signal, while
the output signal of the first flip-flop and the output signal of the second
Circuits for Signal Generation and Synchronization 339

flip-flop are applied to the second XOR gate to produce a Dn phase error
signal.
For each data transition, a pulse, whose width varies with the phase differ-
ence between the reference clock signal, RCK, and the input data, Di , is first
generated at the Up terminal, and a pulse with a fixed width of half of the
clock signal period, or TCK /2, is then produced at the Dn terminal. The ideal
sampling points of the data correspond to instants where the rising edge of the
clock occurs near the center of the data sample, thus yielding the maximum
noise margin. The width of the Up pulse will be TCK /2 if the rising edge of
the signal RCK is nearly aligned with the data center; otherwise, the Up pulse
will become smaller or larger than the Dn pulse for early or late clock signals.
The average value of the difference between the Up and Dn signals is a linear
function of the phase error.
In practical implementations of the Hogge PD, two of the three signals
applied to the XOR gates are affected by the RCK-to-Q delay of flip-flops,
resulting in an increased width of the Up pulses. These delay variations, which
are particularly critical at high frequencies, can cause an increase in the static
phase error, and a reduction of the clock phase margin and jitter tolerance.
A design solution for the equalization of the RCK-to-Q delay can consist of
placing extra delay elements on the path of the data signal to the XOR gate
input.

6.3.2.2 Binary phase detector

Ideal
Nonideal
Dn

Di D Q D Q VH
1 2 Up
Q Q −π φL
Up−Dn

RCK 0 φL π
Q Q
3 4 VL
D Q D Q
Phase difference ∆φ
(a) (b)

FIGURE 6.20
(a) Circuit diagram and (b) characteristic of a binary PD.

The binary PD, which is also known as the Alexander or bang-bang PD [9],
is shown in Figure 6.20 and is generally used in high-speed clock and data
recovery circuits. It consists of four flip-flops and a pair of XOR gates. The
input signal is received at the D terminals of the first and third flip-flops.
The first, second, and fourth flip-flops are enabled by the rising edge of the
clock pulse, while the sampling instants of the third flip-flop correspond to
the falling edges of the clock pulse. In addition to the retimed data that can
be obtained at the output of the second or fourth flip-flop, the binary PD
340 Data Converters, Phase-Locked Loops, and Their Applications

generates the Up and Dn pulses indicating whether the clock signal is leading
or lagging the input data signal.
By sampling two adjacent input data bits and the in-between data tran-
sition, the binary PD can deliver the early, late, or no transition information.
If the logical states of the first data bit and data transition are identical but
differ from that of the second data bit, the clock is early; and if the logical
states of the signal transition and the second data bit are equal but differ from
that of the first data bit, the clock is late. On the other hand, if all logical
states are similar or if the logical states of the first and second data bits are
identical but differ from that of the data transition, there is no data transition
and a zero dc output is generated.
With Q1 , Q2 , and Q4 denoting the output of the first, second, and fourth
flip-flops, it can be deduced that
− CK is early (E), if Q2 = Q4 =
6 Q1
− CK is late (L), if Q2 =
6 Q4 = Q1
− There is no transition (X), if Q2 = Q4 = Q1 or Q2 = Q1 6= Q4
While the binary PD can effectively align the clock with the data signal,
the average value of its Up and Dn output signals is not proportional to the
magnitude of the phase difference. Instead, the output characteristics is a
discrete function, which can assume only one of two logical states depending
on the result of each phase comparison. By detecting the phase information
only at the zero-crossings, the performance of the binary PD can be sensitive
to the data transition density.
In practice, due to non-ideal effects such as jitter and metastability, the
characteristic of the phase detector, that is ideally binary, may exhibit a fi-
nite slope for a small range, |△φ| < φL , of input phase around zero (see
Figure 6.20).

6.3.2.3 Half-rate phase detector

Di D Q D Q
1 L1
Q CK Q
Di D Q D Q
L1 L2 Up RCK I
CK Q CK Q Up
Q
RCK Dn 2
D Q
Dn
CK Q CK Q
L3 L4
D Q D Q D Q D Q
3 L2
RCK Q Q CK Q
(a) (b)

FIGURE 6.21
Circuit diagram of half-rate PDs with the (a) linear and (b) binary character-
istics.

The PDs described previously are assumed to operate at the full rate or
Circuits for Signal Generation and Synchronization 341

to use a clock frequency equal to the baud rate of the input data. Generally,
half-rate PDs are employed to enable operation at a higher speed with a clock
frequency equal to half the input data rate, as they can relax the requirements
set for the acquisition loop components. This is in contrast to full-rate archi-
tectures, which require more system components to work at higher frequencies
and then quickly reach the operating limit of the IC manufacturing process.

• Half-rate linear PD
The circuit diagram of a half-rate linear PD is depicted in Figure 6.21(a). This
PD circuit, which is the half-rate version of Hogge’s detector, consists of four
latches and two XOR gates [10].
The outputs of the first and third latches follow the data at the D inputs
whenever the clock signal is in the high and low state, respectively. They
are processed by the XOR gate to generate the signal Dn, whose width is
dependent on the phase difference between the half-rate clock and the input
data. The retimed data at half rate can be obtained at the outputs of the
second and fourth latches, which are, respectively, enabled on the low and high
levels of the clock signal. A full-rate output can be obtained by interleaving
the two retimed data streams using a multiplexer controlled by the half-rate
clock signal.
The two latches included in each PD path operate as a master-slave flip-
flop. Hence, the outputs of the second and fourth latches change on both edges
of the clock signal, and the Up signal provided by the XOR gate is a pulse
with a constant width of half the clock period, or TCK /2, in the case where a
data transition is detected. In the locked state, the width of the Dn becomes
TCK /4, while that of the Up pulse is TCK /2. To equalize the effect of both PD
outputs, the Up signal can be scaled down by a factor of 2. This is realized
in practice by sizing the charge pump circuit such that the current source
controlled by the Up signal is two times smaller than the one steered by the
Dn signal.

• Half-rate binary PD
The circuit diagram of a half-rate binary PD is shown in Figure 6.21(b) [11].
The incoming data are applied to flip-flops enabled by the in-phase clock
signal, the complement of the in-phase clock signal, and the quadrature clock
signal, respectively. The output signals of the first and second flip-flops are
then compared to that of the third flip-flop using XOR gates to generate the
Up and Dn signals. Note that the latches L1 and L2 are introduced to align in
time the flip-flop output signals. If a data transition occurs between the rising
edge of the in-phase and quadrature clock signals, a pulse will be generated
at the Up or Dn terminal indicating whether the clock signal is leading or
lagging the input data; otherwise, both the Up and Dn signals remain at the
low level.
The aforementioned PD architecture samples the input data at the rising
and falling edges of the in-phase clock, while the quadrature clock is used
342 Data Converters, Phase-Locked Loops, and Their Applications
Di

Di D Q D Q RCKI
1 L1
Q CK Q RCKQ
RCK I FF1
Q Up1
2 FF2
D Q 0

MUX
Dn1 Up FF3
1
FF4
D Q D Q
3 L2 Up1
Q CK Q 0
Up2

MUX
Dn
1 Up2

Q CK Q Dn2 Dn1
4 L3
D Q D Q Dn2

RCK Q Up

Dn
(a) (b)

FIGURE 6.22
(a) Circuit diagram of a half-rate binary interleaved PD; (b) timing diagram.

to track the data transition. Its jitter tolerance is degraded as the operat-
ing frequency is increased. A solution can consist of increasing the number of
sampling instants [12]. This approach is exploited in the half-rate PD imple-
mentation shown in Figure 6.22(a) [13,14]. The symmetric architecture of this
PD circuit helps ensure the matching of delays in the signal paths.

The input data are sampled at 0o , 90o , 180o , and 270o of the clock phases
using four flip-flops in parallel. The synchronization of data samples, which
is particularly useful at high frequencies, is performed using three latches
controlled by the in-phase clock signal. The decoding logic for the Up and
Dn signals is based on XOR gates and 2-to-1 multiplexers. Each XOR gate
produces either an Up1/Up2 or Dn1/Dn2 signal by comparing data samples of
two adjacent signal paths. The two multiplexers with the select line controlled
by the in-phase and quadrature clock signals, respectively, keep the transfer
of the input signals to the Up and Dn terminals within a phase angle of
180o . The timing diagram of the half-rate binary interleaved PD is depicted in
Figure 6.22(b), where the shaded sections represent the invalid time intervals
of the Up1/Up2 and Dn1/Dn2 waveforms.

In the locked state, the quadrature clock edges are aligned with the data
transitions and the retimed data can be obtained at the output of the first
or third flip-flop. The multiplexer selection signals can be delayed by the
total amount of signal propagation delay up to the multiplexer input and the
multiplexer setup time to improve the timing margin.
Circuits for Signal Generation and Synchronization 343

6.3.3 Charge-pump circuit

In practice, the PFD or PD incorporated in PLLs does not provide sufficient
drive currents to achieve an adequate loop bandwidth. A charge-pump circuit
is therefore required to convert the logic pulses generated by the PFD or
PD into current signals that are used to drive the loop filter providing the
VCO control voltage. The associated current amplification contributes to an
increase in the loop bandwidth. The transfer characteristic of the charge pump
is generally determined in accordance with the operation principle of the PFD
or PD.
V DD
V DD
VB1 T
1
I1

T3
Up S1 Up

VP VDD VP
T
T4
Dn S2 C Dn C
T’

I2 T
V 2
B2

(a) (b)

FIGURE 6.23
(a) Conceptual diagram and (b) implementation of a charge-pump circuit.

The conceptual diagram of a charge-pump circuit is shown in Fig-

ure 6.23(a). The current sources I1 and I2 should be identical. Their con-
nections to the output node are controlled by the Up and Dn signals. The
current obtained at the output node will be ideally zero, if the Up and Dn
signals are identical. Otherwise, the average output current over a cycle is
Ip △φ/2π, where Ip is the maximum output current and △φ is the phase
difference between the input signals.
A charge-pump circuit can be implemented as shown in Figure 6.23(b).
The complementary transistor pair, T − T ′ , is used to equalize the delay of
the inverter. Due to the difference in the electron mobility of nMOS and
pMOS transistors and the asymmetry in rise and fall times of the Up and
Dn signals, a dynamic mismatch between the output currents corresponding,
respectively, to the Up and Dn control voltages can be observed during the
operation of this charge-pump circuit. The design of the charge-pump circuit
can be improved by minimizing the charge injection errors due to switches
and the charge sharing from parasitic capacitances. These charge errors are
known to result in a phase offset when a PLL is in the lock state.
For the charge-pump circuit of Figure 6.24(a) [15], two transistors, T5
and T6 , are used to remove the residual charge from the nodes, x and y,
during the inactive phases of the Up and Dn signals, thereby mitigating the
charge-sharing problem caused by parasitic capacitances at these nodes. The
charge-pump current flowing through the transistors, T3 and T4 , is defined
344 Data Converters, Phase-Locked Loops, and Their Applications
VDD VDD
T11 T1 T3 T4
Up Up T1
T15 T7

x
T13 T I1
IB T9 T3 5
VB1
VP VP
VB2 VDD
VDD
T14 T10
T4
T6 I2
y
VDD C C
T12 T2 T5 T6
Dn Dn T2
T8

(a) (b)

FIGURE 6.24
Circuit diagrams of charge-pump structures with reduced charge sharing due
to the use of (a) compensation switches and (b) nonoverlapping switching
pulses.

by the voltages, VB1 and VB2 , set by the biasing circuit section, T7 − T15 . A
drawback to this charge-pump circuit is the limited dynamic range available
at the output node, due to the overdrive voltages required to maintain the
transistors, T3 and T4 , in the saturation region.
An alternative charge-pump structure is shown in Figure 6.24(b) [16, 17].
The current I1 applied to the current mirror T3 − T4 will be directed to the
output if the signal Up is high, while the input current of the current mirror
T5 − T6 will be transferred to the output if the signal Dn is low. Due to the
fact that this charge-pump circuit operates without switching pulse overlap,
the charge redistribution associated with overlap capacitances of switches and
parasitic capacitances of current sources is reduced.
For the aforementioned charge-pump circuits with switched currents I1
and I2 , the switches controlled by the Up and Dn pulses can be assumed to
be, respectively, closed for the time periods TU p and TDn . The output charge
can then be expressed as

△Q = I1 TU p − I2 TDn (6.16)

Ideally, no charge should be transferred to the output in the lock state because
I1 = I2 and TUp = TDn . In practice, the mismatch between the current levels
and the difference in arrival times of the Up and Dn pulses can introduce
a steady-state phase offset and increase frequency spurs in the acquisition
loop. Furthermore, the transient glitch caused by parasitic capacitors can also
contribute to the increase of the spur and jitter levels.
In the case of the charge-pump circuit structure shown in Figure 6.25, the
effect of the charge sharing between the parasitic and output capacitors is at-
tenuated using an operational amplifier configured as a unity-gain buffer [18].
Circuits for Signal Generation and Synchronization 345
V DD

I1

T1 T2
Up Up

+ VP

T T4
Dn 3 Dn

I2

FIGURE 6.25
Charge-pump circuit with a reduced charge-sharing error.

The charge pump is implemented as switched current source and sink I1 and
I2 , which can be connected to the capacitor C defining the output voltage, VP .
The upper switches consist of p-channel transistors, while the lower switches
are realized with n-channel transistors. For Up and Dn pulses associated with
a phase difference, the capacitor C should ideally be charged by either the
current source or the current sink. In the lock state, no current should be
supplied to the capacitor C by the charge-pump circuit so that the output
voltage will remain unchanged.
V DD
T5 T6 T7 T8

VP

C
T1 T2 T3 T4
Dn Dn Up Up

I2 I1

FIGURE 6.26
Charge-pump circuit with an improved current matching.

The charge-sharing errors that can cause mismatch between the current
source and sink are reduced by maintaining the output node of all switches
connected to the output voltage. In this way, the nonideal voltage variation
applied to parasitic capacitors is reduced to the small level of the amplifier
offset voltage. However, the accuracy of the nonideal charge cancelation, espe-
cially in the lock state, can be limited by the inherent mismatching between
the n-channel and p-channel transistors.
The inherent mismatch between the nMOS and pMOS transistors can be
346 Data Converters, Phase-Locked Loops, and Their Applications

eliminated using the charge-pump circuit of Figure 6.26 [19]. Here, only nMOS
switches are required. The currents I1 and I2 are transferred to the output
when either the Up signal or the Dn signal assumes the high level. However,
the overall circuit performance can be limited by the dynamic range of the
current mirror T5 − T6 . In general, it should also be noted that performance
improvement is achieved at the price of a power consumption increase.

6.3.4 Loop filter

I I I I
V V V V
VDD T’ C
R T1
T VDD
T2 R
C Cp
C
(a) (b) (c)

FIGURE 6.27
(a) Circuit diagram and (b) CMOS implementation of a first loop filter; (c)
alternative MOS implementation and its equivalent circuit.

R2
I I
V V

R R1
C2 C2 C3
C1 C1

(a) (b)

FIGURE 6.28
Circuit diagrams of (a) second-order and (b) third-order loop filters.

The loop filter plays an important role in the determination of PLL character-
istics. Generally, it is designed based on the trade-off to be achieved between
the lock time, the phase noise, and the residual level of reference spurs. A large
loop filter bandwidth helps reduce the lock time, but is also associated with
a low attenuation of the phase noise and reference spurs, whereas a narrow
bandwidth leads to an improved suppression of the phase noise and reference
spurs while increasing the lock time. In practice, the order of the loop filter
is increased to satisfy the high attenuation requirement of all unwanted fre-
quencies beyond the cutoff frequency. However, the calculation of the loop
filter components then becomes cumbersome, and computer methods must be
employed.
The circuit diagram of a first-order filter is shown in Figure 6.27(a). It con-
sists of a resistor connected in series with a capacitor, and can be characterized
Circuits for Signal Generation and Synchronization 347

by a transfer function of the form

 
1 s
R s+ 1+
V (s) RC ωz
H(s) = = = (6.17)
I(s) s sC

where ωz = 1/RC. The closed loop of a PLL using a first-order filter is

characterized by a second-order transfer function due to the extra single pole
introduced by the VCO. Because the damping factor of the closed-loop transfer
function is inversely proportional to the zero at ωz , the loop bandwidth is
enlarged by decreasing the zero frequency. In the s-domain, the stability of a
second-order linear system is not affected by the loop gain.
Due to the fact that the loop filter generally requires a resistor with a high
resistance, the resistor R can be implemented using a CMOS transistor pair,
as illustrated in Figure 6.27(b). However, this simple approach may be limited
at low supply voltages, as the effective resistance of the CMOS transistor pair
becomes a function of the input node voltage (or VCO control voltage). An
alternative implementation of a first-order filter is shown in Figure 6.27(c). To
reduce the resistance dependence on the voltage, the resistor R, which is real-
ized by an nMOS transistor, is permutated with the pMOS transistor-based
capacitor. But, the equivalent model of the filter should take into account
the well-substrate parasitic capacitance, Cp , associated here with the MOS
capacitor structure.
For a second-order filter, as depicted in Figure 6.28(a), the transfer function
is given by

1 s
V (s) s+ 1+
RC1 ωz
H(s) = =  =   (6.18)
I(s) C1 + C2 s
sC2 s + sCT 1 +
RC1 C2 ωp

where ωz = 1/RC1 , ωp = (C1 + C2 )/RC1 C2 , and CT = C1 + C2 . In practice,

the filter components are designed to satisfy the constraints of robust stability,
and noise and spur rejection while keeping the component sizes as small as
possible.
To improve the suppression of the reference spurs while keeping the band-
width sufficiently large to meet the requirement of a high lock speed, a third-
order filter, as shown in Figure 6.28(b), can be used. This is achieved by setting
the pole frequency due to R2 and C3 to be lower than the reference frequency,
but higher than the loop bandwidth. Using the voltage division principle, the
voltage across the R1 C1 or C2 branch is of the form (sR2 C3 + 1)V (s). The
input current I is then given by

(sR2 C3 + 1)V (s) (sR2 C3 + 1)V (s) − V (s)

I(s) = + (6.19)
Z(s) R2
348 Data Converters, Phase-Locked Loops, and Their Applications

where  
1 1 R1 C1 s + 1
Z(s) = R1 + = (6.20)
sC1 sC2 R1 C1 C2 s2 + (C1 + C2 )s
Hence,
V (s) R1 C1 s + 1
H(s) = = (6.21)
I(s) D(s)
where

D(s) = R1 R2 C1 C2 C3 s3 +[R1 C1 (C2 +C3 )+R2 C3 (C1 +C2 )]s2 +(C1 +C2 +C3 )s
(6.22)
Finally, the transfer function, H(s), can be put into the form

s
V (s) 1+
ωz
H(s) = =   (6.23)
I(s) s s2
sCT 1 + +
ωp Qp ωp2

where

1
ωz = (6.24)
R1 C1
C1 + C2 + C3
ωp2 = (6.25)
R1 R2 C1 C2 C3
C1 + C2 + C3
ωp Qp = (6.26)
R1 C1 (C2 + C3 ) + R2 C3 (C1 + C2 )

and

CT = C1 + C2 + C3 (6.27)

Note that the use of a third-order loop filter has a considerable impact on the
design requirements, as the PLL can be prone to instability.

6.3.5 Voltage-controlled oscillator

Generally, an oscillator can be considered a feedback system similar to the
one in Figure 6.29(a).
The oscillator closed-loop transfer function can obtained as

V0 (s) A(jω)
= (6.28)
Vi (s) s=jω 1 + A(jω)

The system will oscillate at the frequency ω0 if A(jω0 ) = −1. The oscillation
Circuits for Signal Generation and Synchronization 349

Magnitude (dB)
A0

V i (s) Σ A(s) V 0 (s) Frequency (Hz)

Phase (rad)
(a)

−π

(b) Frequency (Hz)

FIGURE 6.29
(a) Linear model of an oscillator; (b) open-loop frequency response.

condition or Barkhausen criteria (see Figure 6.29(b)) can then be summarized

as

|A(jω0 )| = 1 (6.29)
arg[A(jω0 )] = −π (6.30)

The oscillatory feature of the system relies on the fact that the feedback signal
is added in phase to the forward one. A phase shift of π is introduced by the
negative feedback and the overall phase shift is 2π. In practice, the use of
the oscillation condition can be limited due to the component imperfections.
Then, an open-loop gain larger than unity at the desired oscillation may be
required in order to ensure the normal circuit operation.

• Fully differential VCO

A voltage-controlled oscillator (VCO) structure with a differential architecture
is shown in Figure 6.30 [20]. It consists of a loop of N delay stages with a
wire inversion. The ring will oscillate with a period of 2N times the stage
delay. The differential delay stage using a replica biasing circuit is depicted
in Fig 6.31(a) [20]. Fig 6.31(b) shows the circuit diagram of a differential
delay stage with symmetric loads. The tail current, which is applied to the
differential transistor pair T1 − T2 , is driven by T7 . The voltages Vc and VB are
generated by the replica biasing circuit, which should adjust the bias currents
of the delay stage to provide a wide tuning range over the temperature and
process variations.
An alternative structure of the delay cell, which also achieves a good power-
supply noise rejection, is shown in Figure 6.32 [15]. Transistors T5 − T6 should
fix the output voltage at the minimum value of VDD − VT , where VT is the
transistor threshold voltage, and set an output swing and a common-mode
level without the requirement for a replica biasing circuit. That is, the bias
current IB must be greater than the current, IL , flowing through the pMOS
350 Data Converters, Phase-Locked Loops, and Their Applications

−+ −+ −+ −+ V−
0

+− +− +− +− V+
0

FIGURE 6.30
Oscillator using differential delay stages.
V DD V DD
T T T T
4 6 4 6
VP T3 T5 Vc T3 T5

Vc
V+ V−
0 0
+ T2 T1 T1 T2
V +i V−
i

T8 T7 T
7
VB VB

(a) (b)

FIGURE 6.31
(a) Replica biasing circuit; (b) delay buffer.

transistor loads. A common practice is to have IB = 2IL . It should be noted

that the parasitic capacitance introduced at the output nodes by T5 − T6 can
limit the operating frequency range.
V DD

T8 T3 T4

T6 IL

T5
V+ V−
0 0
T9 T1 T2
V+
i V−
i

IB 2 IB

VP
T10 T7

FIGURE 6.32
Delay buffer using pMOS transistor diodes.

Let us consider a delay buffer consisting of a differential pair

loaded by transistors in the triode region. The related equivalent
model is shown in Figure 6.33.
Circuits for Signal Generation and Synchronization 351
VDD

RL CL RL CL

V+ V−
0 0
T1 T2
V+ V−
i i

2I B

FIGURE 6.33
Equivalent model of the delay buffer.

The differential output voltage can be written as

dV0 (t) V0 (t) IB
=− + (6.31)
dt RL CL CL
where RL is the output load capacitor and CL denotes the out-
put load resistor. An expression of V0 is then given by

V0 (t) = RL IB (1 − 2e−t/τ ) (6.32)

where τ = RL CL is the time constant. It was assumed that the

output voltage initially takes the value −IB RL and can increase
up to IB RL . The delay of the buffer can be defined as the time
required for the change of V0 from the initial value to zero, that
is,
td = ln(2)τ (6.33)
In practical circuits, the parameter Td involves a variable con-
tribution due to transistor noise. This delay uncertainty gives
rise to clock jitter. Using the relation
dV0 (t) IB
= (6.34)
dt t=td CL

the average jitter component can be obtained as

vn2 C2
△t2d = 2
= vn2 2L (6.35)
[(dV0 (t)/dt)|t=td ] IB

where vn2 denotes the voltage variance of the total noise.

It should be noted that an additional buffer may be required to provide the

single-ended version of the output signal [22]. Figure 6.34 shows the circuit
352 Data Converters, Phase-Locked Loops, and Their Applications

diagram of a differential-to-single-ended converter. Two source followers, a

differential stage, and two inverters are required in this design. The input
impedance of the buffer is increased by the source followers T6 −T7 and T8 −T9 ,
while the output drive capability is improved by the two inverters T10 − T11
and T12 − T13 .
VDD

T T T T
4 11 13
V+ 3
i T T
6 8

V−
i
V
0
T1 T2

T10 T12
VB
T T T
7 5 9

FIGURE 6.34
Differential-to-single-ended buffer.

Using a VCO, the jitter of the output clock is only affected by that of
the reference signal, because the loop acts as a lowpass filter. The periodicity
of the signal delivered by a VCO is useful in PLL applications such as clock
and data recovery. Furthermore, by inserting a frequency divider in the loop,
the output clock period can be a fraction of the reference signal to meet the
frequency synthesizer specifications.

• Pseudo-differential VCO
A delay stage can also be implemented using a pseudo-differential structure,
as shown in Figure 6.35. Cross-coupled inverters help align the complimentary
signal phases.

−+

+−

FIGURE 6.35
Pseudo-differential implementation of the delay stage using inverters.

An alternative VCO structure with quadrature outputs is represented in

Figure 6.36. It is designed by adding feedforward inverters between the nodes
with opposite signal phases of a ring of four inverters. A pair of cross-coupled
inverters exhibits a negative transconductance and can operate as a regen-
erative circuit whose positive feedback causes the switching of output levels.
Circuits for Signal Generation and Synchronization 353

VI VQ

VQ VI

FIGURE 6.36
Quadrature ring oscillator using inverters.

Assuming that each inverter stage exhibits a propagation delay of Td , the os-
cillation frequency is approximatively given by, f0 ≃ 1/(4Td). To sustain a
stable oscillation, feedforward inverters should be sized notably smaller than
other inverters. The oscillation frequency can be controlled by tuning the bias
current that is related to the inverter propagation delay.

+ + v1 v0
vi gm vi C0 v0
i g
0
− −

v2
(a) (b)

FIGURE 6.37
(a) Equivalent model of an inverter; (b) representation of a node of the ring
oscillator.

To analyze the ring oscillator, each inverter can be modeled as the

transconductance stage depicted in Figure 6.37(a), where gmi is the transcon-
ductance, g0 denotes the output conductance, and C0 is the output capaci-
tance. With reference to Figure 6.37(b), the following node equations can be
written

dv0 (t)
h1 gm v1 (t) + gL v0 (t) + CL =0 (6.36)
dt
dv0 (t)
h2 gm v2 (t) + gL v0 (t) + CL =0 (6.37)
dt

where hi (i = 1, 2) is the scaling factor of the i-th inverter, and gL and CL are
the output load conductance and capacitance, respectively. Combining (6.36)
354 Data Converters, Phase-Locked Loops, and Their Applications

and (6.37), we obtain a general expression given by

P
X dv0 (t)
G xi vi (t) + v0 (t) + τ =0 (6.38)
i=1
dt

where P = 2, xi = hi /P , G = gm /gL and τ = CL /gL represent the dc gain

and time constant, respectively.
The total phase shift around the loop should be a multiple of 2π, and
the waveforms at each inverter output and input nodes are assumed to be
sinusoidal and characterized by

v0 (t) = A cos(ωj t − φ) (6.39)

vi (t) = A cos(ωj t − φ × i)) (6.40)

where φ = 2πj/N and j is an integer that can take any value from 0 to
N − 1, with N being the number of input (or output) nodes (here N = 4).
Substituting (6.39) and (6.40) into (6.38) yields
P
X    
2πj 2πj
G xi cos ωj t − i + cos ωj t −
N N
i=1
  (6.41)
2πj
− ωj τ sin ωj t − =0
N

By expanding (6.41) and then equating the cos(ωj t) and sin(ωj t) terms, the
oscillation frequency and the required minimum dc gain for the j-th mode are
obtained as follows
 
P
P 2πj
xi sin (i − 1)
N
ωj τ = i=1   (6.42)
PP 2πj
− xi cos (i − 1)
i=1 N
1
G = Gj =   (6.43)
P
P 2πj
− xi cos (i − 1)
i=1 N

Initially, each inverter is in the linear region, where it can operate as a

transconductor. All oscillation modes characterized by a dc gain, Gj , that
is lower than the inverter gain, G, start to build up. They are then sustained
in the steady state provided the above frequency and gain equations are sat-
isfied.
In practice, however, the ring oscillator generates a signal that differs from
a sinusoidal waveform and may look like a triangular or square waveform
depending on the value of the inverter transition time. Hence, the oscillation
amplitude is determined by the nonlinear switching characteristic of inverters.
Circuits for Signal Generation and Synchronization 355

In the special case of a ring oscillator consisting of only one loop of single-
ended inverters, xP = 1 and all other xi coefficients are reduced to zero.
Because the oscillation condition requires a gain of −1 at dc, the number, N ,
of inverters should be odd. The oscillation frequency is given by
 
1 π
f0 = tan (6.44)
2πτ N
where τ denotes the time constant.

6.4 Applications
PLLs find use in a wide variety of applications, including, but not limited to,
frequency synthesizers, clock, and data recovery circuits.

6.4.1 Frequency synthesizer

Charge Loop
In PFD pump filter VCO Out

Frequency divider
N

FIGURE 6.38
Block diagram of a frequency synthesizer based on the PLL.

In general, a frequency synthesis consists of generating a desired frequency

from one or more reference signals, each at a given frequency and generated by
a precise crystal oscillator. The block diagram of a frequency synthesizer based
on the PLL is shown in Figure 6.38. It includes an integer-N programmable
divider in the feedback path. The output frequency is given by
f0 = N · fref (6.45)
where N is the division ratio and fref is the frequency of the input reference
signal.
Based on the continuous-time linear model of the PLL, the relationship
between the phase angles of the error, input, and output signals is of the form
Θe = Θi − Θ0 /N (6.46)
Assuming that the transfer functions of the filter and VCO are H(s) and
Kv /s, respectively, the closed-loop transfer function can be expressed as
Θ0 (s) G(s)
T (s) = = (6.47)
Θi (s) 1 + G(s)
356 Data Converters, Phase-Locked Loops, and Their Applications

and the error transfer function is

Θe (s) 1
Te (s) = = (6.48)
Θi (s) 1 + G(s)
where G(s) denotes the open-loop transfer function given by
Kp Kv H(s)
G(s) = (6.49)
sN
By reducing H(s) to a constant, the frequency synthesizer becomes a first-
order system that is unconditionally stable. However, in practice, the transfer
function of the loop filter should include a pole/zero pair, which is used to
increase the frequency range.
Although the linear model in the s-domain provides a helpful set of design
equations, a charge-pump-based PLL should be accurately described and op-
timized in the z-domain. The direct conversion of the PLL continuous-time
equations into the z-domain can be computationally intensive. For this rea-
son, the method based on the impulse invariant transformation1 is generally
adopted. The closed-loop transfer function is written as
b 0 (z)
Θ b
G(z)
Tb(z) = = (6.50)
b
Θi (z) b
1 + G(z)
where
b
Kp Kv H(z)
b
G(z) = (6.51)
N
and (   )
b −1 −1 H(s)
H(z) = (1 − z )Z L (6.52)
s2 t=nT /N

Here, T is the sampling frequency, and Z and L−1 denote the z-transform (or
modified z-transform) and inverse Laplace transform, respectively. Note that
the correspondence between the models is ensured only at the time nT /N .
b the value of the time-domain function should be zero
For the evaluation of H,
at the initial time instant.

Let us consider the third-order frequency synthesizer shown in

1 Let F (s) be the transfer function of a system in the s-domain. Using the impulse

invariant transformation, its z-domain version can obtained as

     
1 − e−T s F (s)
Fb(z) = Z F (s) = (1 − z −1 ) · Z L−1
s s t=kT
It is assumed that the equivalent discrete representation is provided by the series connection
of an ideal sampler with the sampling period T , a zero-order hold stage, and the analog
model of the system.
Circuits for Signal Generation and Synchronization 357
Charge pump
VDD
I1

Up VCO
In S1 I Loop filter
P
PFD VP Kv s Out
Dn
S2 R

I2 C

Frequency divider
N

FIGURE 6.39
Block diagram of a third-order frequency synthesizer.

20 log 10 G(s)/N 20 log 10 G(s)/N

−40 dB/dec −40 dB/dec

ωu ωp ωu
0 ω 0 ω
ωz ωz
−40 dB/dec −20 dB/dec
−20 dB/dec

G(s) G(s)
ωz ωu ωp ωz ωu
0 ω 0 ω

−90 o −90 o
φ φ
M M
−180 o −180 o

(a) (b)

FIGURE 6.40
Magnitude and phase of the open-loop transfer function: (a) C2 6= 0, (b)
C2 = 0.

Figure 6.39. The loop filter has a second-order transfer function

of the form
s
VP (s) 1+
ωz
H(s) = =   (6.53)
IP (s) s
sCT 1 +
ωp

where ωz = 1/RC1 , ωp = (C1 + C2 )/RC1 C2 , and CT = C1 + C2 .

358 Data Converters, Phase-Locked Loops, and Their Applications

The open-loop transfer function is given by

Kp Kv H(s)
G(s) = (6.54)
sN
s
1+
ω
= Kp Kv  z  (6.55)
s
s2 N CT 1 +
ωp

The combination of the PFD and charge-pump circuit can be

characterized by the gain factor, Kp = Ip /2π. The magnitude
and phase of the open-loop transfer function are depicted in Fig-
ure 6.40. At the frequency, ωu , the magnitude of the open-loop
transfer function is equal to 1 (or 0 dB).

To determine the zero and pole frequencies needed to obtain the

desired phase margin, we compute
   
o ωu ωu
φM = 180 − ∠G(jωu ) = arctan − arctan (6.56)
ωz ωp
where ωu is the unity-gain frequency. The phase margin is max-
imum for a value of ωu , which can be obtained by setting the
derivative of φM with respect to ωu equal to zero. That is,

dφM 1 1 1 1
= ·  2 − ·  2 = 0 (6.57)
dωu ωz ωu ωp ωu
1+ 1+
ωz ωp
and p
√
ωu = ωz ωp = ωz 1 + η (6.58)
where
η = C1 /C2 (6.59)
By substituting Equation (6.58) into (6.56), the maximum value
of φM is obtained as
!
p  1
φM = arctan 1 + η − arctan √ (6.60)
1+η

Recalling that arctan x + arctan y = arctan[(x − y)/(1 + xy)] and

solving Equation (6.60) for η gives
q
η = 2 tan2 φM + 2 tan φM 1 + tan2 φM (6.61)

The stability of the loop in the s-domain is guaranteed, provided

Circuits for Signal Generation and Synchronization 359

the capacitors are chosen such that Equation (6.61) is satisfied.

The phase margin can be selected between 30◦ and 70◦ . For a
PLL design with a high phase margin, a wide stability range is
traded off for a slow loop response speed and reduced attenu-
ation of the reference (or input) frequency. A common rule of
thumb is to begin the design with a 43◦ phase margin.
Given ωu and φM , the initial values of the filter components are
determined as follows. By definition, we have
s  2
ωu
1+
Kp Kv ωz
|G(jωu )| = 2
·s   =1 (6.62)
N CT ωu ωu 2
1+
ωp

By combining Equations (6.57) and (6.62), and recalling that

ωp /ωz = 1 + η and CT = C1 (1 + 1/η), it can be shown that
r
Kp Kv ωp Kp Kv η
= ·√ =1 (6.63)
N CT ωu2 ωz N C1 ωu2 1+η

Therefore, according to Equation (6.63), we find that

Kp Kv η
C1 = 2
·√ . (6.64)
N ωu 1+η

From Equations (6.58) and (6.59), we respectively obtain

√
1+η
R= (6.65)
ωu C1
and
C1
C2 = (6.66)
η
The s-domain analysis is limited by the fact that it does not
take into account the sampling nature of the loop. It is then not
suitable for the prediction of jitter performance and nonlinear
acquisition process. Simulations are necessary to fine-tune the
values of the filter components. Note that a fast settling response
requires a wide closed-loop bandwidth.
As a rule of thumb, the closed-loop bandwidth of a charge-pump
PLL should be chosen to be less than approximately one-tenth
of the reference frequency. Otherwise, the stability, speed, and
phase noise of a charge-pump PLL will be affected by the sam-
pling process.
360 Data Converters, Phase-Locked Loops, and Their Applications

Stability analysis in the z-domain

To take into account the sampling effects, it is necessary to per-
form the z-domain analysis of the loop [23, 24]. The open-loop
transfer function, G(s), can be converted from the s-domain to
the z-domain using the impulse invariant transformation. By
performing the partial expansion of G(s)/s, we obtain
 
G(s) Kp Kv 1 ωp − ωz 1 ωp − ωz 1
= + · − · (6.67)
s N CT s3 ω z ω p s2 ωz ωp2 s(1 + s/ωp )

The inverse Laplace transform of G(s)/s can then be written as

   
−1 G(s) K p K v t2 ω p − ω z ωp − ωz −ωp t
L = + t− (1 − e ) (6.68)
s N CT 2 ωz ωp ωz ωp2

The equivalent transfer function in the z-domain is given by

   
b z−1 −1 G(s)
G(z) = ·Z L (6.69)
z s t=kT

Using z transform tables, it can be shown that

b Kp Kv
G(z) = ×
N CT
 2  (6.70)
T z+1 ωp − ωz T ωp − ωz 1 − e−ωp T
· + · − ·
2 (z − 1)2 ωz ωp z − 1 ωz ωp2 z − e−ωp T

or equivalently,

Kp Kv pz 2 + qz + r
b
G(z) = (6.71)
N CT z 3 − (2 + α)z 2 + (1 + 2α)z − α

where

α = e−ωp T (6.72)
2   
T T 1−α ωz
p= + − 1− (6.73)
2 ωz ωz ωp ωp
  
T 2 (1 − α) T (1 + α) 2(1 − α) ωz
q= − − 1− (6.74)
2 ωz ωz ωp ωp
2   
T α Tα 1 − α ωz
r=− + − 1− (6.75)
2 ωz ωz ωp ωp

and T denotes the period of the clock signal. The parameter of

the charge-pump PLL should then be chosen such that the roots
b
of the characteristic equation, 1 + G(z), remain inside the unit
Circuits for Signal Generation and Synchronization 361

circle defined by |z| = 1 in the z-plane. In general, the stability

condition in the z-domain is more constraining than that in the
s-domain.

Time-domain analysis
The operation or acquisition process of a charge-pump PLL can
be accurately modeled using a time-domain analysis based on
difference equations and state-space representation. The input
phase, θi , and the output phase, θ0 , are related by difference
equations of the form

θi (t) = θi (0) + ωi t (6.76)

Z t
θ0 (t) = θ0 (0) + ωv t + Kv vp (τ )dτ (6.77)
0
θe (t) = θi (t) − θ0 (t) (6.78)

where θe is the phase error, ωi represents the input frequency,

ωv is the free-running frequency of the oscillator, Kv is the VCO
gain, and vp denotes the output voltage of the loop filter or the
VCO control voltage, which is identical to the voltage across the
capacitor C2 . It was assumed that the initial conditions for the
input and the output phases are ωi (0) and ω0 (0), respectively.
The state-space representation of the filter can be written as

dvp vp vC1 ip
=− + + (6.79)
dt RC2 RC2 C2
vC1 vp vC1
= − (6.80)
dt RC1 RC1
where vC1 represents the voltage across the capacitor C1 and ip is
the charge-pump output current, which is used to drive the loop
filter. Assuming that the output capacitor of the charge-pump
circuit is either charged for a positive phase error or discharged
for a negative phase error, the current ip is given by
(
Kp · sign(θe ) if 0 ≤ t ≤ tp
ip = (6.81)
0 if tp < t < tr

where Kp represents the gain associated to the PFD and charge-

pump circuit, sign(θe ) denotes the polarity (i.e., 1 or −1) of the
phase error, θe , tp represents the turn-on duration of the current
IP , and tr is the time at which the next rising edge of either the
VCO or the reference signal occurs. Tools for symbolic analy-
sis can be used to solve the system of equations characterizing
the charge-pump PLL. By using linear models, the analysis is
362 Data Converters, Phase-Locked Loops, and Their Applications

valid only near locked states. However, due to the fact that the
PFD, for instance, is actually a nonlinear and time-variant com-
ponent, the loop may be affected by nonlinear mechanisms such
as cycle slip, which is caused by a large frequency difference be-
tween the reference signal and the feedback signal. In practice,
this difference is minimized by setting the initial control voltage
appropriately, and thereby facilitating the acquisition process.

Note that the synthesis of a frequency, which is N/M times the reference
frequency, can simply be performed by adding a divider with a ratio of M at
the input of the PLL.
The aforementioned topology is commonly used due to its simplicity. How-
ever, the output frequency can only change by integer multiples of the refer-
ence frequency. Furthermore, the reference spurs, which appear centered on
the reference frequency and its harmonics, are related to the amount of jitter in
the retimed signals. Hence, the achievable resolution of the output frequency
is limited because the loop bandwidth, as set by the loop filter, should be at
least ten times smaller than the reference frequency to prevent undesirable
signal components caused by the sampling action in the phase detector from
reaching the input of the VCO and corrupting the output frequency. This can
result in a slow settling (or lock) time for the frequency synthesizer.

Charge Loop
In PFD pump filter VCO Out

Frequency
CK divider

Σ∆ digital
N modulator

FIGURE 6.41
Block diagram of a ∆Σ fractional-N frequency synthesizer.

To overcome the resolution-bandwidth trade-off of integer-N frequency

synthesizers, a ∆Σ fractional-N architecture can be used [27]. This last ap-
proach is capable of generating frequencies over wide bandwidths with a very
fine frequency resolution to accommodate the narrow channel spacing of wire-
less telephony applications. The block diagram of a ∆Σ fractional-N frequency
synthesizer is depicted in Fig 6.41. It is generally based on the concept of divi-
sion ratio averaging, which is implemented using a PLL whose feedback path
includes a multi-modulus divider controlled by a ∆Σ modulator. The divi-
sion ratio is dynamically switched between two or more values to realize the
fractional frequency division.
An dual-modulus frequency divider can be implemented as shown in Fig-
Circuits for Signal Generation and Synchronization 363

D Q D Q
1 2
CK Q CK Q F
0
F
i
Mod 0 Q CK
3
Q CK Q D
4 Mod i
Q D

In F F F F F F F F
i 0 i 0 i 0 i 0
2/3 counter 2/3 counter 2/3 counter 2/3 counter
Mod 0 p Mod i Mod 0 p Mod i Mod 0 p Mod i Mod 0 p Mod i

Out

CK Q CK Q CK Q CK Q

p D Q p D Q p D Q p D Q
0 1 N−2 N−1

FIGURE 6.42
Block diagram of a dual-modulus frequency divider.

b+1 1
K Σ p
k
Quantizer
z −1 z −1

FIGURE 6.43
Block diagram of a second-order ∆Σ modulator.

ure 6.42. This modular structure consists of a plurality of 2/3 counters ar-
ranged in a cascade combination [28]. Each 2/3 counter realizes a division by
a factor of 2 or 3, depending on whether the control signal pk is set to a logic
state 0 or 1.
In operation, the prescaler logic block of each 2/3 counter first divides the
frequency of the incoming signal, Fi , and the resulting signal, F0 , is applied
to the following counter cell. The division ratio is determined by the logic
state of the control signals applied to the end-of-cycle logic block of each 2/3
counter cell. Upon completion of a division cycle, the end-of-cycle logic block
of the last 2/3 counter cell in the divider chain generates a signal, M od0 ,
which is transferred successively to the preceding 2/3 counter cells after being
retimed by each cell. The division cycle corresponds to the clock period of
the F0 signal available at the output of the last 2/3 counter, whose M od0
terminal can serve as the divider output. To avoid the perturbation of the
364 Data Converters, Phase-Locked Loops, and Their Applications

current division operation, the updated control signals for the division ratio
should transit through latches, which are synchronized with the respective
division cycle, on their way to each 2/3 counter cell. A new division ratio can
be set only when a division cycle is completed.

The basic principle of the 2/3 counter cell can be extended to any
P/(P + 1) cell. Even if the division ratio of each counter cell of the
frequency divider is an integer at any instant, its repetitive switching
between the integers P and P + 1 by the modulator will give rise to a
fractional division with a ratio comprised between these last two integer
values. With the division ratio equal to P during (1 − η)T and P + 1
during ηT over a time period of T , the average output frequency is given
by
F0 = [η(P + 1)T + (1 − η)P T ]fref /T = (P + η)F i , (6.82)
where Fi is the input frequency of the P/(P + 1) counter and η is deter-
mined by the modulator output.

The overall division ratio of the frequency divider can be put into the form

N = 2n + 2n−1 pn−1 + 2n−2 pn−2 + · · · + 2p1 + p0 (6.83)

where p0 , p1 , · · · , pn−1 denote the control signal logic states from the first to
the last 2/3 counter. Using n 2/3 counter cells in cascade, the possible division
ratios range from 2n (if all pk = 0) to 2n+1 − 1 (if all pk = 1).
The block diagram of a second-order ∆Σ modulator is depicted in Fig-
ure 6.43. Generally, the data word length in the modulator should be long
enough to prevent the occurrence of an overflow in the first accumulator.
Based on simulations, it was shown in [27] that the parameters K and M can
be adequately chosen as −0.5M < K < 0.5M and M < 2b /2.5, where b is the
accumulator word length. The computation resolution, which is initially set
to b bits, is increased to b + 1 bits in certain steps to accommodate possible
numerical overflows in the adders. The quantization operation is reduced to
the overflow of the second adder, the sign bit of which is used as the modulator
output.
Using a linear model of the modulator, the z-transform of the output can
be expressed as

H(z) 1
Pk (z) = K(z) + EQ (z) (6.84)
1 + M · H(z) 1 + M · H(z)
where EQ is the quantization error and

2 − z −1
H(z) = (6.85)
(1 − z −1 )2
Circuits for Signal Generation and Synchronization 365

At dc, or z = 1, and M · H(z) ≫ 1, we can obtain

K EQ
Pk ≃ + (6.86)
M M ·H
For a slow-varying input signal, the time average of the binary output sequence
produced by the modulator is a high-resolution representation of the value
K/M .
A problem generally associated with ∆Σ fractional-N frequency synthesiz-
ers is the increased level of in-band spurs. Ideally, the PFD and charge-pump
circuits should deliver an output signal that is proportional to the phase dif-
ference between the reference and feedback signals. However, their practical
characteristics are not fully linear. In the lock condition, the phase difference
can still take different values due to the changing division ratio in the feedback
path. This in turn stimulates nonlinearities of the PFD and charge-pump cir-
cuits, generating a noise floor that boosts the in-band phase noise. Note that
the use of a higher-order ∆Σ modulator helps reduce the in-band quantization
noise, but at the price of an increased level of the out-of-band noise.

−60

−80

−100
Phase noise (dBc/Hz)

−120

−140

−160 Total
VCO
−180
∆Σ
−200 PFD

−220
4 5 6 7 8
10 10 10 10 10
Frequency offset (Hz)

FIGURE 6.44
Noise figure of narrow-band PLL.

The typical ratio of the PLL bandwidth to the phase detector frequency
is less than 1/100 in wireless and wireline applications, but only less than
1/15 in digital system applications such as the clock signal generation for a
microprocessor and high-speed I/O link systems.
Figures 6.44 and 6.45 show the noise contribution of each block in a narrow-
band PLL and a wide-band PLL, where the PLL bandwidth is about 100
kHz and 1 MHz, respectively, and the clock frequency is assumed to be 25
MHz. The VCO noise determines the overall phase noise performance in the
narrow-band PLL, while quantization noise of the ∆Σ modulator is dominant
at high frequencies in the wide-band PLL. The choice of the loop bandwidth
in the design of a wide-band ∆Σ fractional-N PLL is eventually limited by
366 Data Converters, Phase-Locked Loops, and Their Applications
−60

−80

−100

Phase noise (dBc/Hz)

−120

−140

−160 Total
VCO
−180
∆Σ
−200 PFD

−220
4 5 6 7 8
10 10 10 10 10
Frequency offset (Hz)

FIGURE 6.45
Noise figure of wide-band PLL.

the quantization noise and can involve a trade-off between the minimization
of the quantization noise and VCO noise.
Several techniques can be used for quantization noise reduction either in
the analog or in the digital domain. DAC-based noise canceling and phase
rotator-based fractional division are two approaches to reduce the quantiza-
tion noise. However, the level of noise reduction with both techniques can be
limited by the linearity and matching requirements of analog components. Al-
ternatively, in order to suppress the quantization noise at certain frequencies,
a digital finite-impulse-response filter can be inserted along the path of the
control bits generated by the ∆Σ modulator.

6.4.2 Clock and data recovery

In serial data transmissions, the signal is generally distorted by the transmis-
sion channel (coaxial cable, optic fiber). Because it is generally impractical to
transmit the necessary sampling clock signal separately from data, the timing
information is usually derived from the transmitted data, which are asyn-
chronous and noisy. This is realized using a clock recovery circuit, which can
be based on a PLL structure. With reference to Figure 6.46, the incoming data
should be retimed by the D flip-flop, which is synchronized by the recovered
clock signal in such a way that the sampling clock edge is aligned with the
middle of the data bit period in order to minimize the bit-error rate.
A clock and data recovery (CDR) circuit, which relies on a PLL consisting
of a phase detector, a charge-pump circuit, a filter, and a VCO, is generally
unable to capture the incoming data if the free-running frequency of the VCO
is more than a few hundred parts-per-million (ppm) from the frequency of the
input data.
With the VCO free-running frequency exhibiting a wide variation over
the IC process, temperature, and supply voltage, it is impossible for the PLL
Circuits for Signal Generation and Synchronization 367

Di D Q D0
(Noisy data) (Retimed data)
Q
Clock
recovery CK (Recovered clock)
circuit

FIGURE 6.46
Principle of a clock and data recovery circuit.

to lock under all circumstances without relying on a frequency acquisition

aid. Hence, the PLL used for clock and data recovery applications can be
configured to include a frequency loop and a phase loop. The first one achieves
the clock signal frequency acquisition by reducing the difference between the
free-running frequency of the VCO and a reference frequency, while the second
one is enabled for the phase locking of the clock signal with the incoming data
signal. A PLL with a dual-loop configuration may be implemented with or
without an external reference clock signal.

TABLE 6.1
CDR Structure Comparison
CDR circuit based on
Dual loop PI GVCO
Wide bandwidth Good Not good Very good
Power efficiency Not good Good Good
Fast locking Not good Not good Very good
Capture range Wide Narrow Narrow

In addition to dual-loop PLLs, other structures can be used for the imple-
mentation of CDR circuits. They can be based on a phase interpolator (PI)
and a gated voltage-controlled oscillator (GVCO). Table 6.1 provides a com-
parison of their essential characteristics, especially for multi-lane applications.

VDD
I1

Up VCO
Din S1 I Loop filter
Binary P CK I
VP Kv s
PD Dn CK Q
S2 R
C2
I2 C1

FIGURE 6.47
Block diagram of a single-loop binary CDR.
368 Data Converters, Phase-Locked Loops, and Their Applications

A single loop that can be used for phase tracking in a CDR circuit is shown
in Figure 6.47. It consists of a binary phase detector, a charge pump, a loop
filter, and a quadrature VCO. In the lock state, the edge of the clock signal,
CKI , should be aligned with the center of the data eye.

Stability in the z-domain of the single-loop CDR based

on a binary PD
To take into account the sampling effects, it is necessary to per-
form the z-domain analysis of the loop [23,24]. Using the impulse
invariant transformation [25], the response in continuous-time
can be related to one in the discrete-time as follows,

ĝ(n) = [pτd (t) ∗ g(t)]|t=nT (6.87)

Z ∞
= pτd (t)g(t − τ )dτ (6.88)
−∞ t=nT

or equivalently

Z −1 {Ĝ(z)} = L−1 {Pτd (s)G(s)}|t=nT (6.89)

where pτd (t) and g(t) are the impulse responses associated to
the transfer functions Pτd (s) and G(s), respectively.

p(t) p (t)
τd τd
1 1

t t
0 T 0 τd T
(a) (b)

FIGURE 6.48
(a) Ideal PD pulse; (b) PD pulse with delay.

In the ideal case, the PD output sequence is supposed to be gen-

erated without a delay. However, in a practical implementation,
it exhibits a delay, τd , due to the switching speed of gates and
transistors, as shown in Figure 6.48. To take into account the
effect of the delay, τd , on the stability in the z-domain, the loop
delay can be put into the form,

Td = q · T + τd (6.90)

where T is the clock signal period, 0 ≤ τd < T , q = ⌊Td /T ⌋, and

⌊x⌋ denotes the largest integer not greater than x.
The PLL open-loop transfer function, G(s), can then be con-
verted from the s-domain to the z-domain using the impulse-
invariant transformation. By performing the partial expansion
Circuits for Signal Generation and Synchronization 369

of G(s), we obtain
  
Kp Kv 1 ωp − ωz 1 1
G(s) = + − (6.91)
N · CT s2 ωz ωp s s + ωp
Using the s-to-z domain equivalences given in Table 6.2, the
impulse-invariant transform of the PLL transfer function can be
obtained as,

Kp Kv T 2 αz 3 + βz 2 + γz + δ
Ĝ(z) = (6.92)
2 · N · CT z q+1 (z − 1)(z − z0 )
where
 2   
τd 2 ωp − ωz τd z0 z1 − 1
α= 1− + 1− + (6.93)
T T ωz ωp T ωp T
2
(2 + z0 )τd 2(1 + z0 )τd
β = 1 − z0 − 2
+
 T  T 
2 ωp − ωz (2 + z0 )τd 2 + z0 − 3z0 z1
− 1 + z0 − − (6.94)
T ωz ωp T ωp T
(1 + 2z0 )τd2 2z0 τd
γ = −z0 + 2
−
T  T 
2 ωp − ωz (1 + 2z0 )τd 1 + 2z0 − 3z0 z1
+ z0 − − (6.95)
T ωz ωp T ωp T
 2
  
τ 2 ωp − ωz τd 1 − z1
δ = z0 − d2 + + (6.96)
T T ωz ωp T ωp T
z1 = exp(ωp τd ) (6.97)

and

z0 = exp(−ωp T ) (6.98)

θi Σ G(z) θ0

FIGURE 6.49
PLL linearized model in the discrete-time domain.

Based on the PLL linearized model of Figure 6.49, the closed-

loop transfer function can be written as,

θ0 (z) Ĝ(z)
= (6.99)
θi (z) 1 + Ĝ(z)
370 Data Converters, Phase-Locked Loops, and Their Applications

TABLE 6.2
Impulse Invariant Transformation: s-to-z Domain Equivalences

s domain z domain

1 T z(1 − τd /T ) + τd /T
·
s zq z(z − 1)

1 1 z(1 − z0 z1 ) + z0 z1 − z0
q
·
s + ωp ωp z z(z − z0 )
where z1 = exp(ωp τd ) and z0 = exp(−ωp T )

1 T 2 z 2 (1 − τd /T )2 + z(1 + 2τd /T − 2τd2 /T 2) + τd2 /T 2

·
s2 zq 2z(z − 1)2

In general, the stability condition2 in the z-domain is more con-

straining than that in the s-domain. The parameters of the
charge-pump PLL should be chosen such that the roots of the
characteristic equation, 1 + Ĝ(z), remain inside the unit circle
defined by |z| = 1 in the z plane.
A useful stability condition can be derived by relating the anal-
ysis of the locus behavior to the radius of curvature (see Ap-
pendix B.1) [26]. The open-loop transfer function, Ĝ(z), has a
pole of order q + 1 at z = 0, a pole at z = r0 (along the real
axis and inside the unit circle), and two poles at z = 1. For the
charge-pump PLL to be stable, it is required that the root locus
departing at z = 1 should first migrate inside the unit circle
before it can cross the unit circle. That is,

RC1 > (1 + C2 /C1 )(Td + T /2) (6.100)

This last condition is more conservative than the requirement

to have all poles inside the unit circle, but an obvious advantage
is its simplicity due to the linear behavior.
2 Based on Jury test, a charge-pump PLL characterized in the z-domain by a third-order

(q = 0) closed-loop transfer function with a denominator of the form,

D(z) = a3 z 3 + a2 z 2 + a1 z + a0
is stable provided
D(1) > 0, D(−1) < 0, |a0 | < a3
and
|a20 − a23 | > |a0 a2 − a1 a3 |
Circuits for Signal Generation and Synchronization 371

Control
voltage/code

Current−starved
inverter
CT CT CT

(a) (d)

b1 b2 bN
VDD VDD
VC − T7 T6 T4 T4 IDAC 2 N−1
C 2C 2 C
+
I CP
I CP
T2
T2
IC Vi V0 Vi V0
T1 T1
R bN b N−1 b1
I CN
I CN VDD I 2I 2 N−1I
T5 T3 T3 IDAC 1 VB

(b) (c)

FIGURE 6.50
(a) Ring VCO based on current-starved inverters; (b) current-starved inverter
with variable bias voltage; (c) current-starved inverter using a digital tuning
code; (d) VCO based on inverters with variable load capacitors.

VDD MIM Capacitor Varactor

L L
C array
N−1
2 C
VC
bN
+
V0
−
V0
T3 T4
2C
b2
T1 T2 C
b1
C min
TB 0
VB

FIGURE 6.51
LC VCO with coarse and fine tunings.

PLL and CDR circuits can be implemented using either ring or LC oscilla-
372 Data Converters, Phase-Locked Loops, and Their Applications

tors. Ring oscillators, as shown in Figure 6.50(a), consist of delay stages that
can easily be designed. They are scalable, exhibit a wide tuning range, and
can inherently provide multi-phase output signals.
A current-starved inverter can be tuned by varying the bias voltage, as il-
lustrated in Figure 6.50(b). Assuming that transistors T6 and T7 operate in the
saturation region and VGS6 = VGS7 , we obtain ID6 /(W6 /L6 ) = ID7 /(W7 /L7 ),
provided that the threshold voltages of both transistors are identical. Due to
the high gain of the amplifier, V + ≃ V − = VC . Hence, ID7 = IC = VC /R.
Another tuning approach consists of using switched current-sources con-
trolled by a digital code, as shown Figure 6.50(c).
Inverters can also be tuned by means of variable load capacitors, as shown
in Figure 6.50(d).
However, VCOs based on ring oscillators feature a poor phase noise per-
formance compared to LC VCOs. Figure 6.51 shows the circuit diagram of
the LC VCO. Coarse tuning can be performed using either switched metal-
insulator-metal (MIM) capacitor arrays, or MOS varactors that are switched
between accumulation and depletion regions.
The accuracy of MIM capacitor arrays can be limited by the parasitic
components of switches. On the other hand, MOS varactors are known to
exhibit a large capacitance spread (or ratio between the capacitances when a
varactor is turned on and off, respectively), and can then also be employed for
fine tuning. The bias-dependent capacitance is proportional to the number of
gate fingers used in the layout, the gate length and width. The capacitance
spread is maximized when transistors are configured with minimum finger
length.

6.4.2.1 Dual-loop CDR

A dual-loop CDR is first locked to the frequency of an external oscillator
that is close to a fraction of the data rate, and then the phase is adjusted to
appropriately align the clock signal edges and data outputs.

D0 1
MUX

Phase 0
Di detector Charge Loop
pump filter VCO CK
1
MUX

0 Up D Q
FL 1
Q
RCK Lock FL
PFD detector
Dn D Q
2
Frequency Q
divider

FIGURE 6.52
Block diagram of a dual-loop PLL requiring an external reference clock signal.
Circuits for Signal Generation and Synchronization 373

Referring to Figure 6.52, the block diagram shows a dual-loop PLL [29]
requiring a reference clock signal. Before the closing of the data-acquisition
loop by the lock detector, the frequency-acquisition loop should bring the
VCO free-running frequency near the desired operating range, if necessary.
The data-acquisition loop minimizes the remaining frequency error and aligns
the phase of the VCO for an optimal sampling of the incoming data. The lock
detector continuously monitors that the difference between the reference signal
frequency and the divider output frequency remains within a predetermined
range.
An approach to perform the lock detection can consist of monitoring the
Up and Dn pulses that are generated by the three-state PFD [30]. This can
simply be realized, as shown in the inset of Figure 6.52, by a lock detector
structure whose components are two D flip-flops, inverters, and a NOR gate.
The output signal FL is set to the high logic state indicating the frequency-
locked mode only in the case where the Up and Dn pulses are at the low logic
state. When the Up and Dn signals are in different logic states due to the fact
that one of the PFD inputs is leading or lagging the other, the output signal
FL is maintained to the low logic state. Depending on the signal propagation
delay, the resulting error in the detection of phase alignment between the Up
and Dn pulses is within 5 to 15% of the full-scale phase deviation of the PFD.
Another scheme for implementing the lock detector relies on the use of a
counter-based frequency comparator to monitor the reference clock frequency
and the divider output frequency [31]. The choice of Gray counters may help
reduce the occurrence of latch metastability due to the fact that the reference
clock and the divider output signal can be asynchronous with each other.
After a given time period, the lock detector determines whether or not the
frequency difference between the two signals is within a predetermined range.
The counters should then be reset before the beginning of the next counting
interval.

D0

Phase Charge CK I
detector pump 1 VCO
Di
R
Frequency Charge C2
detector pump 2
RCK I D Q D Q C1
1 3 Up
Di Q Q

RCK Q CK Q
Divider
RCK Q D Q
2 Dn RCK I CK I
Q Divider

FIGURE 6.53
Block diagram of a dual-loop PLL without a reference clock signal.

A dual-loop PLL can also be designed to operate without a reference clock

signal, as shown in Figure 6.53. It requires two separate charge pumps driven
374 Data Converters, Phase-Locked Loops, and Their Applications

by a phase detector and a frequency detector, respectively. In one implemen-

tation of the frequency detector, three D flip-flops and two AND gates are
necessary [32]. During the frequency acquisition, the frequency detector deliv-
ers Up and Dn signals with a frequency that is equal to the difference between
the input data frequency and quadrature clock signal frequency. When the
free-running frequency of the VCO is set within the loop capture range, the
Up and Dn signals are maintained at a low logic level. It is then not necessary
to disable the frequency detector, which can continuously track the frequency
changes without affecting the operation of the data acquisition loop. Because
the VCO is equivalent to a gain element in the frequency domain, a zero
is not needed in the transfer function of the filter included in the frequency
loop. Hence, the charge-pump circuit controlled by the frequency detector is
connected to the node between the resistor R and capacitor C1 .
With Vc being the control voltage delivered by the loop filter in response
to the charge-pump current Ip , the filter impedance function can be expressed
as
Vc (s) N (s)
Z(s) = = (6.101)
Ip (s) sC2 (s + ωp )
where ωp = (C1 + C2 )/RC1 C2 . Assuming that ωz = 1/RC1 , the numerator
is given by N (s) = s + ωz for the data acquisition loop or N (s) = 1 for the
frequency acquisition loop.
The signal CKQ is 90o out of phase with the signal CKI . By implementing
the VCO as a four-stage ring oscillator, the quadrature signals, CKI and CKQ ,
are available at the outputs of two of the stages. The input range of the FD
can be numerically predicted to be on the order of 25% of the desired VCO
free-running frequency.
Dual-loop CDRs are not power efficient because an individual PLL is re-
quired for each lane. The PI-based CDR improves the power efficiency by using
a single PLL that is shared by all lanes, while the GVCO-based CDR uses a
single PLL that sets the control signal for all lanes. In a PI-based CDR, the PI
resolution is generally limited due to the conflicting design trade-offs between
linearity, area, and power consumption. As a result, the phase step that is pro-
duced when the PI switches from one phase to another can contribute to the
jitter generation. In contrast to PI-based structures, GVCO-based CDRs take
advantage of the injection to simultaneously detect and adjust the phase in
relation to the incoming data, resulting in a wide bandwidth and a small lock-
ing time. However, the capture range (or the jitter tolerance) of GVCO-based
CDRs can be limited by mismatches between GVCOs.

6.4.2.2 Phase interpolator-based CDR circuit

A CDR circuit can also be based on phase interpolator (PI), as shown in
Figure 6.54. This architecture is generally adopted in high-speed serial links
to avoid the need of using a PLL for each of the input/output pins [33]. A single
PLL then generates in-phase and quadrature clock signals that are distributed
Circuits for Signal Generation and Synchronization 375

to all channels. It is connected via the voltage-controlled oscillator to the data

recovery circuit section. The PI converts the generated clock signals into a
signal with the optimal phase for data recovery.

RCK

PD FSM & DLPF PI

Di

I Q
CK
PFD CP LPF QVCO

N
Frequency divider

FIGURE 6.54
Phase interpolator-based CDR.

VDD

RL RL

VCK
out

− −
VI VQ
+ T2 T4 + T6 T8
VI T1 T3 VQ T5 T7

IS IS QS QS

S1 S1 S 2 S2 S 2 P−2 S 2 P−2

TB TB TB
VB 1 VB 2 VB N

FIGURE 6.55
Phase interpolator (PI).

The PI-based CDR consists of a PLL that generates a quadrature clock

signal at the data rate of the input data and a data recovery circuit that
aligns the clock signal phases to the transitions on the incoming data stream.
The data recovery loop includes a phase detector (PD), a finite-state machine
(FSM) and a digital lowpass filter (DLPF), and a PI. A binary PD (or bang-
bang PD) provides signals that are related to the sign of the sampling phase
error between an interpolated version of the clock signals and transitions of
the input data. The following FSM includes demultiplexers (or deserializer),
376 Data Converters, Phase-Locked Loops, and Their Applications
S1
M Log 2 (M)

Binary−to−thermometer
Up 1:M DMUX S1
Counter
P S2

encoder
Σ Σ z 1 S2
P−2
Dn 1:M DMUX
Counter S 2 P−2
S 2 P−2
M
IS

2−out−of−4
decoder
IS
CK out 2 MSBs QS
QS

FIGURE 6.56
Finite-state machine and digital lowpass filter.

D Q D Q
1
Q Q

D Q
2 D0
Q
D2

D4
In
D6
Out
D1

D3

D5

D7
CK 2 2 2

D Q

FIGURE 6.57
Circuit diagram of a 1-to-8 demultiplexer.

roll-over counters, and a summer. Its output is applied to a digital lowpass

filter, that is based on an integrator, to generate a P -bit binary code. This
latter is used to configure the phase interpolator so that one out of 2P phases
is selected each time to align the sampling clock to the center of the input
data. Circuit diagrams of the PI, demultiplexer, FSM, and DLPF are shown
in Figures 6.55, 6.56, and 6.57, respectively.
Circuits for Signal Generation and Synchronization 377
o
90
+
MSB MSB−1 IS IS QS QS VQ
+ +
0 0 1 0 1 0 VI VQ
− +
− + VI VI
0 1 0 1 1 0 VI VQ o
180 0
− −
1 0 0 1 0 1 VI VQ
+ −
1 1 1 0 0 1 VI VQ V−
Q

o
270
(a) (b)

FIGURE 6.58
(a) MSB decoding table; (b) quadrant illustration on the clock phase circle.

The PI produces an output clock signal that is a weighted sum of the

quadrature clock signals, VI and VQ . Hence,

VCKout = αVI + (1 − α)VQ (6.102)

where VI = VI+ − VI− , VQ = VQ+ − VQ− , and 0 ≤ α ≤ 1 and α represents a

linear weighting coefficient. By using a P -bit digital code for the PI control,
the phase quadrant (or the I/Q polarity) can be selected by two most sig-
nificant bits (MSBs), while each quadrant is subdivided into 2P −2 steps that
are associated to the combinations of other P − 2 bits. Figure 6.58 shows the
MSB decoding table and quadrant illustration on the clock phase circle. A
2-bit selection of the I/Q polarity allows for a complete 360◦ phase rotation
with the phase step determined by a weighting digital-to-analog converter
with a resolution of P − 2 bits. By choosing the weighting coefficients as α
and 1 − α, the PI can generate arbitrary phase shifts from 0◦ to 360◦ . To
simplify the implementation, the phase interpolation is based on weighting
coefficients that are linear functions of the clock phase, instead of sinusoidal
functions generally associated to a phasor rotating in a circle. The resulting
signal amplitude variation has no detrimental effect on the data sampling that
essentially depends on zero-crossings of the clock signal.

6.4.2.3 CDR circuit based on a gated VCO

CDR circuits based on PLL are characterized by a wide capture range and a
good jitter rejection performance, and generally find applications in systems
(serial links) operating in continuous mode. A fast acquisition time is often
not required because a steady and uninterrupted stream of bits is transmitted.
For burst-mode systems, such as asynchronous transfer mode (ATM) net-
works and local area networks (LANs), where data are transmitted only for
a limited period of time, the acquisition time should be minimized in order
to meet the low latency requirement. In this case, suitable CDR architectures
can be based on an injection locked oscillator or gated oscillator [34].
The circuit diagram of a CDR based on a gated VCO is shown in Fig-
378 Data Converters, Phase-Locked Loops, and Their Applications
D Q D0

Edge detector

Di

RCK

CK
PD CP LPF

Gated VCO

FIGURE 6.59
CDR based on a gated VCO.

Lock time Lock time

Control voltage (V)

Control voltage (V)

Cycle
slip

0 0
(a) Time (s) (b) Time (s)

FIGURE 6.60
Representation of the oscillator control voltage in a CDR (a) without phase
reset and (b) with phase reset.

ure 6.59. It is composed of a PLL section which tracks the clock signal fre-
quency and a data recovery section that achieves the phase acquisition (or
aligns the clock transition to the center of the data eye). The PLL section
includes a binary phase detector (PD), a charge-pump (CP) circuit, a lowpass
filter (LPF), and a gated VCO (GVCO). The data recovery section consists
of an edge detector and a GVCO. The recovered clock signal (RCK) is used
to trigger the D flip-flop that provides the recovered data, Dout . By using a
GVCO, the phase of the recovered clock can be periodically reset to prevent
a cycle slip. The delay of the edge detector is typically sized so that a rising
edge of the clock signal is located at the center of the data eye whenever the
oscillation resumes.
The PD is designed to track phase variations and its performance remains
limited in the presence of frequency variations. In this latter case and during
the pull-in process, the VCO control voltage is adjusted to minimize the dif-
ference between the VCO output frequency and the data rate at the input. To
minimize the frequency error in a CDR without phase reset, the VCO control
Circuits for Signal Generation and Synchronization 379

voltage can alternatively be changed in the right and wrong directions, leading
to a cycle slip, as shown in Figure 6.60(a). The cycle slip process is due to
the PD periodic output. On the other hand, in a CDR with phase reset, the
VCO control voltage tends to keep moving in the same direction, preventing
a cycle slip and resulting in a reduced lock time, as shown in Figure 6.60(b).
The GVCO oscillation frequencies should match the data rate. Once the
GVCO control voltage reaches the steady state, the GVCO is no longer reset
and the CDR circuit can now operate normally by aligning the clock signal
with data sampling instants.
However, in practice, the tolerance of the CDR to continuous identical
digits can be affected by mismatches in oscillation frequencies among gated
oscillators that can lead to a drift in clock phases.
A CDR based only on a GVCO with a symmetric circuit topology can
used to relax the timing requirements.

D Q D0

Gated VCO

Dτ1
1
D01
MUX

Dτ
Dτ0
0
Di

GS

RCK

FIGURE 6.61
Reference-free CDR circuit based only on a gated VCO.

In applications (high-speed access networks such as LANs), where the fine

delay for timing adjustment has to be set in accordance with a known target
clock frequency, the data recovery can be implemented as shown in Figure 6.61.
When implemented using differential building blocks, the data recovery
circuit features symmetric loops that operate complementarily and help avoid
the timing mismatch between the signals from both loops [35]. As a result,
an edge of the recovered clock signal can be aligned with the middle of the
data eye. The differential circuit for the AND gate implementation is shown
in Figure 6.62(a). The realized logic function is of the form,
Z =X·Y (6.103)
where X = X + − X − , Y = Y + − Y − , and Z = Z + − Z − . To implement the
OR gate, the following Boolean logic identities should be exploited:
Z = X ·Y (6.104)
=X +Y (6.105)
380 Data Converters, Phase-Locked Loops, and Their Applications
VDD VDD

RL RL RL RL

− −
Z Z

+ +
Z Z
− − +
Y X Y
T2 T4 T2 T4
Y+ T1 T3 X
+
T1 T3 Y
−

+ T5 T6 + T5 T6
X S
− −
X S

TB TB
VB VB

(a) (b)

FIGURE 6.62
(a) Differential circuit for the AND and OR gate implementations; (b) differ-
ential implementation of the multiplexer.

Dτ

Τd

RCK

τA
Dτ1

Dτ0

τG
GS

D01 τS

FIGURE 6.63
Waveforms of the CDR based on a gated VCO.

or equivalently

Z =X +Y (6.106)

where X = X − − X + , Y = Y − − Y + , and Z = Z − − Z + . The AND and OR

gates are realized using the same circuit configuration so that their propaga-
tion delays can be as close as possible.
Figure 6.62(b) presents the differential implementation of the 2:1 multi-
plexer.
The waveforms of the data recovery circuit based on a gated VCO are
represented in Figure 6.63.
Circuits for Signal Generation and Synchronization 381

The gated VCO oscillates at a frequency f0 given by

f0 = 1/(2Td) (6.107)

where Td is half of the oscillation period and is set by one of both oscillator
loops. The oscillation frequency is then determined by the propagation delays
of buffer circuits, the logic gate (AND or OR), and the 2:1 multiplexer.
To design the data recovery circuit so that the signal edge can be detected
by the 2:1 multiplexer, the delay of the gating signal, τG , must be smaller than
the propagation delay of the AND and OR logic gates, τA . Hence, τG < τA .
On the other hand, the difference, τA − τG , should be small enough to avoid
any unnecessary increase of the jitter.
At a data rate of 12.5 Gb/s, a value of 6.9 ps can be attributed to τG ,
while τA is on the order of 7 ps.

6.4.2.4 Reference-less dual-loop CDR circuit

A dual-loop CDR can also be designed without an external reference clock
signal, as shown in Figure 6.64(a). It consists of a binary phase detector (PD),
a rotational frequency detector (FD), two charge-pump circuits, CP1 and CP2 ,
a loop filter, and a VCO. The circuit diagram of the half-rate binary PD is
depicted in Figure 6.64(b), where D0 and D180 represent the recovered data.

D0
Di D Q
1 0
MUX

Q Up
1
D Q
2 CK 0
CK 90 Q

D Q
3
CK Q
0 0
MUX

Dn
D Q
4 1
Q
D 180 CK 90
(b)

Up
Di I P1
Binary Biais
CP1
PD circuit
Dn
CK 0
R CK 45
VCO
C1 CK 90
FUp
I P2 CK 135
Biais
FD CP2
circuit
FDn
C2

(a)

FIGURE 6.64
Dual-loop CDR with a half-rate binary PD.

A reference-less dual-loop CDR [36–38] extracts the clock frequency di-

382 Data Converters, Phase-Locked Loops, and Their Applications
Dn Up

D Q FUp
6
Di D Q Q
CLR
1
Q

D Q D Q D Q FDn
2 5 7
CK 135 Q Q Q
CLR CLR
0

MUX
D Q
3 Dn45
1
CK 45 Q
CK
135
D Q
4
Q

FIGURE 6.65
Rotational frequency detector (FD).

VCP
2

VCP CK 45 CK 90 CK 135 CK 0
1

−+ −+ −+ −+

+− +− +− +−
VCN CK 225 CK 270 CK 315 CK 180
1

VCN
2
(a)
VDD VDD
−+ VC − T1 T3 VCP T4
1 T6 VCP
VCP 2
+ k
+− I CP

T2
IC Vi V0
T1
R
I CN

T2 VCN T3
k VCN T5 VCN
Current−starved 1 2
inverter
(b) (c) (d)

FIGURE 6.66
(a) VCO; (b) pseudo-differential inverter stage; (c) voltage-controlled bias
circuit; (d) current-starved inverter.

rectly from the input data stream, but its frequency acquisition range is lim-
ited to about ±50% of the data rate due to the effects of the sampling process
on the frequency detector. The VCO is driven by a first-order frequency loop
towards the frequency lock state by directly extracting the frequency error
from the incoming data stream, Di . A second-order phase loop including the
PD then takes over to appropriately align the data bits and the sampling
edges of the clock signal, thus minimizing the phase error. The phase loop has
a capture range that is smaller than the one of the frequency loop.
The half-rate binary phase detector of Figure 6.64(b) samples the input
data using the clock signals CK0 , CK90 , CK180 , and CK270 . The output signal
Circuits for Signal Generation and Synchronization 383

of each of the XOR gates is valid for the phase range of 270◦. Specifically for
the topmost multiplexer, the inputs selected by the low and high logic states
are valid from 90◦ to 360◦ and from 270◦ to 360◦ + 180◦, respectively, while
for bottommost multiplexer, the inputs selected by the low and high logic
states are valid from 180◦ to 360◦ + 90◦ and from 360◦ to 360◦ + 2700◦ ,
respectively. By using the clock signals CK0 and CK90 as selection signals for
the multiplexers, only the valid 180◦ portions of each of the XOR outputs can
be transferred to the PD outputs. When the phase loop is in the locked state,
the edges of quadrature clock signals are aligned with the data transitions.

The rotational FD is represented in Figure 6.65. It generates the signals

F U p and F Dn using the clock signals CK45 and CK135 , and the PD output
signals, U p and Dn. The rotational FD generates an FUp pulse if a data tran-
sition occurs between the clock phases, 0◦ and 45◦ , and the next between 135◦
and 180◦ . It also produces an FUp pulse if a data transition occurring between
the clock phases, 180◦ and 225◦ , is followed by another one between 315◦ and
360◦ . For a data transition that takes place between the clock phases, 315◦
and 0◦ , and the next between 180◦ and 225◦ , or for a data transition that takes
place between the clock phases, 135◦ and 180◦ , and the next between 0◦ and
45◦ , a FDn pulse is generated. In the locked state, data transitions can only
occur around the edges of the clock signals CK90 and CK270 . Consequently,
there is no data transition taking place between 315◦ and 45◦ , and between
135◦ and 225◦ . That is, the signal Dn45 is set to the low logic state. Because
the rotational FD is reset using the signal Dn45, it remains disabled as long
as the frequency loop is the locked state.

In the phase domain, the phasor representing the phase difference between
data transitions and clock signal edges rotates in a clockwise direction if the
clock frequency is lower than the data rate, and an anticlockwise direction if
the clock frequency is higher than the data rate. It remains stationary if the
phase difference is equal to zero.

A four-stage ring oscillator that produces quadrature outputs is repre-

sented in Figure 6.66(a). It consists of pseudo-differential inverter stages, as
shown in Figure 6.66(b). The oscillation frequency can be adjusted using the
voltage-controlled bias circuit of Figure 6.66(c), where k = 1, 2. The circuit
diagram of a current-starved inverter is represented in Figure 6.66(d).

Each delay stage produces an output current that not only flows into its
own parasitic load capacitors, but also the parasitic interstage coupling capac-
itor. As a result, the delay stage matching can be improved due to phase error
averaging. Assuming that △φ is the phase difference between adjacent delay
stages and N is the number of stages, the phase shift around the loop that,
by taking into account the feedback phase inversion, is of the form, N △φ + π,
should be equal to 2π.
384 Data Converters, Phase-Locked Loops, and Their Applications

6.4.2.5 Reference-less single-loop CDR circuit using a linear phase

detector

A reference-less CDR circuit can also be designed, as shown in Figure 6.67,

by exploiting the single-sided frequency detection capability of the half-rate
linear PD [39]. It is based on a single-loop structure that is composed of a PD,
a CP circuit, a filter, and a VCO. The circuit diagram of a half-rate linear
PD is represented in Figure 6.68, where flip-flops are triggered either by the
recovered clock signal RCK or by its complementary version RCK, and D0
is the recovered data.

VDD
I1

Up
Di S1 I Loop filter
Linear P
VP VCO RCK
PD Dn
S2 R
C2
I2 C1

FIGURE 6.67
Single-loop CDR circuit using a linear PD (I1 = 2I2 ).

θ
D0
Di

Up
RCK
Di D Q D Q
1 3 Dn
RCK Q Q

RCK Q Q
2 4
D Q D Q

FIGURE 6.68
Half-rate linear PD.

The timing diagram of Figure 6.69, where ⊕ is the exclusive OR operation,

illustrates the CDR operation when the clock frequency is equal to half the
data rate. It was assumed that the duration of one data bit is 2π and the clock
signal frequency, fRCK , is half the data frequency, fDi . In the case where the
sampling edges of the clock signal are exactly aligned with the data eye (or
center), the Up and Dn pulses take the widths of π and 2π, respectively.
Assuming that I1 = 2I2 = I and θ is the phase difference between the center
of the data and the rising edge of the clock signal, the average current delivered
Circuits for Signal Generation and Synchronization 385

Di 0 1 2 3 4 5 6

CK

Q1 0 1 2 3 4 5 6

Q2 0 1 2 3 4 5 6

Q3 1 3 5

Q4 0 2 4

Up 0+ 1 1+ 2 2+ 3 3+ 4 4+ 5 5+ 6

Dn 1+ 0 0+ 1 1+ 2 2+ 3 3+ 4 4+ 5

FIGURE 6.69
Timing diagram of a half-rate linear PD.

by the CP circuit can be expressed as

θ+π 2π
I¯P = αI1 × − αI2 × (6.108)
2π 2π
θ
= αI for − π < θ < π (6.109)
2π

where α is the bit transition density.

1
2 αΙ
αΙ

1 3
Average CP current

Average CP current

αΙ αΙ
4 4

1
0 2 αΙ

1 1
αΙ n = 1/2 αΙ
4 4
n=1
n=2
1 n=4
2 αΙ− π 0 π
0
0 fD 4 fD 2 fD
i i i
(a) Phase (b) Clock signal frequency

FIGURE 6.70
Phase (a) and frequency (b) characteristics of a half-rate linear PD.

General expressions of the average CP current can be derived by analyzing

the PD timing diagram under various operating conditions.
When fRCK = fDi /n, where n is an integer greater than 2, and the sam-
pling edges of the clock signal are exactly aligned with the data eye, the widths
of the Up and Dn pulses are (n − 1)π and nπ per every n/2 bits, respectively.
386 Data Converters, Phase-Locked Loops, and Their Applications

The average CP current is given by

θ + (n − 1)π I nπ
I¯P = αI × −α × (6.110)
nπ 2 nπ
θ + (n − 2)π/2
= αI for − π < θ < π (6.111)
nπ
When fRCK = fDi /n, where n is an odd integer greater than or equal to 3,
and θ = ±π/2, the widths of the Up and Dn pulses are 2(n − 1)π and 2nπ
per every n bits, respectively. Depending on the value of θ, the average CP
current can be written as
θ + π/2 + (n − 1)π I nπ
I¯P = αI × −α × (6.112)
nπ 2 nπ
θ + (n − 1)π/2
= αI for − π < θ < 0 (6.113)
nπ
and
θ − π/2 + (n − 1)π I nπ
I¯P = αI × −α × (6.114)
nπ 2 nπ
θ + (n − 3)π/2
= αI for 0 < θ < π (6.115)
nπ
The phase characteristic is represented in Figure 6.70(a) for various values of
n.
The average CP current with respect to the phase is defined as
Z π
¯ 1
IP = IP dθ (6.116)
2π −π

Because it also shows a dependence on the clock signal frequency, the fre-
quency characteristic of the half-rate linear PD can be plotted as shown in
Figure 6.70(b). Data points from the frequency characteristic can be interpo-
lated to derive an equation of the following form:
  

 αI 2fRCK fDi
 1− if fRCK ≤
I¯P = 2 fDi 2 (6.117)

 fDi
0 if fRCK >
2
The half-rate linear PD can then be used for frequency detection provided the
clock signal frequency does not exceed half the frequency of the input data.
After the frequency acquisition, the CDR enters the next operation mode that
consists of minimizing the phase difference between the clock signal and the
input data.
In addition to providing a phase detection capability, a full-rate linear PD
can also be used to detect a frequency difference [40]. A reference-less CDR
Circuits for Signal Generation and Synchronization 387
θ
Di
Up
RCK

Dn
Di D Q D Q
1 2 D0
RCK Q Q

RCK

FIGURE 6.71
Full-rate linear PD.

Di 1 2 3 4 5

CK

Q1 0 1 2 3 4

Q2 0 1 2 3 4

Up 0 + 1 1+ 2 2+ 3 3+ 4 4+ 5

Dn 0+ 1 1+ 2 2+ 3 3+ 4

FIGURE 6.72
Timing diagram of a full-rate linear PD (fRCK = fDi ).

Di 1 2 3 4 5

CK

Q1 1 3 5

Q2 −1 1 3

Up 1+ 2 1+ 3 3+ 4 3+ 5

Dn 1+ 1 1+ 3 3+ 5

FIGURE 6.73
Timing diagram of a full-rate linear PD (fRCK = fDi /2).

based on a single-loop architecture with I1 = I2 (see Figure 6.67) that includes

a full-rate linear PD then has a frequency detection capability as long as the
clock frequency is lower than the frequency of the incoming data.
The circuit diagram of a full-rate linear PD is shown in Figure 6.71. The
retimed data is available at the D0 terminal. Note that θ represents the phase
difference between the center of the received data and the rising edge of the
recovered clock. The timing diagram of Figures 6.72 and 6.73 illustrate the
operation of a full-rate linear PD, when fRCK = fDi and fRCK = fDi /2,
respectively. Note that fRCK is the frequency of the recovered clock signal
and fDi is the frequency of the received data.
388 Data Converters, Phase-Locked Loops, and Their Applications
1
2 αΙ αΙ

1 3
Average CP current

Average CP current
αΙ αΙ
4 4

1
0 αΙ
2

1 1
αΙ n = 1/2 αΙ
4 4
n=1
n=2
1 n=4
2 αΙ− π 0 π
0
0 fD 2 fD 2 fD
i i i
(a) Phase (b) Clock signal frequency

FIGURE 6.74
Phase (a) and frequency (b) characteristics of a full-rate linear PD.

Assuming that fRCK = fDi /n, where n is a number, and the duration of
one bit of the received data is 2π, the pulse width at the Dn output is nπ
per every n bits, while the pulse width at the Up output is (2n − 1)π per
every n bits. The Dn pulse is generated by computing the XOR logic function
of a given bit and only the adjacent bit at the n-th position, while for the
generation of the Up pulse, it requires an estimate of the XOR logic function
of a given bit and each of the consecutive neighboring bits from the first to
the n-th position. Hence, assuming that I1 = I2 = I, the average CP current
can be expressed as

θ + (2n − 1)π nπ
I¯P = αI × − αI × (6.118)
2nπ 2nπ
θ + (n − 1)π
= αI × for − π < θ < π (6.119)
2nπ

Simulation results show that the average CP current is always positive

regardless of θ if fRCK ≤ fDi , whereas it is always equal to zero if fRCK > fDi .
The expression of the average CP current as a function of the clock frequency
is given by
  
 αI 1 − fRCK if fRCK ≤ fDi
I¯P = 2 fDi (6.120)

0 if fRCK > fDi

Therefore, the full-rate linear PD has a single-sided frequency detection ca-

pability. The phase and frequency characteristics of a full-rate linear PD are
shown in Figures 6.74(a) and (b), respectively.
On the other hand, it should be noted that a binary PD does not exhibit
a frequency detection capability.
Circuits for Signal Generation and Synchronization 389

6.5 Delay-locked loop

In applications (multi-phase clock generation and synchronization, memory
interface) where the desired clock frequency is already available, a voltage-
controlled delay line (VCDL) can be used instead of a VCO. Hence, while
the PLLs generate a new clock signal, the delay-locked loops (DLLs) actually
retard the incoming clock signals in such a way that the delay in the output
clock signals is greatly reduced.
The block diagram of a DLL is shown in Figure 6.75. The output signal
is generated by delaying the input clock. The phase difference between the
VCDL output and reference clock signals is provided by a phase detector whose
output is applied to the loop filter, which generates the VCDL control voltage.
The delay cell is actually equivalent to a gain stage and the stabilization of
the loop can be achieved using a first-order lowpass filter.

CK Up
Phase Charge
detector pump
RCK Dn C

VDD
VCDL

T2
CK
Buffer T1

CK1 CK 2 CK N

FIGURE 6.75
Block diagram of a DLL.

The closed-loop phase transfer function is given by

Θ0 (s) 1
T (s) = = (6.121)
Θi (s) 1
1+
Kd Kp H(s)
where Kd is the gain of the VCDL and H is the transfer characteristic of
the loop filter, which is realized here by a charge-pump circuit loaded by a
capacitor and is then similar to an integrator.
A VCDL can be implemented as shown in Figure 6.76(a) [18]. The biasing
circuit uses a current mirror to source and sink current corresponding to the dc
level of the control voltage, Vc . Transistors T1 − T2 operate as a current source
and the inversion of the input signal is achieved by T3 − T4 . The time delay
is related to the output load capacitance. The inverter structure depicted
in Figure 6.76(b) can be adopted to improve the output driving capability.
390 Data Converters, Phase-Locked Loops, and Their Applications
V DD V DD
T T T2
B2 2
V BP
T
B3
I

T4 T
4
T6
V V In Out
i 0
T T3 T5
3

I
T T
B4 B1
Vc V BN
T T
1 1

(a) (b)

FIGURE 6.76
(a) Delay line-based oscillator using inverters; (b) inverter stage with an im-
proved driving capability.

Generally, single-ended structures like the ones of Figure 6.76 are sensitive to
the power supply noise, which affects the phase of the output signal.
T CK τ DL

τ DL T CK

CK CK

RCK RCK

Up Up

Dn Dn
(a) (b)

FIGURE 6.77
DLL signal waveforms during abnormal operation: (a) stuck false lock (τDL <
TCK ), (b) harmonic lock (TCK < τDL < 2TCK ).

DLLs with a wide operating range are required in various applications.

In general, a DLL can lock the input clock period, TCK , to the time delay,
τDL , associated to the VCDL and replica buffer, only if the value of τDL is
comprised between TCK /2 and 3TCK /2. As a result, with τDL = N · TCK ,
where N is an integer greater than or equal to one, the rising edge of the
input clock is aligned with the one of the output generated by the VCDL. A
wide-range DLL can feature a significantly large spread between the minimum
and maximum values of τDL , and therefore, be subject to false lock problems.
A PFD is often used as a phase detector in a DLL because its operat-
ing range is not limited by the duty cycle ratio of the clock signal. But,
its improper state setting, that can be expected to occur at the operation
start, can cause a stuck false lock. For a correct operation under the condition
TCK > τDL , the Dn signal should be high to allow that the delay τDL can
increase until it reaches the value TCK . Meanwhile, the Up signal may become
Circuits for Signal Generation and Synchronization 391
6
False lock
detector
Lock RST

CK Up
Phase Charge
detector pump
RCK Dn C

VDD
VCDL

T2
CK
Buffer T1

CK1 CK 2 CK N

FIGURE 6.78
Block diagram of a wide-range DLL.

CK CK 4

D Q D Q D Q D Q D Q D Q

6 CK 1 CK 2 CK 3 CK 4 CK 5 CK 6

Up Dn
D Q D Q D Q D Q D Q

Lock RST

FIGURE 6.79
Circuit diagram of the false lock detector.

high as a result of RCK arriving later than CK. This leads to a stuck false
lock, as shown in Figure 6.77(a). A measure for counteracting the stuck false
lock can consist of resetting the PFD.
When the DLL is unable to distinguish the normal lock case (N = 1) from
the other cases (N > 1), as shown in Figure 6.77(b), the false lock is said to
be harmonic. An effective way to prevent this situation is to always keep the
condition τDL < 2TCK satisfied.
The frequency lock range of a conventional DLL appears to be very limited,
392 Data Converters, Phase-Locked Loops, and Their Applications
RST Lock

VDD 1 0

MUX
Up
D Q 1
1
CK R Q

RCK R Q
2
D Q 1

MUX
Dn
0 0

FIGURE 6.80
Circuit diagram of the phase detector.

and a solution to achieve a wide operation range then consists of using an extra
control circuit to help meet the locking requirements set on the delay τDL .
The block diagram of a wide-range DLL is shown in Figure 6.78. It consists
of a phase detector, a charge-pump circuit loaded by a capacitor, a multi-phase
voltage-controlled delay line, and a false lock detector [41].
The circuit diagram of the false lock detector is depicted in Figure 6.79. It
comprises a harmonic lock detector that helps maintain the delay τDL less than
2TCK and a reset circuit that can correct the effect related to the improper
state setting of the phase detector.
Figure 6.80 shows the circuit diagram of the phase detector, which is re-
alized by adding two input signals, RST and Lock, to a conventional PFD.
In normal operation, the delay τDL can be reduced only when the rising
edge of RCK occurs between the times TCK and (7/6)TCK . Hence, the Up
signal can take the high level only during (α − 1)TCK , where 1 < α < 7/6. To
correct a malfunction caused by the improper PD state setting, the state of
the Dn signal is checked against CK4 , and if the Dn signal is high at the arrival
of the rising edge of CK4 , the phase detector will be reset so that the normal
operation can resume. On the other hand, the increase of the delay τDL can
only take place provided the rising edge of RCK occurs before the duration
TCK . After an occurrence of the improper PD state setting, the phase detector
should be reset. Here, this is achieved by checking if the state of the Up signal
is high at the arrival of the rising edge of CK4 .
For normal operation of the phase detector, the signal Lock must be in
the high state. When the signal Lock takes the low state, the Up output is
set to the high level. Subsequently, the harmonic lock can be prevented by
increasing the delay line control voltage until the delay τDL becomes less than
(7/6)TCK . In general, the maximum capture range is (N + 1)TCK for a false
lock detector using a number N of multi-phase clocks.
A DLL is less prone to stability problems than a PLL whose loop band-
width is often determined by a high-order narrowband filter requiring large
components with a high sensibility to the IC process, voltage, and tempera-
Circuits for Signal Generation and Synchronization 393

ture variations. The requirement to use such a loop filter in a PLL also results
in a longer acquisition time, usually in the 1/2 to 1 microsecond range, while
a DLL can lock to the data rate in just a few clock cycles. By employing
components with high values, a PLL occupies a large chip area compared to a
DLL. Because a DLL adjusts the amount of delay or phase without affecting
the frequency in order to achieve the desired synchronization, its operating
frequency range is severely limited. Furthermore, a DLL may falsely lock into
a harmonic frequency of the reference clock signal.

6.6 PLL with a built-in self-test structure

Typically, functional tests of PLLs consist of verifying parameters such as
loop gain, loop bandwidth, lock time, capture range, lock range, and jitter.
These tests are realized by applying a stimulus to the PLL and then observing
the corresponding response. But, their design and execution may be time-
consuming. The lock range, for instance, is determined only after the phase
lock has been achieved and by gradually increasing or decreasing the stimulus
frequency until the phase locking condition is no longer met. Furthermore, a
tester allowing a high precision control of signal transition timing is required.
Unknown
frequency
Binary counter
Reset

Known Frequency divider

Output register
frequency 2R

Dout

FIGURE 6.81
BIST circuit for the frequency measurement.

By designing a PLL with a built-in self-test (BIST) structure [42–45], the

number of test devices required after the manufacturing phase is reduced. The
BIST circuit is preferably designed to operate without affecting the internal
signal path of the PLL. It can then be connected to usual PLL outputs, some
of which are: VCO output, frequency divider output, and phase lock indicator
output.
A simple BIST circuit is shown in Figure 6.81. It is based on pulse count-
ing using a gated binary counter and a reference frequency, and can be used
to verify the VCO center frequency or any PLL frequency range. The out-
put count is the digital representation of the quantity 2R−1 funknown /fknown ,
where fknown and funknown are the known and unknown frequencies, respec-
tively, and 2R is the frequency divider factor.
394 Data Converters, Phase-Locked Loops, and Their Applications

6.6.1 Gain, capture and lock range, and lock time

VDD
Test I1

f REF 1 In Up VCO
S1 I Loop filter
0 P
PFD VP Kv s Out
Dn
S2 R
C2
I2 C1

Frequency divider
N

f REF Frequency
Phase delay
f∆ circuit
2 f REF measurement Dout
Delay f REFi circuit

FIGURE 6.82
Circuit diagram of a PLL with BIST for the measurement of gain, capture,
and lock characteristics.

f REF

1 1
D Q D Q
Delay 0 0

Q Q
f∆
2 f REF

FIGURE 6.83
Phase delay circuit.

In general, the PLL open-loop gain can be written as,

Kp Kv H(s)
GOL = (6.122)
N ·s
where H(s) is the filter transfer function, Kp denotes the gain of the phase
detector and charge-pump section, Kv is the VCO gain, and N is the frequency
divider factor. The open-loop gain is a suitable characteristic to be tested
because it is dependent on parameters that determine the PLL behavior.
The verification of the open-loop gain GOL , the capture and lock range, and
the lock time can be performed by using the BIST structure of Figure 6.82,
that is based on phase shifting. To determine the open-loop gain, the PLL
loop is open by preventing the feedback signal applied at the PFD input to be
dependent on the VCO oscillation frequency. The frequency divider output is
used to generate an input to the PLL at the same frequency as the feedback
signal. As a result, no phase difference will be detected by the PFD and the
charge-pump circuit will not source nor sink current. Ideally, the output of the
Circuits for Signal Generation and Synchronization 395

Delay

REF clock

Signal at f v /N

Signal at 2 f v /N

In

Current I P

Capacitor
output

FIGURE 6.84
PLL waveforms during a test.

loop filter will then remain unchanged. From this last state, the application at
the PLL inputs of a phase shift lasting only one cycle of the feedback signal,
whose frequency equals fREF , affects the VCO output frequency that first
changes quickly and then remains constant as soon as the phase shift becomes
zero again. Next, the VCO output frequency change can be quantified to
ascertain the open loop gain.
Using the phase delay circuit of Figure 6.83 in the implementation of the
PLL BIST, a 25% duty cycle output pulse can be delayed by half a clock cycle
relative to the frequency fv /N in response to the detection of the high logic
state just taken by the control signal Delay.
The PLL waveforms during a test are shown in Figure 6.84. Initially, the
PLL is locked to align the rising edges of the reference and feedback clock
signals, such that the frequency fv /N is equal to fREF . Following the intro-
duction of a phase shift, the PLL begins to adjust the VCO frequency in order
to re-align the reference and feedback clocks.
Especially, the application of a phase shift, △θi , that lasts ρ clock cycles,
to the PLL inputs leads to a VCO frequency variation, △ωv . The VCO can
be described by the next equation,
△ωv = Kv Vtune (6.123)
where Vtune is the tuning voltage generated at the filter output. Assuming
that the loop filter is reduced to a single capacitor, the instantaneous current
and voltage can be written as,
dvtune
ic = C (6.124)
dt
Considering only variations of average current and voltage, we arrive at
Vtune
Ic = C (6.125)
△t
396 Data Converters, Phase-Locked Loops, and Their Applications

where △t = ρ/fREF , Ic = Kp △θi , and Kp = Ip /(2π). Hence,

ρKv Ip △θi
△ωv = (6.126)
2πfREF C
The feedback phase change due to the VCO frequency step can be derived as,
△θv △ωv |ρ=1 · △t Kv Ip △θi
△θf b = = = 2 (6.127)
N N 2πfREF NC
The open-loop gain is then given by
△θf b Kv Ip
GOL = = 2 (6.128)
△θi 2πfREF NC
Using the fact that △θi = 2πfi and △ωv = 2π△fv , where fi and △fv de-
note the input frequency and the VCO frequency variation, respectively, and
combining (6.126) and (6.128) yield
△θf b △fv
GOL = = (6.129)
△θi ρfREF fi N
The value of the open-loop gain can be determined by performing frequency
measurements. To reduce the effect of possible duty-cycle distortions or mis-
match between the sink and source charge-pump currents, the measurements
can be realized for an input phase lead and phase lag, ±fi , and then be aver-
aged.
The capture range is the range of input frequencies over which the PLL can
still lock onto the incoming signal, while the lock range is the input frequency
range within which the PLL is able to remain in a previously acquired lock
state. In the specific case of PLLs using edge-sensitive PFDs, the capture
range and lock range seem equal.
One measurement approach is to continuously apply a frequency shift to
induce a slow and controlled change of the VCO output frequency towards
its maximum (or minimum) value so that several measurements can be per-
formed during the frequency transition. This is realized by connecting the
PLL’s input to a version of the frequency divider output with a frequency
equal to twice (or half) the internal feedback frequency. The output frequency
is monitored continuously until no further significant change can take place
within a specified time interval, that is, the minimum (or maximum) value is
reached, and the last frequency count is retained.
The lock time is the amount of time required by the PLL to acquire a
locked state with an input signal within its capture range after the power-up
or a frequency change.
When a lock detector is part of the PLL circuit, its indication can be
exploited for the lock-time measurement. Alternatively, the lock time can also
be measured by first driving the VCO to its maximum frequency and then
counting the number of reference clock cycles until the lock state is reached
within some defined margin.
Circuits for Signal Generation and Synchronization 397

6.6.2 Jitter
The PLL clock jitter is another characteristic that can be measured using the
BIST approach. It is a fundamental limitation in high-speed applications.

Ideal

T T T

Phase jitter

∆φ (n−1) ∆φ (n) ∆φ (n+1)

Period jitter

T(n−1) T(n) T(n+1)

FIGURE 6.85
Phase and period jitter.

Time−to−digital Phase
converter difference

VDD
I1

Up VCO
In S1 I Loop filter
P
PFD VP Kv s Out
Dn
S2 R
C2
I2 C1

Frequency divider
N

FIGURE 6.86
Circuit diagram of a PLL with time-to-digital converter-based BIST for jitter
measurement.

Jitter can be classified as phase jitter, period jitter (see Figure 6.85), or
cycle-to-cycle jitter.
Phase jitter refers to the deviation of rising or falling edges of a clock signal
as compared to the ideal clock signal. It can be defined as,

Jφ (n) = △φ(n) − △φ (6.130)

where Jφ (n) is the phase jitter during the cycle n, and △φ is the average value
of the phase offset.
Period jitter is used to describe the random period fluctuation with respect
398 Data Converters, Phase-Locked Loops, and Their Applications
VDD
I1

Up VCO
In 1 S1 I
P Frequency divider Phase
PFD VP Kv s Counter
N difference
Dn
In 2 S2
C
I2

FIGURE 6.87
Circuit diagram of a time-to-digital converter.

DUT

In PLL Constant delay D Q Error

f REF counter
Q
0
Adjustable delay
1

Oscillation frequency
f REFi counter
Enable

Oscillation
period difference

FIGURE 6.88
Circuit diagram of a PLL with delay-based BIST for cycle-to-cycle jitter mea-
surement.

Delay
buffer

In

Binary
8:1 Multiplexer
Increment counter

Selection
bits Out

FIGURE 6.89
Circuit diagram of an adjustable delay.

to the ideal or average period. Its definition for the clock cycle n can be stated
as,
JT (n) = T (n) − T (6.131)

where T (n) is the period jitter during the cycle n, and T is the ideal period
of the clock signal.
Cycle-to-cycle jitter is defined as the deviation in period length of adjacent
Circuits for Signal Generation and Synchronization 399

cycles of a signal. It is calculated by using the following formula,

Jcc (n) = T (n) − T (n − 1) (6.132)
where Jcc (n) denotes the cycle-to-cycle jitter for the cycle n.

Jitter is better described by taking many measurement samples that can

be processed to determine peak-to-peak and RMS values.

Let N be the number of samples obtained by measuring the

phase offset △φ(n) or the period values T (n). The peak-to-peak
jitter can be defined as the largest swing in phase offset or period
values and is given by
Jφ,P P = max{△φ(1), △φ(2), · · · , △φ(N )}
− min{△φ(1), △φ(2), · · · , △φ(N )} (6.133)
or
JT,P P = max{T (1), T (2), · · · , T (N )}
− min{T (1), T (2), · · · , T (N )} (6.134)
The RMS jitter can be expressed as
v
u N
u1 X
Jφ,RMS = t (△φ(n) − △φ )2 (6.135)
N n=1

or
v
u N
u1 X
JT,RMS =t (T (n) − T )2 (6.136)
N n=1

where
N
1 X
△φ = △φ(n) (6.137)
N n=1

and
N
1 X
T = T (n) (6.138)
N n=1

represent the average phase offset and period, respectively. Note

that the period jitter can be linked to the phase jitter by an
equation.
400 Data Converters, Phase-Locked Loops, and Their Applications

Several methods can be adopted to implement BIST circuits for PLL jitter
measurements. They generally exploit the concept of time interval evaluation.
The PLL BIST circuit of Figure 6.86 is based on a time-to-digital converter
that can detect the phase difference between the reference and feedback clock
signals. The time-to-digital converter, as shown in Figure 6.87, is composed
of a phase and frequency detector (PFD), a charge-pump circuit loaded by a
capacitor C, a voltage-controlled oscillator (VCO), a frequency divider, and a
counter.
The PFD is enabled only at each sampling instant to detect the phase
difference between the reference and feedback clock signals that is assumed to
be proportional to the time delay △T . The corresponding voltage variation,
△V , generated at the output of the charge-pump circuit can be written as,
Ip
△V = · △T (6.139)
C
where Ip is the charge-pump current. The change of the VCO oscillation fre-
quency, △fv , is translated into the frequency variation △f at the frequency
divider output. Hence,
△fv Kv △V
△f = = (6.140)
N N
where N is the frequency divider factor, and Kv is the gain of VCO. The signal
frequency is attenuated by the frequency divider to allow a proper operation of
the counter. When its evaluation by the counter lasts Tc , the count difference
can be obtained as
△Count = △f · TC (6.141)
Combining (6.139), (6.140), and (6.141) yields
N ·C
△T = · △Count (6.142)
Kv IP TC
The count difference is proportional to the phase difference between the ref-
erence and feedback clock signals. An initial test with a known △T can be
exploited for the determination of the coefficient N · C/(Kv IP TC ). Note that
the measurement accuracy can be limited by mismatch non-linearities and
power-supply noise. The charge-pump current should then be sized as large
as possible to reduce the measurement error to about a few picoseconds.
A jitter measurement method that uses constant and adjustable delay lines,
a phase detector, and counters, as shown in Figure 6.88, makes it possible to
estimate the auto-correlation function of the reference and feedback clock
signals around the signal period. Cycle-to-cycle jitter is measured by counting
all events where the signal and its delayed version differ. The output of the
D flip-flop is compared with the expected logic state, and the error counter
is incremented each time an error is found out. When the maximum count,
E, is reached, the counter output is latched and then reset. Figure 6.89 shows
the circuit diagram of an adjustable delay line that consists of a counter, a
multiplexer, and delay buffers.
Circuits for Signal Generation and Synchronization 401

To measure the RMS jitter, the adjustable delay line is first set to exhibit
the minimum time delay guaranteeing that the error count can remain equal
to zero for each group of E cycles of the PLL input signal. Next, the delay
line counter is incremented after each E cycles to adjust the time delay, and
its counts for which the error count is, for instance, 15.9% and 84.1% of E
are recorded. This can be interpreted as the standard deviations (±σ) of a
random variable (jitter) with normal distribution.
For the peak-to-peak jitter measurement, it is required to store the delay
line counter contents for which the error count is first equal to one and first
equal to E (or any other magnitude range boundaries). The adjustable delay
line is operated in a self-oscillating mode to determine the delay in both cases,
so that the delay difference can then be computed.
Vernier delay lines [46] can also be used to measure the period or phase
error in a PLL with a high accuracy. However, in addition to the large area
overhead, the long latency of delay-line-based measurements limits the appli-
cation to relatively low frequencies.

Undersampling
DUT flip−flop

PLL fD
In D Q Out
N
f REF fB
Q
PLL
(N−1) fS

FIGURE 6.90
Circuit diagram of a PLL with undersampling-based BIST for jitter measure-
ment.

Signal at f D

Signal at f S

Signal at f B

Unstable Unstable Unstable

transition transition transition

FIGURE 6.91
Waveforms illustrating the undersampling principle.

An undersampling method [47] can be adopted to ease the speed and area
requirements of the PLL BIST circuit. Figure 6.90 shows the circuit diagram
of a PLL with undersampling-based BIST for jitter measurement. The D flip-
flop receives the output signal that is generated by the PLL under-test at
the frequency fD . Its sampling frequency fS (with fS = fD (N − 1)/N ) is
set by a second PLL (or any reference source). Jitter characteristics can then
be determined by monitoring the output samples of the D flip-flop to detect
402 Data Converters, Phase-Locked Loops, and Their Applications

signal transitions occurring after a relatively long stopover at the same logic
level and capturing amplitude variations that are caused by jitter.
By sampling at a rate, fS , slightly lower than the transmitted data rate,
fD , a signal is produced at a much slower frequency, fB , called the beat fre-
quency. This is related to the fact that both frequencies, fS and fD , are very
close to each other so that a sequence of data samples at the same logic level
will first be acquired before switching to the other logic level. Due to fluc-
tuations of data edges induced by jitter, amplitude variations are produced
around the rising and falling edges of the signal fB when the sampling takes
place around rising or falling edges of the data sequence fD . Figure 6.91 shows
waveforms illustrating the undersampling principle. The timing information
of signal sequences with amplitude variations can be collected and analyzed
as data samples with normal distribution. The accuracy of the jitter determi-
nation is improved by increasing the size of collected data samples.
The undersampling method is capable of evaluating jitter with sub-
picosecond resolution in applications requiring gigabit data transfers.

6.7 PLL specifications

A PLL will operate at the free-running frequency, ω0 , when it is not locked
to an input signal. This frequency is determined by the VCO components.
A nonlinear model of the PLL is necessary for the characterization of the
acquisition process.
Filter output (V)

Filter output (V)

BW 1
BW 2
Lock time

Lock time
Pull−in time

Time (µs) Time ( µs)

(a) (b)

FIGURE 6.92
Transient response of the VCO control voltage due to a step signal in the PLL
input: Illustration of the (a) lock time and (b) pull-in time.

A PLL is generally designed to meet a specified lock range, lock time,

pull-in range, pull-in time, pull-out range, and loop noise bandwidth.
Circuits for Signal Generation and Synchronization 403

Let the frequency range of the PLL input signal be in the frequency range
from ω0 − △ω to ω0 + △ω.
Lock range, ±△ωL , is the angular frequency range over which the PLL
acquires a lock within the first cycle of the input signal or within a given
frequency tolerance. The lock range is affected by the difference between the
input and free-running frequencies. Note that △ωL ≥ △ω. The parameter
△ωL is centered at the free-running angular frequency and determines the
PLL operating frequency range. It decreases with increasing loop bandwidth.
However, a significant increase of the loop bandwidth may cause loop insta-
bility.
Lock time, tL , is the time after which the PLL can lock in one single-
beat note between the input reference frequency and the output frequency.
The lock time, as illustrated in Figure 6.92(a)) for two loop bandwidths, is
primarily a function of the loop characteristics.
Pull-out range, ±△ωpo , is the angular frequency range over which the
PLL operation is stable. The pull-out range is smaller than or equal to the
pull-in range.
Pull-in range, ±△ωpi , is the angular frequency range over which the PLL
would naturally become locked after the cycle slipping occurrence, as shown in
Figure 6.92(b), where the frequency of the input step is assumed to lie outside
the lock range. Cycle slipping occurs when the PFD is unable to accurately
follow the phase error variations caused by large frequency offsets, for instance.
In the event of a cycle slip, the PLL momentarily loses the frequency lock
before settling at the actual output frequency.
Hold range, ±△ωH , is the input frequency range over which the PLL can
maintain static lock. It then represents the maximum static tracking range.
When the frequency offset of the input signal is less than the holding range
but larger than the pull-in range, the PLL is said to be conditionally stable.
Theoretically, the hold range can be high enough. However, in practice, it can
be limited by the operating or tuning range of PLL components, especially
the voltage-controlled oscillator.
Note that △ωH > △ωpi > △ωpo > △ωL .
Pull-in time, tp , is the transient time required by the PLL to always
become locked. The pull-in process has a nonlinear nature and can be slow and
unreliable. Hence, the pull-in time is dependent on the PLL initial conditions
(frequency and phase errors) and loop characteristics.
Loop noise bandwidth, Bn , is the one-sided bandwidth of a unity-gain
and ideal lowpass filter, which transmits as much noise power as does a linear
PLL model. The signal components located outside Bn are greatly attenuated.

After the lock is achieved, the accuracy of the acquisition loop can still
be limited by the effects of the jitter, phase offset, and step-size errors. The
jitter is a random variation of the clock signal transitions due to noise. The
phase offset, which is constant in nature, is essentially caused by mismatches
404 Data Converters, Phase-Locked Loops, and Their Applications

between circuit components and timing misalignment. The step-size errors are
associated with the minimum resolution of the delay or VCO control signal.

6.8 VCO-based analog-to-digital converter

A VCO-based analog-to-digital converter (ADC) is an alternative architecture
for analog-to-digital conversion. It relies on time resolution that is improved
with the continued down-scaling of CMOS process technology and is in the
order of tens of picoseconds for a 130-nm CMOS process.

VCO Digital
Σ output
v0
EN y(n)
Input N
Counter D Q D Q
voltage
vi

CK

FIGURE 6.93
Block diagram of an open-loop VCO-based ADC.

CK

t
vi

t
v
0

φ
T
6π
e(n−1)
4π
e(n)
2π

t
(n−1)T nT (n+1)T

FIGURE 6.94
Waveforms of the open-loop VCO-based ADC.
Circuits for Signal Generation and Synchronization 405

The block diagram of an open-loop VCO-based ADC is shown in Fig-

ure 6.93. It includes a ring VCO, a counter, and a differentiator. The VCO
consists of delay (or inverter) stages and its oscillation frequency is set by
the input voltage, vi . A 2N -modulo counter determines the total number of
rising transitions in the VCO output during every period of the clock signal,
T = 1/fs , with fs being the clock signal frequency. The resulting output dig-
ital code is proportional to the value of the input voltage that determines the
propagation delay of each VCO inverter.
Note that the phase increment of the VCO output must remain lower than
2π during a sampling interval, otherwise the sampled value will not contain the
complete information about the phase variation. The clock signal frequency
should then be kept greater than the highest VCO oscillation frequency to
avoid phase roll-over. This corresponds to an operation in the oversampling
mode.
Waveforms illustrating the operation principle of the open-loop VCO-based
ADC are represented in Figure 6.94.
By modeling the VCO as an ideal integrator with an input voltage signal,
vi , and an output phase signal, φ, the relationship between the VCO output
phase and input voltage can be written as:
Z (n+1)T
φ(n) = Kv vi (n) dt + φi (n) (6.143)
nT
= Kvi (n) + φi (n) (6.144)

where K = Kv T , the VCO gain is represented by Kv , and φi is the initial

phase. It is assumed that the sampling frequency is much higher than the
signal bandwidth so that the input signal can be considered constant between
two consecutive sampling instants.
The counter is supposed to play the role of a quantizer characterized by
the following function:
   
φ φ φ
q = − mod2N (6.145)
2π 2π 2π

where mod2N (φ/2π) denotes the remainder of the division of φ/2π by 2N .

In comparison to φ/2π, the quantizer output q(φ/2π) is shifted down by half
the quantization step size. As a result, the quantization error, given by e =
q(φ/2π) − φ/2π, is comprised between −1 and 0. The output code generated
by the differentiator can be put into the following form:

1
y(n) = (φ(n) + e(n − 1)) (6.146)
2π
1
= (Kvi (n) − e(n) + e(n − 1)) (6.147)
2π
406 Data Converters, Phase-Locked Loops, and Their Applications

Using z-transforms, it can be shown that

1
Y (z) = (KVi (z) − E(z) + z −1 E(z)) (6.148)
2π
1
= (KVi (z) − (1 − z −1 )E(z)) (6.149)
2π
Hence, the VCO-based ADC achieves a first-order noise shaping. An output
decimation stage is required to filter out unwanted out-of-band quantization
noise.

6.9 PLL based on time-to-digital converter

PLL can also be designed using time-to-digital converters (TDCs) that gener-
ally find applications in time difference measurements. It has the advantage of
requiring a simple digital lowpass filter instead of the conventional PLL loop
filter that demands large and leaky integrating capacitors.

Digital loop filter

kp

DCO
CK START
TDC Σ DAC VCO Out
STOP
+

ki
Q D
SCK
Retimer CK
Accumulator

Frequency divider
N

∆Σ Modulator
N

FIGURE 6.95
Fractional-N PLL based on TDC.

A fractional-N PLL based on a TDC is shown in Figure 6.95, where the

programmable multi-modulus frequency divider is controlled by a delta-sigma
modulator to achieve a fractional frequency resolution, and SCK is the system
clock signal available at the output of the retimer flip-flops that synchronize
the reference (or feedback) clock signal, RCK, with the incoming clock signal,
Circuits for Signal Generation and Synchronization 407
Coarse
tuning
P−Q MSBs
FCW DLF VCO Out
P P Q LSBs

Σ ∆Σ Mod DAC Fine

+ tuning

1 − z−1
Q D
Differentiator SCK
CK START
Variable
Retimer CK
phase
TDC Accumulator
STOP
Phase
Σ
error

Counter
Reference
phase

FIGURE 6.96
PLL based on counter-assisted TDC.

CK. Note that SCK serves also as a clock signal for building blocks with
synchronization and purely digital logic functions.
A fractional-N PLL can also be designed by using a counter-assisted
TDC [48], as shown in Figure 6.96. In the phase-locked state, the desired
PLL output frequency is equal to the reference frequency multiplied by the
value of the frequency command word (FCW). By defining the FCW as the
fractional frequency division ratio, the fine frequency resolution is set by the
FCW word length, P .
The phase error quantizer, which consists of a counter, a TDC, and an
adder, compares the variable phase of the output signal with the phase of
the reference clock signal (CK). The counter can be considered to have a
resolution of 2π because it is incremented by one at every rising edge of the
output signal. To achieve a fine resolution, the TDC measures the fractional
phase, or time interval between the reference edge and the preceding rising
edge of the output signal.
The TDC should include output synchronization flip-flops triggered by the
PLL output signal because the TDC and counter operations are synchronized
to the edges of the reference clock signal and PLL output signal, respectively,
instead of the same signal.
The digital phase error is differentiated to obtain a frequency word, which
is then compared with the specified frequency command word (FCW). The
resulting frequency errors are accumulated to generate a phase error sequence
that is used to drive the digital loop filter (DLF).
The most-significant bits (MSBs) of the DLF output are directly used to
control the coarse capacitor array of the VCO, while the least-significant bits
(LSBs) are first applied to a delta-sigma modulator (∆Σ mod) followed by a
408 Data Converters, Phase-Locked Loops, and Their Applications

DAC and the resulting signal is then used to tune the fine capacitor array of
the VCO.
The DLF can consist of a proportional path and an integration path and
be designed using a transfer function of the form

H(z) = HP I (z) (6.150)

where
1
HP I (z) = kp + kI (6.151)
1 − z −1
with kp and kI being constant numbers that can be related to the loop charac-
teristics (bandwidth and phase margin). To suppress out-of-band quantization
noise, the DLF transfer function can alternatively be chosen as

H(z) = HP I (z)HLP F (z) (6.152)

where
4
Y λi
HLP F (z) = (6.153)
i=1
1 − (1 − λi )z −1
and λi are constants.
However, TDC-based PLLs can exhibit phase noise and spurious tone per-
formances that are limited due to the finite resolution of TDC and DCO.

6.9.1 Flash TDC

The classical approach of realizing a TDC consists of counting the number of
sequential inverter delays that occur between two rising edges of START and
STOP signals. Figure 6.97(a) shows a Flash TDC that comprises a chain of
delay elements (or buffers), D flip-flops, and a thermometer-to-binary encoder.
The rising edge of the START signal is successively delayed by a series of
delay elements and applied to the inputs of flip-flops that are triggered at the
rising edges of the STOP signal. A thermometer code, that corresponds to
the number of signal transitions that have occurred within the measurement
interval, △T , is then generated at the flip-flop outputs.
Figure 6.97(b) shows the waveforms illustrating the operation of a TDC
using 4 flip-flops.
In general, the generation of an N -bit output code requires the use of 2N
flip-flops. Hence,
τ = TS /2N (6.154)
and the measured time difference, △T , is given by
N
X
△T = τ 2k−1 bk (6.155)
k=1

where τ is the propagation delay of each buffer, TS is the period of the STOP
Circuits for Signal Generation and Synchronization 409
Delay
buffer
START

D Q D Q D Q D Q
1 2 N−1 N

STOP

Thermometer−to−binary encoder

(a) Out
∆T
Delay
Quantization error
START Q1 = 1

D2 Q = 1
2

D3 Q3 = 1

D4 Q4 = 0

D5 Q5 = 0

STOP
(b)

FIGURE 6.97
(a) Flash TDC; (b) waveform representation.

signal, bk is the k-th bit of the output code, and N is the number of bits of
the output code.
Based on CMOS implementations, the resulting resolution is generally
limited to a few hundred picoseconds.

6.9.2 Vernier TDC

The improvement of the resolution can be achieved by adopting a Vernier
TDC structure, as shown in Figure 6.98, where two chains of delay elements
are used.
Assuming that the propagation delay of a buffer in the upper chain, tau1 ,
is slightly greater than the one of a buffer in the lower chain, τ2 , the time
difference between the START and the STOP signals is successively decreased
at each TDC stage by τ = τ1 − τ2 , until it becomes less than τ . The time
difference, △T , is measured with the resolution τ and then encoded as a
binary number. Hence,
N
X
△T = τ 2k−1 bk (6.156)
k=1
410 Data Converters, Phase-Locked Loops, and Their Applications

START

D Q D Q D Q D Q
1 2 N−1 N

STOP

Delay
buffer Thermometer−to−binary encoder

(a) Out
∆T Delay1
START Q = 1
1
D Q = 1
2 2
D Q3 = 1
3

D Q = 0
4 4
D Q = 0
5 5

STOP

CK 2 Delay2
CK 3

CK 4

CK 5
(b)

FIGURE 6.98
Vernier TDC.

where bk is the k-th bit of the output code. In practice, the resolution can
be limited by component noise and mismatches. Vernier TDCs can exhibit a
resolution as low as 25 picoseconds.
TDC architectures based on chains of delay elements are simple. However,
their dynamic range, DR = 2N τ , can be extended only by augmenting the
number of delay elements, which, in turn, leads to an increase of the power
consumption and a decrease of the maximum sampling rate. An improvement
can be achieved by adopting TDCs based on switched ring oscillators.

6.9.3 Switched ring oscillator TDC

A switched ring oscillator (SRO) TDC [49] is an alternative architecture to
achieve sub-gate-delay resolution. It relies on ring VCOs that are switched
between two frequencies to achieve a first-order noise shaping of the quantiza-
tion error. The input signal is integrated by VCOs, whose output phases are
quantized and then differentiated. The quantization error is first-order shaped
because its value at the end of a measurement period is transferred to the next
Circuits for Signal Generation and Synchronization 411

measurement period. The TDC resolution can be improved by choosing high

oversampling ratios.

I1
+
+

VH I2

Phase quantizer

Differentiator
ROM encoder
+
V+ T VC + B
T IN VL
Time difference generator

IN
+
+

Digital
CK Σ output
I1 D0
+
+

T REF VH I2
Phase quantizer

ROM encoder

Differentiator
+
V− T VC + B

VL

IN
+
+

FIGURE 6.99
Block diagram of an SRO TDC.

VDD

T2
Vi+ V0−
T1
T IN Up R
V+
T
PFD VC
VT−
T REF Dn R
T3
Vi− V0+
T4

VDD
(a) (b)

FIGURE 6.100
(a) Block diagram of the time difference generator; (b) circuit diagram of the
VCO delay stage.
412 Data Converters, Phase-Locked Loops, and Their Applications

D Q
I1 S1
D
Q
SN+1

D Q
I2 S2
D
Q
SN+2

D Q
I N−1 SN−1
D
Q
S2N−1

D Q
IN SN
D
CK Q

FIGURE 6.101
Circuit diagram of the phase quantizer.

TABLE 6.3
ROM Encoder for N = 16
Address Data Out
S1 00001
S2 00010
S3 00011
S4 00100
.. ..
. .
S28 11100
S29 11101
S30 11110
S31 11111

The block diagram of the SRO-TDC is shown in Figure 6.99. It consists

of a time difference generator, VCOs, phase quantizers, read-only memory
(ROM) encoders, digital differentiators, and a B-bit subtractor. The time
difference generator provides a continuous-time pulse-width modulated signal
that corresponds to the time difference between the input signal, TIN , and
Circuits for Signal Generation and Synchronization 413

reference signal, TREF , and is used to switch the VCO control voltages between
two reference levels, VH and VL . The oscillation frequency of VCOs can be
set either at FH or at FL , depending on the (high or low) value of the control
voltages. The VCO phase accumulation is achieved at a faster rate for FH
than for FL , because FH is higher than FL . The VCO output phases roll
over to zero when they reach 2π. They are quantized before being applied
to ROM encoders. The ROM encoder outputs are differentiated and then
applied to the subtractor that generates the TDC output code. The phase
wrapping around 2π is taken into account by using modulo (two’s complement)
arithmetic operations in the differentiators.
Note that the phase accumulation will not exceed π radians in one clock
period, if FH is selected to be less than fs /2, with fs being the sampling
frequency.
The block diagram of the time difference generator is represented in Fig-
ure 6.100(a). It is realized using a phase-frequency detector (PFD) and XOR
gates (or a single differential XOR gate).
The VCO is based on the delay stage, whose circuit diagram is depicted
in Figure 6.100(b). To obtain a pseudo-differential structure, resistors are in-
serted in feedforward paths, and the sources of all NMOS transistors are con-
nected to the control voltage.
Figure 6.101 shows the circuit diagram of the phase quantizer. Sense-
amplifier D flip-flops are used to sample the VCO output phase, while a tran-
sition detector consisting of AND gates compares adjacent sampled phases to
detect phase transitions.
The content of a ROM encoder for N = 16 is represented in Table 6.3.
The transition decoder outputs are used to address the ROM encoder that
converts the thermometer-coded values of the quantized VCO phases into a
5-bit binary code with 31 levels.
The following figure-of-merit (FOM) can be used to characterize noise-
shaping TDCs:
P
FOM = ENOB (6.157)
2 × min(2fi , fs )
where fi represents the input signal frequency, fs is the sampling frequency,
P denotes the power consumption, ENOB is the effective number of bits that
can be obtained as ENOB = (SNDR − 1.76)/6.02, and SNDR is the signal-to-
noise-plus distortion ratio.

6.10 High-speed input/output link transceiver

Clock and data recovery (CDR) circuits are generally required in the design of
a high-speed input/output (I/O) bus based on standards such as Peripheral
414 Data Converters, Phase-Locked Loops, and Their Applications

Component Interconnect Express (PCIe), QuickPath Interconnect (QPI), and

Double Data Rate (DDR).

Chip 1 Connector
Package
Socket
Line card
Backplane
Via stub trace

Chip 2
Package
Socket
Line card

Line card trace Board

FIGURE 6.102
Representation of a line card/backplane link.

Timing margin Sampling point

UI

1
Amplitude

Vertical
Jitter eye opening

−1

Voltage noise
t−T t+T
Time
Voltage margin

FIGURE 6.103
Outline of a binary eye diagram.

A typical backplane/line card application is shown in Figure 6.102. The

I/O link transceiver goal is to achieve a multi-gigabit-per-second signaling rate
for the communication from the chip on one line card to the chip on another
line card and with the lowest power consumption. However, the undesirable
electrical characteristics of the transmission channel (or the long trace on
the line card and backplane) and crosstalk between neighboring channels can
degrade the signal waveform. Specifically, the transmitted signal is affected by
skin effects and dielectric losses of the channel and reflections due to via stubs
on circuit boards and other impedance discontinuities of the chip packages
Circuits for Signal Generation and Synchronization 415

and connectors. This can result in signal attenuation of about 20-30 dB for
10-Gb/s data and inter-symbol interference (ISI) that can be seen from an eye
diagram.
The dispersive nature of the transmission channel can lead to a significant
spreading of the data pulse. That is, adjacent symbols can overlap into each
other, resulting in inter-symbol interference and possible bit errors.

The bit error rate (BER) is the likelihood of a bit misinterpretation

due to component imperfection. In the presence of a noise source charac-
terized by a Gaussian distribution with zero mean, the BER expression
is given by  
Vz,pp 
BER = Q  q (6.158)
2
2 Vz,n
2 are the peak-to-peak voltage swing (or vertical eye
where Vz,pp and Vz,n
opening) and noise voltage variance at the input of the decision device,
respectively, and the Q-function is defined as
Z ∞  
1 u2
Q(x) = √ exp − du (6.159)
2π x 2

When the comparator used in the implementation of the decision device

is assumed to have a decision threshold voltage, Vthr , and the probability
of the transmitted signal taking one of both logic states is the same, or
say equal to 1/2, the BER expression can be rewritten as
   
1 Vz,pp /2 − Vthr  1  Vz,pp /2 + Vthr 
BER = Q  q + Q q (6.160)
2 V2 2 V2
z,n z,n

where Vthr may be affected by the comparator offset voltage, Vof f . With
the voltage Vthr set to 0, for instance, the value of Vz,pp required for a
BER of 10−12 is such that
q
2
Vz,pp ≥ 14 Vz,n (6.161)

because Q(7) ≃ 10−12 . Note that the BER can also be obtained by
transmitting a pseudo-random bit stream to the channel and recording
the number of transmission errors.

To display the eye diagram on an oscilloscope, the signal of interest is

repetitively sampled and applied to the vertical input, while the horizontal
416 Data Converters, Phase-Locked Loops, and Their Applications

time base is synchronized to the symbol rate. An eye diagram, as represented in

Figure 6.103, can indicate the best point for sampling, the amount of jitter, and
voltage noise. With increasing data rates, the effect of the ISI that makes the
width of a data bit exceed one data period (also known as a unit interval, UI)
becomes dominant. It is caused by the superposition of delayed and distorted
versions of the signal and results in the reduction of both the voltage and
timing margins in which the signal can be sampled, so that the bit error rate
(BER) is improved. In practice, the ISI effect is mitigated using equalizers
with an appropriate number of coefficients (generally less or equal to 16).

Coefficient
update
x(t) ∆ ∆ ∆

a0 a1 a2 a N−1
e
N
d Σ
Σ
Buffer
y FIFO
Tx D0
FFE CK register

FIGURE 6.104
Block diagram of the transmitter section with a feedforward equalizer.

CK
CDR
RCK
BC DFE

z z FIFO
Rx Di CTLE Σ Retimer Data
u register

Σ
Σ

e
bM b2 b1
Coefficient
Update

∆ ∆ ∆
M

FIGURE 6.105
Block diagram of the receiver section with a decision feedback equalizer.

I/O circuits are composed of transmitter (Tx) and receiver (Rx) sections.
The Tx block diagram is shown in Figure 6.104. It consists of a feedforward
equalizer (FFE), first-in first-out (FIFO) registers, and buffers.
A FFE is used to realize the transmit pre-emphasis, or the pre-distortion
of the transmitted signal to anticipate the channel distortion and loss. Espe-
Circuits for Signal Generation and Synchronization 417

cially, it adjusts the magnitude of high-frequency signal components that are

supposed to be attenuated by the channel.
The FFE error signal is of the form, e = d − y, where d represents the
desired signal and y is the equalizer output computed as follows:
N
X −1
y(k) = an x(k − n) (6.162)
n=0

To minimize the error function E(e2 ) approximated by the instantaneous es-

timate e2 , the equalizer coefficients are updated in a direction opposite to the
gradient of the error signal power given by

∂e2 (k)
= −2e(k)x(k − n) (6.163)
∂an

In the discrete-time domain, the equalizer coefficients are estimated by means

of the least-mean square (LMS) algorithm according to

∂e2 (k)
an (k) = an (k − 1) − µ (6.164)
∂an
= an (k − 1) + 2µe(k)x(k − n) n = 0, 1, · · · , N − 1 (6.165)

where µ is the adaptation step size. In the continuous-time domain, the coef-
ficient update equations are equivalently expressed as

dan (t)
= 2µe(t)x(t − n△) n = 0, 1, · · · , N − 1 (6.166)
dt
To reduce the hardware complexity, a sign-sign LMS algorithm, where the er-
ror e and samples of the input signal x are replaced by their respective signs,
can be adopted.

The Rx block diagram is represented in Figure 6.105. It is composed of a

continuous-time linear equalizer (CTLE), a decision feedback equalizer (DFE),
a clock data recovery (CDR) circuit, retimer flip-flops, and FIFO registers.
A CTLE can consist of several cascaded gain stages, as shown in Fig-
ure 6.106. It is designed to provide a digitally selected amplification to high-
frequency signal components.

A peaking gain stage can be based on the source-degenerated differen-

tial pair structure shown in Figure 6.107(a). Assuming that the gain stage
is loaded by capacitors CL and modeling the input transistors as a simple
transconductance gm , we can obtain the following transfer function:

1 + s/ωz
G(s) = G0 (6.167)
(1 + s/ωp1 )(1 + s/ωp2 )
418 Data Converters, Phase-Locked Loops, and Their Applications
CTLE

Peak Gain Gain

In Out

BC

FIGURE 6.106
Block diagram of a CTLE.
VDD 12

RL RL
8
V0
Gain (dB) 4
Vi
T1 T2
0
CS
−4
R S tuning

−8
RS C S tuning
IB IB
−12
10 7 10 8 10 9 10 10 10 11
(a) (b) Frequency (Hz)

FIGURE 6.107
Peaking gain stage (a) and its magnitude frequency response (b).
VDD

VDD RL RL
2

RL RL
VDD 1 1
V0
RL RL
T3 T4
V0
RF
Vi Vi
T1 T2 T1 T2
T5 T6

RF

RS RS IB
1 RS 3
2
IB IB IB IB IB IB
1 1 2 2

(a) (b)

FIGURE 6.108
(a) Conventional gain stage; (b) gain stage with active feedback.

where
gm RL
G0 = (6.168)
1 + gm RS
ωz = 1/RS CS (6.169)
1 + gm RS /2
ωp1 = (6.170)
RS CS
Circuits for Signal Generation and Synchronization 419

and

ωp2 = 1/RL CL (6.171)

By implementing RS and CS as digitally programmable resistor and capacitor

arrays, respectively, the peaking gain stage should provide a high-frequency
boost, whose peak can be controlled by a digital code. Figure 6.107 shows the
effect of tuning either the resistor RS , or the capacitor CS , on the magnitude
frequency response. The level of the high-frequency boost is modified essen-
tially by varying the capacitor CS , while variations of the resistor RS affect
both the high-frequency boost and dc gain.
The amplification provided by the peaking gain stage may be insufficient.
Other amplifier stages are then required to maximize both the gain and band-
width. Figure 6.108(a) shows a conventional gain stage, while Figure 6.108(b)
presents a gain stage with active feedback.
The multistage CTLE can provide a peaking in the order of 25 dB at
Nyquist frequency corresponding to the data bit rate.

Possible error
Original signal

Decision
Channel
threshold

0 0 1 0 1 1 0 0 0
Feedback
compensation sequence

0 0 1 1 1 1 0 0 0 Without equalization
0 0 1 0 1 1 0 0 0 With equalization

FIGURE 6.109
Signal waveforms illustrating the operation of a DFE.

A DFE [50] is required to mitigate the channel ISI. It makes use of pre-
vious decisions to cancel the interference from symbols that are subsequently
received. The feedback filter helps cancel the post-cursor ISI. The difference
between the input, z, and output, ẑ, of the decision device constitutes an
error signal, e = ẑ − z, which can then be minimized to update the equal-
izer coefficients. In the discrete-time domain, this translates into the following
equations:

∂e2 (k)
bm (k) = bm (k − 1) − µ (6.172)
∂bm
= bm (k − 1) − 2µe(k)ẑ(k − m) m = 1, 2, · · · , M (6.173)

where ∂e2 (k)/∂bm = 2e(k)ẑ(k − m) and µ is the adaptation step size. The
420 Data Converters, Phase-Locked Loops, and Their Applications

implementation complexity can be reduced by using the sign-sign LMS algo-

rithm. That is:

bm (k) = bm (k − 1) − 2µsign(e(k))sign(ẑ(k − m)) m = 1, 2, · · · , M (6.174)

In the continuous-time domain, the coefficient update equations can equiva-

lently be expressed as:
dbm (t)
= −2µe(t)ẑ(t − m△) m = 1, 2, · · · , M (6.175)
dt
The optimum equalizer coefficients are such that the ISI contributions of the
previous symbols are canceled from the current decision.
Figure 6.109 shows signal waveforms illustrating the operation of a DFE.
Due to ISI, when the data sequence 001011000 is transmitted without equal-
ization, the received data sequence 001111000 contains a possible error due to
the effect of the channel ISI. With the use of an appropriate DFE, the margin
between data bits is now restored so that the received data sequence is likely
to be sampled correctly. Note that the DFE can be considered as a non-linear
equalizer because of the non-linear characteristic of the decision device.

VDD

RL RL

V0

Vi z1 z2 zM
T1 T2 T21 T22 T42 T2M T4M
T11 T12 T32 T1M T3M

RS
IB IB IB IB IB
IB IB 1 2 2 M M

FIGURE 6.110
Circuit diagram of the DFE input summer stage.

The filter section of the DFE consists of delay elements that can be imple-
mented using D flip-flops or sample-and-hold circuits and an input summer
stage. Let u be the input signal of the DFE provided by the CTLE. The signal
at the input of the decision device is given by
M
X
z(k) = u(k) − bm (k)ẑ(k − m) (6.176)
m=1

where the equalizer coefficients and samples of the decision device output
signal are represented by bm and ẑ(k − m), respectively. Figure 6.110 shows
the circuit diagram of the DFE input summer stage. The summation in cur-
rent mode generally offers the advantage of a simple implementation and high
Circuits for Signal Generation and Synchronization 421

operation speed over its voltage mode counterpart. Adjustable equalizer co-
efficients (or post-cursor taps) are implemented by using transconductance
stages with variable tail currents, IBj , where j = 1, · · · M , that can be con-
trolled by digital-to-analog converters (DACs) with resolution of at least 6
bits. Hence, the magnitude of the feedback tap coefficient currents are set
by DAC-controlled current sources that are driven by digital DFE update
circuits. The first post-cursor tap is set to a negative polarity, while other
post-cursor taps are designed with a bipolar polarity to take into account the
effect of reflections that can occur in some channels. The summer settling
performance can be limited by the RC time constant set by the output load
resistance and capacitance. To accurately cancel the post-cursor ISI from the
most recent bit, all operations performed by the DFE must be completed in
one UI, or say before the arrival of the next symbol.

Σ + z odd
d
e D Q
−
b1
Σ
CK
1
u z
u Σ z 0
z
b1
Coefficient

b1 CK
Update

CK
Σ +
D Q
− z even
∆
(a) (b)
CK

b1 −
u 1
CK D Q z
0
+
CK
b1 −
CK
(c)

FIGURE 6.111
(a) Block diagram of a one-tap equalizer; (b) half-rate implementation; (c)
implementation using loop unrolling.

For the specific case of a 10-Gb/s binary link, the UI of 100 ps may not be
sufficient to allow the DFE operating at the full rate to settle as required. The
critical timing constraints can be alleviated by adopting time-interleaved (half-
rate, quarter-rate or eighth-rate) architectures and using DFE loop unrolling
422 Data Converters, Phase-Locked Loops, and Their Applications

(or coefficient speculation) [51, 52], but at the expense of increased power
consumption and chip area. Due to the fact that the number of parallel slicing
paths grows as a power of two of the number of speculative coefficients, the
loop unrolling is often limited to the first coefficient) [53] and helps eliminate
the potential feedback delay associated with the first coefficient.
The block diagram of a one-tap equalizer is shown in Figure 6.111(a), while
the corresponding half-rate and unrolled implementations are depicted in Fig-
ures 6.111(b) and (c), respectively. A half-rate DFE still has the same timing
constraint for comparators and latches as the full-rate DFE, but specifications
of the clock buffer are relaxed.
In the one-tap DFE implementation using loop unrolling, the timing con-
straint of the feedback loop is alleviated by making two speculative decisions
each cycle. Hence, it is necessary to use two comparators with thresholds set
by the first coefficient and its negative value, respectively. The decision of one
comparator is made as if the previous output was in the high logic state, and
the decision of the other comparator as if the previous output bit was in the
low logic state. The multiplexer then selects one of both decisions once the
logic state of the previous bit is known.
TC
Eye E out
monitor

CK
u CDR Out
In CTLE Σ
z z
RCK
EN
Modulo−M
FBE counter C
Count

Update &
control logic

FIGURE 6.112
Block diagram of an eye monitor-based equalizer.

At high BERs, an adaptive equalizer designed to minimize the comparator

decision error can exhibit a performance that is degraded due to the channel
noise and loading effects of the internal equalizer nodes. In this case, the
adaptation approach relying on the error estimated by an eye monitor can
contribute to a performance improvement.
The block diagram of an eye monitor-based equalizer is shown in Fig-
ure 6.112. The eye monitor provides an error signal that can be used as a
figure of merit for monitoring the equalizer performance, and for adapting the
feedback equalizer (FBE) coefficients and tuning the CTLE. The counter has
Circuits for Signal Generation and Synchronization 423
D Q
1a

TC DAC
1 D Q
1b
z +
D Q
VT − 1c
1

D Q
D Q
1d

D Q Retimer,
2a combiner E out
& M

D Q 2

Early
2b Sel
VT +
2 D Q
− 2c

D Q Frequency
TC DAC D Q D Q
2 2d divider
Early

M
Late

I0 Q0 512 CK out
D Q D Q D Q
15 2
rotator

rotator
Phase

Phase

CK Q CK Q Register
φ late
15
Sel

Early
Register
I0 φ early
RCK 2 Q0
I0

FIGURE 6.113
Block diagram of an eye monitor.

a modulo M . It is reset whenever the count reaches M − 1, and the carry-out

signal C0 is then set to 1. The CDR generates the sampling clock by aligning
the phase of the reference clock signal CK to the transitions of the incoming
data stream. The recovered data is then obtained by sampling the incoming
data with a recovered clock.
An eye monitor can be implemented as shown in Figure 6.113. It uses a
rectangular mask to characterize the opening of an eye diagram. An error is
detected whenever a data transition passes inside the mask. The eye monitor
output can be related to the mask error rate (MER), or say, the number of
data transitions that fall inside the defined mask normalized by the whole
number of transitions during the same time period. Hence,

N × fout
MER = (6.177)
BR
where fout is the frequency of the output error signal, N is the total divide
ratio inserted in the signal path, and BR is the input bit rate.
The operation of the eye monitor is illustrated in Figure 6.114. The ver-
tical opening of the mask is specified by two reference voltages, VT1 and VT2 ,
while the horizontal opening is set by two phases of the sampling clock sig-
nal, CKEarly and CKLate . The eye trace labeled with a circled 1 is error-free
424 Data Converters, Phase-Locked Loops, and Their Applications

VT
1 1
2
3

VT
2

t Early t Late

Data sampled at the rising

edges of clock signals

Data

Error
Q
1,Early

Q
2,Early
Error
Q
1,Late

Q
2,Late
CK Early CK Late

FIGURE 6.114
Illustration of the eye monitor operation.

while eye traces labeled with a circled 2 and a circled 3 are related to a mask
violation. Signals obtained by comparing the incoming data with VT1 and VT2
are sampled at instants determined by both CKEarly and CKLate . For each
sampling clock signal, the difference between the sampled values is detected
using an XOR logic gate that can generate a pulse signal whenever a violation
occurs for each side of the mask. An OR logic gate is then required to combine
the resulting error signals. One violation for each side of the mask can be ob-
served in the timing diagram of Figure 6.114. Note that the errors associated
to the left and right sides of the mask can also be counted separately.
The CDR can also be designed to be decision-directed by the eye moni-
tor [54].
Output drivers can be realized as a limiting amplifier or a linear ampli-
fier that can drive various output loads and appropriately set the differential
voltage output swing, say from 800 mV to 1200 mV, for instance.
Circuits for Signal Generation and Synchronization 425

6.11 Relaxation oscillator

Relaxation oscillators can be used to produce triangular and clock signals.
They find applications in the design of class D power amplifiers, switching
power supplies, dual-slope analog-to-digital converters, and function genera-
tors.
VT τd

VDD VH

I VH − 0 t

VL
+
VT S Q
τd
C R Q Q
−
1

I VL + 0 t
Q
1

0 t
(a) (b)

FIGURE 6.115
(a) Block diagram of a relaxation oscillator; (b) waveforms.

VDD
T13 T12 T11 T3

T6 T5 T1 VH −

+
VT S Q
VREF +
T12
VDD C R Q
− T9 −
T10 T6 T2

VDD VL +

R T8 T7 T4

FIGURE 6.116
Circuit diagram of a relaxation oscillator.

The block diagram of a relaxation oscillator is represented in Fig-

ure 6.115(a). The constant currents I1 and I2 that are used to charge and
discharge the capacitor C are provided by a reference generator. Two com-
parators determine whether the voltage, VT , across the capacitor C exceeds
426 Data Converters, Phase-Locked Loops, and Their Applications

the threshold voltages VH and VL , and then set or reset an SR latch. When
the voltage VT rises above VH , the output of the upper comparator changes
to the high state, and the outputs Q and Q then become 1 and 0, respec-
tively. Consequently, the switch S1 is open while S2 is closed, leading to the
discharge of the capacitor C through the current sink I2 . On the other hand,
when the voltage VT falls below VL , the output of the lower comparator goes
to the high state, and the outputs Q and Q become 0 and 1, respectively. The
capacitor C can then be charged by the current source I1 , because the switch
S1 is closed while S2 is open. Figure 6.115(b) shows waveforms that illustrate
the operation of the relaxation oscillator.
The period of the resulting oscillation can be expressed as
 
1 1 1
T = = Tc + Td = C(VH − VL ) + + 4τd (6.178)
f I1 I2
where Tc and Td are the charging and discharging times, respectively, τd is
the propagation delay from the comparator inputs to the SR latch outputs,
and f is the oscillation frequency. The oscillation period is sensitive to process
fluctuations because it is a function of process-dependent characteristics (I1 ,
I2 , and τd ). The adoption of process variation-aware design techniques can
help improve the accuracy of the oscillation period.
The circuit diagram of the relaxation oscillator is represented in Fig-
ure 6.116. Transistors T1 −T4 operate as switches. Note that transistors T3 and
T4 help reduce the effect of charge sharing that can be associated to parasitic
capacitances. For oscillations in the kilohertz range, the capacitor C should
be in the order of few picofarads.

6.12 Class D amplifier

A class D power amplifier is basically a non-linear switching amplifier. It relies
on the principle of pulse-width modulation (PWM) to generate a rectangular
wave signal that is used to drive switching output stages in either single-
ended or bridge-tied-load configurations. The efficiency of a class D amplifier
can reach 100% in the ideal case, but it is in the order of 90% in practical
designs.
In comparison with open-loop structures, closed-loop class D power ampli-
fiers offer the advantages of reducing the non-ideal effects that can be caused
by switching dead times, finite on-resistances of switches, and supply voltage
noises [55].
The circuit diagram of a class D amplifier with a second-order loop filter
is represented in Figure 6.117. It includes a loop filter, two comparators, two
drivers, four power MOSFET switches, LC filters, and a speaker. For audio
applications, the input frequency is typically comprised between 20 Hz and 20
Circuits for Signal Generation and Synchronization 427
R2

VDD
C C
L +
M2 V0

Driver
R + V+
V−
F
R1 − C0
M1
Vi+ −+ − VSS
VT
Vi− + − VDD
M4
R1 −
VF+ L −
V0
V−

Driver
+
C C

C0
R M3
− VSS
R2

FIGURE 6.117
Circuit diagram of a class D amplifier using a triangular reference signal.

kHz. The difference of the loop filter output signals is compared with a high-
frequency triangular signal to generate a pulse-width modulated signal that
is used to drive the switching output stage. The duty cycle of the pulse-width
modulated signal is such that its average content corresponds to the input
analog signal. Figure 6.118 shows the waveforms illustrating the operation
of a class D amplifier. The outputs V + et V − are not two complementary
signals of equal amplitude but opposite phase. In addition to the differential
voltage, Vd = V + − V − , there is thus a significant common-mode component,
Vc , available at the outputs.

In the time domain, the filter output can be expressed as

VF (t) = h(t) ∗ [Vi (t) + V (t)] (6.179)

where ∗ is the convolution product, h(t) represents the loop

filter impulse response, VF (t) = VF+ (t) − VF− (t) and V (t) =
V + (t) − V − (t). More specifically, we have
(
+ 1 if VF+ (t) > VT (t)
V (t) = (6.180)
0 if VF+ (t) < VT (t)

and (
1 if VF− (t) > VT (t)
V − (t) = (6.181)
0 if VF− (t) < VT (t)
428 Data Converters, Phase-Locked Loops, and Their Applications
VF+ VT VF−
1

−1
Time

1
V+
0
Time

1
V−
0
Time

1
Vd 0
−1
Time

1
Vc 0.5

0
Time

FIGURE 6.118
Class D amplifier waveforms.

The differential rectangular-wave PWM signal V (t) can take

each of the values 1, 0, and −1. It is fed back to the loop filter
input, providing the negative feedback.

Gate V
driver DD
V
PWM

Delay M2
∆
V
∆

M1
− VSS

FIGURE 6.119
Half bridge with the switch driver.
Circuits for Signal Generation and Synchronization 429

Switch drivers are required in order to quickly turn on and off the power
MOSFETs, because comparators are unable to support large currents. They
can be realized based on the operation principle of a two-phase nonoverlapping
clock signal generator and a level shifter. Figure 6.119 shows half bridge with
the switch driver that can help control the delay between turn-on times, as
required to reduce the total harmonic distortion. The gate driver and delay
can be implemented by cascading an even number of inverters.
A pulse-width modulated waveform can be generated by comparing a sig-
nal with a reference (carrier) signal. The carrier is chosen as a sawtooth wave-
form and a triangle waveform to perform a single-sided modulation (leading
or trailing edge) and a double-sided modulation, respectively [56]. The spec-
tral characteristics of the signal obtained by modulating a sine wave can be
determined using double Fourier series (see Appendix B.2).
Consider an input sine wave of the form, M · A · π cos(ωt), with A rep-
resenting the amplitude. In the case of a double-sided modulation, it can be
shown that

VP W M (t) = M · A cos(ωt)
 
m·M m + n  n   n 
+∞ J
2 π
+∞ X
X n
− 4A sin π sin π sin mωc t + nωt − π
m=1 n=−∞
mπ 2 2 2
n6= 0
(6.182)

where M is the modulation index, ωc is the angle frequency of the carrier

signal, Jn represents the Bessel function of n-th order, n is the index to the
harmonics of the input signal, and m denotes the index to the harmonics of
the carrier signal.
It can be noted that only intermodulation components at mωc t ± nωt are
present in the spectrum. Because the modulated signal does not contain any
harmonics of the carrier frequency, the intermodulation components with the
lowest angle frequencies are located around 2ωc .
On the other hand, the double-sided modulation produces a signal that
exhibits a common-mode component, and is then also known as a three-level
(class BD) pulse-width modulated signal.
Generally, a post filter is required at the amplifier output for the inter-
modulation component suppression.
An LC filter is required for the reduction of high-frequency undesired com-
ponents related to the modulation process. Its frequency response varies with
the speaker load impedance. The equivalent circuit of the LC filter is repre-
sented in Figure 6.120(a). For differential signals, the load resistance, RL , is
equal to half the speaker resistance. The transfer function of the LC filter can
then be put into the form,

V0d (s) ω02

H(s) = = 2 (6.183)
Vi (s) s + s(ω0 /Q) + ω02
430 Data Converters, Phase-Locked Loops, and Their Applications

10
L V0
Vi 0

Gain (dB)
C1 RL −10 Q = 0.707
Q = 1.4
−20 Q = 0.3

−30
10 3 10 4 10 5
(a) (b) Frequency (Hz)

FIGURE 6.120
LC filter (a) equivalent circuit and (b) gain response.

√ p
where ω0 = 1/ LC and√Q = RL C/L. The LC filter frequency √ response is
overdamped for Q √ < 1/ 2, critically damped when Q = 1/ 2, and under-
damped for Q > 1/ 2. The effect of Q on the frequency response is illustrated
in Figure 6.120(b). The critically damped response is preferred because a high
peaking can cause the amplifier to malfunction due to the operation in over-
current condition, while the overdamped response can be related to the loss
of some high-frequency components of the audio signal. A typical LC filter
has a Butterworth response with a cut-off frequency√of about 40 kHz and can
exhibit a maximally flat passband. Hence, Q = 1/ 2 and the values of the
filter components can be derived as follows:
√ √
C = 1/( 2RL ω0 ) and L = 2RL /ω0 (6.184)
The load resistance, RL , is equal to half the speaker resistance which is gen-
erally in the range from 4 Ω to 8 Ω.
For common-mode signals, the load resistance RL can be removed. The
transfer function of the resulting lossless LC filter is given by
V0c (s) ω2
H(s) = = 2 0 2 (6.185)
Vi (s) s + ω0
√
where ω0 = 1/ LC.
The choice of Butterworth filter response for 8 Ω speakers results in in-
ductors L of 33 µH that can be very large and bulky for portable devices. A
solution in this case can consist of using a class D amplifier based on filterless
modulation schemes.
For input frequencies up to 20 kHz, a class D amplifier designed with a
carrier frequency of 315 kHz can achieve a maximum power efficiency of about
90%. The total harmonic distortion (THD) computed by taking into account
all harmonics within the audio range (that is, from 20 Hz to 20 kHz) is in the
order of −76 dB when the input frequency is equal to 2 kHz. It is increased
to −66 dB for an input frequency of 6 kHz.
Circuits for Signal Generation and Synchronization 431

To improve the power efficiency, a class D amplifier should be designed with

comparators exhibiting a low propagation delay in the order of a few tens of
nanoseconds and output power MOSFETs featuring low on-resistances.
R4

αR
R3 C3
VDD

R2 C2 (1−α) R
L +
M2 V0

Driver
C1 Phase V+
VF− detector
R1 C0
M1
Vi+ −+ − VSS
VCO
Vi− + − VDD
M4
R1 C1
VF+ L V0−
R2 V−

Driver
C2 CK

R3 C3 (1−α) R C0
M3
− VSS
R4

αR

FIGURE 6.121
Circuit diagram of a class D amplifier using a rectangular reference signal.

For applications requiring a bandwidth up to 500 kHz and a high switch-

ing frequency, such as power-line communications, the class D amplifier of
Figure 6.121, that requires a rectangular reference signal, may be more suit-
able [57]. It consists of a loop filter, a voltage-controlled oscillator (VCO), a
phase detector (PD), an output driver, and a filter. The difference between
the input and output signals is filtered to generate the control voltage of the
VCO. The PWM signal is delivered at the output of the PD that operates
by comparing the phase of the VCO output signal with that of a rectangular
reference signal. It is then used to drive the amplifier output stage.
The VCO can be realized using a pseudo-differential architecture consisting
of current-starved inverters and cross-coupled inverters. In the locked state,
the average of the VCO control signal should ideally be equal to zero. Because
the difference between the input and output signals also has an average value
of zero, the output signal must be identical to the inverted-phase version of
the input signal in the passband frequency range of the loop filter. This is
required so that the loop can track the input signal variations.
A class D amplifier designed with a reference frequency of 20 MHz can
exhibit a power efficiency in the order of 80% and a total harmonic distortion
(THD) of −67 dB for input signal frequencies up to 60 kHz. The power effi-
ciency is reduced to about 70% and the THD is −60 dB when the reference
432 Data Converters, Phase-Locked Loops, and Their Applications

and input frequencies are set to 60 MHz and 500 kHz, respectively. The max-
imum power efficiency is achieved when the duty cycle of the reference signal
is equal to 50%.

6.13 Summary
Circuits for clock signal generation and synchronization were described at the
behavioral and architectural level. Specifically, they are used to reduce the
voltage and timing errors in the clocking or data transmission networks.
In addition to a low jitter performance, it is important to achieve a low
power consumption and die area in portable equipment. Either passive or
active methods can be used to reduce the clock jitter induced by the power
supply noise. The first method employs filters on the power supply lines, while
the second one regulates the power supply by relying on a feedback control
loop that keeps the voltage constant.
Circuit architectures and techniques that can be used in the design of
input/output transceivers for high-speed serial links, relaxation oscillators,
and class D power amplifiers, were also reviewed.

6.14 Circuit design assessment

1. Phase and frequency detector
The phase and frequency detector of Figure 6.122 [2] possess the
advantage of not having a dead zone. Use SPICE simulations to
obtain the transient response of the circuit and show that the error
detection range is limited in the range from −π to π.
2. Single-ended VCO based on inverters
Consider the VCO structure shown in Figure 6.123(a). It consists
of N inverters (see Figure 6.123(b)), capacitors, and transistors op-
erating as switches controlled by Vc .
Why must the number of stages, N , be odd?
With the assumption that each stage can be modeled with a first-
order transfer function of the form
V0 A0
(s) = (6.186)
Vi s
1+
ω0
where A0 is the dc gain and ω0 is the −3 dB bandwidth, find the
oscillation frequency of the VCO.
Circuits for Signal Generation and Synchronization 433
V DD

T1

Dn
T2

T3
Vi

V DD

T4
V
0
Up
T5

T6

FIGURE 6.122
Phase and frequency detector.

CK1 CK2 CKN

V DD
T1

T T TN In Out
1 2
T2
VC
C C C

(a) (b)

FIGURE 6.123
(a) VCO structure; (b) circuit diagram of the inverter.

3. Ring oscillator
A ring oscillator [58], as shown in Figure 6.124, can consist of N
delay stages in a unity feedback loop. For a single-ended configura-
tion, the number N of stages should be odd so that the total phase
shift can satisfy the required oscillation condition.

Assuming that all transistors operate in the saturation region, verify

that the application of Kirchhoff’s current law at the drain node of
434 Data Converters, Phase-Locked Loops, and Their Applications
VDD VDD VDD

R R R
1 V1 2 V2 VN
N

T1 T2 TN
C C C

FIGURE 6.124
Circuit diagram of a ring oscillator.

each delay stage leads to:

V1 − VDD dV1
Node 1 +C + K(VN − VT )2 = 0 (6.187)
R dt
V2 − VDD dV2
Node 2 +C + K(V1 − VT )2 = 0 (6.188)
R dt
.. ..
. .
VN − VDD dVN
Node N +C + K(VN −1 − VT )2 = 0 (6.189)
R dt
where K = (1/2)µn Cox (W/L), C = CL +Cp , CL and Cp are the load
capacitance and the total parasitic capacitance at the drain node
of each delay stage, respectively, and VT is the transistor threshold
voltage.
The output of the ring oscillator can be considered to be a sinusoidal
waveform of the form,
V0 (t) = B + A cos ωt (6.190)
To find the amplitude, A, the dc level, B, and the signal frequency,
f = ω/2π, the phase relationship can be exploited to write:
  
T T
V1 (t) = V2 t + − (6.191)
2 2N
 
N −1
= B + A cos ωt + π (6.192)
N
where T is the signal period.
Show that the current equation for the node 2 can be rewritten as,
B + A cos(ωt) − VDD
− ωCA sin(ωt)
R
   2
N −1
+ K B + A cos ωt + π − VT = 0
N
(6.193)
Circuits for Signal Generation and Synchronization 435

Combining each of the following sets of trigonometric relations,

(1) sin ωt = −1 and cos ωt = 0

(2) sin ωt = 0 and cos ωt = 1
(3) sin ωt = 0 and cos ωt = −1

with Equation (6.193), show that



 B − VDD

 (1) + ωCA + K(B − A sin(π/N ) − VT )2 = 0

 R
B + A − VDD
 (2) + K(B − A cos(π/N ) − VT )2 = 0

 R

(3) B − A − VDD + K(B + A cos(π/N ) − VT )2 = 0

R
(6.194)
Deduce that
1
B = VT + (6.195)
2RK cos(π/N )
v
u
u VDD − B
u − K(B − VT )2
t R
A= (6.196)
K cos2 (π/N )
B − VDD
+ K(B − A sin(π/N ) − VT )2
f= R (6.197)
2πCA

Verify that all transistors operate in the saturation region, provided

V1 (t) ≥ VN (t) − VT , Vk (t) ≥ Vk−1 (t) − VT , where k = 2, · · · , N , and
B − A ≥ VT .
4. Analysis of a second-order PLL
Consider the linear equivalent model of the second-order PLL shown
in Figure 6.125.

Loop
filter
Charge
In PFD pump VCO Out

Frequency divider
N

FIGURE 6.125
Block diagram of a second-order PLL.
436 Data Converters, Phase-Locked Loops, and Their Applications

Estimate the closed-loop phase transfer function, T , of the PLL.

Show that T can be put into the following form:
!
ζ
N 1+2 s
Θ0 (s) ωn
T (s) = = !2 (6.198)
Θi (s) ζ s
1+2 s+
ωn ωn

where
r
Kv IP
ωn = (6.199)
NC
r
1 Kv IP CR2
ζ= (6.200)
2 N

By applying an angular frequency step to the PLL, the input phase

angle, Θi , can be written as
(
0 for t < 0
Θi (t) = (6.201)
△ωt for t > 0

Prove that the phase error is given in the s-domain and time domain
by
△ω
Θe (s) = (1 − T (s)) 2 (6.202)
s
and

 N △ω p
 p
 sin( 1 − ζ 2 ωn t) exp(−ζωn t) for ζ < 1


 ωn 1 − ζ 2
Θe (t) = N △ωt exp(−ωn t) for ζ = 1


 N △ω
 p

 p 2 sinh( ζ 2 − 1ωn t) exp(−ζωn t) for ζ > 1
ωn ζ − 1
(6.203)
respectively.
The noise bandwidth of the PLL is defined as
Z +∞
Bn = |T (jω)|2 dω (6.204)
0

Verify that
1 + 4ζ 2
Bn = N 2 ω n (6.205)
8ζ
The parameter ζ is generally chosen around the value ζm , which
minimizes Bn . Find ζm .
Circuits for Signal Generation and Synchronization 437

5. Frequency detection capability of PDs

A second-order PLL can be modeled using the block diagram shown
in Figure 6.126(a). Practical circuit implementations of full-rate
binary and linear phase detectors (PDs) are represented in Fig-
ures 6.126(b) and (c), respectively. The phase difference between
the center of the data and the rising edge of the clock signal is
represented by θ.
Charge pump θ

VDD Di

I1
RCK
Up Loop filter Dn
VCO
Di S1 I
P VP Di D Q D Q
PD VP Kv s RCK Up
1 2
Dn Q Q
S2 R
RCK
I2 C
Q Q
3 4
D Q D Q

(a) (b)

Up

Dn
Di D Q D Q
1 2 D0
RCK Q Q

(c)

FIGURE 6.126
(a) PLL block diagram; (b) full-rate binary PD; (c) full-rate linear PD.

αΙ

1
Average CP current

Average CP current

1 2 αΙ
2 αΙ

0 0

1
2 αΙ 1
2 αΙ
n=4
αΙ n=2
n=1
−π 0 π 0 fD 2 fD 3 fD 2 2 fD
i i i i
(a) Phase (b) Clock signal frequency

FIGURE 6.127
Phase (a) and frequency (b) characteristics of a full-rate binary PD.

To show that the full-rate binary PD does not have a frequency

detection capability, verify that:
− the phase and frequency characteristics of the full-rate binary PD
can be obtained as shown in Figures 6.127(a) and (b), respectively.
438 Data Converters, Phase-Locked Loops, and Their Applications
f RCK

fD
i

f RCK (0)

t
0 τ

FIGURE 6.128
Transient response of the frequency acquisition loop.

− the average CP output current, I¯P , is always equal to zero re-

gardless of θ if fRCK = fDi /2k , where k is an integer.
For restricted frequencies of the clock signal, the full-rate linear PD
can detect a frequency difference, and can then be used in the imple-
mentation of clock and data recovery circuits based on a single-loop
architecture, as shown in Figure 6.126(a). Its average CP current
as a function of the clock frequency is given by
  
 αI 1 − fRCK if fRCK ≤ fDi
I¯P = 2 fDi (6.206)

0 if fRCK > fDi

where α is the bit transition density.

Use the following equations
dVP (t) I¯P (t) dI¯P (t)
= +R (6.207)
dt C dt
fRCK (t) = Kv VP (t) (6.208)

to show that
dfRCK (t)
+ AfRCK (t) = B (6.209)
dt
where
Kv αI/2CfDi
A= (6.210)
1 + Kv RαI/2fDi
Kv αI/2C
B= (6.211)
1 + Kv RαI/2fDi

Deduce that the frequency acquisition loop has a first-order tran-

sient behavior from the initial state to the final state, as shown in
Figure 6.128, that can be described by:

fRCK (t) = fDi − (fDi − fRCK (0)) e−t/τ (6.212)

Circuits for Signal Generation and Synchronization 439

where the time constant can be written as

 2fDi 
τ = RC 1 + (6.213)
Kv RαI

The following loop parameters can be used for simulations: R = 1

kΩ, C = 160 pF, α = 0.5, I = 100 µA, Kv = 2 GHZ/V, fDi = 2
GHz, fRCK (0) = 1 GHz.
6. Jitter-peaking-free PLL
Consider the PLL of Figure 6.129(a) that consists of a phase de-
tector (PD), a charge pump circuit, a loop filter, and a voltage-
controlled oscillator (VCO). The loop filter transfer function is given
by
Vf (s) 1 1 + s/ωz
H(s) = =R+ = (6.214)
Ip (s) sC sC
where ωz = 1/RC.
Charge pump
VDD
I1

Up VCO
In S1 I Loop filter
P
PD VP Kv s Out
Dn
S2 R JTRAN
JTOL
Gm
I2 C
G0
Gain

(a)

Phase detector
& charge pump
Filter VCO
Θe Kp
ωz ωp ωp
Θi Σ H(s) Kv s Θ0 1 2
Vp Vf
(c) Frequency

(b)

FIGURE 6.129
PLL block diagram (a) and its linear equivalent model (b); PLL with a cas-
caded VCDL (c).

Use the equivalent linear model of Figure 6.129(b) to show that:

− the input-output phase transfer function, also known as the jitter
transfer function (JTRAN), can be obtained as follows
Θ0 (s) ω 2 (1 + s/ωz )
G(s) = = 2 n (6.215)
Θi (s) s + 2ζωn s + ωn2
p
where ωn = KP Kv /C, ζ = RCωn /2, and ωz = 1/RC;
440 Data Converters, Phase-Locked Loops, and Their Applications
Vf

In Charge
PD pump VCO Out

VCDL C

Loop filter
(a)

JTRAN
JTOL

G0
Gain

ωp ωp
1 2
(b) Frequency

FIGURE 6.130
Jitter transfer function and tolerance for a second-order PLL (a) and a PLL
with a cascaded VCDL (b).

− the error transfer function, E(s), is inversely proportional to the

jitter tolerance (JTOL) characteristic and can be written as
Θe (s) Θ0 (s) s2
E(s) = = 1+ = 1−G(s) = 2 (6.216)
Θi (s) Θi (s) s + 2ζωn s + ωn2

Typically, the damping factor ζ is selected between 0.5 and 2. When

ζ is greater than one, the transfer
p functions G and E exhibit two real
poles, ωp1 and ωp2 , at (−ζ ± ζ 2 − 1)ωn , where ωn is the undamped
natural frequency.
Verify that the magnitudes of the functions G and E can be repre-
sented as the asymptotic bode plots of Figure 6.129(c).
It can be shown that the −3 dB bandwidth (in rad) and the level
of gain peaking (in dB) can be expressed as,
q p
BW = ωn 1 + 2ζ 2 + 2 ζ 4 + ζ 2 + 1/2 (6.217)

and

Gm = 20 log10 |G(ωm )|
 
8ζ 4
= 10 log10 p (6.218)
8ζ 4 − 4ζ 2 − 1 + 1 + 8ζ 2
Circuits for Signal Generation and Synchronization 441

where qp
ωn
ωm = 1 + 8ζ 2 − 1 (6.219)
2ζ
Design a PLL assuming that the input frequency (or reference fre-
quency) is 2 MHz, the VCO gain is Kv = 0.375 MHz/V, and using
the following steps:
− set the level of the gain peaking to 1.4 dB to determine the
damping factor, ζ;
− set the loop bandwidth, BW , to one tenth of the reference
frequency due to the stability requirement associated to the PD
discrete-time nature to determine the undamped natural frequency,
ωn ;
− compute R and C assuming that Kp = 10/2π mA/rad.

Due to the presence of a closed-loop zero at a frequency lower than

that of the poles, the magnitude of G(s) exhibits a gain in excess of
unity, known as jitter peaking. In the PLL circuit of Figure 6.130(a),
the elimination of the closed-loop zero contributes to the improve-
ment of the jitter filtering by lowering the bandwidth of the jitter
transfer function.
• Assuming a linear phase detector and using
1
Vf = (Θi − Kd Vf − Θ0 ) (6.220)
Cs
1
= Θe (6.221)
Cs
Kv
Θ0 = Vf (6.222)
s
show that
Θ0 (s) ωn2
G(s) = = 2 (6.223)
Θi (s) s + 2ζωn s + ωn2
and
Θe (s) s2
E(s) = = 2 (6.224)
Θi (s) s + 2ζωn s + ωn2
p p
where ωn = Kv /C and ζ = (Kd /2) 1/Kv C .
Verify that the PLL will not exhibit jitter peaking, as illustrated
in the asymptotic bode plots of Figure 6.130(b), if the PLL √ com-
ponents are selected so that the damping factor ζ is equal to 2/2
(second-order Butterworth response).
The −3 dB bandwidth (in rad) of the PLL is given by
q p
BW = ωn 1 − 2ζ 2 + 2 ζ 4 − ζ 2 + 1/2 (6.225)
442 Data Converters, Phase-Locked Loops, and Their Applications

Design a PLL with a bandwidth, BW , of 40 kHz, a VCO gain, Kv ,

of 0.375 MHz/V, and using the following steps:
√
− set the damping factor to 2/2 and determine the undamped
natural frequency, ωn ;
− compute C using Kp = 10/2π µA/rad and deduce Kd (in rad/V).

• When a binary phase detector is used, the phase error becomes

almost equal to zero, Θe ≃ 0, and the output phase, Θ0 , is related
to the control voltage, Vf , by the VCO transfer function. Use

Θi = Θ0 + Kd Vf (6.226)
Kv
Θ0 = Vf (6.227)
s
to show that
Θ0 (s) 1
G(s) = = (6.228)
Θi (s) 1 + s/ωp
where ωp = Kv /Kd .
7. Design of a PLL for clock recovery applications
Consider the phase-locked loop (PLL) shown in Figure 6.131 [21]. It
includes a phase and frequency detector (PFD) based on two XOR
gates, a charge-pump (CP) circuit, a loop filter, a voltage-controlled
oscillator (VCO) with four differential delay stages, and a D flip-flip
used for retiming the recovered clock signal.
With the assumption that I1 and I2 are nominally equal to IP , the
CP provides the charge ±IP to the capacitor C1 .
Show that the transfer function of the section including the PFD,
CP, and loop filter is given by

Vc IP 1 + RC1 s
(s) = (6.229)
△φ 2π (C1 + C2 )s + RC1 C2 s2
where Vc is the VCO control voltage and △φ is the phase difference
between the PD inputs.
Determine the closed-loop transfer function of the PLL in the s-
domain and z-domain.
Use the SPICE program to perform the transient analysis of the
PLL.
8. Fourth-order charge-pump PLL
Consider the fourth-order charge-pump PLL shown in Figure 6.132.
The frequency division by N is performed by cascading six divide-
by-two stages, each of which is based on a D flip-flop whose in-
verted output node is connected back to the data input node. The
Circuits for Signal Generation and Synchronization 443

D Q Out

Q VDD
I1
CP &
In Up Loop filter
S1 VCO
Vc
Dn
S2
R −+ −+ −+ −+
C2
PFD I2 C1 +− +− +− +−

FIGURE 6.131
Circuit diagram of a third-order charge-pump PLL.

VDD V DD

D Q I1
1 Loop filter
CK Up
R Q S1 I R2
P VC
VP VCO Out
Dn
RCK R Q S2 R1
2 C2 C3
D Q I2 C1

PFD
Frequency divider Q D

N Divide by 2

FIGURE 6.132
Circuit diagram of a fourth-order charge-pump PLL.

circuit diagrams of a charge-pump circuit and a VCO are depicted

in Figures 6.133(a) and (b), respectively. Assuming that the pole
frequency due to R2 and C3 is at least ten times higher than the
loop bandwidth, and C3 ≤ C2 /10, the third-order loop filter can
be considered a second-order filter section followed by a first-order
filter section providing an attenuation α of the spurious sidebands
at the multiples of the reference frequency. Hence,

Kp Kv η
C1 ≃ 2
·√ (6.230)
N ωu 1+η
√
1+η
R1 ≃ (6.231)
ωu C1
C1
C2 ≃ (6.232)
η
444 Data Converters, Phase-Locked Loops, and Their Applications
V DD

VB
TB
V DD
T3 T4
Up T1 T T
3 4

I1 L

Vp Out+ VC Out−
V DD

I2
T T
5 6

T5 T6
Dn T2 C T T C
1 2

(a) (b)

FIGURE 6.133
(a) Charge-pump circuit; (b) VCO circuit.

and
√
10α/10 − 1
R2 ≃ (6.233)
ωref C3
where
q
η = 2 tan2 φM + 2 tan φM 1 + tan2 φM (6.234)

Here, Kp = IP /(2π), ωref = 2πfref , and fref is the reference fre-

quency.

For a reference frequency of 37.5 MHz, a VCO free-running fre-

quency of 2.4 GHz, ωu /(2π) = 200 kHz, φM = 65o , α = 10 dB,
Kv = 100 MHz/V, N = 64, and IP = 200 µA, first determine the
initial values of the filter components and then use MATLAB® and
SPICE simulations to size and fine-tune the values of the loop com-
ponents in a given CMOS technology such that the charge-pump
PLL can exhibit a loop bandwidth of 200 kHz.
9. Relaxation oscillator
A relaxation oscillator can be implemented as shown in Fig-
ure 6.134(a). The capacitors C1 and C2 are alternatively charged by
the current source I up to the reference voltage VREF and then dis-
charged to the ground depending on the logic states of the RS latch
outputs. Transistors T1 − T2 and T3 − T4 operate as CMOS invert-
ers. Figure 6.134(b) shows the waveforms illustrating the oscillator
operation. Complementary square-wave clock signals are generated
at the RS latch outputs.
Circuits for Signal Generation and Synchronization 445

Comp 1 VC τd
− 1
VREF
+
S Q 0 t
VREF VC τd
2
R Q
+ VREF
VDD
t
I −
Comp 2 Q
T
1
T1 T3
0 t
Q
T4 1
T2 C1 C2
0 t
(a) (b)

Comp

FIGURE 6.134
(a) Circuit diagram of a relaxation oscillator; (b) waveforms.

Verify that the oscillation period can be expressed as

T = (C1 + C2 )VREF /I + 2τd (6.235)

where τd is the propagation delay of the latched comparator.

Taking into account the comparator offset voltages, the oscillation
period becomes T ± △T . Show that the absolute accuracy of the
period is of the form

△T = (C1 Vof f1 + C2 Vof f2 )/I (6.236)

where Vof f1 and Vof f2 represent the offset voltages of the first and
second comparators, respectively.
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A
Logic Building Blocks

CONTENTS
A.1 Boolean algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
A.1.1 Basic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
A.1.2 Exclusive-OR and equivalence operations . . . . . . . . . . . . . . . . . . . . . . . . 454
A.2 Combinational logic circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
A.2.1 Basic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
A.2.2 CMOS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
A.3 Sequential logic circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
A.3.1 Asynchronous SR latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
A.3.2 Asynchronous S R latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
A.3.3 D latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
A.3.4 D flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
A.3.5 CMOS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
A.4 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

A.1 Boolean algebra

Boolean algebra is used to describe the relations between inputs and outputs
of a digital circuit. The input and output signals are considered to be Boolean
variables (X, Y, Z) whose values are either 0 (logic low level) or 1 (logic high
level).

A.1.1 Basic operations

NOT AND OR
0=1 0·X =0 0+X =X
1=0 1·X =X 1+X =1
X=X X ·X =X X +X =X
X ·X =0 X +X =1

453
454 Data Converters, Phase-Locked Loops, and Their Applications
• X +X ·Y =X • X ·Y +X ·Z +Y ·Z =X ·Y +X ·Z
• X +X ·Y =X +Y • (X + Y )(X + Y ) = X
• X(X + Y ) = X • (X + Y )(X + Z) = X · Z + X · Y
• X(X + Y ) = X · Y • (X +Y )(X +Z)(Y +Z) = (X +Y )(X +Z)

A.1.2 Exclusive-OR and equivalence operations

• X ⊕Y = X ·Y +X ·Y
• X(Y ⊕ Z) = X · Y ⊕ X · Z (X ⊕ Y ) ⊕ Z = X ⊕ (Y ⊕ Z) = X ⊕ Y ⊕ Z
• X ⊙Y = X ⊕Y = X ·Y +X ·Y = X ⊕Y = X ⊕Y
• X ⊕0=X X ⊕X =0
• X ⊕1=X X ⊕X =1
• X ⊕Y =X ⊕Y =X ⊕Y =X ⊕Y
• (X · Y ) ⊕ (X + Y ) = X ⊕ Y (X · Y ) ⊕ (X · Y ) = X ⊕ Y = X ⊙ Y
• X + Y = (X ⊕ Y ) ⊕ (X · Y )
• X · Y = (X ⊕ Y ) ⊕ (X + Y )
• X · (Y ⊕ Z) = (X · Y ) ⊕ (X · Z)
• If X · Y = 0, then X + Y = X ⊕ Y

A.2 Combinational logic circuits

A.2.1 Basic gates

A A A
A Y Y Y Y
B B B
Inverter AND OR XOR

FIGURE A.1
NOT, AND, OR, and XOR gates.

Combinational circuits are digital circuits whose outputs depend only on the
current states of inputs. Figure A.1 shows the NOT, AND, OR and XOR
gates. Boolean expressions that relate the state of the output to the ones of
inputs are given in Table A.1.
Logic Building Blocks 455

TABLE A.1
Logic Equations of NOT, AND, OR, and XOR Gates

Gate type Inverter AND OR XOR

Boolean function Y =A Y = A·B Y =A+B Y =A⊕B

D0 MUX
D0 D0 0
Y Y
Y D1 1
D1

D1 S
S
(a) S (b) (c)

FIGURE A.2
2-to-1 Multiplexer: (a) circuit diagram, (b) switch-based implementation, (c)
symbol.

A multiplexer permits the transmission of only one of many data inputs

to the output. In general, a multiplexer with 2k inputs and one output has k
select bits that are used to choose the input to be connected to the output
node. The circuit diagram, switch-based implementation, and the symbol of
a 2-to-1 multiplexer are illustrated in Figure A.2. The Boolean expression for
the output of the 2-to-1 multiplexer can be written as
(
D0 if S = 0
Y = (A.1)
D1 if S = 1

or equivalently,
Y = D0 · S + D1 · S (A.2)
where D0 and D1 are the data inputs, and S denotes the selection signal.
A 4-to-1 multiplexer can be realized using logic gates as illustrated in Fig-
ure A.3(a), or using 2-to-1 multiplexers configured as shown in Figure A.3(b).
Its symbol is depicted in Figure A.3(c). The logic equation of the 4-to-1 mul-
tiplexer output is given by

Y = S1 · S0 · D 0 + S1 · S0 · D 1 + S1 · S0 · D 2 + S1 · S0 · D 3 (A.3)

where D0 , D1 , D2 , and D3 represent the data inputs, and S0 and S1 are the
selection inputs.
Decoding is necessary in applications such as interfacing, where it is often
necessary to convert one digital format to another. In general, a binary decoder
asserts one of 2k output lines for each combination of the k input signals,
provided it is enabled. It is implemented using k inverters and 2k AND gates
with k + 1 inputs.
456 Data Converters, Phase-Locked Loops, and Their Applications
D0
MUX
D0 0
D1 D0 00
D1 1
0 D1 01
Y Y Y
1 D2 10
D2 D2 0
D3 11
D3 1 S1
D3 S1 S0
(b) S0 (c)

(a) S1 S0

FIGURE A.3
4-to-1 Multiplexer based on logic gates (a) and 2-to-1 multiplexers (b); (c)
symbol.

Y0 Y0 DMUX

Y0 0 Y0
EN D D D
Y1 1 Y1
Y1 Y1
S
D S S
(a) (b) (c) (d)

FIGURE A.4
(a) 1-out-of-2 Decoder with an enable signal; 1-to-2 demultiplexer: (b) circuit
diagram, (c) switch-based implementation, (d) symbol.

The circuit diagram of the 1-out-of-2 decoder with an enable signal is

shown in Figure A.4(a).
A demultiplexer is a logic circuit that switches a data input toward one
of the outputs depending on the digital code applied at the selection inputs.
The circuit diagram, switch-based implementation, and symbol of a 1-to-2
demultiplexer are represented in Figures A.4(b), (c), and (d), respectively.

Y0
0 Y0
2−out−of−4 Decoder

S1
Y1 Y1
1
S0
Y2 2 Y2

EN 3 Y3
Y3

EN S 1 S0

FIGURE A.5
2-out-of-4 Decoder: (a) Circuit diagram, (b) symbol.
Logic Building Blocks 457

Figure A.5 shows the circuit diagram and symbol of a 2-out-of-4 decoder,
which consists of two inverters and four AND gates. The Boolean equations
of the outputs can be derived as

Y0 = EN · S1 · S0 (A.4)
Y1 = EN · S1 · S0 (A.5)
Y2 = EN · S1 · S0 (A.6)

and

Y3 = EN · S1 · S0 (A.7)

where EN is the enable signal, and S1 and S0 represent the bits of the input
code. For each input code, a different output line is asserted by the decoder.
Note that each output line is numbered in accordance with the decimal equiv-
alent of the input binary code.
Note that a 1-to-4 demultiplexer can be obtained from the 2-out-of-4 de-
coder by connecting the incoming data D to the enable input.

D0 Y0

S Y S

D1 D Y1
(a) (b)

FIGURE A.6
2-to-1 Multiplexer (a) and 1-to-2 demultiplexer (b) based on tri-state buffers.

A multiplexer and demultiplexer can also be implemented using tri-state

buffers, that operate as an open or closed switch depending on the logic level
applied to selection input. Figures A.6(a) and (b) show the circuit diagrams
of the 2-to-1 multiplexer and 1-to-2 demultiplexer, respectively.

A.2.2 CMOS implementation

TABLE A.2
Truth Table of CMOS Inverter

A T1 T2 Y
0 OFF ON VDD
VDD ON OFF 0
458 Data Converters, Phase-Locked Loops, and Their Applications
Inverter NAND NOR
A A
A Y Y Y
B B

VDD VDD
T4 T3 T4
A
VDD
Y
T2 T3
T2 B
A
A Y Y
T1 T1
B
T2 T1

FIGURE A.7
CMOS implementations of (a) inverter, (b) NAND and (c) NOR gates.

A static CMOS inverter consisting of an nMOS transistor and pMOS transis-

tor is shown in Figure A.7(a). It operates according to Table A.2. When the
input is at VDD , the nMOS transistor is on while the pMOS transistor is off.
The output is then set to 0 V. On the other hand, when the input takes the
value of 0 V, the nMOS transistor is off while the pMOS transistor is on. As
a result, the output level equals VDD . Assuming that the leakage current is
negligible, an unloaded inverter should not dissipate a static power because
the path between the supply voltage and ground is interrupted in the steady
state.

TABLE A.3
Truth Table of CMOS NAND Gate

A B T1 T2 T3 T4 Y
0 0 OFF OFF ON ON VDD
0 VDD ON OFF ON OFF VDD
VDD 0 OFF ON OFF ON VDD
VDD VDD ON ON OFF OFF 0

The circuit diagram of a two-input NAND gate is depicted in Fig-

ure A.7(b). By connecting two nMOS transistors in series between the output
node and ground, the output will be set to 0 V only if the level of both inputs
is VDD . Due to the two parallel pMOS transistors connected between the sup-
ply voltage and the output node, the output level will equal VDD if either the
input A or B is 0 V. This is summarized in Table. A.3.
A CMOS NOR gate can be implemented as shown in Figure A.7(c). Its
operation is illustrated by Table. A.4. By inserting two nMOS transistors in
Logic Building Blocks 459

TABLE A.4
Truth Table of CMOS NOR Gate

A B T1 T2 T3 T4 Y
0 0 OFF OFF ON ON VDD
0 VDD ON OFF OFF ON 0
VDD 0 OFF ON ON OFF 0
VDD VDD ON ON OFF OFF 0

parallel between the output node and ground, the output will be set to 0 V if
either the input A or B is at VDD . The connection of two pMOS transistors in
series between the supply voltage and ground forces the output to be at VDD
only if the level of both inputs is equal to 0 V.

A Y A Y A Y

(a) (b) (c)

FIGURE A.8
(a) Inverter and its implementations based on (b) NAND and (c) NOR gates.

A A
XOR
A
Y Y Y
B

B B
(a) (b) (c)

FIGURE A.9
(a) XOR gate and its implementations based on (b) NAND and (c) NOR
gates.

The NAND and NOR gates are universal logic elements. Each of them
can be used for the implementation of any logic function, as illustrated in
Figures A.8 and A.9 in the case of the inverter and XOR gate, respectively.
Assuming that complementary signals are available, the XOR gate and
multiplexer can also be realized as shown in Figure A.10. For the XOR gate,
the pull-up transistors are configured based on the function A ⊕ B, while the
structure of the pull-down transistors is determined by the function A ⊕ B.
The output is at the logic high level when only one of the inputs is set to the
logic high level. When the logic level of both inputs is either high or low, that
of the output is low. Considering the circuit diagram of the 2-1 multiplexer,
which is also composed of pull-up and pull-down transistors, it can be shown
that the implemented logic function is of the form A · S + B · S. For any given
460 Data Converters, Phase-Locked Loops, and Their Applications
VDD VDD
T8 T4 T8 T4
A B A B

T7 T3
T7 T3 S S
XOR B A A 0

MUX
A Y Y
Y Y B 1
B T6 T2
T6 T2 B S
A A
S
T5 T1 T5 T1
B B A S

(a) (b)

FIGURE A.10
CMOS implementation of (a) XOR gate and (b) 2-1 multiplexer.

logic state of the selection signal, S, the logic level of only one of the inputs
is transferred to the output.

VDD

Y X Y
X
EN

(a) EN (b)

FIGURE A.11
(a) Tri-state buffer and (b) its symbol.

Tri-state buffers allow multiple logic circuits to share a common data bus,
provided only one of the logic circuits is active at any given time. Figure A.11
shows the circuit diagram and symbol of a tri-state buffer. The output signal
of a tri-state buffer can be written as

(
X if EN = 1
Y = (A.8)
z if EN = 0

where z denotes the high-impedance state. It can then assume one of three
states: logic low, logic high, or high impedance state. In the transfer mode,
that is, when EN = 1, the tri-state buffer is equivalent to a closed switch.
In the disconnect mode, that is, when EN = 0, the tri-state buffer output is
isolated from the input by a high impedance.
Logic Building Blocks 461

A.3 Sequential logic circuits

Sequential circuits are digital circuits whose outputs depend not only on the
current state of inputs, but also on the previous state of outputs. Basic se-
quential circuits include latch and flip-flop. A latch is sensitive to either the
high level or the low level of its inputs and is said to be level-sensitive or
transparent, while a flip-flop can change its output state only at an edge of
the clock signal and is said to be edge-triggered.

A.3.1 Asynchronous SR latch

S
S R Q+ Q+
Q S Q
0 0 Q Q No change
0 1 0 1 Reset Q+
1 0 1 0 Set Q+
Q R Q
R 1 1 0 0 Forbidden
(a) (b) (c)

FIGURE A.12
SR Latch: (a) Circuit diagram, (b) symbol, (c) truth table.

The asynchronous set-reset (SR) latch is one of the simplest sequential

circuits. Figure A.12 shows the circuit diagram, symbol, and truth table of
an SR latch implemented with two NOR gates. The characteristic equation of
the SR latch is given by

Q+ = R · S + R · Q = R · (S + Q) (A.9)

where Q and Q+ denote the current and next states of the output, respectively.
In the case where the condition (R = S = 1) is not supposed to occur, we
have

Q+ = S + R · Q, with the assumption that S·R = 0 (A.10)

A.3.2 Asynchronous S R latch

Another simplest form of the latch circuit can be implemented using two
NAND gates. Figure A.13 shows the circuit diagram, symbol, and truth table
of the S R latch, whose characteristic equation is of the form

Q+ = S + R · Q (A.11)
462 Data Converters, Phase-Locked Loops, and Their Applications

S S R Q+ Q+
Q S Q
0 0 1 1 Forbidden
0 1 1 0 Set Q+
1 0 0 1 Reset Q+
Q R Q
R 1 1 Q Q No change
(a) (b) (c)

FIGURE A.13
S R latch: (a) Circuit diagram, (b) symbol, (c) truth table.
D
Q Q
D Q
C C

C Q
Q Q
D
(a) (b) (c)

FIGURE A.14
D latch: (a) Implementation based on SR latch, (b) implementation based on
S R latch, (c) symbol.

A.3.3 D latch
A D (data) latch is used to capture the logic level of the signal at the data
input when it is enabled by the control signal. Figure A.14 shows the circuit
diagrams of D latches based on an SR latch and S R latch, respectively, and
the D-latch symbol. It can be found that the characteristic equation is

Q+ = D · C + C · Q (A.12)

Hence, the latch output follows the D input when the control signal C is at
the logic high level. When the C input is low, the latch output is maintained
at the state previously acquired when the C input was high. Note that the
outputs Q and Q of the D flip-flop are complementary.

A.3.4 D flip-flops
The operation of flip-flops is synchronized by either the rising or falling edge
of a clock signal (CK). D flip-flops, whose outputs can only change at one
edge of the clock signal, exhibit a characteristic equation of the form

Q+ = D. (A.13)

A D flip-flop can be implemented using a master-slave configuration, which

consists of two D latches that are connected in series and controlled by inverted
phases of the clock signal. Figure A.15 shows the circuit diagram, symbol, and
truth table of the master-slave D flip-flop. The input data are captured when
the clock signal is low, but its state is transferred to the output only at the
Logic Building Blocks 463

D CK Q+ Q+

D D Q D Q D Q x 0 Q Q
x 1 Q Q

C Q C Q Q 0 0 1

1 1 0
CK
(a) (b) (c)

FIGURE A.15
D flip-flop with master-slave configuration: (a) Circuit diagram, (b) symbol,
(c) truth table.

beginning of the next clock phase. Provided the setup and hold requirements
are met, the aforementioned master-slave D flip-flop is referred to as a device
triggered by the rising edge of the clock signal.

D CK Q+ Q+
Q x 0 Q Q
D Q
CK x 1 Q Q

Q 0 0 1
Q
1 1 0

(a) (b) (c)

FIGURE A.16
D flip-flop: (a) Circuit diagram, (b) symbol, (c) truth table.

PR

PR CLR D CK Q+ Q+

0 1 x x 1 0 Asynchronous set to 1

PR 1 0 x x 0 1 Asynchronous reset to 0
Q D Q 0 0 x x 1 1 Forbidden
CK 1 1 x 0 Q Q
Q 1 1 x 1 Q Q
Q CLR
Normal operation
1 1 0 0 1

1 1 1 1 0
D

CLR
(a) (b) (b)

FIGURE A.17
D flip-flop with asynchronous (preset and clear) inputs: (a) Circuit diagram,
(b) symbol, (c) truth table.
464 Data Converters, Phase-Locked Loops, and Their Applications

A D flip-flop can also be realized by relying on the use of an edge detector

so that the input pulse can occur synchronously with a transition of the clock
signal. Figure A.16 shows the circuit diagram, symbol, and truth table of a D
flip-flop triggered by the rising edge of the clock signal. Six NAND gates are
required in this implementation of the D flip-flop. The state of the data input
is captured at the rising edge of the clock signal. It is then transferred to the
output a short time after the edge occurrence due to the gate propagation
delay.
In some applications, it may be necessary to asynchronously drive the flip-
flop, thereby bypassing the clock signal control. Figure A.17 shows the circuit
diagram, symbol, and truth table of a D flip-flop with asynchronous inputs.
The D input is synchronous, while the preset and clear inputs, which are used
to, respectively, set or reset the outputs regardless of the signal levels on the
other input nodes (and especially the clock signal node), are asynchronous.
The asynchronous set and reset functions are activated by the low level of
signals, which are then denoted as P R and CLR. Asynchronous inputs are
required to determine the initial state of the flip-flop and are not used during
the normal operation.

A.3.5 CMOS implementation

D D
Q Q

C C

Q Q
D
(a) (b)

FIGURE A.18
Circuit diagrams of conventional D latches (a) with a single data input and
(b) with complementary data inputs.

V DD V DD
T5 T6 T7 T8

Q Q Q
Q
T1 T2 T5 T6
D D D D
T1 T2
T3 T4
φ φ φ φ
T3 T4

(a) (b)

FIGURE A.19
CMOS implementations of (a) dynamic and (b) static D latches.
Logic Building Blocks 465
V DD V DD
T7 T8 T9 φ T 10

T5 T6 T
11
T7 T8

Q Q
T T4 Q
3 Q
φ φ T
5
T
6
φ φ
T
1
T
2
T
3
T4
D D
D D
T T
1 2

(a) (b)

FIGURE A.20
CMOS implementations of ratio-insensitive (a) dynamic and (b) static D
latches.

D latches can be designed by substituting each logic gate of the circuit dia-
grams shown in Figure A.18 with its CMOS implementation. However, the re-
sulting maximum operating frequency appears to be limited by the long delay
of the critical path, especially at low supply voltages. An approach to reduce
the critical path delay is to use latches with differential cascode structures [1],
such as the ones depicted in Figure A.19. The first latch in Figure A.19(a)
is a dynamic logic circuit based on cross-coupled transistors, which can track
the changes of the input data only during one phase of the clock signal, while
the second latch in Figure A.19(b), which uses cross-coupled inverters acting
as a storage element, can be considered a static logic circuit. A static latch
possesses an output storage node that remains connected to either the sup-
ply voltage or ground, while a dynamic latch exhibits a conducting path to
the supply voltage or ground only during the evaluation of the input data. In
general, dynamic CMOS logic circuits require less silicon area due to the num-
ber of transistors needed than their static counterparts. However, they can be
affected by charge sharing at the output nodes. One solution to prevent vari-
ations in the logic level consists of using sufficiently large static inverters to
isolate the output nodes of the dynamic latch stage.
The latches of Figure A.19 have the drawback of being sensitive to the
aspect ratio between the nMOS and pMOS transistors, especially in the case
where the input transistor is of the pMOS type. This is due to the fact that
the current delivered by input section should overcome that from the cross-
coupled transistors in order for the latch to switch, thereby increasing the
length of the switching period.
Ratio-insensitive latches can be designed as shown in Figure A.20. Extra
transistors are used so that the input node can be formed by connecting
together the gate terminals of nMOS and pMOS transistors.
Flip-flops can be realized using two latches in a master-slave configuration,
as shown in Figure A.21. The state of the input is acquired by the master latch
when the clock signal becomes low. It is then transferred to the outputs of the
slave latch when the clock signal goes high. The master latch is transparent,
466 Data Converters, Phase-Locked Loops, and Their Applications
V DD
V DD T7 T8
T T
3 4
φ φ
Q
Q
T5 T6 T5 T6
T
1
T2

φ φ
T T2 T
3
T
4
1
D D

FIGURE A.21
CMOS implementation of a semi-static D flip-flop.
V DD
T5 T6 V DD
φ φ
T7 T8 T9 T8
S T3 T6
R Q
T3 V DD T4
Q
Q
T
9 T3 T4
Q
T T
D 1 2 D T T
S 1 2 R

T
φ 10

(a) (b)

FIGURE A.22
CMOS implementations of (a) D flip-flop and (b) S R latch.

φ φ

D Q

φ φ φ φ
VDD

φ φ

FIGURE A.23
Transmission gate flip-flop.

while the slave latch remains opaque — and vice versa. This flip-flop has the
advantage of using only one clock signal, but it can be prone to a substantial
voltage drop at the outputs due to the capacitive coupling effect between the
master and slave latches.
Another approach to design flip-flop relies on the structure depicted in Fig-
ure A.22(a) [2, 3]. The first stage is based on a sense amplifier and the second
Logic Building Blocks 467

stage is an S R latch, which can be implemented as shown in Figure A.22(b).

When the clock signal becomes low, the input differential transistor pair is in
the cutoff region and the output nodes of the sense amplifier are precharged
through transistors T7 and T8 to the high logic state. The S R latch then
holds its previous logic state. When the rising edge of the clock signal occurs,
the sense amplifier is enabled and can track the input data to produce a tran-
sition from the high state to the low state on one of the outputs. The S R
latch updates its outputs according to the actual state of the sense amplifier.
By applying the high state of the input data to the node D, T3 , T1 , and T10
provide a discharge path to the node R, while T4 and T6 are biased in the
cutoff and conduction region, respectively. On the other hand, when the high
state of the input data occurs at the node D, a discharge path is supplied
to the node S by T4 , T2 , and T10 , while T3 and T5 operate in the cutoff and
conduction region, respectively. After the completion of the state transition
at one of the output nodes, the inputs become decoupled from the outputs
and the sense amplifier then remains unaffected by any subsequent change
of input data during the active clock phase. If the state of the input data
changes, the discharge path will be interrupted, leaving the node at the low
logic level floating. In order to prevent this floating node from being charged
by the leakage or coupling currents, another discharge path should be provided
by using the nMOS pass transistor T9 . This pass transistor also helps equal-
ize the voltage values of the two differential branches during the pre-charge
and reset the output nodes prior to the next sensing of the input data. The
primary feature of the sense-amplifier flip-flop is the provision of high input
impedance. However, the operation speed can be limited by the propagation
delay introduced by the output latch.
A master-slave D flip-flop that is triggered by the rising edge of the clock
signal can be realized, as illustrated in Figure A.23, by using two transmission
gate-based latches enabled by complementary clock signals. It is particularly
suitable for operation at high supply voltage. Its hold time may be limited by
mismatches between the inverters on the clock and data paths.
V DD V DD
T3 T6 T9 T3 T6 T9
φ φ

Q Q
T2 T5 T8 T2 T5 T8
φ φ φ φ

T1 T4 T7 T1 T4 T7
D φ D φ

(a) (b)

FIGURE A.24
CMOS implementations of (a) rising-edge and (b) falling-edge triggered D
flip-flops.

More efficient circuits for D flip-flops can be derived using true single-
468 Data Converters, Phase-Locked Loops, and Their Applications
VDD

3
R

2
φ
D
1
φ φ
Q
φ R

FIGURE A.25
Circuit diagram of a retentive TSPC D flip-flop.

phase clocking (TSPC) techniques [4]. TSPC D flip-flops operate with only
one clock signal, and offer advantages such as a small circuit area for clock
lines, a reduced clock skew, and high-speed operation. Figure A.24 shows
the circuit diagrams of the rising-edge and falling-edge triggered D-flip-flops,
which consist of three clocked inverting stages. The output signal is available in
an inverted version. When the clock slope is not sufficiently steep, both nMOS
and pMOS clocked transistors simultaneously operate in the conduction region
during the clock transition. As a result, the logic level of internal signals may
become undefined and a race condition may occur.
In comparison with conventional master-slave flip-flops, TSPC flip-flops
have the advantages of reducing the load of the clock distribution network and
the switching power dissipation. Moreover, by requiring only a single-phase
clock signal, they are less affected by clock skews caused by process variations.
However, the operation of TSPC flip-flops may be affected by data loss that is
inherent to a dynamic operation. Figure A.25 shows the circuit diagram of a
retentive TSPC D flip-flop [5]. The signal R can be used to reset the flip-flop.
When the clock signal goes low, the actual logic state of the data is kept on
the node 3. Meanwhile, the next logic state of the data is transferred to the
node 1, while the node 2 is pre-charged to the supply voltage VDD without
effecting the retention process on the node 3 due to the pMOS transistor with
the gate connected to the node 2. The data transfer begins at the rising edge
of the clock signal. If the node 1 is charged to VDD , the node 2 is discharged
to ground by the nMOS transistor with the gate connected to the node 1 and
a high logic state is held on the node 3. If, on the other hand, the node 1 is
discharged to ground, the node 2 is not discharged and a low logic state is kept
on the node 3. The forward-conditional feedback paths between the nodes 2
and 3 and between the nodes Q and 3 help avoid data loss on the node 3
during the data transfer phase by preventing the discharge of the node 2 due
to leakage current, and during the retention phase by inducing the discharge
of the node 3 to counteract possible contention transitions, respectively. For
Logic Building Blocks 469

a high-speed and power-efficient design, transistors with a minimum width

should preferably be used in the feedback paths.

A.4 Bibliography
[1] J. Yuan and C. Svensson, “New single-clock CMOS latches and flipflops
with improved speed and power savings,” IEEE J. of Solid-State Circuits,
vol. 32, pp. 62–69, Jan. 1997.
[2] M. Matsui, H. Hara, Y. Uetani, L.-S. Kim, T. Nagamatsu, Y. Watanabe,
A. Chiba, K. Matsuda, and T. Sakurai, “A 200 MHz 13 mm2 2-D DCT
macrocell using sense-amplifying pipeline flip-flop scheme,” IEEE J. of
Solid-State Circuits, vol. 29, pp. 1482–1490, Dec. 1994.
[3] J. Montanaro, R. T. Witek, K. Anne, A. J. Black, E. M. Cooper, D. W.
Dobberpuhl, P. M. Donahue, J. Eno, G. W. Hoeppner, D. Kruckemyer, T.
H. Lee, P. C. M. Lin, L. Madden, D. Murray, M. H. Pearce, S. Santhanam,
K. J. Snyder, R. Stephany, and S. C. Thierauf, “A 160-MHz, 32-b, 0.5-W
CMOS RISC microprocessor,” IEEE J. of Solid-State Circuits, vol. 31, pp.
1703–1714, Nov. 1996.
[4] J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J.
of Solid-State Circuits, vol. 24, pp. 62–70, Jan. 1989.
[5] F. Stas and D. Bol, “A 0.4V 0.08fJ/cycle retentive true-single-phase-clock
18T flip-flop in 28nm FDSOI CMOS,” in Proc. of the IEEE ISCAS, Bal-
timore, MD, USA, March 2017, pp. 2779–2782.
B
Notes on Circuit Analysis

CONTENTS
B.1 Radius of curvature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
B.2 Spectral analysis of PWM signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
B.3 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Proofs of some equations and results that were used to characterize PLL
circuits are presented.

B.1 Radius of curvature

θi Σ λ G(z) θ0

FIGURE B.1
Variable gain model of the PLL in the discrete-time domain.

Based on the variable gain model of Figure B.1, the closed-loop transfer
function can be written as,

θ0 (z) λĜ(z)
= (B.1)
θi (z) 1 + λĜ(z)

where 1 + λĜ(z) is the characteristic equation, and λ represents the loop gain.
An approach that can be adopted to select a gain value for stability is the
root locus, which is a plot of the characteristic equation roots as a function of
the gain, λ.
Figure B.2 shows two examples of root loci for the charge-pump PLL [1]
with a second-order lowpass filter.
In Figure B.2(a), C1 = 2 pF and C2 = 0. At the intersections between the
unit circle and the root loci, λ = λ1 or λ2 , with λ2 > λ1 . When 0 < λ < λ1 , all
the roots are inside the unit circle, and the stability condition is met. When

471
472 Data Converters, Phase-Locked Loops, and Their Applications
λ = λ3
1 1
λ = λ1

Imaginary axis

Imaginary axis
0.5 0.5
λ = λ2
0 0

−0.5 −0.5
λ = λ1
−1 −1
λ = λ3
−1 −0.5 0 0.5 1 −1 −0.5 0 0.5 1
Real axis Real axis
(a) (b)

FIGURE B.2
Root loci of the closed-loop transfer function poles: (a) C2 = 0, (b) C2 6= 0.

λ1 < λ < λ2 , the roots departing at z = 1 are located outside the unit circle
while others remain inside the unit circle. Hence, θ0 starts to grow, and then
θi − θ0 tends to increase, causing a decrease of λ. This process is repeated
for several successive cycles until the roots outside the unit circle move back
inside the unit circle, thus disclosing the existence of a stable limit cycle.
In Figure B.2(b), C1 = C2 = 2 pF. The root loci cross the unit circle
when λ = λ3 . It can be verified that, in any case, there is no stable region of
operation.
A useful stability criterion can be derived by relating the analysis of the
locus behavior to the radius of curvature. Let the transfer function, Ĝ(z), be
of the form,
PK
N (z) ak z k
Ĝ(z) = = Pk=0L
(B.2)
D(z) l=0 bl z
l

√
where z = x + jy and j = −1. The Taylor series expansions of N (z) and
D(z) about z are given by

K
X N (k) (x)
N (x + jy) = (jy)k (B.3)
k!
k=0
L
X D(l) (x)
D(x + jy) = (jy)l (B.4)
l!
l=0

where N (k) (x) and D(l) (x) represent the nth and lth derivatives of N (x) and
D(x), respectively. Substituting (B.3) and (B.4) into (B.2) and rearranging
the result in real and imaginary parts, and setting the imaginary part equal
to zero, we arrive at

g(x, y) = Q1 (x) − y 2 Q3 (x) + y 4 Q5 (x) − · · · = 0 (B.5)

Notes on Circuit Analysis 473

where
XR
N (r) (x)D(R−r) (x)
Qr (x) = (−1)r (B.6)
r=0
r!(R − r)!

In general, at a given point (x, y) on a curve implicitly defined by the equation

y
1 C: g(x,y) = 0

Osculating
circle
ρ
−1 0 1 x

−1

FIGURE B.3
Representation of the radius of curvature ρ at (x, y) = (1, 0).

C : g(x, y) = 0, the curvature κ and the radius of curvature ρ can be estimated

as,

gxx gy2 − 2gxy gx gy + gyy gx2

κ(x, y) = (B.7)
(gx2 + gy2 )3/2
1
ρ(x, y) = (B.8)
|κ(x, y)|

where for u, v ∈ {x, y}, gv = ∂g/∂v, guv = ∂gv /∂u, and guu = ∂ 2 g/∂u2.
In Figure B.3, the curve C : g(x, y) = 0 is assumed to be a portion of the
root locus with the double pole at z = 1. The radius ρ of the osculating circle
is called the radius of curvature at the point (x, y) = (1, 0) on the curve.
If the root locus has to first move toward the inside of the unit circle before
it can cross the unit circle, then the next requirement should be satisfied,

1
<1 (B.9)
κ(1, 0)

where κ(1, 0) is assumed to be positive. From (B.5), it can be shown that

gy (1, 0) = 0. Furthermore, gx (1, 0) = Q′1 (1) and gyy (1, 0) = −2Q3 (1), where
Q′1 (x) = dQ1 (x)/dx, and Equation (B.9) can be rewritten as,

Q′1 (1)
− <1 (B.10)
2Q3 (1)
474 Data Converters, Phase-Locked Loops, and Their Applications

where
K X
X L
Q′1 (1) = − (k − l)(k + l − 1)ak bl (B.11)
k=0 l=0
K L
1 XX
Q3 (1) = − (k − l)[(k − l)2 − 3(k + l) + 2]ak bl (B.12)
6
k=0 l=0

In the special case of the charge-pump PLL with a second-order lowpass

filter, it can be shown that

Q′1 (1) = 4Ĝ0 (1 − r0 )2 (B.13)

  
τd RC1 RC1 C2
Q3 (1) = −Ĝ0 (1 − r0 )2 1 − 2 q + − + (B.14)
T T T (C1 + C2 )

where Ĝ0 = Kp Kv T 2 /(2 · N · CT ).

B.2 Spectral analysis of PWM signals

In general, the pulse-width modulated (PWM) waveform, that is generated
by comparing an input signal with a carrier signal, is not periodic. Its spectral
analysis requires the use of double Fourier series expansion [2] because the
input signal frequency cannot be directly related to the carrier frequency.

Carrier Input

y 2k π + M π cos(y)

Slope y/x
2π

0 x

− 2π 0 2π 4π 6π 8π 10π

PWM output

FIGURE B.4
Geometric surface for the spectral analysis of a PWM signal.
Notes on Circuit Analysis 475

Let x = ωc t and y = ωt. The input signal can be written as,

u(y) = 2kπ + M π cos(y) (B.15)

For a single-sided modulation, the carrier is a sawtooth signal. The spectral

analysis of the PWM signal can be performed using a geometric surface, de-
fined as F (x, y) and illustrated in Figure B.4. Hence,
(
1 if (x − |x|2π ) ≤ u(y)
F (x, y) = (B.16)
0 otherwise

where |x|2π is the closed multiple of 2π, which is less than x. The function
F (x, y) remains identical in each 2π-square and is then periodic in two dimen-
sions. The double Fourier series of F (x, y) can be written as,
+∞
X
1
F (x, y) = A00 + [A0n cos(ny) + B0n sin(ny)]
2 n=1
+∞
X
+ [Am0 cos(mx) + Bm0 sin(my)] (B.17)
m=1
+∞
X +∞
X
+ [Amn cos(mx + ny) + Bmn sin(mx + ny)]
m=1 n=−∞
n6= 0

In the complex form, the Fourier coefficients of F (x, y) can be expressed as

Z 2π Z 2π
1
Amn + jBmn = F (x, y)ej(mx+ny) dxdy (B.18)
2π 2 0 0

Taking into account the definition of F (x, y) and assuming that m, n 6= 0, we

have
Z 2π Z 2kπ+Mπ cos(y)
1
Amn + jBmn = F (x, y)ej(mx+ny) dxdy (B.19)
2π 2 0 0
Z 2π
j
=− 2 (ej[m(2kπ+Mπ cos(y))+ny] − ejny )dxdy (B.20)
2π m 0
Z 2π
j
= − 2 ej2mkπ ejmMπ cos(y) ejny dxdy (B.21)
2π m 0
j j(2mkπ+nπ/2)
=− e Jn (mM π) (B.22)
πm
where the Bessel function is given by
Z 2π
j −n
Jn (z) = ejz cos(φ) ejnφ dφ (B.23)
2π 0
476 Data Converters, Phase-Locked Loops, and Their Applications

Hence, for m, n 6= 0, we obtain

j
Amn = sin(2mkπ + nπ/2)Jn (mM π) (B.24)
πm
and
j
Bmn = − cos(2mkπ + nπ/2)Jn (mM π) (B.25)
πm
For the special cases where m, n = 0, it can be shown that
A00 = 2k (B.26)
A0n = M/2 (B.27)
B0n = 0 (B.28)
J0 (mM π)
Am0 = sin(2mkπ) (B.29)
mπ
1 − J0 (mM π) cos(2mkπ)
Bm0 = (B.30)
mπ
By inserting the Fourier coefficients into Equation (B.17), we arrive at
F (x, y) = k + M cos(y)
+∞
X +∞
X
sin(mx) J0 (mπM )
+2 −2 sin(mx − 2mkπ)
mπ mπ
m=1 m=1 (B.31)
+∞ X
X +∞
Jn (mπM )
−2 sin(mx + ny − 2mkπ − nπ/2)
m=1 n=−∞
mπ
n6= 0

By choosing to set k equal to 1/2, then multiplying the resulting series by

2 (waveform with a pulse height of 2) and ignoring the dc component, the
Fourier series can be written as,
FADS (x, y) = M cos(y)
+∞
X +∞
X
sin(mx) J0 (mπM )
+2 −2 sin(mx − mπ)
mπ mπ
m=1 m=1 (B.32)
+∞ X
X +∞
Jn (mπM )
−2 sin(mx + ny − mπ − nπ/2)
m=1 n=−∞
mπ
n6= 0

or equivalently,
FADS (x, y) = M cos(y)
X∞
1 − J0 (mπM ) cos(mπ)
+2 sin(mx)
mπ
m=1 (B.33)
X∞ +∞
X Jn (mπM )
−2 sin(mx + ny − mπ − nπ/2)
m=1 n=−∞
mπ
n6= 0
Notes on Circuit Analysis 477
Input
Vi+
+
Input V+
V+
i −
+ VT
PWM Carrier PWM
output −1 Σ output
− V+ Vd
VT −
Carrier V−
Vi− +
(a) (b)

FIGURE B.5
Generation of (a) two-level and (b) three-level PWM waveforms.

Vi+ VT Vi−
1

−1
Time

1
V+
0
Time

1
V−
0
Time

1
Vd 0

−1
Time

FIGURE B.6
Two-level and three-level PWM waveforms.

A double-sided modulation requires the use of a triangular carrier signal.

Figure B.5 shows circuit structures that can be used for the generation of
two-level and three-level PWM waveforms. Two-level and three-level PWM
waveforms are represented in Figure B.6. The modulation switching method
can be either of class AD (that is, the output can take two voltage levels) or
class BD (meaning that the output can assume three voltage levels).
For a two-level PWM waveform, the Fourier series can be derived as follows

FADD (t) = FADS (t) − FADS (−t) (B.34)

478 Data Converters, Phase-Locked Loops, and Their Applications

Hence,

FADD (x, y) = M cos(y)

+∞
X J0 (mπM/2)
+2 sin(mπ/2) cos(mx)
mπ/2
m=1 (B.35)
X∞ +∞
X Jn (mπM/2) m + n 
+2 sin π cos(mx + ny)
m=1 n=−∞
mπ/2 2
n6= 0

The output spectrum contains harmonics of the switching frequency, and inter-
modulation components between the input and carrier frequencies that occur
symmetrically around each of the carrier frequency harmonics.
In the case of a three-level PWM waveform, we have

FADD (t) − FADD ,π (t)

FBDD (t) = (B.36)
2
where
FADD ,π (x, y) = M cos(y − π)
+∞
X J0 (mπM/2)
+2 sin(mπ/2) cos(mx)
mπ/2
m=1 (B.37)
+∞ X
X +∞
Jn (mπM/2) m + n 
+2 sin π cos(mx + n(y − π))
m=1 n=−∞
mπ/2 2
n6= 0

Thus,

FBDD (t) = M cos(y)

+∞ X
X +∞
Jn (mπM/2) m + n  n   n 
−4 sin π sin π sin mx + ny − π
m=1 n=−∞
mπ 2 2 2
n6= 0
(B.38)

Due to the fact that the output spectrum does not contain any harmonics of
the carrier frequency, the intermodulation components are located symmetri-
cally around the even harmonics of the carrier frequency.
Notes on Circuit Analysis 479

B.3 Bibliography
[1] Z. Wang, “An analysis of charge-pump phase-locked loops,” IEEE Trans.
on Circuits and Systems–I, vol. 52, pp. 2128–2138, Oct. 2005.
[2] K. Nielsen, “A review and comparison of pulse width modulation (PWM)
methods for analog and digital input switching power amplifiers,” Proc. of
the 102nd AES Convention, Munich, Germany, Preprint 4446 (G4), Mar.
1997.
Index

A resistor, 128
Active component, 133 termination resistor, 130
Active element, 133
Alexander phase detector, 338 B
Algorithmic ADC, 155 Background calibration, 211
bipolar, 158 Bandpass decimation filter, 256
ratio-independent, 157 Bandpass delta-sigma modulator,
unipolar, 158 193
Algorithmic DAC, 78 4-2 cascaded, 226
Amplifier, 2 cancelation logic, 226
multiply-by-two, 156 dc-to-fs /4 transformation, 225
Analog-to-digital converter (ADC), bandwidth frequency, 224
11, 91, 404 fourth-order, 225
algorithmic, 155 lowpass prototype
cyclic, 155 transformation, 225
delta-sigma modulator, 184 oscillator, 289
flash, 115 passband center frequency, 224
averaging, 127 resonator, 224
folding, 131 second-order, 225
integrating ADC Bang-bang phase detector, 338
dual slope, 108 Barrel shifter, 280
interpolating, 131 Beat frequency, 402
pipelined, 143 Bessel function, 429, 475
sub-ranging, 142 Binary code, 15
successive approximation bipolar, 17
register, 92 offset, 18
time-interleaved, 159 one’s complement, 18
VCO-based, 404 sign-magnitude, 17
AND gate, 379, 454, 455 two’s complement, 18
Anti-aliasing filter, 12 dynamic range, 18
Arithmetic overflow, 241 fractional, 15
Averaging ADC offset reduction, 129 unipolar, 15
Averaging network BCD, 16
cross-connection, 130 Gray, 15
dummy preamplifier, 128 Binary counter, 263
over-range preamplifier, 130 Binary phase detector, 339, 340
preamplifier, 128 Binary-coded decimal code, 16

481
482 Index

Binary-to-thermometer decoder, Circular-to-Gray encoder, 139

276 Circular-to-thermometer encoder,
Binary-weighted resistor DAC, 49, 50 132
Bit error rate (BER), 415, 416 Class D power amplifier, 426, 430,
Boolean algebra, 453 431
Built-in self-test (BIST), 7, 287, Clock and data recovery (CDR), 366,
296–298, 393 413
frequency measurement, 393 Clock signal
phase shifting, 394 four-phase nonoverlapping, 329
time interval evaluation, 400 period, 148
undersampling, 401 two-phase nonoverlapping, 328,
Butterworth 429
filter, 430 Combinational circuit, 454
CMOS inverter, 458
C NAND gate, 458
Calibration, 184, 211, 234, 269, 270 NOR gate, 458
off-line, 211 tri-state buffer, 460
Canonic signed digit, see CSD XOR gate, 459
Capacitor Comparator
MIM, 372 metastability, 121
MOS varactor, 372 Compensation FIR filter, 253, 259
Capacitor array, 372, 407, 419 Continuous-time linear equalizer
Capture range, 396 (CTLE), 417
Cascaded delta-sigma modulator, Continuous-time modulator, 194
213 clock jitter, 194, 195
dynamic range, 224 excess loop delay, 195
overload condition, 224 impulse invariant
Cascaded integrator-comb filter, see transformation, 195
CIC filter Counter, 405
CDR, see also Clock and data CSD code, 255
recovery, 372, 374, 377, 384, Current scaling DAC, 49
386, 424 Current-starved inverter, 372
dual-loop, 372, 374, 381 Current-steering DAC, see
GVCO-based, 377 Switched-current DAC
PI-based, 375 Cycle slip, 378
power efficient, 374 Cyclic ADC, 155
reference-less, 381, 384, 386
stability, 370 D
Charge-pump circuit, 343, 344, 346, D flip-flop, 336, 462, 464
374, 378, 389, 392, 400 DAC pulse
Charge-pump PLL, 334, 359–361, half-clock-period delayed
442, 471, 474 return-to-zero, 37, 194,
Charge-scaling DAC, 68 236
CIC filter, 241, 247, 263 nonreturn-to-zero, 37, 68, 194,
passband droop, 247, 259 236
Index 483

return-to-zero, 37, 68, 194, 207, column, 56

236 complexity, 45
series-resistor, 207 row, 56
DAC unit element, 270 Delay-locked loop (DLL), 326, 389,
Data converter characterization 390, 392, 393
differential nonlinearity, 27 Delta-sigma
dynamic range, 29 ADC, 23, 184, 189
effective number of bits, 30 DAC, 258
gain error, 26 data converter, 184
glitch impulse, 31 Delta-sigma modulator
integral nonlinearity, 28 bandpass, 189
latency time, 31 continuous-time, 194
offset error, 26 dc-to-fs /4 transformation, 193
settling time, 31 discrete-time, 188
signal-to-noise and distortion dynamic range, 191
ratio, 30 first-order, 186
signal-to-noise ratio, 29 linear model, 188
spurious-free dynamic range, 31 loop filter, 189
total harmonic distortion, 29 lowpass, 189
two-tone intermodulation multi-bit quantizer, 189
distortion, 31 noise transfer function, 193
Data-weighted averaging, 211, 275, oscillator, 288
280, 281 output sequence, 187
Decimation filter, 238 oversampling ratio, 192
arithmetic overflow, 241 power-efficient, 316
cascaded integrator-comb filter, quantization noise, 186, 189
240 transfer function, 185
down-sampler, 238 signal transfer function, 185
linear-phase frequency response, single-stage, 185, 197
238 stability, 188, 192, 234
lowpass filter, 238 synthesis, 234, 236
passband, 246, 247 time-domain equations, 186
stopband, 246, 247 Demultiplexer, 326, 375
multistage, 245 1-to-2, 456
polyphase, 256 Design flow, 4
single stage, 245 Dichotomy technique, 273
Decimation ratio, 246 Differential nonlinearity, 100, 102
Decision feedback equalizer (DFE), Differential nonlinearity (DNL), 296,
417, 419 298
Decoder, 49, 53, 56 Differentiator, 243, 263, 265, 269,
2-out-of-4, 45, 457 405, 412
3-out-of-8, 42, 45 Digital delta-sigma modulator, 258
N -out-of-2N , 43 Digital filter, 408
binary-to-thermometer, 43, 52 Digital signal processor (DSP),
4-bit, 44 296
484 Index

Digital-to-analog converter (DAC), Equalizer, 416, 420, 422

11, 35, 276, 421 full-rate, 422
binary-weighted, 38 half-rate, 422
bipolar, 76 loop unrolling, 422
mismatch noise, 281 time-interleaved, 421
Nyquist DAC, 35 Error-feedback modulator, 266, 267
segmented, 38 2-1 cascaded, 268
thermometer-coded, 38 third-order, 267
unipolar, 76 ESL, 271, 279
Discrete-time modulator, 188 Excess loop delay
Dither signal, 272, 279 analysis, 205
DLL, see Delay-locked loop impulse invariant
DNL, see Differential nonlinearity transformation, 205
Double-sampling bandpass modified z-transform, 205
modulator, 230 compensation, 207
SC implementation, 230 Eye diagram, 415, 416, 423
Double-sided modulation, 429, 477 Eye monitor, 422, 423
Down-sampler, 259
Down-sampling, 238 F
Driver, 429, 431 False lock, 390, 391
Dual slope ADC Feedforward equalizer (FFE), 416
zero reading, 115 Figure-of-merit (FOM), 287, 413
Duty cycle, 328, 390, 395, 427 Filter
Dynamic element matching, 210 approximation function, 234
Dynamic element-matching response, 234
calibration, 270 Filter coefficient
Dynamic range, 285 CSD, 254
radix-2 CSD, 254, 255
E Finite-impulse response filter, see
Effective number of bits (ENOB), FIR filter
282, 286, 287 FIR filter, 241
Efficiency, 426, 430, 431 direct form, 249, 259
Element selection logic, 276 linear phase, 248, 250
butterfly shuffler, 279 linear-phase, 261
Encoder, 115, 117, 119, 123, 140, Parks-McClellan algorithm, 246
274, 278 polyphase, 249, 259
1-out-of-2N , 43, 119 transpose form, 248
circular-to-Gray, 139 Flash ADC
circular-to-thermometer, 132 bubble correction, 119
Gray-to-binary, 118 bubbles, 117
majority logic, 119 feedthrough error, 125
thermometer-to-binary, 123, gate-based encoder, 119
148, 150 Gray code, 117
thermometer-to-Gray, 118 ROM-based encoder, 119
three-input AND, 120 thermometer code, 117
Index 485

Flip-flop Half-clock-period delayed

master-slave, 465 return-to-zero pulse, 37,
true single-phase clocking, 468 194
Folding ADC Half-rate binary PD, 341
amplitude quantization, 133 Half-rate linear PD, 341
circular code, 132 Hardware description language, 4
folding signal High speed, 125, 296, 326, 328, 339,
zero-crossings, 133 365, 374, 397, 413, 432
resolution, 136 Histogram, 282
Folding amplifier, 135 Hogge phase detector, 337–339
Folding and interpolating ADC, Hold range, 403
136 Hybrid DAC, 71
bit synchronization, 136 bipolar, 73
coarse ADC, 136 unipolar, 71
fine ADC, 136
over-range detection, 141 I
transfer characteristic, 139 Impulse invariant transform, 234
under-range detection, 141 Impulse invariant transformation,
Fourier 195, 203, 368
series, 429, 474 Impulse-invariant transformation,
transform, 285 236
Fractional-N PLL, 406 INL, see Integral nonlinearity
Frequency detector, 374, 381, 383 Input/output
Frequency divider, 352, 362, 364 device, 290
Frequency response link transceiver, 414
critically damped, 430 synchronization, 292
overdamped, 430 Integral nonlinearity, 100
underdamped, 430 Integral nonlinearity (INL), 296, 298
Frequency synthesizer, 352, 356, 357, Integrating ADC
362 dual-slope, 108
Full-scale range, 187 accuracy, 110
conversion cycle, 110
G multiple-slope, 108
Gain stage, 417 single-slope, 108
active feedback, 419 Integrator, 186, 193, 197, 198, 202,
peaking, 419 206, 209, 213, 214, 216, 220,
Gated voltage-controlled oscillator, 222, 227, 263, 265, 288, 331,
367, 374, 377, 381 376, 389, 405
Glitch, 38, 39, 45, 51, 52, 63, 68, 70 Inter-symbol interference (ISI), 38,
Gray code, 15 415, 416, 419
Intermodulation component, 285,
H 478
Half-band FIR filter, 247, 251, 259, Intermodulation distortion (IMD),
262 285
two-fold decimation, 253
486 Index

Interpolation filter, 258, 259, 263, oscillator, 288

265 second-order
multistage, 258 gm -C, 203
single-stage, 258 switched-capacitor, 202
Inverter, 328, 372, 389, 458, 459 Lowpass modulator
cross-coupled, 431 2-1 cascaded
current-starved, 383, 431 cancelation logic, 218
pseudo-differential, 383
M
J Microprocessor
Jitter, 23, 24, 32, 37, 68, 194, 197, digital signal processor, 290
326–403, 416, 440 micro-controller, 290
Missing code, 145, 151
K Mixed-signal integrated circuit, 2
Kirchhoff’s current law, 126 verification, 4
Modulator order, 193
L Modulo arithmetic, 280, 413
Latch Monotonicity, 102
S R, 336, 461 MOS varactor, 372
D, 462, 465 Moving-average filter, 239
metastability, 373 Multi-bit DAC
SR, 461 component mismatch, 211
LC filter, 429 dynamic element matching, 211
LC oscillator, 371 nonlinearity, 222
Least-mean square algorithm, 417, attenuation, 222
420 Multi-bit modulator, 210
Lock detector, 373, 392, 396 attenuation of tones, 213
Lock range, 396, 403 DAC
Lock time, 396, 403 digital calibration, 211
Loop noise bandwidth, 403 nonlinearity, 210
Loop unrolling, 421 dynamic range, 212
Lowpass decimation filter, 256 Multiplexer, 326, 380, 383, 422
Lowpass delta-sigma modulator, 193 2-to-1, 263, 275, 288–290, 455
1-1 cascaded, 214 4-to-1, 290
cancelation logic, 215 Multiplying DAC, 78, 82, 148
1-1-1 cascaded, 215, 216, 218 Multirate system
2-1 cascaded, 217, 218 commutative rule, 257
2-1-1 cascaded, 219, 220, 223 Multistage
cancelation logic, 220 decimation filter, 246
inter-stage scaling coefficient, interpolation filter, 258
223 modulator, 213
2-2 cascaded, 220, 222, 223
cancelation logic, 222 N
inter-stage scaling coefficient, NAND gate, 118, 328, 329, 336, 458,
224 461, 464
Index 487

Noise power half-rate binary, 381, 382

bandwidth, 193 half-rate linear, 384, 386
ratio, 286 Phase quantizer, 413
Noise shaping TDC, 410 Phase-locked loop (PLL), 326, 355,
Nonreturn-to-zero pulse, 37, 194 356, 393
NOR gate, 458 acquisition process, 361
NOT gate, 454 applications, 355
Nyquist built-in self-test, 400
ADC, 23, 91, 164 capture range, 374, 396
converter, 184 characteristics, 346
DAC, 35 charge-pump, 334, 361
rate, 12 clock and data recovery, 366
closed-loop bandwidth, 359
O digital filter, 408
Offset binary coding, 18 dual-loop, 373
Offset voltage, 97, 99, 100, 110, 115, feedback system, 329
126, 128, 130, 145, 153, 155, first-order filter, 347
159, 167, 345, 415, 445 fractional-N, 365, 406
On-chip tuning circuit, 234 frequency synthesizer, 355,
One’s complement representation, 18 362
OR gate, 379, 424, 454 gain, 394
Oscillator, 288, 290 instability, 348
Oversampling, 23, 184, 189, 224, 258 jitter, 397, 400, 401
linear model, 330, 369
P lock range, 396
Parallel interfacing, 294 lock time, 396
Parallel-to-serial converter, 293 lock-in range, 330
Partial-fraction expansion, 232 noise bandwidth, 436
Passive element, 133 nonlinear model, 402
PD, see Phase detector nonlinear region, 330
Peaking, 417 second-order filter, 347
PFD, see Phase and frequency second-order loop, 331
detector static phase error, 330
Phase TDC-based, 408
interpolator, 367, 374, 376, 377 third-order filter, 347, 442
noise, 372, 408 Pipelined ADC, 143
shifting, 394 1.5-bit/stage, 151
Phase and frequency detector 2.5-bit/stage, 155
(PFD), 330, 333, 334, correction logic, 146
336–338, 343, 358, 362, 365, flash sub-ADC, 148
373, 390, 400, 432, 442 missing code, 145
Phase detector, 368, 374, 392, 431, multiplying DAC, 148
437 residue signal, 144
binary, 375, 378, 381 Pipelining, 249
full-rate linear, 386, 388 PLL, see Phase-locked loop
488 Index

Power amplifier (PA) nonlinearity errors, 49

class D, 426 segmented, 46
Power efficient, 374, 469 two-stage, 49
Pseudo-random noise generator, 279 Return-to-zero pulse, 37, 194
Pull-in Ring oscillator, 372, 383, 433
process, 378 ROM encoder, 119, 413
range, 403 Root locus, 471
time, 403 Rounding, 243
Pull-out range, 403 Rounding quantizer, 191
Pulse counting, 393 Runtime overflow, 253
Pulse-width modulation, 426, 431,
474 S
spectral analysis, 474 SAR ADC
three-level PWM, 478 algorithm, 92
two-level PWM, 477 charge redistribution, 95
PWM, see Pulse-width modulation bipolar, 98
unipolar, 98
Q differential architecture, 92
Quantization error, 12, 19, 188, 405 self-calibrating, 102
rounding quantizer, 20 single-ended architecture, 92
Quantization noise, 184–186, 189, Second-order bandpass modulator
191, 195, 197, 199, 201, 210, gm -C operational amplifier
213–217, 219, 220, 222 circuit, 234
Quantization noise transfer function, z −1 to −z −2 transformation, 227
185, 235, 238 resonator, 233
Quantizer two-path structure, 228
1-bit, 194 mismatches, 229
full-scale range, 191 Second-order modulator, 211
mid-riser, 13 Sequential logic circuit, 461
mid-tread, 13 S R latch, 336, 461
step size, 190 D flip-flop, 462
D latch, 462
R SR latch, 461
R-2R ladder DAC, 50 Serial interfacing, 294
Radius of curvature, 370, 471 Serial-to-parallel converter, 293
Random access memory (RAM), 211 Sign-magnitude representation,
Read-only memory (ROM), 412 17
Real-time operating system (RTOS), Signal transfer function, 185, 235
4 Signal-to-noise and distortion
Receiver, 416 (SINAD), 282
Regenerative latch, 148 Signal-to-noise ratio (SNR), 20, 22,
Relaxation oscillator, 425, 426, 444 272, 282, 285
Resistor-string DAC, 39–49 delta-sigma ADC, 23
intermeshed, 45 jitter, 24
monotonicity, 48 oversampling, 22
Index 489

Signal-to-quantization noise ratio, Switching scheme, 36, 38, 48, 49, 57,
192, 193 64, 66, 68
Sine wave, 187 Synthesis, 234, 235, 237
Single-stage modulator System on a chip, 1, 2, 6, 7, 9
first-order
1-bit quantizer, 197 T
dithering, 198 TDC, see Time-to-digital converter
tones, 198 Testbench, 4
higher-order, 199 Thermometer-to-binary encoder,
multi-bit quantizer, 199, 210 123, 408
second-order, 198 Time difference generator, 413
third-order, 198 Time division multiplexing, 290
stability, 199 Time-interleaved ADC, 159
Smoothing filter, 14, 37 clock skew error
SNR, see Signal-to-noise ratio (SNR) delay-locked loop, 162
Spurious tone, 279, 281, 408 gain and offset errors
Spurious-free dynamic range calibration, 163
(SFDR), 68, 282 gain dispersion, 163
SQNR, see Signal-to-quantization offset dispersion, 163
noise ratio timing skew error, 162
SRO-TDC, 412 Time-to-digital converter (TDC),
Stability, 370, 392, 471 400, 406, 407, 410, 412
criterion, 472 Total harmonic distortion (THD),
Standard deviation, 100 285, 430, 431
State-space representation, 237, 301 Transceiver, 414
Sub-ranging ADC, 142 Transconductance, 233, 234, 417, 421
Successive approximation register, Transmitter, 416
see SAR Tri-state buffer, 275, 460
Summer stage, 156, 420 Truncation, 243
Swapper, 279 Truncator, 211
Switched ring oscillator (SRO), 410 Tuning, 372
Switched-capacitor integrator, 197, inverter, 372
202 Two’s complement code, 13, 18
Switched-current DAC, 51
binary-weighted, 52 U
current source Undersampling, 401, 402
cascode configuration, 57 Unit element, 270, 279
output impedance, 57 Unit interval, 416, 421
element spread, 53 Up-sampler, 263, 265
glitches, 52 Up-sampling, 259
monotonicity, 52, 54
segmented, 54 V
thermometer-coded, 52 Vector quantizer, 275
two-stage decoding, 56 Vector-feedback ESL, 271, 275
Switching block, 279 Vernier delay line, 401
490 Index

Vernier TDC, 409 X

Via, 414 XOR gate, 118, 132, 139, 140, 279,
Voltage-controlled delay line 330–442, 454
(VCDL), 389, 392
Voltage-controlled oscillator (VCO), Z
400, 405, 431 Zero-stuff circuit, 263
Voltage-scaling DAC, 39

W
Walsh transform, 287
White noise, 21, 270, 286