STUDENT NAME:

STUDENT ID NUMBER: SECTION NUMBER IN THIS COURSE:

FINAL EXAMINATION – SPRING 2023

COURSE NAME: Computer Architecture

COURSE NUMBER:
SOC2060

EXAMINATION DATE: TIME:

EXAMINATION DURATION: 60 Minutes

ADDITIONAL MATERIALS None

ALLOWED TO USE:
- Answers will only be evaluated if they are readable.
- Show all your work. For some questions, you may get partial credit even if the
SPECIAL INSTRUCTIONS: end result is wrong due to a calculation mistake. If you make assumptions,
state your assumptions clearly and precisely.

Please do not open the examination paper until directed to do so.

___________________________________________________________________
READ INSTRUCTIONS FIRST:
Desks should be free from all unnecessary items (books, notes, technology, food, water, clothes)
Use of any electronic device (Phone, iPod, iPad, laptop) is not allowed during the examination.
Cheating, talking to fellow students, singing, turning back are not allowed
Write your Name (capital letters), ID number and Section number in each page of your examination paper.
Final answers must be written by only blue or black, non-erasable pen. Do not use highlighters or correction pen.
All answers should be written in the space provided for each question, unless specified the other way.
If you have a problem please raise your hand and wait quietly for a Proctor.
You are not allowed to leave the exam room until you submit the exam papers.
STUDENT NAME:
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1.[10 points] ISA and ISA Trade-offs

(a)[10 points] True/False questions - Circle T if the statement is true, circle F otherwise:

In MIPS, condition codes are set automatically when a general purpose register is written: T / F
The performance of a Multi-cycle MIPS is always better than a Single-cycle MIPS: T / F
In Multi-cycle MIPS, intermediate states are recorded in PC and memory : T / F
The behavior of the entire processor is specified fully by a finite state machine: T / F
In Multi-cycle MIPS, control signals for the next state are determined in current state: T / F
In Single-cycle MIPS, the most complex operation slows down everything: T / F
By adopting pipelining, more concurrency can be achieved: T / F
In Multi-cycle MIPS, most of the datapath is idle when a memory access is happening: T / F
The resource contention can be avoided by adopting pipelining: T / F
In Single-cycle MIPS, the memory contains both instructions and data: T / F

2. [10 points] Single-Cycle Processor Datapath

Below is the picture of a single-cycle MIPS processor.

And the formats of instructions are as follows

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PCSrc1=Jump
Instruction [25– 0] Shift Jump address [31– 0]
left 2
26 28 0 1

PC+4 [31– 28] M M

u u
x x
ALU
Add result 1 0
Add Shift
RegDst

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Jump left 2 PCSrc2=Br Taken
Branch
MemRead
Instruction [31– 26]
Control MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25– 21] Read

Read register 1
PC address Read
Instruction [20– 16] data 1
Read
register 2 Zero
Instruction 0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction u register M data
u M
memory Instruction [15– 11] x u
1 Write x Data
data x
1 memory 0
Write
data
16 32
Instruction [15– 0] Sign
extend ALU
control

Instruction [5– 0]

And ALUControl2:0 is doing the same job as F2:0 of following ALU Design.

(a)[10 points] A new R-type instruction “lw2” needs to be added to the instruction set. The semantics
of “lw2” is as follows:
lw2: Rd <- Memory[Rs + Rt]
PC <- PC + 4

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Control Signal Value

RegDst 1
PCSrc1 0
Branch 0
MemRead 1
MemtoReg 1
ALUControl2:0 010
MemWrite 0
ALUSrc 0
RegWrite 1
PCSrc2 0

3.[40 points] Multi-Cycle Processor Datapath

Below is the picture of a multi-cycle MIPS processor.
And instruction formats are the same as question 2.

And ALUControl2:0 is doing the same job as F2:0 in the following ALU Design.

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(a)[10 points] List all the values of control signals at “write back” phase of LW (Load Word) instruction.
If a control signal doesn’t affect the “write back”, write X meaning “don’t care”.
Control Signal Value
IorD X
RegWrite 1
IRWrite 0
RegDst 0
MemtoReg 1
PCWrite 0
PCSrc1:0 XX
ALUControl2:0 XXX
ALUSrcB1:0 XX
ALUSrcA X

(b)[10 points] List all the values of control signals at “memory access” phase of LW (Load Word)
instruction. If a control signal doesn’t affect the “memory access”, write X meaning “don’t care”.
Control Signal Value
IorD 1
RegWrite 0
IRWrite 0
RegDst X
MemtoReg X
PCWrite 0
PCSrc1:0 XX
ALUControl2:0 XXX
ALUSrcB1:0 XX
ALUSrcA X

(c)[10 points] List all the values of control signals at “decode / register operand fetch” phase of
BRANCH instruction. If a control signal doesn’t affect the “decode and register operand fetch”, write X
meaning “don’t care”.
Control Signal Value
IorD X
RegWrite 0
IRWrite 0
RegDst X
MemtoReg X
PCWrite 0
PCSrc1:0 XX
ALUControl2:0 010
ALUSrcB1:0 11
ALUSrcA 0

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(d)[10 points] List all the values of control signals at “execute / address generation” phase of BRANCH
instruction. If a control signal doesn’t affect the “execute and address generation”, write X meaning
“don’t care”.
Control Signal Value
IorD X
RegWrite 0
IRWrite 0
RegDst X
MemtoReg X
PCWrite 0
PCSrc1:0 01
ALUControl2:0 110
ALUSrcB1:0 00
ALUSrcA 1

4.[26 points] Caching

We have a byte addressable machine with L1, L2 cache and a memory. The size of a block is 16 bytes.
The size of L1 cache is 512 bytes, the size of L2 cache is 2048 bytes, and the size of the memory is 2 giga
bytes. The latency of L1 cache is 4 cycles, the latency of L2 cache is 8 cycles, and the latency of memory
is 100 cycles. The L1 cache is a direct-mapped cache and the L2 cache is a fully associative cache. You are
running a program which reads a byte from the memory 5 times. Assume both caches are empty and
the memory has all the data which your instructions are accessing.
(a)[3 points]
The address of the first byte to load is 0 and now the byte is loaded into a register. Specify how many
cycles are needed for the load and specify the starting address(es) of block(s) of L1 and L2 caches.

The number of cycles needed: 112 cycles

Starting address(es) of block(s) in L1 cache: 0
Starting address(es) of block(s) in L2 cache: 0

(b)[5 points]
The address of the second byte to load is 16 and now the byte is loaded into a register. Specify how
many cycles are needed for the load and specify the starting address(es) of block(s) of L1 and L2 caches.

The number of cycles needed: 112 cycles

Starting address(es) of block(s) in L1 cache: 0, 16
Starting address(es) of block(s) in L2 cache: 0, 16

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(c)[6 points]
The address of the third byte to load is 1025 and now the byte is loaded into a register. Specify how
many cycles are needed for the load and specify the starting address(es) of block(s) of L1 and L2 caches.

The number of cycles needed: 112 cycles

Starting address(es) of block(s) in L1 cache: 16, 1024
Starting address(es) of block(s) in L2 cache: 0, 16, 1024

(d)[6 points]
The address of the fourth byte to load is 18 and now the byte is loaded into a register. Specify how many
cycles are needed for the load and specify the starting address(es) of block(s) of L1 and L2 caches.

The number of cycles needed: 4 cycles

Starting address(es) of block(s) in L1 cache: 16, 1024
Starting address(es) of block(s) in L2 cache: 0, 16, 1024

(e)[6 points]
The address of the fifth byte to load is 15 and now the byte is loaded into a register. Specify how many
cycles are needed for the load and specify the starting address(es) of block(s) of L1 and L2 caches.

The number of cycles needed: 12 cycles

Starting address(es) of block(s) in L1 cache: 0, 16
Starting address(es) of block(s) in L2 cache: 0, 16, 1024

5.[14 points] Performance Evaluation

You need to choose a better processor to preform your experiment out of 2 processors A and B. The
clock frequency of A is 600 MHz and the clock frequency of B is 700 MHz. Processor B has 3 more
types of instructions (E,F,G), therefore the total number of executed instructions on B is 50% more
than Processor A to perform your experiment.

Processor A Processor B
Instruction CPI Frequecy Instruction CPI Frequecy
Class of Class of
Occurrece Occurrece
A 3 40% A 2 15%
B 2 25% B 2 15%
C 2 25% C 2 10%
D 8 10% D 3 10%
E 1 10%
F 2 20%
7
G 2 20%
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(a)[8points]. What is the CPI of each processor A and B? Show your work.

CPIA
CPIA = 0.4*3 + 0.25*2 + 0.25*2 + 0.1*8 = 3.0

CPIB
CPIB = 0.15*2 + 0.15*2 + 0.1*2 + 0.1*3 + 0.1*1 + 0.2*2 + 0.2*2 = 2.0

(b)[6points]. Which processor are you going to choose? Show your work in terms of total execution
time. On Processor A, the total number of instructions to perform your experiment is 1,000,000. If
the total time on processor A and B are the same, choose the one with more instructions for next
experiments.

Processor A or B?: Choose B

Total Time on Processor A: 1,000,000*3/600*10**6 = 0.005

Total Time on Processor B: 1,500,000*2/700*10**6 = 0.0043