Digital 7

Master-Slave Flip-Flops
• The transparent D latch is so called ‘level’

triggered. We can see it exhibits transparent
behaviour if EN=1. It is often more simple to
design sequential circuits if the outputs
change only on the either rising (positive
going) or falling (negative going) ‘edges’ of
the clock (i.e., enable) signal
• We can achieve this kind of operation by
combining 2 transparent D latches in a so
called Master-Slave configuration
Master-Slave D Flip-Flop
Master Slave Symbol
Qint
D D Q D Q Q D Q
CLK
• To see how this works, we will use a timing diagram

• Note that both latch inputs are effectively connected
to the clock signal (admittedly one is a complement
of the other)
Master-Slave D Flip-Flop
Master Slave
Qint
D D Q D Q Q
See Q changes on rising

CLK edge of CLK
CLK
CLK
Note propagation delays
D have been neglected in
the timing diagram
Qint
Q
D Flip-Flops
• The Master-Slave configuration has
now been superseded by new F-F
circuits which are easier to implement
and have better performance
• When designing synchronous circuits it
is best to use truly edge triggered F-F
devices
• We will not consider the design of such
F-Fs on this course
Other Types of Flip-Flops
• Historically, other types of Flip-Flops
have been important, e.g., J-K Flip-
Flops and T-Flip-Flops
• However, J-K FFs are a lot more
complex to build than D-types and so
have fallen out of favour in modern
designs, e.g., for field programmable
gate arrays (FPGAs) and VLSI chips
Other Types of Flip-Flops
• Consequently we will only consider
synchronous circuit design using D-type
FFs
• However for completeness we will
briefly look at the truth table for J-K and
T type FFs
J-K Flip-Flop
• The J-K FF is similar in function to a
clocked RS FF, but with the illegal state
replaced with a new ‘toggle’ state
J K Q Q  comment Symbol
0 0 Q Q hold J Q
0 1 0 1 reset
1 0 1 0 set K Q
1 1 Q Q toggle
Where Q is the next state
and Q is the current state
T Flip-Flop
• This is essentially a J-K FF with its J
and K inputs connected together and
renamed as the T input
Symbol
T Q Q  comment Q
0 Q Q hold T
1 Q Q toggle Q
Where Q is the next state

and Q is the current state
Asynchronous Inputs
• It is common for the FF types we have mentioned
to also have additional so called ‘asynchronous’
inputs
• They are called asynchronous since they take
effect independently of any clock or enable inputs
• Reset/Clear – force Q to 0
• Preset/Set – force Q to 1
• Often used to force a synchronous circuit into a
known state, say at start-up.
Timing
• Various timings must be satisfied if a FF
is to operate properly:
– Setup time: Is the minimum duration that
the data must be stable at the input before
the clock edge
– Hold time: Is the minimum duration that the
data must remain stable on the FF input
after the clock edge
Applications of Flip-Flops
• Counters
– A clocked sequential circuit that goes through a
predetermined sequence of states
– A commonly used counter is an n-bit binary
n
counter. This has n FFs and 2 states which are
n
passed through in the order 0, 1, 2, ….2 -1, 0, 1, .
– Uses include:
• Counting
• Producing delays of a particular duration
• Sequencers for control logic in a processor
• Divide by m counter (a divider), as used in a digital
watch
Applications of Flip-Flops
• Memories, e.g.,
– Shift register
• Parallel loading shift register : can be used for
parallel to serial conversion in serial data
communication
• Serial in, parallel out shift register: can be used
for serial to parallel conversion in a serial data
communication system.
Counters
• In most books you will see 2 basic types
of counters, namely ripple counters and
synchronous counters
• In this course we are concerned with
synchronous design principles. Ripple
counters do not follow these principles
and should generally be avoided if at all
possible. We will now look at the
problems with ripple counters
Ripple Counters
• A ripple counter can be made be cascading
together negative edge triggered T-type FFs
operating in ‘toggle’ mode, i.e., T =1
Q0 Q1 Q2
‘1’ ‘1’ ‘1’
Q Q Q
T T T
Q Q Q
CLK
• See that the FFs are not clocked using the

same clock, i.e., this is not a synchronous
design. This gives some problems….
Ripple Counters
• We will now draw a timing diagram
CLK
Q0
Q1
Q2
0 1 2 3 4 5 6 7 0
• Problems:
See outputs do not change at the same time, i.e., synchronously.
So hard to know when count output is actually valid.
Propagation delay builds up from stage to stage, limiting
maximum clock speed before miscounting occurs.
Ripple Counters
• If you observe the frequency of the counter
output signals you will note that each has half
the frequency, i.e., double the repetition
period of the previous one. This is why
counters are often known as dividers
• Often we wish to have a count which is not a
power of 2, e.g., for a BCD counter (0 to 9).To
do this:
– use FFs having a Reset/Clear input
– Use an AND gate to detect the count of 10 and
use its output to Reset the FFs

Digital 7

Uploaded by

Copyright:

Available Formats

Digital 7

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital 7

Uploaded by

Copyright:

Available Formats

Master-Slave Flip-Flops

• The transparent D latch is so called ‘level’

• To see how this works, we will use a timing diagram

See Q changes on rising

Where Q is the next state

• See that the FFs are not clocked using the

You might also like