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SUBJECT : ELECTRONIC CIRCUITS AND DEVICES

SUBJECT CODE : 308432
LAB REPORT NO : 6

TITLE : DIODE APPLICATIONS AS CLAMPERS(B)

SUBMITTED TO : Ma’am Anila Ahmed

SEMESTER : 4th
SECTION : B

Marks Obtained
Group Group Group
Member 1 Member 2 Member 3
NAME Mahnoor Dua Naseem Ifrah Gohar
Khan
REGISTRATION # 220701002 220701014 220701058
LAB REPORT 6 6 6
PERFORMANCE
TOTAL MARKS
DEPARTMENT OF AVIONICS ENGINEERING

DEADLINE 1st April, 2024

DATE OF SUBMISSION 31st April, 2024

Objectives:

The objective of this Lab exercise is to verify the behavior of Diode Circuit as a
Clamper in various configurations such as:

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1. Series Positive Clamper and Series Negative Clamper

2. Biased Positive Clamper and Biased Negative Clamper

On Hardware and Using LTSpice Simulation Software.

Equipment Required:

1. Oscilloscope
2. Bread Board
3. Diode (1N4007)
4. Resistors 10k
5. Capacitor 10𝜇F
6. Trainer set with 9V ac source

Theory/Background:

A Clamper Circuit is a circuit that adds a DC level to an AC signal. Actually, the

positive and negative peaks of the signals can be placed at desired levels using
the clamping circuits. As the DC level gets shifted, a clamper circuit is called as a
Level Shifter.
A Clamper circuit can be defined as the circuit that consists of a diode, a resistor
and a capacitor (energy storing element) that shifts the waveform to a desired DC
level (adds DC voltage) without changing the actual appearance of the applied
signal. Sometimes the circuit may have a dc battery (𝑉𝐵𝑖𝑎𝑠) to set the reference
level to which an ac voltage level is added.

Types

1. Positive Clamper
2. Negative Clamper
3. Biased Positive
Clamper

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a. With positive reference voltage

b. With negative reference voltage

4. Biased Negative Clamper

a. With positive reference voltage

b. With negative reference voltage

1. Postitive Clamper: Circuit Diagram & Input/Output Waveforms

Operation
During the negative half cycle, the diode is forward biased and hence voltage at
output is the forward voltage drop of diode and the capacitor charges to the
value
(𝑉𝑝(𝑖𝑛) – 0.7 𝑉) .
During the positive half cycle, the diode is reverse biased. The applied voltage
appears at output. During this cycle the capacitor discharges and this voltage
(stored in capacitor, that is being discharged) is added to the input voltage. So
the output voltage is the sum of the input voltage and the capacitor (discharge)
voltage. The amount that is discharge depends on the value of resistor 𝑅𝐿 and
capacitor C. For a good clamping action, RC time constant should be atleast ten
times the period of the input frequency.

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The net effect of the clamping action is that the capacitor retains a charge
approximately equal to the peak value of the input less the diode drop. The
capacitor voltage acts essentially as a battery in series with the input voltage.
Hence a dc level equal to (𝑉𝑝(𝑖𝑛) − 0.7) will be added to input voltage.

Input Sine Wave

1

0.8

0.6

0.4

0.2
Amplitude

-0.2

-0.4

-0.6

-0.8

-1
0 0.5 1 1.5 2
Time (s)

INPUT WAVEFORM OUTPUT WAVEFORM

CIRCUIT:

Results:
Comparing the results obtained in above figure with the output shown in Figure
1, we observe ac input voltage is 12𝑉. However a dc level has been added to
output voltage and hence the negative peak of output is shifted to -0.7 and
postive peak to 23. Ideally the positive peak (assuming no discharge from

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capacitor during positive cycle) should be at (𝑉𝑝(𝑖𝑛) – 0.7 𝑉) = 24 − 0.7 = 23.3𝑉.

This can be obtained by increasing either the value of 𝑅 or 𝐶, as discussed earlier.
2. Negative Clamper: Circuit Diagram & Input/Output Waveforms

Reverse the orientation of the diode and capacitor in the previous circuit, to
obtain a negative series clamper.

Operation
During the postive half cycle, the diode is forward biased and maximum current
flows through the diode (instead of Load Resistor 𝑅𝐿) and hence voltage at output
is the forward voltage drop of diode. The capacitor charges to the value
(𝑉𝑝(𝑖𝑛) – 0.7 𝑉) due to this forward current.
During the negative half cycle, the diode is reverse biased. The applied voltage
appears at output. Again during this cycle the capacitor discharges and this
voltage (stored in capacitor, that is being discharged) is added to the input
voltage. So the output voltage is the sum of the input voltage and the capacitor
(discharge) voltage. Applying KVL to the above circuit:

+𝑉𝑝(𝑖𝑛)+𝑉𝑐 + 𝑉𝑜 = 0.

Here 𝑉𝑐 represents capacitor voltage and is equal to 𝑉𝑝(𝑖𝑛) − 0.7. Note that the sign
of input voltage has been taken positive since it’s a negative half cycle. This
implies,
𝑉𝑜 = 2𝑉𝑝(𝑖𝑛) − 0.7.

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The net effect of the clamping action is that the capacitor retains a charge
approximately equal to the peak value of the input less the diode drop. The
capacitor voltage acts essentially as a battery in series with the input voltage.
Hence a dc level equal to −(𝑉𝑝(𝑖𝑛) − 0.7) will be added to input voltage. The
positive peak of input has shifted to 0.7𝑉 and negative to −2𝑉𝑝(𝑖𝑛) + 0.7𝑉.

3. Positive Clamper With Positive Biased Reference Voltage:

Circuit Diagram & Input/Output Waveforms
In the circuits discussed above we were restricted to add dc level of peak input
voltage, A dc level of any desired value can be added using biased reference
voltage.
A Positive clamper circuit, if biased with some positive reference voltage, that
voltage will be added to the output to raise the clamped level. Using this, the
circuit of the positive clamper with positive reference voltage is constructed as
below.

Operation
To clamp the input signal by a voltage other than peak value, a dc source is
required. Let the input signal swing form +10 V to -10 V. During positive half
cycle, the diode is forward biased, and conducts current till the input voltage is
less than 5V, the capacitor starts charging and a DC biased equal to 𝑉𝐵𝐼𝐴𝑆 − 0.7
appears on the output, when the voltage exceeds 5V, the diode becomes reverse

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biased and the dc level due to capacitor charge is added to the input. In the
negative half cycle when the voltage becomes less than 5𝑉 (considering 𝑉𝐵𝐼𝐴𝑆 =
5𝑉), then the Diode conducts. During input voltage variation from –5 V to -10 V,
the capacitor charges to 5 V with the polarity shown in Figure 4. After that D
becomes reverse biased and hence the becomes open circuit. Then complete ac
signal is shifted upward by an additional 5 V (capacitor charged voltage). This
DC shift in voltage level can be controlled setting reference voltage to any
desired value.

INPUT WAVEFORM OUTPUT WAVEFORM

CIRCUIT:

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4. Positive Clamper With Negative Biased Reference Voltage:

Circuit Diagram & Input/Output Waveforms

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I
N
P
U T
W
AV E
FO
RM
OUTPUT WAVEFORM

Task 1: Simulate Negative Clamper on LTSpice. Show circuit

diagram as well as simulation results

Negative Clamper Circuit:

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Simulation Result:

Task 2: Simulate Positive Clamper with positive bias voltage = 5V

on LTSpice. Show Circuit Diagram as well as Simulation Results.

Positive Clamper with Positive Bias Circuit :

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Simulation:

Task 3: Explain the operation of Positive Clamper with Negative

Biased Reference Voltage for both Cycles. Simulate the circuit for
Negative Biased Voltage (take any value for it) on LTSpice. Show
Circuit Diagram as well as Simulation Results.

Initial State (Before Negative Half Cycle):

The capacitor holds the voltage at the negative biased reference level
(from the previous positive half cycle).
The diode is reverse-biased again as the input signal is negative.

Negative Half Cycle (Input Signal is Negative):

As the negative half cycle of the input signal starts, the diode remains
reverse-biased, preventing the discharge of the capacitor through the
diode.
The capacitor maintains its voltage at the negative biased reference
level.

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End of Negative Half Cycle:

At the end of the negative half cycle, the input signal starts to rise
towards zero.
The capacitor voltage remains clamped at the negative biased
reference level.
The diode remains reverse-biased, maintaining the charge on the
capacitor.
Positive Clamper with Negative Biased Circuit:

Simulation Result:

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Task 4: Design the circuit for a negative clamper with positive

reference voltage. Explain the circuit operation for the complete
input cycle. Verify your results by simulating the circuit on
LTSpice.

Initial State:
Initially, the capacitor is charged to the positive reference voltage (Vref) through
the diode when the input signal (Vin) is at a lower voltage level.
The diode is forward-biased, allowing the capacitor to charge to Vref.

Positive Half Cycle of Input (Vin is Positive):

As the positive half cycle of the input signal starts, the diode becomes reverse-
biased because the voltage at the anode is higher than at the cathode.
The capacitor remains charged to Vref as the diode blocks any discharge path.
The voltage across the resistor and capacitor combination follows the input signal
with an offset of Vref.
So, the output voltage (Vout) follows Vin with an offset of Vref during the
positive half cycle.

Negative Half Cycle of Input (Vin is Negative):

As the negative half cycle of the input signal starts, the diode remains reverse-
biased, maintaining the charge on the capacitor.
The voltage across the resistor and capacitor combination still follows the input
signal with an offset of Vref, resulting in Vout tracking Vin with the offset
maintained.

End of Input Cycle:

At the end of the input cycle, regardless of the polarity of the input signal, the
capacitor maintains the charge of Vref.
Therefore, the output waveform (Vout) follows the input waveform (Vin) with an
offset of Vref for the entire input cycle.

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Negative Clamper with Negative Biased Circuit:

Simulation Result:

CONCLUSION:

In this lab, the experiment provided a comprehensive understanding of diode

clampers and their applications in electronic circuits. By examining both positive and
negative clamper configurations, we gained practical experience in circuit design,
analysis, and troubleshooting. This knowledge is essential for further exploration in
the field of electronics and serves as a foundation for understanding more complex
circuitry and systems.

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