Gianluca Guagliardo Z#23442507 09/24/2022
Homework 1 (Op-Amp and Diode Circuits)
Gianluca Guagliardo
10/21/2022
EEE 3300-001: Electronics 1
Prof. Vance Peterson
Introduction
In the present “PSPICE Homework 1” you will find TWO PARTS:
PART 1: OP-AMPS [2x Analysis and circuit Designs]
The applications on this specific homework are:
Small Signal COMPARATORS, INVERTERS, LOW PASS FILTER, BUFFER
PART 2: DIODES [3x Analysis and circuit Designs]
HALF bridge rectifier DIODE and DC Power Supplies R-C
FULL bridge rectifier DIODE and DC Power Supplies R-C
FULL bridge rectifier DIODE and DC Power Supplies with a Zener Diode
The above-mentioned applications are all accomplished by means of using the following
electronics devices such as:
OP-AMPS – Model Ua741 Operational Amplifier
Regular silicon Diodes Model D1N4148
Zener Diodes as Voltage regulators
Resistors and Capacitors of different values depending on design
The below proposed solutions and designs are key to familiarize with the most basic
electronic components while allowing you to create and simulate with PSPICE the actual
circuit applications.
Gianluca Guagliardo Z#23442507 09/24/2022
Part I: Op-Amps
Problem 1: (10 points):
Problem 1 analytic solution:
In order to eliminate the 10KHz signal on V0(t), I need to subtract Vs2 out of V0(t), to
accomplish this, I will inject [-Vs2(t)] on A(shown above).
I will choose inverter configuration as follows:
So, we could use 𝑅𝐸 = 2𝑘 => Gain = -1, then on the 2nd Stage of the Circuit:
= -(Vs1 (t)+ Vs2 (t))
Figure 2 – 2nd stage
This last stage inverts all signals coming in and subtracts signal (-Vs2) from V01(t)
eliminating the 10KHz signal out of V0(t) so V0(t) will be mostly a 200Hz signal.
Gianluca Guagliardo Z#23442507 09/24/2022
Now onto the analysis of the 2nd stage we know that
𝑹𝑩
𝑽𝟎(𝒕) = − 𝑹𝑨 ∗ 𝑽𝟎𝟏 (𝒕) + [𝑲] ∗ 𝑽𝒔𝟐(𝒕)
And that
𝑽𝟎𝟏 (𝒕) = −(𝑽𝒔𝟏 (𝒕) + 𝑽𝒔𝟐 (𝒕))
Let’s find out [K] as a function of resistors RA, RB, RC, RD:
𝑽𝟎𝟏 −𝑽𝑩
𝒗𝑩 = ((−𝑽𝑺𝟐 ) ∗ 𝑹𝑫/𝑹𝑪 + 𝑹𝑫, 𝑰𝟑 = , 𝑽𝑶 (𝒕) = 𝑽𝑩 − 𝑰𝟑 ∗ 𝑹𝑩
𝑹𝑨
(𝑽𝟎𝟏 −𝑽𝟖 ) 𝑹 𝑹
𝑽𝑶(𝒕) = 𝑽𝑩 − ∗ 𝑹𝟖 = 𝑽𝑩 − 𝑽𝟎𝟏 (𝑹𝑩) + 𝑽𝑩 (𝑹𝑩 )
𝑹𝑨 𝑨 𝑨
𝑹 𝑹
Using common factor: 𝑽𝟎 (𝒕) = 𝑽𝑩 (𝟏 + 𝑹𝑩) − 𝑽𝟎𝟏 (𝑹𝑩)
𝑨 𝑨
Replacing VB and V01 by:
𝑉𝑆2 𝑅𝐷 𝑅𝐵 𝑅𝐵
𝑉0 (𝑡) = − ∗ (1 + ) + (𝑉𝑆1 + 𝑉𝑆2 ) ( )
𝑅𝐶 + 𝑅𝐷 𝑅𝐴 𝑅𝐴
If we want to eliminate Vs2(t) [10kHz] signal, then we adopt a gain of 10, thus RB = 10k,
𝑅𝐷 10𝑘
RA = 1k and making 𝑅 (1 + ) = 10k, thus RC = 1k, RD = 10k
𝐶 +𝑅𝐷 1𝑘
Problem 1 PSPICE:
To understand the circuit below, it is critical to understand that there are three distinct
stages, each represented by an OP Amp and its unique configuration. Below is a brief
explanation of what each component of the circuit does and why.
Figure 1: Complete Linear
combiner circuit
Gianluca Guagliardo Z#23442507 09/24/2022
1st STAGE: The first stage involves ADDING and INVERTING the two Input Signal
sources that are connected to PIN 2. (-). So, by adding and inverting both signals, the output of
this first stage is a COMBINED LOW FREQUENCY SIGNAL (200Hz) with the HIGH FREQUENCY
SIGNAL (10kHz) mounted on top.
2nd STAGE: The goal here is to only INVERT the 10Khz signal source, allowing the
Inverted VS2 to be injected onto the final 3rd stage. And with the same GAIN as in Stage 1, the
GAIN of both the first and second stages is 1. And, as previously stated, is inverting the signal so
that the actual [GAIN = -1].
3rd STAGE: We have a configuration on the final third stage that will ADD the two
signals coming into the OP AMP #3. (2 & 3 Pin). However, we know that the signal arriving at
Pin 3 (+) will retain its sign, whereas the signal arriving at Pin 2 (-) will be inverted once more. In
addition, because we are using a 12-volt power supply, we sized the RESISTORS for a GAIN of 10
times on this final stage of our circuit. This is visible in the Analytic solution. Based on the
preceding concept:
on Pin 2 (-) we see V01 consisting of (Vs1 + Vs2) and
on Pin 3(+) we see (Vs2)
then but adding both signal together and sizing RESISTORs accordingly the output signal of this
3rd stage will be a clean:
V out = [10x] * (Vs1) “1.1v 200Hz”, which is basically a V out signal as follows:
Amplitude=11V and FREQ=200Hz, where the 10Khz signal component has been
completely eliminated.
SEE BELOW PSPICE SCREENSHOTS DEPICTING THE ABOVE:
Gianluca Guagliardo Z#23442507 09/24/2022
Below you will see a screenshot that shows the INPUT to OP AMP #3 (small RED and
GREEN signals) and a clean (PURPLE) V out. We only showed half cycle for a cleaner screenshot.
GREEN small Signal is (Vs1 + Vs2) (1.1v 200Hz + 1.2v 10,000Hz)
RED small Signal is (Vs2)
PURPLE amplified Signal is (V out) (11V and 200 Hz)
Gianluca Guagliardo Z#23442507 09/24/2022
Problem 2: (10 points):
Problem 2.1 analytic solution:
In this problem we are using an OP-AMP 741 as a Comparator as seen below
V0(t)
-14V
When the signal Vs(t)=VIN is above VREF then the output of the OP-AMP(741) will go HIGH
to +14V, while VIN is below VREF the OP-AMP output will go low to –14 volts.
Let’s find RA and RB:
RB
If VREF = 5 volts, then +14 ∗ RA+RB = +5 =>
+14RB = 5RA + 5RB =>
9RB = 5RA =>
9
𝑅𝐴 = 5 𝑅𝐵 =>
If we adopt RB = 1kΩ then we get that RA = 1.8kΩ
Gianluca Guagliardo Z#23442507 09/24/2022
Problem 2.2 analytic solution:
Using a 741 OP-AMP as a BUFFER it would not show any improvement when creating
the Voltage Divider(VREF)
A Buffer would only help presenting a HIGH INPUT IMPEDANCE
Buffer Config
But in the design, the OP-AMP 741 already has HIGH INPUT IMPEDANCE. Therefore, the
below configuration will work accordingly.
RA // RB = 1k, which in series with Zin is Zin + 1k = Zin and therefore there is NO NEED FOR
Zin
A BUFFER
Gianluca Guagliardo Z#23442507 09/24/2022
Problem 2.3 analytic solution:
This configuration is widely known as OPEN LOOP COMPARATOR, as such it compares
level of voltages between the (+)(3) and (-)(2) pins of the OP-AMP.
In this case, the Voltage Divider RA & RB on the (+)(3) pin creates a REFERENCE
VOLTAGE which could in some cases be controlled by a Variable Resistor RB (not the case here).
From part 2.1 of this exercise, we can tell that the REFERENCE VOLTAGE has been set at
5VDC by using a 14Vdc source and RESISTORS RA=1.8k and RB=1.0k.
Now, it is key to understand that a HIGH GAIN OP AMP that is in an OPEN LOOP will go
into SATURATION on the output providing either +V or -V depending on power configuration.
This means, that when the voltage on Pin (3) is greater than voltage on Pin (2) then the Vout will
be +V, on the contrary Vout will be -V
Then, in our circuit when we apply an AC Voltage source on pin (3) and that AC Voltage
goes over the Vref =5Vdc then Vout will change accordingly to +14 or -14 volts depending on the
Amplitude of the Voltage source.
In our case, there are 2 scenarios:
a) Where the INPUT Voltage SOURCE is 1.6 volts peak sinewave at 200Hz
As mentioned before if the INPUT Voltage NEVER reaches 5 volts due to the fact the peak of
the input signal is only 1.6 volts, then the Output Vout will remain at -14 volts (See PSPICE
diagram below)
b) Where the INPUT Voltage SOURCE is 5.6 volts peak sinewave at 400Hz
Here, the 5.6 volts INPUT AC Voltage will go over the 5 volts Reference Voltage then
switching from -V to +V at Vout will occur and will stay at +V for as long as the sinewave stay
over the 5 volts mark. When Vsin falls under 5 volts then again, the output of the OP-Amp will go
to -V and remained there until next cycle. (See PSPICE diagram below)
Gianluca Guagliardo Z#23442507 09/24/2022
Problem 2.3 PSPICE:
If Vs(t) is AC of amplitude 1.6V and has a frequency of 200Hz the output would look like
the following below:
If Vs(t) is AC of amplitude 5.2V and has a frequency of 400Hz the output would look like
the following below:
Gianluca Guagliardo Z#23442507 09/24/2022
Problem 3 (10 points):
Problem 3.1 analytic solution:
The Diagram below depicts an OP-AMP (Inverter and Integration) of the v0(t), acting as a
Low Pass Filter.
Figure 3: op-amp circuit
Problem 3.2 analytic solution:
There are 2 ways to solve this circuit:
𝑉 (𝑆 )
• Finding 𝑉 0 (𝑠) in the Freq/Domain
𝑖𝑛
• Finding V0(t) and Vin(t) in the time domain
Using the first one:
𝑽𝒐 (𝑺) 𝒁 𝟏
1. 𝑯(𝒔) = = − 𝒁𝟐 where 𝒁𝟐 = 𝑹𝟑 // 𝑿𝑪 = 𝑹𝟑 // 𝒋𝒘𝒄
𝑽𝒊𝒏 (𝑺) 𝟏 𝟏
𝟏
𝑹𝟑 ∗( ) 𝑹𝟑 𝑹𝟑
𝒋𝒘𝒄𝟏
2. 𝒁𝟐 = 𝟏 = =
(𝑹𝟑 + ) 𝒋𝒘𝑹𝟑𝑪𝟏 +𝟏 𝟏+𝒋𝒘𝑪𝟏 𝑹𝟑
𝒋𝒘𝒄𝟏
Replacing 2 into 1:
𝑉0 (𝑆) 𝑅 1
𝐻 (𝑆 ) = = − (𝑅3 ) ∗ (1+𝑗𝑤𝐶 and in order to find the cut-off Freq:
𝑉𝑖𝑛 (𝑆) 2 1 𝑅3 )
𝑽 (𝑺) 𝟏
We know that at fc the cut-off frequency => 𝑽 𝟎 (𝑺) = at 𝑊𝑐 = 2𝜋𝑓𝑐
𝒊𝒏 √𝟐
𝟏 𝟏 𝟏
= => =>
|𝟏+𝒋𝒘𝒄𝑪𝟏 𝑹𝟑 | √𝟐 √𝟏𝟐 +(𝒘 𝒄 )𝟐(𝑪 𝟏)
𝟐 (𝑹
𝟑)
𝟐
𝟏
𝟐 = 𝟏 + (𝒘𝒄 )𝟐 (𝑪𝟏)𝟐 (𝑹𝟑 )𝟐 => 𝒇𝒄 = = 𝟓𝟎𝟓. 𝟐𝟓𝑯𝒁
𝟐𝝅𝑪𝟏 𝑹𝟑
Gianluca Guagliardo Z#23442507 09/24/2022
Problem 3.3 analytic solution:
𝒓𝒂𝒅
When w1 = 𝟐𝝅 ∗ 𝟏𝟎𝟎𝑯𝒛 => 𝟔𝟐𝟖 𝒔𝒆𝒄
𝑮 ≅ 𝟏 − 𝒋(𝟎. 𝟐)
|G| = √𝟏𝟐 + (𝟎. 𝟐)𝟐 ≅ 𝟏. 𝟎𝟐
(−𝟎.𝟐)
∅ = 𝒂𝒓𝒄𝒕𝒂𝒏 = −𝟏𝟏°
𝟏
Problem 3.4 analytic solution:
𝒓𝒂𝒅
When w2 = 𝟐𝝅 ∗ 𝟓𝟎𝟎𝟎𝟎𝑯𝒛 => 𝟑𝟏𝟒, 𝟏𝟓𝟗 𝒔𝒆𝒄
𝑮 ≅ 𝟏. 𝟐 ∗ 𝟏𝟎−𝟒 − 𝒋(𝟎. 𝟎𝟏𝟎𝟏𝟎) => |𝐆| ≅ 𝟎. 𝟎𝟏
𝟎.𝟎𝟏𝟎𝟏
∅ = 𝑻𝑨𝑵−𝟏 (𝟏.𝟐∗𝟏𝟎−𝟒 ) = −𝟗𝟎°
Problem 3 PSPICE:
The figure above shows that the green signal is the sum of the two input sources while
the red signal is the output of the low pass filter configuration which is the filtered version of
the combined input signal (100Hz + 50kHz signal). Note that the red signal is a 100Hz signal with
almost no 50kHz signal on it. Screenshot below shows in detail the sawtooth shape of the
output signal.
Gianluca Guagliardo Z#23442507 09/24/2022
Part II: Diodes
Problem 4 (10 points):
Problem 4.0 analytic solution:
Figure 4.3. Full-Wave
Diode Bridge Rectifier
REQUIREMENTS
Vripple < 1.2 Volts
C < 250 uF
R < 100kΩ
Find C2 and R2 for these requirements.
𝑇
Referring to Unit 13’s Full Wave Rectifier Formula we get 𝑉𝑟𝑖𝑝𝑝𝑙𝑒 ≅ 𝑉𝑝𝑒𝑎𝑘 ∗ 2𝑅𝐶 with
𝑉𝑝𝑒𝑎𝑘 = 𝐴 − (0.7 𝑉𝑜𝑙𝑡𝑠) ∗ 2 =>
𝑉𝑝𝑒𝑎𝑘 = 18 − 2(0.7 𝑉𝑜𝑙𝑡𝑠) = 16.6 𝑉𝑜𝑙𝑡𝑠
𝟏
𝑽𝒓𝒊𝒑𝒑𝒍𝒆 ≅ (𝟏𝟔. 𝟔) 𝟏𝟓𝟎𝑯𝒛
𝟐𝑹𝟐 𝑪𝟐
If we adopt Vripple < 1.2V we get that Vripple = 0.8 Volts =>
𝟏𝟔. 𝟔
𝟎. 𝟖 ≅
𝟐(𝟏𝟓𝟎)𝑹𝟐𝑪𝟐
𝟏𝟔.𝟔
𝑹𝟐 𝑪 𝟐 ≅ = 𝟎. 𝟎𝟔𝟗 => 𝑰𝒇 𝑰 𝒄𝒉𝒐𝒐𝒔𝒆 𝒄𝟐 ≤ 𝟐𝟎𝟎𝒖𝑭
𝟐(𝟏𝟓𝟎)(𝟎.𝟖)
𝟎.𝟎𝟔𝟗 𝟏
𝑹𝟐 ≅ ∗ 𝟏𝟎−𝟔 = (𝟎. 𝟎𝟔𝟗) ∗ 𝟐𝟎𝟎 ∗ 𝟏𝟎𝟔 𝛀 ≅ 𝟑𝟒𝟔𝛀
𝟐𝟎𝟎
Gianluca Guagliardo Z#23442507 09/24/2022
𝑪𝟐 = 𝟐𝟎𝟎𝒖𝑭 & 𝑹𝟐 = 𝟑𝟒𝟔Ω
0.8𝑉
The percentage of ripple is : 16.6𝑉 ∗ 100 = 4.8%
𝑇
Note that the percentage of Vripple validates the use of the equation 𝑉𝑟𝑖𝑝𝑝𝑙𝑒 ≅ 𝑉𝑝𝑒𝑎𝑘 ∗ 2𝑅𝐶
(approximated formula from Taylor series)
Problem 4.0 PSPICE:
15.910V
15.326V
It can be seen that the Vripple is approximately 0.6V which is better than the analytical value
calculated above.
Gianluca Guagliardo Z#23442507 09/24/2022
Problem 5 (10 points):
Problem 5.0 analytic solution:
Figure 5.1. Full-Wave
Diode Bridge Rectifier
Given the following requirements:
𝑉𝑠𝑖𝑛 = 𝐴 = 15𝑉
𝑉𝑟𝑖𝑝𝑝𝑙𝑒 < (0.05) ∗ 14.3𝑉 = 0.715𝑉
𝑇
Referring to the Full Design Rectifier Formula again 𝑉𝑟𝑖𝑝𝑝𝑙𝑒 ≅ 𝑉𝑝𝑒𝑎𝑘 ∗ 2𝑅𝐶
𝑉𝑝𝑒𝑎𝑘 = 15𝑉 − 0.7 = 14.3 𝑉𝑜𝑙𝑡𝑠
1
(14.3)( )
440
𝑉𝑟𝑖𝑝𝑝𝑙𝑒 < if I adopt C1 = 33uF then ,
2𝑅1 𝐶1
1
(14.3)( ) 14.3
𝑅1 ≤ 440
= 20,763.60 ∗ 106 = 688.7052Ω
2(0.715)(33)
𝐂𝟏 = 𝟑𝟑𝐮𝐅 & 𝐑 𝟏 = 𝟔𝟖𝟖. 𝟕𝛀
Then for the design I choose the following practical values
𝐂𝟏 = 𝟑𝟑𝐮𝐅 & 𝐑 𝟏 = 𝟔𝟖𝟎𝛀
Gianluca Guagliardo Z#23442507 09/24/2022
Problem 5.0 PSPICE:
As you can see the Vripple is approximately 0.7V which is consistent with the analytical
value calculated above.
Gianluca Guagliardo Z#23442507 09/24/2022
Problem 6 (10 points):
Problem 6.0 analytic solution:
Figure 6.1. Full-Wave
Diode Bridge Rectifier with
Shunt Regulator
𝐼𝑧𝑚𝑖𝑛 = 7 𝑚𝐴
𝑅𝑧 = 19𝛺
𝑉𝑍0 = 𝑉𝑍 − 𝐼𝑧 ∗ 𝑅𝑧 if 𝑉𝑧 = 4.7𝑉 => 𝑽𝒁𝟎 = 𝟒. 𝟕𝑽 − 𝟐𝟎𝒎𝑨 ∗ 𝟏𝟗𝜴 = 𝟒. 𝟑𝟐𝑽
𝐼𝑧 = 20 𝑚𝐴
𝑉𝑠𝑚𝑖𝑛 = 𝑉𝑝𝑒𝑎𝑘 − 0.7 − 𝑉𝑟𝑖𝑝𝑝𝑙𝑒
𝑉𝑠𝑚𝑖𝑛 −𝑉𝑍0 −𝐼𝑍𝑚𝑖𝑛 ∗𝑟𝑍
𝑅1 ≤ where 𝑉𝑠𝑚𝑖𝑛 = 15𝑣 − 0.7 − 0.258𝑣
𝐼𝐿𝑚𝑎𝑥 +𝐼𝑍𝑚𝑖𝑛
𝑉𝑠𝑚𝑖𝑛 = 14.042𝑣00000000
14𝑣−4.32𝑣−7𝑚𝐴∗19𝛺
𝑅1 ≤ adopting R1 as 220 𝛺
𝐼𝐿𝑚𝑎𝑥 +7𝑚𝐴
14𝑣 − 4.32𝑣 − 7𝑚𝐴 ∗ 19𝛺
220𝛺 ≤
𝐼𝐿𝑚𝑎𝑥 + 7𝑚𝐴
Solving for 𝐼𝐿𝑚𝑎𝑥 :
14𝑣−4.32𝑣−7𝑚𝐴∗19𝛺
𝐼𝐿𝑚𝑎𝑥 ≤ − 7𝑚𝐴 => 𝐼𝐿𝑚𝑎𝑥 ≤ 36.4 𝑚𝐴
220𝛺
𝑉𝑧 4.7𝑉
Based on the above 𝑅𝐿,𝑚𝑖𝑛 must be 𝑅𝐿,𝑚𝑖𝑛 ≥ 𝐼 => 𝑅𝐿,𝑚𝑖𝑛 = ≈ 129.1𝛺
𝐿𝑚𝑎𝑥 36.4 𝑚𝐴
Now we are only missing the value of C, which can be calculated just as we’ve done in
𝑇 14
previous designs using the following approximated formula: 𝑉𝑟 ≈ 𝑉𝑠,𝑝𝑒𝑎𝑘 2𝑅 = 440∗2∗220∗𝐶
1𝐶
Adopting a ripple value of Vr = 0.25V we can solve for C as shown below:
14
𝐶= = 𝟐𝟖𝟗. 𝟐𝟓 𝒖𝑭
0.25 ∗ 2 ∗ 440 ∗ 220
Gianluca Guagliardo Z#23442507 09/24/2022
Then adopting practical values of C, we’ll make C = 330 uF, therefore recalculating Vr we
have
14
𝑉𝑟 = ≅ 0.22𝑉
330 ∗ 10−6 ∗ 2 ∗ 440 ∗ 220
Problem 6.0 PSPICE:
In the figure below you can see Vc (green signal) and Vout(red signal). It can also be seen
that Vripple is within the 0.2V calculated and a very stable almost no ripple Vout.
This is the difference between using a Zener diode as a voltage regulator and not using a
Zener diode in previous designs. A Zener diode is strongly recommended in every DC power
supply design for improved regulation.
