CHAPTER 1: PARITY- result of an operation leave the indicated register

with an even number of 1s.

MICROPROCESSOR: integrated circuit in a very small size.
ADDRESS AND ADDRESS BUS: output of program counter
Microprocessor Consists Of: is address, wires that caries it is address bus.
*COUNTER- driven by the clock signal: output is given to the *ADDRESS- output of program counter
decoder A.
*ADDRESS BUS- group of wires that carries the address
*SWITCH CONTROL CIRCUIT- responsible for switch
position. *DATA BUS- from memory to register through group of
wires.
*DECODER B- 3:8 decoder.
*INTERNAL DATA BUS- within the microprocessor.
*DECODER A- 4:16 decoder.
*EXTERNAL DATA BUS- outside the microprocessor.
*REGISTER ARRAY- consists of 16-3-bit register.
WORD LENGTH: group of bits that microprocessor
*COMMON BUS- connected to register a, register b. recognize.
*REGISTER I- store data from the common bus. FETCH: places the content of the program counter on the
*CONTROL UNIT- generate signals which select the address bus.
operation of ALU. DECODE: the operation code from instruction register to
MOV A, C- copy data from register c to register a. generate appropriate control signal.

MOV B,C – copy data from register c to register b. EXECUTE: executes the instruction.

LOAD A- activate input enable signal for register a. ACCUMULATOR: major working register.

LOAD B- activate input enable signal for register b. STACK POINTER: a programmer uses frequently.

*ALU (ARITHMETIC LOGIC UNIT)- microprocessors major - memory address of the stack area.
logic device, data processing logic. STACK: special memory area.
MEMORY: it is a combination of register array and the GENERAL PURPOSE REGISTER: use as simple storage
decoder circuit. area.
PROGRAM: the sequence of instructions written for - Used to store intermediate result of the operation.
specific operation - B, C, D, E, H, L
PROGRAM COUNTER: the counter used in small model is MEMORY ADDRES REGISTER: gives the address the
used to locate instruction in a proper sequence. memory location that the processor wants to use.
STATUS REGISTER (FLAG REGISTER): use to stores the INSTRUCTION REGISTER: holds the operation code that is
result of certain conditions. currently executing.
CARRY- set when the summation of two 8-bit number is INTRUCTION DECODER: takes the instruction opcode
greater than 11111111. form instruction register and decodes it to generate
BORROW- generated when a large number is subtracted appropriate control signals.
from a smaller number. TEMPORARY DATA REGISTER: arises because the ALU has
ZERO- set when the contents of register are 0 after any no storage has no storage on its own.
operation. CONTROL LOGIC: important block in the microprocessor.
NEGATIVE OR SIGN- set when any arithmetic or logical - Maintains the synchronization in operation of diff.
operation gives a negative result. parts of microprocessor.
AUXILLARY CARRY- set when an addition in the first 4-bits MICROPROGRAMMED: the architecture of control logic is
causes a carry into the fifth bit. much like the architecture of a very special purpose
OVERFLOW FLAG- used to represents sign and remaining microprocessor.
bits. INTERNAL DATA BUS: connects the diff parts of
microprocessor together.
MICRO-COMPUTERS: smaller computers * AC- Auxiliary Carry Flag (set if there is an overflow out bit
of 3/ D3 to D4)
- Integration of microprocessor and supporting * P-Parity Flag (number of 1s present in the accumulator)
peripherals. * CY-Carry Flag (set if there is an outflow out of bit 7)
MINI-COMPUTERS: scaled up version of microprocessor. C. INSTRUCTION REGISTER
- CPU stores this opcode in instruction register
- Used for scientific calculation, research and data 4. SIXTEEN BIT REGISTERS
processing application. A. PROGRAM COUNTER (PC)
- acts as a pointer to the next instruction
MAIN FRAME COMPUTERS: uses two or more CPU. B. STACK POINTER (SP)
- Used for complex scientific calculations and larger - used to hold the address of the most recent stack entry
data processing applications. ADDRESS BUFFER: 8-bit unidirectional buffer
- Used to drive A15-A8.
CHAPTER 2: ADDRESS/DATA BUFFER: 8-bit bidirectional buffer
- Used to drive multiplexed address/data bus (AD7-
8085A:
AD0)
- accept, process or provide 8-bit data INCREMENTER/DECREMENTER ADDRESS LATCH: 16-bit
simultaneoutly. register is used to incrementor decrement the contents of
- Operates on a single 5+v power supply program counter or stack pointer.
- On chip clock generator. INTERRUPT CONTROL: processor fetches, decodes, and
- 16 address lines executes instructions in a sequence
- Provides 8 bit I/O - Has five interrupt inputs RST 5.5, RST 6.5, RST 7.5,
- External hardware is required to separate address TRAP, INTR.
lines and data lines. SERIAL INPUT/OUTPUT CONTROL: provides two lines
- Ability to share system bus with direct memory (SOD & SID)
access controller. *SOD (Serial Output Data): used to send/transmit data
- Used to implement three chip microcomputer. serially bit by bit to the external data
*SID (Serial Input Data): used to receive/accept data
REGISTERS: serially bit by bit from external device
1. GENERAL PURPOSE REGISTERS TIMING AND CONTROL CIRCUITRY: responsible for all the
- B, C, D, E, H, and L are 8-bit general purpose registers. Can operation
be used as a separate 8-bit or 16-bit register pairs BC, DE, - Also generates signals required to interface
and HL (functions as a data or memory pointer, also called external devices to the processor
as scratchpad register).
- to store intermediate results than the memory locations. PIN DEFINITIONS
2. TEMPORARY REGISTERS Vcc - requires a single +5V power supply
A. TEMPORARY DATA REGISTER Vss - Ground reference
- ALU has 2 inputs. One input is supplied by accumulator X1 and X2 - LC & RC or crystal is connected at these two
and other from temporary data register. pins
- The programmer cannot access this temporary data CLK OUT - used as a system clock for other devices. its freq
register. is half the oscillator freq
- internally used for execution of most arithmetic and logical ALE (ADDRESS LATCH ENABLE): lower half of an address
instructions. must be latched in T1.
B. W AND Z REGISTERS RD and WR: used to control the direction of the data flow
- are used to hold 8-bit data during execution. between processor and memory or I/O device/port.
- not available for programmer, 8085 uses it internally. IO/M: indicates whether I/O operation or memory operation
- CALL instruction is used to transfer program control to a is being carried out
subprogram or subroutine S0 AND S1: indicates the type of machine cycle in progress.
3. SPECIAL PURPOSE REGISTERS READY: used by the microprocessor to sense whether a
A. REGISTER A (ACCUMULATOR) peripheral is ready or not for data transfer
-It is a tri-state eight bit register. INTA (INTERRUPT ACKNOWLEDGE): indicates that the
- Used in arithmetic, logic, load, and store operations as processor has acknowledge an INTR interrupt.
well as input/output operations. HOLD: indicates that another master is requesting for the
B. FLAG REGISTER use of address bus, data bus, and control bus.
- 8-bit register in which five of the bits carry significant HLDA: active high signal, used to acknowledge HOLD
information in the form of flags request.
* S-Sign Flag (set when D7 is 1) RESET IN: a low in this pin (0000)
* Z-Zero Flag (set if the result of ALU is zero) RESET OUT: processor is being reset
CLOCK CIRCUIT: *SIGLE SIGNAL: represented by a line; it may have status
*LC TUNED CIRCUIT: a LC resonant tank circuit either logic 0 or logic 1 or tri-state; represented by a cross.
*RC TUNED CIRCUIT: output frequency is not exactly Tri-state dotted lines. Two straight lines represent valid
stable state or stable state.
*CRYSTAL OSCILLATOR CIRCUIT: most stable circuit *GROUP OF SIGNALS: called a bus; these signals are
*EXTERNAL CLOCK: applied at X1 input and X2 input is kept grouped and shown in the form of block.
open. SIGNAL TIMINGS:
TYPES OF INTERRUPTS *ACCESS TIME: time where the device will [put the dat from
*HARDWARE: MPU pins are used to receive interrupt selected location on the data bus.
requests MACHINE CYCLES:
TRAP: nonmaskable interrupt, unaffected by any mask or *OPCODE FETCH CYCLE: nature of instruction to be
interrupt enable; highest priority; edge and level triggers; executed; processor places the contents of the program
avoids false triggering caused by noise and transients. counter on the address lines.
[TRAP ACKNOWLEDGE – clears the flipflop] *MEMORY READ CYCLE: read the contents of R/W memory
RST 7.5: 2nd highest priority; maskable interrupt; positive or ROM; processor places the address on the address lines
edge triggered, and the positive edge trigger is stored from the stack pointer, general purpose register pair or
internally by the D-flip-flop; cleared by software reset using program counter, and through the read process, reads the
SIM instruction or generated ACKNOWLEDGE signal data from the addressed memory location.
RST 6.5 AND 5.5: both are level triggered; RST 6.5 3rd *MEMORY WRITE CYCLE: store the data into data memory
priority, RST 5.5 4th priority; can be masked using SIM or stack memory; processor places the address on the
instructions. address lines from the stack pointer or general purpose
INTR: maskable interrupt, but not the vector interrupt; register pair and through the write process, stores the data
lowest priority. into the addressed memory location.
*SOFTWARE: cause of interrupt is an execution of the *I/O READ CYCLE AND WRITE CYCLE: similar to the
instructions memory eread and memory write machine cycles; IO/M
*MASKING AND UNMASKING OF INTERRUPTS signal is high for IO read and IO write machine cycles.
EI (ENABLE INTERRUPT): enable flip-flop (enable RST 7.5, INTERRUPT ACKNOWLEDGE CYCLE: read an instruction
6.5, 5.5, & INTR) from the external device.
DI (DISABLE INTERRUPT): resets the interrupt enable flip- BUS IDLE CYCLE:
flop (disables RST 7.5, 6.5, 5.5, and INTR) *DAD INSTRUCTION: adds the contents of a
SIM (SET INTERRUPT MASK): used ot set interrupt mask specified register pair to the contents of HL register pair.
and to send serial output; transfer the contents of *ONE BYTE INSTRUCTION: doesn’t require any
accumulator to interrupt control logic and serial I/O port additional machine cycle
*PENDING INTERRUPTS: *TWO BYTE INTRUCTION: one additional memory
RIM (READ INTERRUPT MASK): used to handle pending read machine cyle
interrupts; loads the status of the interrupt mask. *THREE BYTE INSTRUCTION: two additional
INPUT/OUTPUT, MEMORY AND SYSTEM BUS: hardware memory read machine cycles.
components/modules of the computer.
*SYSTEM BUS: connects major computer CHAPTER 3:
components/modules. DATA TRANSFER OPERATIONS:
*GENERATION OF CONTROL SIGNALS: *DATA TRANSFER INSTRUCTION: copy data from
MEMR (Memory Read): read data from the source to destination
memory ARTIHMETIC OPERATION:
MEMW (Memory Write): write data from the *ADDITON: 8-bit number that can be added to the content
memory of the accumulator.
IOR (I/O Read): read data from the I/O device. *SUBSTRACTION: 8-bit number that can subtracted to the
IOW (I/O Write): write data in I/O device contents.
INSTRUCTION CYCLE: *INCREMENT/DECREMENT
*MACHINE CYCLE: each memory or I/O operation requires LOGICAL OPERATION:
a particular time period; to move byte of data in or out of the *LOGICAL: 8-bit number; can be logically ANDed, Ored or
microprocessor Exclusive-Ored.
*T-STATES: each machine cycle consist of 3 to 6 clock *ROATE: allow shifting of each bit in the accumulator either
periods/cycles. left or right.
REPRESENTATION OF SIGNALS: *COMPARE: 8-bit number; can be compared for equality,
*CLOCK SIGNAL: greater than, or less than with the contents of the
OPERATING FREQ- divides the clock freq provided accumulator.
at x1 and x2 inputs by 2. *COMPLEMENT: replaces all 0s by 1s and all 1s by 0s.
BRANCHING OPERATIONS: change the sequence of the *MOV M, rs: copies data from the source register into
program, either unconditionally or under certain test memory location pointed by the HL register pair.
conditions. *MOV rd, M: instruction copied data from memory location
STACK, I/O, AND MACHINE CONTROL OPERATIONS: whose address is specified by HL register pair into
allow the transfer of data from register pair to stack memory destination register.
and from stack memory to the register pair. *LXI rp, data(16): loads immediate 16-bit data specified
INSTRUCTION AND DAT FORMAT: within the instruction into register pair or stack pointer.
*OPCODE: operation is specified by binary code, hence the *STA addr: stores the contents od A register into the
name operation code or simple opcode. memory location whose address is directly specified within
*SOURCE/DESTINATION OPERAND: directly specifies the the instruction.
source/destination operand for the instruction. *LDA addr: copies the contents of the memory location
*SOURCE OPERAND ADDRESS: may be in the 8085 whose address is given within the instruction into the
register or in the memory. accumulator.
*DESTINATION OPERAND ADDRESS: result is stored in *SHLD addr: stores the contents of L register in the memory
one of the operand; given by HL regiter pair because INR M location given within the instruction and contents of H
instruction increments the contents of memory location. register at address next to it.
*NEXT INSTRUCTION ADDRESS: tells the 8085 from where *LHLD addr: copies the contents of the memory location
to fetch the next instruction after completion of execution given within the instruction into the L register and the
of current instruction. contents of the next memory location into H register.
INSTRUCTION FORMATS: *STAX rp: copies the contents of accumulator into the
*FIRST BYTE: opcode memory location whose address is specified by the
*SECOND BYTE: data specified register pair.
*THREE BYTE (SECOND AND THIRD BYTE): address or 16- *LDAX rp: copied the contents of memory location whose
bit data address is specified by the register pair into the
OPCODES FORMATS accumulator.
*DDD: destination register *XCHG rp: exchanges the contents of the register H with
*SSS: source register that D and of L with that of E.
*DD: register pair ARITHMETIC GROUP
*D: direction *ADD r: adds the contents of the specified register to the
*TT: flag type contents of accumulator and stores result in the
*F: flag status accumulator.
DATA FORMATS * ADD M: adds the contents of the memory location pointed
*ADDRESS: 16-bit unsigned integer number used to refer a by HL register pair to the contents of accumulator and
memory location. stores result in the accumulator.
*NUMBER DATA
SIGNED INTEGER: either a positive number or a
negative number
UNSIGNED INTEGER: 8-bit unsigned integer
BCD: binary coded decimal number; ten digits
from 0 through 9; 8085 can store two digit BCD number
*CHARACTERS: used ASCII code to represents characters;
7-bit alphanumeric code that represents decimal numbers,
English alphabets and other special characters.
INSTRUCTION SET OF 8085
*M: memory location pointed by HL register pair
*r: 8-bit registet
*rp: 16-bit register pair
*rs: source register
*rd: destination register
*addr: 16-bit address/8-bit address
DATA TRANFER GROUP
*MVI r,data (8): directly loads a specified register with an 8-
bit data given within the instruction.
*MVI M,data (8): directly loads an 8-bit data given within the
instruction into a memory location
*MOV rd, rs: copies data from the source register into
destination register.