International Journal of Innovative Technology and Exploring Engineering (IJITEE)

ISSN: 2278-3075, Volume-9 Issue-3, January 2020

FPGA-Based Connected Component Algorithm

for Vegetation Segmentation
Fatima Zahra Bassine, Ahmed Errami, Mohamed Khaldoun

 in numerous image processing systems.

Abstract: In the process of automatic trees recognition and Image Segmentation is an important technique for image
tracking, image target is captured by RGB camera mounted on a processing analysis in precision agriculture, current
UAV, in processing step image captured is subjected to threshold segmentation problems includes the partitioning of an image
and extract selected information, This techniques may be applied
into a number of homogeneous components. There are
to recognize objects with different shapes and sizes. In the case of
remote sensing vegetation, the image usually contains multiple various methods which deal with segmentation and feature
connected areas or overlapped trees; the proposed system uses the extraction for example: Markov Random Field (MRF) model
shape characteristics of the image target to self-identify the [1], Edge Based Segmentation [2], histogram-based methods
suspicious overlapped features. This technique allows distinguish, [3]. However, the segmentation is a challenging assignment
analyze and detect different features in images by assigning a because of the variety and complexity of video frames. To
unique label to all pixels that refers to the same entity or object.
reduce the complexity of the hardware architecture,
In the process of automatically recognizing and tracking the
target of an image, it is first segmented and extracted. The watershed transform [4] using connected component-based
resulting binary image usually contains several connected technique for automatic segmentation.
regions. The system uses the shape characteristics of the target in This paper proposes a wide range of parallel algorithms for
the image to automatically identify the suspected overlapped trees. morphological image processing , the aim of this type of
Therefore, it is necessary to detect and evaluate each connected image processing is to extract or enhance features from
area block separately, in this paper, the improved FPGA-specific
images based on shape, they are typically used for real time
rapid marking algorithm is used to detect and extract each
connected domain. surveillance tasks in industrial systems [5], medical image
processing[6], texture analysis[7]. Moreover, in automatic
Keywords: Precision Agriculture, Segmentation, Connected tasks such as segmentation or classification of desired objects
Components, FPGA.
in the image are time consuming, it has been found that a
I. INTRODUCTION common problem is reveling which is the presence of
overlapped trees due to some connected components in pixel
range. In order to identify objects in a digital pattern, it is
T rees planted in agricultural land provides numerous necessary to locate groups of pixels that are connected to
environmental benefits, since they provide oxygen, each other; a connected region in a binary region refers to the
improving air quality, climate amelioration, conserving maximal set of foreground pixel in which any two objects are
water, preserving soil, and supporting wildlife. Also they are connected by an 8 neighbor’s pixel of foreground pixel, and
an important source of food for humans and other organisms, for convenience. In this paper the proposed algorithm
therefore farmers are very interested in testing innovative consists of three stages: preprocessing, segmentation and
solutions to improve quality and quantity of products, while post-processing steps, to manipulate an image, this paper
reducing time and energy, managing water resources and describe the work on an array of integers that contains the
fertilizers, and reducing emissions and pollution. In this components of each pixel, various objects are founded in
context, precision agriculture is one of many modern farming real-time by region labeling process, Therefore, Dynamic
practices that make production more efficient. Unmanned identification is necessary to detect and evaluate each
aerial vehicle (UAV) remote sensing has excellent potential connected components separately. In this paper, the enhanced
for vegetation mapping, In precision agriculture application fast tagging algorithm adapted to the FPGA is used to detect
of digital image processing, can improve decision making to and extract each connected component in real-time.
find solutions for some challenging problems one of these is
the recognition of important parameters related to agronomy II. RELATED WORK
with Accuracy, precision, and economic efficiency, then
connected component analysis is one of the major steps used In the automatic image recognition and tracking process,
the target image is first segmented and extracted, the
resulting binary image typically contains several connected
Revised Manuscript Received on January 5, 2020 regions and the system uses shape characteristics of the target
* Correspondence Author
Fatima Zahra Bassine*, Electrical department, NEST research group,
image for automatically identify the suspect
ENSEM, Hassan II University Casablanca, Morocco. Email: target. Therefore, it is necessary to separately detect and
[email protected] evaluate each connected zone block.
Ahmed Errami, Electrical department, NEST research group, ENSEM,
Hassan II University Casablanca, Morocco. Email: [email protected].
Mohamed Khaldoun, Electrical department, NEST research group,
ENSEM, Hassan II University Casablanca, Morocco. Email:
[email protected].

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DOI: 10.35940/ijitee.C7993.019320 2422 & Sciences Publication
 FPGA-Based Connected Component Algorithm for Vegetation Segmentation

In order to distinguish different objects in a binary image. 1) Pre-processing

There are several methods commonly used to detect Image pre-processing is performed by converting the image
connected components in binary image of [8][9]: region from RGB color model to an EXG model [12]. To expedite
growing [10] is one of the approaches that segment image by the process, the image is binarized using Otsu’s method [13]
detecting neighboring pixels, values of foreground/object to perform automatic image thresholding, in order to
pixels and background pixels are 1 and 0, it’s a progressive automatically cluster pixels into two groups’ background and
scan, at each pixel “1” found unlabeled, an unused label is foreground (Figure2), which means create a black and white
assigned, the algorithm is completed when the entire image is image. The main idea of Otsu’s algorithm is that all pixels are
scanned. This process is iterated for each boundary pixel in classified into 2 classes using that threshold.
the regions of the image. This method is accurate, various Automatic thresholding Algorithm:
connected component are detected but its time consuming, 1. Select initial threshold value, typically the mean
the algorithm spent the most time of finding the correct 8-bit value of the original image.
position to insert a border pixel in its data because the 2. Divide the original image into 2 portions;
neighborhood of each "1" pixel must be detected one by one, a) Pixel values that are less than or equal to
and a repeated scan of "1" pixels occurs., it is needed to be the threshold are background
completely reconfigurable to make use of parallel processing. b) Pixel values greater than the threshold are
Tracking algorithm [11]: Each pixel in the binary image foreground
with a value "1" is tagged with a label associated with its 3. Find the average mean values of the 2 new images
coordinates, such as number consisting of n, m strings. After 4. Calculate the new threshold by averaging the 2
processing, the target image is scanned and labeled, every 10 means.
pixels is replaced by the smallest label in its surroundings 5. If the difference between the previous threshold
pixels. After labeling, a binary image will be transferred to a value and the new threshold value are below a
labeled image. specified limit,
6. Otherwise apply the new threshold to the original
III. MATERIALS AND METHODS image.
In order to achieve the implementation of the FPGA, this
article proposes a domain tagging algorithm connected with a
fast binary image. Compared to the traditional binary image
tagging algorithm, this algorithm has the characteristics of
simple operation, regularity and flexibility; it is suitable for
FPGA implementation. With a 100 MHz clock rate, images
processed at 384 × 288 pixels can achieve a frame rate of
more than 400 frames per second, which are sufficient
for real-time target recognition systems. The processing
speed can meet the requirements of most real-time target
Fig. 2. Excess green (ExG) histogram for
recognition systems. The algorithm can also be applied to
vegetationclassification with athe Otsu threshold value.
DSP systems embedded in software programming.
2) Segmentation
A. Description of the algorithm
In order to improve the image contrast, a background
The proposed algorithm consists of three steps, as shown template is obtained using a morphological opening over the
in the Figure1. The first step in which removal background is entire image. The full image after background removal is
undertaken, the second step is segmentation it consists on binarized (objects take the value 1 and background 0), the
group trees separation to subsequently detect centers of each black and white image presented in Figure3.b is obtained. As
tree in each frame. Then post processing step where edges of results of this binarization, there will be two overlapped and
all trees appearing in the image are plotted. tree overlapped or more overlapped trees.

Fig. 3. Examples of trees segmentation and detection.

Fig. 1. Block diagram of green crop segmentation
and detection algorithms.

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DOI: 10.35940/ijitee.C7993.019320 2423 & Sciences Publication
 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-9 Issue-3, January 2020

Misclassification can occur at the intersection of 3. Image substitution: the image is replaced pixel by pixel and
probability distribution curves. To correct these errors, the the temporary mark is replaced by the final mark. After three
following methods are ensured: steps, the algorithm generates the marked image.
A. Initial image tagging
 In the detection of a single tree or two overlapped trees, the
Convention of the marking algorithm: when the algorithm
convex hull is used, if it is equal to the tree edge, the
detects the connected domain counterclockwise, it uses w1,
connected component is classified as a single tree, otherwise
w2 to represent the image data of two consecutive lines. In
it is classified as a group of two trees.
the next clockwise direction, the connected domain detection
 In classification of groups of two or more overlapped
uses k0, k to indicate that two consecutive lines are marked
objects, the Hough transform is used to detect the number of
counterclockwise.
circles present, if the results differs with the minimal
The position of the working window is shown in Figures 5
difference in the number of trees detected according to the
and 6, respectively; the initial temporary mark in the
area, Hough determines the amount taken to be true [14], but
counter-clockwise direction is indicated by Z. The initial
if the difference is greater than 1, the number of trees defined
value of the Z tag is 1.
by the area in maintained. This procedure is also useful to
The binary image connected domain labeling algorithm
classify groups of more than three trees.
uses the 8-connection criterion to eliminate the boundary
Based on this idea, we can classify according to the area of
effect of the image by reducing the range of markers.
the connected components found in the image in order to gain
In order to simplify the marking process, the marking
an understanding of the amount of trees that could be in each
process ends in the equipment at a frame-by-frame
frame, individual or groups of trees are detected in Figure 4.
transmission time, and the marking process is divided into
two consecutive types using the intermediate data buffer,
type 1 being used for direct transmission of image sequences
and the equipment initiating transmission of image
sequences. Type 1 uses domain detection connected in
reverse clock order to initially mark binary pixels in the 2 × 3
work window. Type 2 performs horizontal detection of the
connected domain and merging of the image data initially
(a) (b) marked with type 1, and then stores the marked result in the
image storage area.
Fig. 4. Detected connected component. (a)ExG index was
Initial tag of the image 1:
applied to separate plant vegetation from the soil
 Step 1 reads the pixels w1 (2), w1 (1), w1 (0), w0 (2), w0
background, (b) trees are detected and identified using
(1) and the corresponding binary pixel values.
the proposed algorithm.
 Step 2 Read the pixel w0 (1) and compare it with w1 (0),
IV. FAST TAGGING ALGORITHM w1 (1), w1 (1), w1 (2) and w0 (2) in an anticlockwise
direction. If w0 (1) = w1 (0), then k0 (1) = k (2);
Before the marking algorithm, the hardware is used to open if w0 (1) = w1 (1), then k0 (1) = k (1);
an independent image label cache and the connection if w0 (1) = w1 (2), then k0 (1) = k ( If w0 (1) = w0 (2), then
relationship table, then, when acquiring and transmitting k0 (1) = k0 (0);
videos, the image is scanned line by line and then for each otherwise ;
pixel in the video transmission order. Pixel neighborhoods (i. e. w0 (1) ≠ w1 (2), w1 (1), w1 (0), w1 (2)), k0 (1) = Z;
are combined counterclockwise and horizontally for
Z++.
connectivity detection and marks in to equivalence table. The
Step 3 Write the equivalence relationship table and write Z in
detected results update the equivalence table and the mark
the equivalence table with Z as the address.
cache. Finally, depending on the label in the table, merged
from small to large and the merged table is used to replace the W1(2) W1(1) W1(0)
labels in the image marking cache. The following image is W0(2) W0(1)
then the result of final tagging, and the connected
components have a unique continuous natural number in the Fig. 5. Working window for initial marking in
scanning order. counter-clockwise direction.
In this article, the domain labeling algorithm for binary image
is divided into three parts: Initial image tag 2:
1. Preliminary image tagging: assign a temporary tag to each  Step 1 Once you have determined the marker
pixel and record the equivalence relationship of the counter-clockwise, if w0 (1) = w0 (2) = 1 and the
temporary tag in the equivalent list. gradation of the k0 (1) marker ≠k0 (0) is marked, the next
2. Organize the equivalent table: This part is divided into two step is performed.
steps:  Step 2 Suppose that k0 (1)> k0 (0), so Lab (k0 (1)) = k0
(1) All temporary marks with an equivalent relationship are (1) or Lab (k0 (1)) = k0 (0), then Lab (k0 (1)) = k0 (0),
equivalent to their minimum value; otherwise the tracking table is followed and replaced.
(2) The linked areas are renumbered in order of natural
number to obtain an equivalence ratio between the temporary
mark and the final mark.

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DOI: 10.35940/ijitee.C7993.019320 2424 & Sciences Publication
 FPGA-Based Connected Component Algorithm for Vegetation Segmentation

 Step 3 Suppose that k0 (1) <k0 (0), so the Lab (k0 (0)) = image mark is performed at the same time. This makes image
k0 (0) or the Lab (k0 (0)) = k0 (1), then the Lab (k0 (0)) = markers perform real-time processing.
k0 (1), otherwise the tag table is followed and replaced.
D. Implementation of the algorithm on FPGA
Follow-up replacement method: the follow-up replacement
of step 2 is t = lab (k0 (0)); if lab (t) ≠ t, leave t = lab (t), The FPGA (Field Programmable Gate Array) is a large-scale
repeat the execution, direct lab (t) = t; step 3 the follow-up programmable logic device that can be used in various digital
replacement command t1 = lab (k0 (1)) and the above logic systems, including real-time processing, with unique
follow-up process is also executed for lab (k0 (1). advantages. In the real-time implementation of this
algorithm, the FPGA Cyclone2 EP2C8 is used, which
includes 8256 logical units, 18 DSP blocks and 165.888 bits
k (2) k (1) k (0)
of memory. These memory cells can be configured as
k0 (0) k0 (1) memories of different sizes and bits, which can reduce the use
of external memory, reduce the size of the hardware and
Fig. 6. Working window for initial marking in the facilitate miniaturization of the circuit.
horizontal direction.

B. Sorting equivalence tables and image substitution

First, the list of equivalents is analyzed from parity table
address 1, and then the equivalence relationship between
each temporary mark is checked. Since the classification
process starts at equivalent table address 1, the analysis of the
complete equivalence table can be performed again.
The image substitution link replaces each pixel of the
temporary marker image to generate a final marker image.
The specific method is as follows: if the temporary reference
value of the pixel whose coordinates are (n, m) in the image is
S, the lab (S) is written at the position (n, m) in the image.
The image obtained after the substitution, in which the
connected regions are marked with a unique natural number
in order, from top to bottom, appears from left to right.
Fig. 7.FPGA Conception of a Reconfigurable Fast Tag
C. Analysis of the algorithm characteristics
algorithm.
The algorithm design has the following characteristics:
The algorithm of this article marks the identification and Figure7 shows the hardware structure of the FPGA
tracking tree targets. The work of marking the other pixels of implementation of the fast label algorithm, mainly composed
the image is done completed by the algorithm described of a FIFO serial-to-parallel conversion of binary video stream
above, so that the operation has regularity and the same delay, an anti-clockwise marking unit, a fused data
address. When using hardware implementation, only the transmission interface, a horizontal direction, labeling unit, a
functions of the algorithm structure must be defined to be table of mark equivalence relationships, an equivalent mark,
recycled, which saves the algorithm's memory resources. a sorting unit, image mark substitution unit, etc.
During the initial image marking process, the equivalent The FPGA's internal video acquisition unit digitizes the
table is pre-sorted while recording equivalent information, grayscale data collected according to the segmentation
which allows, on the one hand, when there is a complex threshold to generate a binary video and converts the serial
connection relationship between regions, to save all detected binary video into two lines by parallel-serial FIFO delay
equivalents. On the other hand, when the marking algorithm conversion. The counterclockwise marking unit uses the shift
is implemented by a hardware circuit, the image preliminary register to compose the received parallel data stream, and
marking process and the equivalent table preliminary performs counterclockwise connectivity detection on the data
finishing can be performed in parallel and the equivalent in the window to generate an initial equivalence relationship
table preliminary finishing can simplify the next equivalent table and pixel data. The temporary mark is executed, the
table sorting operation, which is equivalent to a compression. fuser unit of the horizontal direction marks; is immediately
In this algorithm, two measures are taken to reduce the after the mark in an anti-clockwise direction and the pixel
number of temporary markers: first, repeatedly use all marker data after the initial mark is formed; and the data in the data
information generated in the range of 8 neighborhoods and window is marked in the horizontal direction. The
execute the horizontal direction in the order of image equivalence judgment, the merging of tag values belonging to
transmission after marking in the opposite direction of the 8 the same region and the monitoring of the replacement tag
lanes. The mark merges and reducing the probability of new equivalence relationship table, all previous equivalent tag
mark values being assigned. Second, when the equivalent values are unified into the smallest tag value and the video
table is sorted, the equivalent mark is merged and replaced in stream of merged parallel tags is finally stored. In the
the order of the address of the equivalent table, so that the memory group consisting of the next two-port RAM
equivalent mark is compared. Small value and will not miss memory, the two-port external RAM marks the pixel data
the equivalent mark. Third, in combination with the video stored in the dual-port external RAM memory last in the next
data stream transmission mode, the ping-pong structure is line of video data processing.
used for pipeline processing, and the replacement of the

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DOI: 10.35940/ijitee.C7993.019320 2425 & Sciences Publication
 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-9 Issue-3, January 2020

V. RESULTS AND DISCUSSION connected in the image. When the software mode is executed
on DSP6416 system, the algorithm can process images of 384
Once a frame image of the video data is marked, the
× 288 pixels up to 50 images, but when implemented in
equivalence relationship table is sorted and merged into the
FPGA, it achieves a processing speed of 400 frames/second
empty video data space. When the next video data image is
with a 100 MHz clock frequency.
transmitted, the previous image data is extracted from the
external dual access RAM so that the tag image substitution
VI. CONCLUSION
is completed.
The tag cache is built by a ping-pong structure via dual In the process of automatically recognizing and tracking the
access RAM in the FPGA, marking two lines of image data, target of an image, it is first segmented and extracted. The
while the external dual access RAM interface stores the resulting binary image usually contains several connected
marked line of image data in the tag cache structure, the regions. The proposed system uses the shape characteristics
ping-pong module shares three 384×10-bit dual access of the target in the image to automatically identify the
RAMs, and each dual access RAM corresponds to one line of suspected targets. Therefore, In the case of remote sensing
image tag data. vegetation, there is a need to develop automatic systems for
The horizontal marker, fuser unit and the external DPRAM plant enumeration in tree seedling crops to save human
interface are used for data storage. When the horizontal fuser resources and improve yield estimation. So it is necessary to
simultaneously stores two of the dual-port RAMs, the detect and evaluate each connected features block separately,
external DPRAM interface performs a memory operation on the improved FPGA-specific rapid marking algorithm is used
the remaining third dual-port RAM to form label cache to detect, extract and label each connected features in the
ping-pong structure storage operations. The external storage studied trees video. Experimental results indicated that the
interface moves the data into the cache memory with a clock algorithm is suitable for real-time processing, 3 lines of tag
frequency 4 times higher to ensure that the external data is data can be moved in a single line of time for transmitting tag
also moved after marking the two remaining dual access data, thus can improve decision making to find solutions for
RAMs. Experience shows that 3 lines of tag data can be some challenging problems one of these is the recognition of
moved in a single line of time for transmitting tag data. essential parameters related to agronomy with Accuracy,
To respond to the real-time pipelined processing of the tag, precision, and economic efficiency.
the dual-entry device RAM also uses a ping-pong structure.
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AUTHORS PROFILE

Fatima Zahra Bassine, received the Master degree

in Telecommunications Systems Engineering (2013)
Department of physics (Electronics and Microwaves
Group) from Abdelmalek Essaadi University. Currently,
she is PhD. Student at the Electrical department, NEST
Research Group (Networking Embedded Systems and Telecoms), at the
National Higher School of Electricity and Mechanics (ENSEM), Hassan II
University Casablanca, Morocco. She served as a reviewer for international
conferences and journals. Her current research interests include Image
Processing Algorithms, Reconfigurable Architectures, Precision
Agriculture, UAVs.

Ahmed ERRAMI, is a professor in the High National

School of Electricity and Mechanics at the Hassan II
University of Casablanca-Morocco. He graduated as
engineer in electrical engineering from the Blaise-Pascal
University of Clermont-Ferrand (France) in 1986 and
received a Doctor of Philosophy PhD grade in 1992 from
the same University. He joined the electrical engineering department at High
National School of Electricity and Mechanics as an Assistant Professor in
1992 and was promoted to Professor in 2007. His research interests are the
development of new configurable hardware architectures around FPGA and
DSP circuits, development of new mobile access protocols of ad hoc type
(low layer aspect) and their implementation on flexible and reconfigurable
hardware architectures, development of new algorithms dedicated to the
processing and synthesis of signal and images and their implementation on
parallel, flexible and reconfigurable hardware architectures.

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DOI: 10.35940/ijitee.C7993.019320 2427 & Sciences Publication