IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 68, NO.

11, NOVEMBER 2019 4205

Recent Developments and Challenges in

FPGA-Based Time-to-Digital Converters
Rui Machado , Jorge Cabral, and Filipe Serra Alves

Abstract— Over the past few years, the gap between field- modern applications require multiple measurement channels
programmable gate array (FPGA) and application-specific inte- (hardware parallelization). The current competitive market
grated circuit (ASIC) performance levels has been narrowed adds the need for lower development time and fast prototyping,
due to the constant development of FPGA technology. The high
performance, together with the lower development costs and a which can be addressed by using field-programmable gate
shorter time to market, turns FPGA-based platforms attractive arrays (FPGAs). During the past few years, FPGA technology
for a huge range of applications, among them time-to-digital has been showing huge improvements, from the fabrication
converters (TDCs). It is, therefore, important to analyze the process and technology to the enhancement of the development
evolution of FPGA-based TDCs to better understand where the tools available. This enabled FPGAs to close the gap, in terms
research efforts should be focused in the near future. This article
presents and discusses the improvements on the FPGA-based of performance, with application-specific integrated circuits
TDC research, aiming to be a starting point for new studies on (ASICs) [1]–[3]. As a result, FPGA-based systems are begin-
this field, with some guidelines for future research. A state-of- ning to be integrated into final products [4], making FPGA
the-art literature review on the FPGA-based TDC is presented, no longer a prototype-only platform. This led to an increasing
aiming to categorize and discuss the existing architectures. This number of research publications regarding the exploration of
discussion addresses architectures’ characteristics, limitations,
and areas of application. FPGA’s architectures to implement TDC systems. Regardless
of that, it is still noticeable a clear difference between ASIC-
Index Terms— Field-programmable gate arrays (FPGAs), and FPGA-based TDC systems. Most of the research work
survey, time-interval measurement, time-to-digital converter
(TDC). on FPGA-based TDCs proposes the TDC as part of an
application. The focus of the research is the application itself,
I. I NTRODUCTION approaching the TDC as a subsystem, typically categorized in
terms of resolution and sample rate. In such cases, the TDC
T IME-TO-DIGITAL converters (TDCs) are used to mea-
sure time intervals and have been applied in the physics
research field, mainly in time-of-flight (ToF) applications, for
design method will be done according to the characteristics of
the time interval to be measured. The major effort is dedicated
to explaining how the different system’s parts are integrated.
a long time. Research works mainly focus on increasing TDC
When the research is focused on the TDC, regardless of
resolution. Although the resolution is an important parame-
the application, the main effort is on increasing the TDC’s
ter, the TDC nonlinearities will directly affect the overall
linearity and resolution, mainly using statistical methods.
system’s precision. Moreover, applications such as all-digital
On the other hand, on ASIC implementations, there is no
phase-locked loops (PLLs), frequency generators, and Light
such clear distinguish. Even when the presented TDC aims to
Detection and Ranging (LiDAR) systems demand for multiple
target a well-defined application, since the TDC architecture
measures per second, in order to increase their reliability.
and its building cells are custom made, its description is still
Therefore, in modern TDC architectures, it is important to
presented in detail. This discrepancy can be explained by the
improve not only the TDC resolution but also its linearity and
high dependence of the TDC systems regarding the hardware
sample rate. Power consumption and resource utilization are
used. While in ASIC development, no architectural limitations
also important factors when choosing an architecture, since
are imposed, and in FPGA implementations, the architecture
Manuscript received June 17, 2019; revised August 14, 2019; accepted of the TDC is beforehand restricted by the available cells
August 22, 2019. Date of publication August 29, 2019; date of current and routing resources. It is, therefore, important to look at
version October 9, 2019. This work was supported in part by a Portuguese
Scholarship from the Fundação para a Ciência e Tecnologia (FCT) and applications that could benefit from FPGA-based TDCs and
Bosch Car Multimedia through the Advanced Engineering Systems for Indus- identify novel research paths.
try (AESI) Doctoral Program under Scholarship PDE/BDE/114562/2016 and FPGA-based TDCs have reached resolutions under 10 ps
in part by the FCT under Project UID/CEC/00319/2019. The Associate Editor
coordinating the review process was Ferran Reverter. (Corresponding author: [2], [3], [5]–[7], with the work by Szplet et al. [8], report-
Rui Machado.) ing resolutions under 1 ps. Recently, the introduction of
R. Machado and J. Cabral are with the ALGORITMI Centre, University Xilinx FPGA UltraScale architecture enabled the exploration
of Minho, 4800-058 Guimaraes, Portugal (e-mail: [email protected];
[email protected]). of different TDC schemes [1], [9]–[11]. The ever-increasing
F. S. Alves is with the International Iberian Nanotechnology Laboratory, number of resources available in FPGAs also contributed to
4715-330 Braga, Portugal (e-mail: [email protected]). the exploration of multiple-chain TDCs, which can achieve
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org. higher linearity values, when comparing to simple tapped-
Digital Object Identifier 10.1109/TIM.2019.2938436 delay line (TDL) approaches.
0018-9456 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 4206 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 68, NO. 11, NOVEMBER 2019

The recent improvements in TDC’s architectures have been

reported in literature reviews over the years [12]–[17]. These
works present reviews on the main TDC techniques, along
with the issues to address when designing TDCs. Although
these works cover some architectures that can be implemented
in FPGA devices, none of them target the different issues that
need to be considered when implementing TDCs in such plat-
forms. Moreover, these works no longer cover the current state
of the art, as in the past few years, and a substantial amount
of research on FPGA-based TDCs has been done. To the
best of the authors’ knowledge, no literature review targeting
Fig. 1. Proposed FPGA-based TDC taxonomy.
FPGA-based TDCs can be found. This article aims to target
this literature gap by presenting a summary and discussion
on the main findings and evolutions regarding FPGA-based the existing architectures’ characteristics and topologies.
TDCs. The main goal is to cluster all the required knowledge Whenever changes to the main architecture were presented in
to implement an FPGA-based TDC and to identify which a research work, subcategories were created. These changes
are the research gaps that may be explored in this field of could be either through statistical methods or through the
application. An exhaustive literature review was performed in introduction of multiple TDC architectures in the same
order to understand in which applications FPGA-based TDCs channel. In the later, the architecture responsible for defining
are being applied and the reported TDC system’s performance the TDC’s resolution is used to define the TDC main category.
key results. The resulting categorization is depicted in Fig. 1.
This article is structured as follows. In Section II, a tax- In order to achieve high-resolution and high-measurement
onomy to categorize the existing TDC implementations is dynamic ranges, it is common to pair high-resolution TDC
proposed, in order to homogenize the nomenclature. The architectures with coarse counters [24], [25]. Every TDC
relevance of this taxonomy, along with the explanation of how architecture can have its dynamic range easily extended by
it was built, is also addressed in Section II. Section III presents employing such techniques, with minor hardware modifica-
the main TDC performance metrics, while Section IV focuses tions. For that reason, the use of coarse counters was not con-
on presenting and discussing the main results of the conducted sidered for the distinction between architectures. For example,
literature review, grouped according to the proposed taxonomy. architectures that only implement a TDL and architectures that
In Section V, the main issues and challenges of the existing extend the TDL range using a coarse counter (usually called
works are pinpointed. Proposals of future work are also given Nutt TDC) are considered to be part of the same group, single
in Section V based on the identified issues and challenges. delay line, and will be discussed together in Section IV.
Finally, in Section VI, the main conclusions are presented.
A. Coarse Counters
II. TAXONOMY The coarse counters’ designation comprises all the systems
With the increasing number of works targeting TDCs, it is that have a resolution defined by the system clock period.
easy to find scenarios where architectures are classified and These architectures are basically composed of counters that
presented as novel when they do not differ too much from are enabled or sampled by the signal to be measured.
the already existing ones. Moreover, some publications used
the circuit topology to classify the implemented TDC, while B. Phased Clocks
others used the TDC’s principle of operation. For example,
The phased clocks’ group includes architectures, where
the same architecture implemented using two ring oscillators
multiple clocks (with phase relationships) are employed. Some
is sometimes referred to as a Vernier TDC [18], while in other
of the architectures included in this group use oversampling
publications, it is designated as a ring-oscillator TDC [19]. The
to achieve better resolutions, while others just use multiple
same TDL structure as presented in [9], [20], and [21] is also
phased clocks and check which phase was the closest to the
called coding line in [8] and [22] or even a carry chain TDC
input signal. Nevertheless, both use phase differences between
in [23].
multiple clocks as the interpolation mechanism to achieve the
During the research process, the authors could not find
TDC’s resolution.
a homogeneous architecture categorization. This lack of
convention presents an unnecessary source of ambiguity for
researchers new to the field. To address this issue and to C. Tapped-Delay Lines
facilitate the analysis of the architectures that will be further The TDL group includes all the TDC architectures that use
presented in this article, the authors decided to propose a the intrinsic propagation delay of the FPGA’s cells as the
standardized classification (taxonomy), based on the authors’ interpolator element. Approaches with multiple delay lines are
experience and in the extensive and in-depth review on often used to improve the TDC’s resolution. This is achieved
FPGA-based TDC architectures performed. The taxonomy by adding an equivalent coding lines that sample the same
was developed considering, as the first categorization criteria, input and by averaging the obtained results. The resolution

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 MACHADO et al.: RECENT DEVELOPMENTS AND CHALLENGES IN FPGA-BASED TDCs 4207

proportionally increases to the number of delay lines used. A. Measurement Range

Nevertheless, the basic structure can still be considered as The measurement range is the maximum time interval that
a TDL. Hybrid architectures were also included in the TDL can be measured by the TDC before it overflows. With the
group. These architectures are the ones built around a two- increasing popularity of TDCs, the need for an increased
stage fine interpolator. In this TDC architecture, the phased dynamic range became more evident. For example, when
clocks and the TDL are mixed. The fine measurement (first applied to time-based accelerometers [26], measurements in
stage) is done by phased clocks, while in the second stage, the range of a few milliseconds are required. While TDLs
a TDL is used to cover only the phase difference between and differential delay lines are popular for high-resolution
clocks, instead of covering the full system clock period. solutions, implementing them so that they can support such
By doing this, the size (number of cells) of the TDL can a large measurement range has a high hardware cost. This
be greatly reduced at the cost of a slightly more complex range extension can easily be achieved by the introduction of
architecture. Since the resolution of this architecture is defined coarse counters.
by the propagation delay of the cells used to build the TDL,
and because the interpolation output is basically identical to
a traditional TDL (a thermometer code), this architecture was B. Resolution and Precision
also included in the TDL group. Resolution, usually referred to as the least significant bit
(LSB) [14], is the minimum time quantity that can be distin-
guished. It is the minimum step increment that can be made
D. Differential TDC in the TDC transfer curve. The TDC precision, sometimes
referred to as single-shot precision or standard deviation, is a
The differential group includes all the TDC architectures,
metric that describes how far from the expected value the
where the resolution is given by the time difference between
measure can be. It usually, but not always, follows a Gaussian
two elements. In this group, two major architecture types can
distribution. The precision rms value, according to [14], can
be found: delay lines, where both the input signal (signal to
be calculated as follows:
be measured) and the sample signal are delayed, and ring 
oscillators (with a phase match detector). Although the delay σTDCrms = σq2 + σINL 2 + σ2
CLK + σextra
2 (1)
lines are basically a TDL, the TDC resolution is given by the
difference between the propagation delays of the two types where√ σq is the quantization error, usually obtained by
of cells used to build the delay lines rather than just a single LSB/ 6, σINL is the TDC integral nonlinearity (INL) standard
propagation delay line. Therefore, it meets the requirements of deviation, σCLK is the uncertainty (jitter) of the system clock,
the differential TDC group. The second architecture is based and σextra represents the contribution from the external sources
on ring oscillators with match detectors. These also meet the of the jitter. A detailed explanation of the presented equation
requirements to be included in the differential TDC group can be found in [27] and [28].
since they are based on two oscillators with slightly different
frequencies, being the resolution of the TDC given by this C. Nonlinearities
frequency difference. Due to process, voltage, and temperature (PVT) conditions,
TDC’s LSB can vary, thus leading to a transfer curve that
differs from the desired linear fit in quantization steps. The
E. Pulse Shrinking most used metrics to characterize TDC nonlinearities are
The pulse shrinking group comprises architectures that the differential nonlinearity (DNL) and the INL. According
employ the FPGA cells’ rise and fall time discrepancies to to [29], DNL can be defined as the deviation of a single
build a delay-line loop that reduces the pulse duration at quantization step from the theoretical value, reflecting the
each loop cycle. Although these architectures are based on delay variation around its ideal value. The INL represents how
a delay line, the TDC resolution is given by the shrinking large an error can be during a single measurement. In a TDL,
factor of the loop cycle and not by the propagation delay of the the measurement of the DNL is usually done by using a code
cells. For this reason, these architectures are grouped as pulse density test [30]. To perform this test, a periodic signal with a
shrinking. Pulse-shrinking architectures are more suitable to frequency unrelated to the system clock frequency should be
be implemented in ASICs and are more difficult to deploy in chosen and used as the input signal. The results from multiple
FPGAs. measurements are recorded, together with the last cell to be
sampled. Considering that every cell on the delay line has
the same propagation delay and because the frequency of the
III. P ERFORMANCE M ETRICS input signal is unrelated to the frequency of the system clock,
the probability for each cell to be the last one sampled is
Before starting any discussion on the FPGA-based TDC
the same. These measurement results can be represented in a
state of the art, it is important to identify the key performance
histogram, and an estimate of the cells’ actual delay can be
indicators that will be used in the upcoming analysis. These
obtained by using the following equation:
metrics are extremely important for a proper TDC character-
ization and should always be presented when introducing a Tclk
τi = n i ∗ (2)
new TDC implementation. N

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 4208 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 68, NO. 11, NOVEMBER 2019

where τi is the i th cell’s delay, n i is the number of times the IV. A RCHITECTURES
i th delay cell was recorded, Tclk is the system clock period, Section III introduced the main performance metrics that
and N is the number of measures performed. If we consider must be addressed when characterizing a TDC architecture.
τ̄ as the expected theoretical delay, calculated as follows: In this section, the main architectures and innovations on
FPGA-based TDCs are presented. The limitations and imple-
Tclk
τ= (3) mentation issues of each architecture are also discussed.
Ncells

where Ncells is the number of cells, which needs to fulfill a A. Coarse Counter Architectural Group
system clock period, and then the DNL of each cell is defined
The course counter architecture can be considered as the
as follows: basic architecture of a TDC. Examples of its deployment to
FPGAs can be found in [35]–[37]. This TDC architecture can
DNLi = τi − τ . (4) be built by using half-adders and a set of registers that are
used to store and update the value of the counter at each
Since the INL represents the nonlinearity along the entire system clock cycle. There are mainly two variants of this
chain, its value can be obtained by adding the DNL values of architecture. In the first variant, the counter register starts
each cell of the TDL at zero and is incremented at each clock cycle if the input

N−1 signal, i.e., the pulse to be measured, hereafter denoted by hit,
INLi = (τi − τ ). (5) is set. In the second variant, timestamps are captured at each
i=0 hit event. By comparing the timestamps recorded, the time
information between two events can be extracted. The range
Usually, the INL and DNL are normalized to 1 LSB. The and resolution of this architecture are given by
normalized results are obtained, dividing the DNL (4) and
INL (5) by τ̄ . range = 2n
1
τ = (6)
f clk
D. Dead Time where n is the number of bits of the counter register and f clk is
Dead time is the time required for the TDC system to the system clock frequency.
complete a conversion and be ready to perform a new mea- The main advantage of this architecture is the simplicity
surement. This system characteristic defines the measurement of its implementation and low count of FPGA’s hardware
rate at which the TDC can operate. Modern applications are resources. However, the maximum achievable resolution is
demanding higher sampling rates; therefore, designing TDCs limited by the system clock frequency. When implementing
with low dead times is crucial. When the sampling rate this architecture, the focus must be in the routing of the
of a TDC is not enough to comply with the application’s enable signals for the sampling registers. If the routing is
requirements, multiple TDCs can be used in an interleaved not considered, it may lead, in the case of a binary counter,
scheme [31]. Dead times of one system clock cycle are usually to errors larger than 1 LSB.
reported in TDL architectures [32]. In pulse shrinking [33] With the evolution of FPGA technology, the maximum
or differential architectures [34], based on ring oscillators, operating frequency is increasing (few hundreds of megahertz).
the dead time can reach several hundreds of nanoseconds The research works in [9] and [11] reported the use of a
depending on the time interval to measure. system clock frequency of 500 MHz, while the work in [21]
reported a 710-MHz system clock. Nevertheless, this range
of frequencies enables a maximum of 1.4-ns resolution, and
E. Power Consumption and Resource Usage to achieve resolutions below some hundreds of picoseconds,
a system clock frequency of >10 GHz is required.
Power consumption on digital devices is usually charac- As the number of bits of the counter increases, it is harder
terized as dynamic (switching) and static (leakage). Dynamic to secure a low skew between the signals fed to the counter
power is directly related to the clock operating frequency, registers. As the clock frequency increases, the effect of
whereas static power is related to the technology being clock skew is largely enhanced. These two factors lead to an
used. When comparing two system solutions, the total power increase in the number of registers susceptible to metastability
consumption can be used. However, due to this technology and, therefore, to an increased probability of counting errors.
dependency, when the power awareness of two designs (archi- The coarse counter architecture should be employed when a
tectures) is compared, the clock frequency and fabrication resolution of a few nanoseconds and high-measurement range
technology need to be considered. Regarding the system’s size, are required.
in FPGA platforms, it is usual to use the amount of FPGA
resources’ utilization as a quantification factor, which is tied
B. Phased Clocks
to the FPGA’s architecture being used. On the other hand,
in ASIC platforms, the system’s size is given in mm2 and, When implementing a TDC using FPGA platforms,
therefore, tied to the technology in use. if the resolution requirements are reduced, a phased clock

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 MACHADO et al.: RECENT DEVELOPMENTS AND CHALLENGES IN FPGA-BASED TDCs 4209

degrade the TDC performance. With resolutions below a few

hundreds of picoseconds, the jitter values from the phase shift
generators (PLLs or clock management unit blocks) and the
routing skew may lead to situations, where the n phase-clock
rise edge arrives before the n − 1 phase-clock rise edge. This
creates a code pattern with bubbles, very similar to the case of
TDL bubbles, jeopardizing the TDC linearity. It is, therefore,
extremely important to minimize the phased-clocks’ generator
jitter and skew. Another aspect to consider is the need for
a synchronization stage. Because multiple clocks are being
used, to avoid metastability, a synchronization stage must be
implemented in order to create a common clock domain for
further measurement code processing. This synchronization
Fig. 2. Phased-clock-based architecture (adapted from [41]). stage will be as big as the number of phases used. It is
important to remember that phase detection architectures’
dynamic range is usually extended by a coarse counter.
approach will minimize hardware utilization and simplify the In this setup, the system can be described by the following
TDC’s architecture. Usually, phased clocks’ architectures in equations:
FPGA devices are built around a PLL or clock manager Tclk
blocks [38]–[42]. Phased clocks’ architectures, besides being τ =
Nphases
easy to implement, offer great linearity while being able Tfine = Tclk − (phase ∗ τ )
to achieve resolutions better than 300 ps [41]. Although
being able to achieve interesting resolutions, this is still the TDCmeasure = n ∗ Tclk + Tfine (8)
main drawback of phased clocks when compared with other where phase is the clock number that sampled the input signal
architectures. Phased clocks’ architectures are based on two (from 0, for the 0◦ phase clock, to n, to the m ◦ phase clock)
main techniques: oversampling and phase detection. and τ is the resolution given by the phase difference between
1) Oversampling: The principle of operation of this archi- clocks.
tecture relies on the use of phased clocks as clock signals to The reported results for this type of architecture show
independent coarse counters, using the hit signal as the coun- systems with great linearity, which do not need calibration
ters’ enable. The architecture is basically the one presented mechanisms to achieve good performance. In [44], a resolution
in Section IV-A, replicated m times, being m the number of of 625 ps has been reported, showing this architecture’s
phased clocks used. The final measurement value tOversampling capabilities. In the same year, a resolution of 156 ps with
is calculated by using the following equation, where n 0 –n m a precision close to 56 ps was reported in [45], proving
represent the number of counts in each counter that are added that phase clocks’ architectures can reach high-performance
and then multiplied by the system resolution (given by the levels with low complexity and hardware count. Recently,
base clock period Tclk , divided by the number of phases used) Sano et al. [41] reported a resolution of 280 ps with linearity
Tclk values for a DNL under half of the system LSB. Note that
tOversampling = (n 0 + n 1 + · · · + n m ) ∗ . (7) the high linearity achieved by these architectures is in part
m
related to the larger LSB size. When more clock phases are
Resolutions equal to 1 ns have been reported by using this implemented, the size of the LSB gets smaller, and the errors
architecture in [38]–[40] and [43]. The main challenge with associated with the clock’s phase generation and routing paths
this architecture is related to the routing of the signal to be get more pronounced, deteriorating the TDC’s linearity.
measured. Since the phase difference between the generated
clocks is the root of the principle of operation, the signal
to be measured must be routed with the minimum skew C. Tapped-Delay Lines
possible to avoid degrading the measurement. The phase TDL architectures are by far the most used and studied
difference generation is critical, and a low-jitter PLL is usually TDC architectures across the literature [1], [2], [5]–[7], [10],
recommended to avoid phase overlap. [11], [20], [21], [23], [31], [43], [46]–[107]. Although simple
2) Phase Detection: Fig. 2 depicts the basic structure of a to implement, special design precautions must be considered
phased clock architecture that uses multiple phases as bins to regarding linearity, if a high-performance TDL TDC is desired.
sample the hit signal. These types of architectures have a lot of The block diagram shown in Fig. 3 represents the basic
similarities with TDL architectures, where the delayed signal structure of a TDL TDC. It uses the system clock signal
is the system clock. Instead of the delay being generated by to sample the progression of the hit throughout the delay
the intrinsic cell propagation time, it is given by the phase line. The input stage is not mandatory but is often used
difference between the clocks used. The higher the number to manipulate the input signal in a way that simplifies its
of clock phases is, the higher the resolution will be. The handling by the remaining of the system. It can also be used
problem with multiple phases, while using a high-frequency to increase the system resolution. The delay line is the core
clock, is the jitter associated with the different phases that of the TDL. It defines the system’s resolution and linearity,

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 4210 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 68, NO. 11, NOVEMBER 2019

In FPGA platforms, the resources available are predefined

from the start, greatly reducing the flexibility on the TDL
implementation. For the same reason, targeting TDL non-
linearities in FPGAs cannot be done by using the methods
employed in ASICs. TDL architectures implemented in FPGA
platforms can be found in the literature using single-chain and
multiple-chain configurations.
Regardless of the TDL implementation, the maximum
achievable resolution is dependent on the intrinsic delay value
of the cells used to build the delay line and on the clock
Fig. 3. TDL TDC block diagram. jitter [68]. The most used delay elements in FPGA platforms
are the CARRY cell primitives, as they have dedicated routing
with the smallest internal propagation delay. There are some
research works [53], [61] that have used lookup table (LUT)
cell primitives to build the delay line. LUT cells are not as
fast as CARRY cells and do not have a dedicated routing
channel. Nevertheless, a resolution similar to many state-of-
the-art FPGA-based TDCs implemented using the CARRY
cell primitives was reported in [61]. In [108], flip-flop cells
were used as the delay element. The hit signal is used to
Fig. 4. TDL architecture. clock the first delay element, and its output, i.e., the flip-
flop’s output, is used as the input clock of the following
delay element. Another set of flip-flops, clocked by the system
which depends on the type of cells used as an interpolation clock, is responsible for sampling the state of the delay line
stage. The sample line block can also hinder the system’s (Q outputs of the flip-flops). The reported solution could
linearity; therefore, its design must be coupled to the delay- not achieve the resolution of TDLs implemented using the
line design. The TDL outputs a thermometer code that must CARRY cell primitives, but a higher linearity was achieved.
be decoded to a binary value. Finally, in order to minimize the When implementing a TDL topology, several issues
system’s nonlinearities, a calibration block can be deployed. must be addressed. Depending on the usage of multiple
The components shown in Fig. 3 are usually implemented per chains or hybrid architectures, some extra issues must be
TDL channel. In multiple-chain TDCs, the base blocks are considered.
replicated for each channel. 1) Single TDL: The first step when implementing a TDL
A measurement starts with the signal to be measured being is the selection of the delay element. After selecting the
fed to the delay line. The signal is then delayed throughout delay element, the TDL must be built, ensuring that the full
the cells, composing the delay line. When a stop signal measurement range is covered. Usually in FPGAs, the stop
arrives, the status of the delay line is sampled. The result is a signal is the system clock; therefore, the TDL must be long
thermometer code that is further decoded. The value from the enough to comprise an entire clock cycle. The dynamic range
decode stage can be directly used to obtain the final conversion can then be extended by using a coarse counter. When opting
value, or it can be passed to a calibration block. In modern for extending the dynamic range, the synchronization between
TDL TDCs, a calibration block is usually implemented due to the two counting methods is crucial. A dedicated mechanism
the increasing impact of process variations on the propagation must be implemented to secure that the value being sampled
delay of the cells used to build the delay lines. Fig. 4 presents by the coarse counter is not metastable at the time of arrival of
the basic architecture of a TDL. The measurement value can the signal to be measured. Usually, two counters incremented
be obtained according to by two clocks with 180◦ phase relation are used. Depending on
tfine = n ∗ τ (9) the value sampled by the TDL, the nonmetastable coarse value
can be selected. When the same TDL is used to sample both
where τ is the delay of each cell element and n is the number transitions on the input signal, the 180◦ phase-clock method
of delay cells traversed by the delayed signal. is not enough to identify the correct value from the coarse
To compensate for PVT conditions, it is often seen, in ASIC counters. Machado et al. [25] identified such an issue and
platforms, TDLs implemented with voltage-controlled cells proposed a novel synchronizer based on three coarse counters
and paired with voltage-controlled oscillators. This technique to address the synchronization problem.
shields the delay line against temperature and voltage vari- To overcome the TDL resolution limitation, without
ations, helping the compensation for any process mismatch increasing the number of delay lines, a wave-union (WU)
during fabrication. Because the effects of nonlinearities are method was proposed in [109]. When using WU launchers
propagated through the delay chain, it is desirable to have a in the TDL input stage, multiple transitions per hit signal
delay chain as short as possible. To address these issues, the are generated. The measurement of these multiple transitions
delay lines in loop configurations paired with a loop counter reduces the nonlinearities in the delay line, improving the
are frequently used in ASIC implementations. overall TDC’s performance. In [87] and [110], a 10-ps

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 MACHADO et al.: RECENT DEVELOPMENTS AND CHALLENGES IN FPGA-BASED TDCs 4211

resolution with a 38-ps precision TDC was implemented on is taken, the time needed to reach a conversion can surpass
a Lattice FPGA using a TDL with a WU launcher. Higher the system clock cycle. Even when placement and routing
precisions, 32 ps [111] and 14 ps [96], were reported by are manually performed, to minimize clock-skew problems,
using Xilinx Virtex-5 and Spartan-6 FPGAs, respectively. one can end up with zero delay cells, resulting in bubble
The process fabrication mismatch in CARRY cells is codes [11], [57]. These bubbles have a negative impact on the
responsible for high variations on the propagation delay of decoding stage. To overcome the problem, a bin realignment
these cells. These variations jeopardize the average propa- can be performed to minimize the bubble occurrence and thus
gation delay achievable and contribute to a highly nonlinear reduce the decoding stage complexity. This is usually done
system. To address the issue, a careful placement of the delay- with the help of a histogram to detect zero delay cells. Another
line cells must be done. Nevertheless, even with a correct solution is to include, into the decoding stage, some bubble
placement, the difference in propagation delays is enough to removal circuitry. Wang and Liu [10] proposed a different
greatly deteriorate the TDC’s performance. Won and Lee [32] solution to the bubble problem in TDLs. It is proposed that
proposed a method to tune the delay line. The proposed counting the number of “1”s in a TDL, instead of determining
method was evaluated in three different FPGA platforms, the TDL’s bin in which the signal’s transition (from 1 to 0
fabricated in different technologies. The best reported result or 0 to 1) occurs, produces the same result as determining
reached a 10.1-ps LSB and precision under 10 ps. With the the hit’s position, with the advantage of enabling the bubble
introduction of Xilinx UltraScale architectures, the FPGA’s occurrences to be ignored.
base structure changed, and with it, new possibilities were 2) Multiple-Chain TDL: To improve the TDL’s resolution
unlocked to improve the TDL resolution. The UltraScale and linearity, multiple-chain TDL architectures can be used.
architecture allows the capture of both carry and sum results The works in [3], [5], [6], [8], [21], [82], [84], [85], and [98]
of the same slice. Liu et al. [9] used this method to implement reported the use of this architecture, where the principle of
a TDL with 2.3-ps resolution and 3.9-ps precision. operation is based on the discrepancies between the delays
TDC calibration mechanisms are often required on modern of the cells used in the TDLs. Two different TDLs imple-
FPGAs. The main techniques used are bin-size decimation mented in the same FPGA will have a different transfer curve.
[1], [2], [52], [90] and bin-by-bin calibration [49], [54], [55], By making these two delay lines sample the same signal, two
[57], [62], [64], [68], [74], [76], [78], [79], [85], [89], [91], different thermometer codes will be obtained. By averaging
[112]–[114]. In bin decimation, the linearity of the TDL can these two values, the system’s nonlinearities are reduced.
be greatly improved at the cost of resolution. This solution Moreover, the average cell propagation delay is also reduced,
also achieves good results when multiple TDLs are used, as it which enables higher resolutions to be attainable. The results
does not increase the utilization of hardware resources [11]. can be further improved by increasing the number of chains
The principle is based on building larger bins by grouping used to average a single signal. When implementing multiple
physical delay cells. This enables the achievement of bins with TDLs, the routing of the signal to be measured must be done
more uniform sizes, increasing the linearity of the chain. The in a way that the offset between channels is minimized.
bin-by-bin calibration technique does not have the drawback of 3) Hybrid TDL: A recent trend is to pair a TDL with phased
reducing the TDL resolution and is more suitable for TDCs clocks’ architectures to reduce the TDL length, reducing hard-
with higher linearity and resolution requirements. However, ware utilization and the effect of nonlinearities [22], [71], [77],
a histogram, stored in an embedded RAM, is usually required [103], [113], [115]. This architecture is based on a two-stage
[11], [21], [114]. Some research works built these histograms conversion. The first stage is built by using phased clocks. The
prior to the implementation or at system startup, by prebuilding second stage is implemented by using a TDL to cover the time
a memory with the calibration values that will stay the same period between two phases of the phased clocks. A resolution
throughout the TDC operation [55], [76], while others use the as low as 1.9 ps was reported in [113]. Because multiple clocks
TDC measurements to update the histograms’ values during will be sampling the same TDL, the routing should be done
normal operation, therefore achieving better results as the to minimize the skew between clocks. Otherwise, the TDL
calibration values are regularly updated based on the PVT behavior will be dependent on the sampling phase.
conditions [21], [57], [112]. Recently, Chaberski et al. [93]
proposed a wire load-regulation technique in order to improve
TDL’s linearity. The method is based on the use of tristate D. Differential Delay Lines
buffers to control the capacitance load on the different stages Differential TDC architectures are based on the difference
of the TDL. The method considerably uses fewer resources between two delay elements to achieve higher time measure-
when compared to the implementation of histograms to do ment resolutions. This time difference can be obtained by
the bin-by-bin calibration. delaying both the start and stop signals, in a TDL, using
The high measurement rate is an important parameter in different delay cells for each signal (see Fig. 5). One can also
modern applications. The decoding stage has an important role implement two oscillators with a slightly different period [116]
in TDL’s dead time. The thermometer code outputted by the (see Fig. 6).
TDL is as big as the TDL’s number of delay elements. A TDL 1) 2-D TDL: On the 2-D TDL topology, both the start and
implemented in an FPGA can easily reach a few hundreds stop signals are delayed. The resolution and the measurement
of cells. The decoding block will, therefore, be composed of time can be calculated by using (10), where τ1 and τ2 are
multiple stages of combinational blocks. If no special care the propagation delays of the cells used to delay the start and

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 4212 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 68, NO. 11, NOVEMBER 2019

Fig. 7. Different frequency oscillators’ Vernier architecture waveforms.

Fig. 5. Differential delay-line architecture (resolution defined by cells’
propagation delay differences).
longer dependent on the cells used. Instead, the resolution
is based on the difference between the two oscillators’ fre-
quencies [114] [see Fig. 7 and (11)]. However, high accuracy
and stability oscillators are required in order to achieve higher
resolutions, which is no easy task [116]. Two variants of
ring oscillator-based TDCs have been presented in the past
few years. One uses two counters, each incremented by one
of the oscillators and a phase detector [116] (see Fig. 6).
Other employs only one counter that is clocked by the slow
oscillator and stops counting once the fast oscillator is able to
surpass it [117] (see Fig. 8). The oscillators are implemented
by using delay lines, with different sizes, disposed in a loop
Fig. 6. Ring oscillator with two independent counters. configuration [114]
τ = T1 − T2 (11)
stop signals, respectively, τ is the TDC resolution, and n is the TringOscillatorTDC = (n 1 − 1) ∗ T1 − (n 2 − 1) ∗ T2 (12)
number of flip-flops at logic level 1. In such an architecture, T1 ∗ T2
the propagation delay of the cells used to build the stop signal’s tmax Conv = (13)
τ
delay line must be smaller than the propagation delay used tringOscillatorTDC = n fine ∗ τ. (14)
in the start signal. Otherwise, all the sample elements would
always be at logic level 1 since the stop signal would never For the two counters’ ring oscillator topology, the mea-
be able to reach the input signal. In addition, as the delay line surement value can be calculated according to (12), where
must cover an entire system clock period, 2-D TDLs tend to be n 1 and n 2 are the slow and fast counters’ values, respectively,
much longer than normal TDLs, increasing the nonlinearities and T1 and T2 are the slow and fast oscillators’ periods,
across the chain respectively (refer to the waveform diagram shown in Fig. 7).
For such a topology, the maximum conversion time is given
τ = τ1 − τ2 by (13), where τ is the TDC resolution. In the ring oscillator
tfine = n ∗ τ. (10) with only one counter, the fine time is obtained by using (14),
where n fine is the number of counts in the counter until the
In fact, this type of architecture will always suffer from fast oscillator is able to overtake the slow one and r is the
the same problems as the ones already described in the resolution of the TDC, given by (11).
TDL section. In ASIC, the number of available cells with When propagating a pulse along a chain of buffers con-
various delay ranges is large, where two cells can be specif- figured as a ring, due to a mismatch on the cells’ rise
ically designed to have slightly different propagation delays. and fall times, a pulse-shrinking/-stretching effect can occur
In FPGAs, however, the choice is limited. This hardens the (see Section E).
process of designing FPGA-based 2-D TDLs. When imple- Apart from pulse-shrinking-based architectures, this phe-
menting 2-D TDLs in FPGAs, the same cell can be used to nomenon is not desired since it will lead to a cease in the oscil-
implement both the start and stop delay chains. The routing of lation behavior. Therefore, a pulse-reshaping mechanism, like
the delay lines is then used to create the difference between the one presented in [34] and [114], needs to be implemented.
each stage of the two delay lines. This process is extremely The high-measurement dead time is another disadvantage of
hard to calibrate. Therefore, getting a uniform delay difference differential TDCs implemented using ring oscillators. Depend-
across the two delay chains is a demanding process and hard ing on the time difference to measure, the conversion time can
to replicate. For these reasons, regarding differential TDCs in reach several microseconds. According to (13), there are two
FPGA platforms, the ring oscillators are often more popular ways to reduce the TDC dead time. One is to decrease the TDC
due to their simpler implementation. resolution, which is not desirable, and the other alternative is
2) Ring Oscillators: Oscillators solve the cell’s delay mis- to increase the oscillation frequency. This can be achieved
match issue. In these architectures, TDC resolution is no by using high-frequency ring oscillators implemented using

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 MACHADO et al.: RECENT DEVELOPMENTS AND CHALLENGES IN FPGA-BASED TDCs 4213

Fig. 8. Ring oscillator with a single counter.

delay-locked loop lines, although they are hard to stabilize

and design. FPGA PLL blocks cloud be an alternative to
implement differential ring oscillators’ TDCs with higher
operating frequencies.

E. Pulse-Shrinking Architecture
The principle of operation of pulse-shrinking TDCs is based
on the delay cells’ rising and falling times’ mismatch [118].
The hit signal starts a ring oscillator that will increment a
counter every oscillation cycle. The counter value will be
proportional to the hit signal length. The minimum resolution
is the amount of time the pulse is shrunk per cycle. This value Fig. 9. Offset canceller pulse-shrinking architecture.
is the sum of the difference between the rise and fall times
of the used delay cells. The drawback of this architecture is
the offset associated with the measurement. With the input
pulse being continuously shrunk, it reaches a point, close to
the end of the measurement, where the pulse is too short to
be detected and increments the counter [118]. Equation (15)
gives the expression to calculate the final measurement value.
Chen et al. [118] reported a resolution between 110 and
115 ps in a Xilinx XC3S200AN FPGA, with an INL in the
range of ±1 LSB. They proposed a pulse-shrinking variant
to address the offset issue, eliminating the time-consuming
process of determining its value through experimental mea-
surements. This is done by using a delay line to add a time,
equal to the minimum pulse required to trigger a flip-flop
transition, to the time to be measured. The proposed changes in Fig. 10. Offset canceller pulse-shrinking waveforms.
the base pulse-shrinking architecture and resultant waveform
changes are depicted in Figs. 9 and 10, respectively,
The possibility to carefully design a custom cell to be used
tin = n ∗ R − toffset . (15)
as the pulse-shrinking element enables a precise control on
The time adder circuit adds an extra time to the input pulse the TDC resolution. Furthermore, high linearity values can
that is equivalent to the time interval at which the pulse can be achieved since the system’s performance is not related to
no longer be detected, thus eliminating the offset associated the individual cells’ propagation delay. However, in FPGAs,
with the measurement. The pulsewidth detector (PWD) block the shrinking factor cannot be fully controlled (it requires
is responsible for detecting if the pulselength (tout ) is smaller exhaustive practical tests).
than the introduced time generated by the delay-line block, When compared with other architectures, like the TDL
in which case it generates an end-of-conversion (EOC) signal architectures, the resolutions and the linearity achieved
that prevents the counter to be further incremented. by pulse-shrinking architectures do not justify the extra
Pulse-shrinking TDCs offer a good solution for a implementation complexity. In fact, FPGA TDLs have
high-resolution time measurement in ASIC platforms. presented superior performance when compared with the

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 4214 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 68, NO. 11, NOVEMBER 2019

FPGA pulse-shrinking architectures. Even when compared the hardware used. However, little focus has been given to the
with some pulse-shrinking architectures implemented in well-known limitation of the existing architectures.
ASICs [119], [120], FPGA TDLs have proved to reach It is interesting to note that a huge increase in the research
similar performance levels. For these reasons, in the focused on FPGA-based TDCs’ architecture was verified
authors’ perspective, pulse-shrinking architectures are not 1 year after Xilinx released the UltraScale architecture. This
a promising approach for high-performance FPGA-based new FPGA architecture helped to introduce some new ideas
time-measurement systems. with enhanced linearity before the calibration is applied.
The main TDC use cases are still the ToF applications.
Nevertheless, some other applications can be found, address-
V. I SSUES , C HALLENGES , AND F UTURE R ESEARCH PATHS
ing temperature [69], [148], [149] and voltage [53], [56]
To better understand the current scenario regarding FPGA- measurements and atomic clocks’ comparison [77]. Most
based TDCs, it is important to analyze the results from of the time, these voltage and temperature applications can
recent FPGA-based TDCs’ implementations. This will help also be used as a calibration mechanism for a TDC in ToF
to identify the TDCs’ architectural limitations that should applications. Automotive applications are beginning to be
be tackled by future research, enabling the use of FPGA- reported in the literature due to the interest of TDCs in
based TDCs in the emerging applications. Table I presents a LiDAR applications. Automotive industry has high-demanding
summary on the recent FPGA-based TDCs, grouped according requirements that future TDC architectures need to address to
to the taxonomy presented in Section II. A limited list of recent obtain a high-performance, mass production system. There-
works on ASIC TDCs is also reported. Note that a comparison fore, it is predictable that LiDAR applications may have an
between ASIC- and FPGA-based TDCs cannot be done in a important contribution to the evolution and improvement of
fair way. Although they may share some applications, usually the existing TDC architectures, not only in FPGA but also in
the goal of these two implementations is not the same. ASIC ASIC platforms. Another interesting application for TDCs is
TDCs are presented in Table I just to highlight the closing gap a frequency-based transducer, like the one presented in [150],
between ASIC- and FPGA-based TDCs’ performances. or the frequency-based accelerometer presented in [26]. These
From the presented literature analysis, the most explored types of applications require both high resolution and large
architecture for a TDC implementation in FPGAs is based on measurement range.
TDLs. This is probably due to the small propagation time on With increasing use of TDCs in automotive applications
the carry logic blocks available in recent FPGAs. In fact, most like LiDAR systems, area and power requirements are get-
of the analyzed research work is focused on improving the ting tighter. Moreover, modern applications targeting wearable
DNL and INL on TDLs rather than exploring novel or alter- devices are usually battery-powered, making power-saving
native architectures. Phased clocks’ architectures offer the best efforts even more crucial. The same can be said regarding
nonlinearity results and very low hardware resource utilization area, as wearable devices usually require a discrete and small
and are simple to implement. Differential TDC topologies have footprint. It was already proved that using multiple TDLs to
higher complexity but are able to offer performance levels measure the same signal can improve the system’s resolution
close to the ones achieved by TDLs. In the case of differential and linearity [3], [5]–[7]. With the increasing popularity of
TDC implemented using ring oscillators, calibration is often multiple-chain TDCs, power and resource utilization must
not required. The authors believe that it would be interesting to become a major concern if the maximum count of delay chains
perform a study regarding the hardware resources’ utilization is to be increased. It is expected that the research focus will
and the power consumption of TDLs, including the calibration shift from trying to achieve higher resolutions to lower hard-
circuits and differential TDC. This kind of information would ware resources’ utilization. An indicative of this path is the
definitely be valuable for designers when deciding which work of Dinh et al. [50], which proposed a mixture between a
architecture to employ in a given application. Although there ring oscillator and a second-stage interpolator based on a TDL
are already some works reporting comparisons between archi- architecture, reducing the required hardware resources for the
tectures [3], [22], [113], [147], there are multiple variables delay-line implementation without compromising the system’s
influencing the results apart from the architecture itself, such resolution. In [113], a phased-clock architecture is enhanced
as the FPGA platform, or the system working frequency, with a TDL architecture, also enabling an area reduction while
among others. A study that homogenizes all these variables, still reaching resolutions around 4.5 ps.
and focuses only on the different TDCs’ architectures, would The tighter requirements of new applications, and the con-
be beneficial to understand the role that the TDC architecture stant miniaturization and evolution of the FPGA technology,
plays on the final system’s performance and characteristics. lead to the appearance of new issues and to issues, pre-
The efforts regarding the improvement of TDCs’ precision viously ignored, that now need to be addressed. Although
can be divided between averaging a group of measurements of important innovations have been achieved in recent years
the same signal, done in parallel by multiple TDC channels, regarding FPGA-based TDCs, from the analyzed literature,
and the use of WU launchers. Architectural improvements some research challenges and issues that need to be addressed
were focused on the platform used and on the application can be identified as follows.
targeted. Obviously, implementing an existing architecture in 1) New implementations with higher resolutions are
a different FPGA platform brings new challenges that need expected to be achieved due to the FPGA technology
to be reported, since a TDC circuit is highly dependent on evolution. The use of new and smaller process technolo-

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 MACHADO et al.: RECENT DEVELOPMENTS AND CHALLENGES IN FPGA-BASED TDCs 4215

TABLE I
OVERVIEW OF R ECENT TDC S ’ P ERFORMANCE

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 4216 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 68, NO. 11, NOVEMBER 2019

TABLE I
(Continued.) OVERVIEW OF R ECENT TDC S ’ P ERFORMANCE

gies in FPGA fabrication will contribute to the reduction problems introduced by the feedback loop. Further
in the propagation time on the basic FPGA blocks, research targeting this architecture should be done to find
enabling even higher resolutions. On the other hand, possible solutions to mitigate these issues. Hybrid archi-
this will also leverage the negative impact that PVT tectures have also shown promising results regarding
conditions have on TDC’s linearity. The possibility of resource utilization and system’s linearity. Nevertheless,
having higher performance PLL blocks will enable the more works targeting synchronization strategies between
generation of an increasing number of clock phases. the two fine measurement stages of these architectures
Therefore, phased clocks will certainly be able to reach are needed.
higher performance values, making them more attractive 3) Since 2016, most of the TDL architectures have started
for a larger range of applications, due to their implemen- to require a bin rearrangement before being passed to the
tation simplicity and low resource utilization and high decoding stage. This is most likely due to the decreasing
automatization capabilities. technology’s size (from 40 to 20 nm), which aggravated
2) The trend points to an increase in the number of TDCs the clock skew effect. If the skew between two flip-flops
per measurement system, in turn, demands low hard- sampling two adjacent delay elements is bigger than
ware resources’ architectures to be able to fit as many their propagation delay, incorrect sampling of the delay
TDC channels as possible in a single FPGA. Although line will occur, leading to the already discussed bubble
128-channel [21] and 256-channel [46] implementations issues. It is mandatory to address this issue when
were already reported, a large FPGA device was used, implementing a TDC. In general, when designing and
and the hardware utilization was on its limits. Archi- targeting an FPGA, the routing and hardware resources
tectures capable of reducing the length of the delay are defined from the start, and the user does not need
chains without compromising system resolution will to be concerned on managing these resources. When
become more popular and will be the focus of future implementing a TDC in FPGAs, this is not the case.
research works [1], [103]. A pure looped TDL with a Several research studies address skew problems by
sampling stage and a cycle counter, similar to a typical rearranging the cells’ position according to some exper-
DLL TDC implementation in ASICs, should be the one imental measurements, until no more bubbles, or only
that, in theory, enables the highest hardware savings a few bubbles, exist. Nevertheless, this is a tedious
without compromising resolution. However, in FPGAs, and exhaustive process as stated in [19]. Moreover,
this approach presents linearity and signal integrity the falling edge propagation time is not equal to the

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 MACHADO et al.: RECENT DEVELOPMENTS AND CHALLENGES IN FPGA-BASED TDCs 4217

rising edge propagation time. A rearranged delay line time to virtually zero is to adopt a topology with two
for a rise-edge detection can have bubble problems when multiplexed TDCs. Nevertheless, this solution increases
propagating the falling edge, which is not acceptable resource utilization as the TDC must be replicated.
in applications that need to measure both signal edges. 6) When using both fine and coarse measurements
An alternative approach to address the skew problem is to characterize a time interval, synchronization
to control the clock routing to the sample flip-flops of mechanisms are required. Dadouche et al. [152]
the delay line. This is obviously a harder procedure to proposed a solution to this synchronization problem.
implement in FPGAs, but it has the potential to achieve The authors addressed this issue in [153], in which
better results for both rising and falling edge propaga- TDCs’ architectures were the hit’s signal rising and
tions; therefore, it is an interesting path of research. It is falling edge is detected by the same delay line. However,
important to understand if FPGA platforms are reaching the synchronization system has always to be calibrated
their limits due to linearization problems, which will based on TDC measurements. Further research should
become harder and harder to solve and will require a be done in this field to improve metrics such as system’s
manual intervention and scenario-specific calibration hardware resource utilization, scalability, and portability.
circuits. 7) As already stated, FPGA-based TDCs implemented
4) At present, market is rapid to change, and time-to- on modern platforms demand for the calibration
market constraints are tighter than ever. As stated in [14], mechanisms. Generally, the calibration mechanisms are
porting an architecture from one application to another is closely coupled to a specific TDC solution. However,
no easy task and requires heavy manual customizations. some calibration mechanisms can be used in multiple
Therefore, research regarding reconfigurable and para- architectures. To the best of the authors’ knowledge,
meterizable TDCs’ architectures is required. In addition, there is no research work comparing the available cal-
tools that can help the designer to generate the base core ibration solutions. A study analyzing the performance,
of the TDC would accelerate the development process robustness against PVT variation, and flexibility of
and contribute to system’s portability and reutilization. the available TDCs’ calibration mechanisms would be
Lusardi et al. [64] addressed this issue with promis- valuable for designers when selecting the appropriate
ing results. Due to its characteristics, phased clocks’ calibration solution to meet the requirements of their
architectures are promising candidates for exploring application.
automated generation of TDCs. Automatically generated Building on the literature analysis performed, it is expected
TDLs offer an extra challenge due to the nonlinearities that FPGA-based TDC’s evolution will continue to be driven
of the delay chain. Nevertheless, some research works by application’s requirements and their performance limited
[1], [32] have explored a multiple-chain architecture, by the programmable logic provided by the available FPGA
which improves the overall TDL’s linearity before cal- devices. With the current performance reports, it is expected
ibration. These works are good use cases to test auto- that FPGA-based TDCs will start to be integrated into com-
matic TDC generation tools. With nowadays inclusion mercial devices rather than being only used in research field
of microprocessors on most FPGAs, systems that allow experiments. Finding a way to fully automate the FPGA-
for programmable logic reconfiguration can also be based TDC implementation process will certainly increase its
used to try to achieve automatically generated TDCs. popularity, reduce the production cost, and ease the use of
An algorithm to analyze the automatically generated these systems in a broader range of applications.
TDL’s nonlinearity could be implemented on the micro-
processor. Depending on the results from the histograms,
the chain’s hardware could be automatically rearranged VI. C ONCLUSION
in order to improve its linearity and reduce missing
codes. In [151], a framework is proposed to dynamically An analysis on FPGA-based TDC architectures has
control the FPGAs routing with precision. The use of been presented together with an overall description of the
such a framework in TDC designs allows the achieve- major TDC subsystems and on the main design issues to be
ment of high linearity architectures in a simplified way. addressed when implementing a TDC. In order to homogenize
5) Modern applications are demanding higher sampling the current FPGA-based TDC architectures, a taxonomy was
rates. TDLs’ architectures are the ones reporting proposed. Based on this taxonomy, different architectures
lower dead times, usually equal to one system clock were presented.
cycle. Future research focusing on the reduction of Over the years, several research studies addressing TDCs
differential ring oscillators’ dead time is of interest have been published, and some reviews regarding the main
as they are already able to reach high-linearity levels. TDC architectures have been written. Nevertheless, these
This may be done by trying to reduce, as much as reviews did not focus on TDC architectures implemented on
possible, the oscillation frequency of the two oscillators. FPGA platforms. Therefore, this article summarizes the main
However, this proposal has a penalty on the system FPGA-based TDC findings on modern platforms. A critical
power consumption per channel, and it is limited by the review on the evolution of these systems over the past years,
maximum allowed operating frequency of the logic used main trends, possible future research topics, and applications
to build the TDC. An alternative to reduce system’s dead was presented.

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 4218 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 68, NO. 11, NOVEMBER 2019

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channel, 10 ps resolution, FPGA-based TDC with 300 MS/s throughput Rui Machado was born in Guimaraes, Portugal,
for open-source PET applications,” in Proc. IEEE Nucl. Sci. Symp. in 1990. He received the M.Sc. degree in electronics
Conf. Rec., Oct. 2011, pp. 1515–1522. engineering and computers from the University of
[136] L. Zhao, X. Hu, S. Liu, J. Wang, and Q. An, “A 16-channel 15 ps Minho, Guimaraes, Portugal, in 2014, where he is
TDC implemented in a 65 nm FPGA,” in Proc. 18th IEEE-NPSS Real currently pursuing the Ph.D. degree in electronics
Time Conf., Jun. 2012, pp. 1–5. and digital systems in a project in partnership with
[137] M. W. Fishburn, L. H. Menninga, C. Favi, and E. Charbon, “A 19.6 ps, Bosch Car Multimedia, Braga, Portugal.
FPGA-based TDC with multiple channels for open source applica- He was an Invited Professor with the Technology
tions,” IEEE Trans. Nucl. Sci., vol. 60, no. 3, pp. 2203–2208, Jun. 2013. School, Polytechnic Institute of Cávado and Ave
[138] Y.-H. Chen, “A high resolution FPGA-based merged delay line TDC (IPCA), Barcelos, Portugal, and with the Department
with nonlinearity calibration,” in Proc. IEEE Int. Symp. Circuits Syst. of Electronics, University of Minho. Since 2017,
(ISCAS), May 2013, pp. 2432–2435. he has been a Scientific Visitor with the International Iberian Nanotechnol-
[139] Q. Xi, F. Changqing, Z. Deliang, Z. Lei, L. Shubin, and A. Qi, “A low ogy Laboratory, Braga. His current research interests include time-to-digital
dead time Vernier delay line TDC implemented in an actel flash-based conversion systems and embedded and digital systems’ design.
FPGA,” Nucl. Sci. Tech., vol. 24, no. 4, 2013, Art. no. 40403.
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[141] J. P. Caram, J. Galloway, and J. S. Kenney, “Harmonic ring oscillator Jorge Cabral received the Ph.D. degree in microsys-
time-to-digital converter,” in Proc. IEEE Int. Symp. Circuits Syst. tems technology from Imperial College, London,
(ISCAS), May 2015, pp. 161–164. U.K, in 2007.
[142] R. Frankowski, M. Gurski, and P. Płóciennik, “Optical methods of the He is currently an Assistant Professor with the
delay cells characteristics measurements and their applications,” Opt. University of Minho, Guimaraes, Portugal. His cur-
Quantum Electron., vol. 48, no. 3, p. 188, Mar. 2016. rent research interest includes embedded systems’
[143] M. Zhang, H. Wang, and Y. Liu, “A 7.4 ps FPGA-based TDC with a applications, and he is in charge of several research
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[146] C. Chen, S. Meng, Z. Xia, G. Fang, and H. Yin, “Pulse shrinking time- in 1989. He received the Ph.D. degree in micro-
to-digital converter for UWB application,” J. Electron., vol. 31, no. 3, electronics research from the University of Minho,
pp. 180–186, 2014. Guimaraes, Portugal, in 2017, with a focus on pull-
[147] J. Zhang and D. Zhou, “An 8.5-ps two-stage Vernier delay-line loop in-based MEMS inclinometers with integrated elec-
shrinking time-to-digital converter in 130-nm flash FPGA,” IEEE tronics.
Trans. Instrum. Meas., vol. 67, no. 2, pp. 406–414, Feb. 2018. He was an Assistant Professor with the Depart-
[148] K. R. Jeyashankar, M. Mahalley, and B. Amrutur, “A time-based low ment of Industrial Electronics, University of Minho.
voltage body temperature monitoring unit,” in Proc. 27th Int. Conf. He has been a Scientific Visitor with the Delft
VLSI Design 13th Int. Conf. Embedded Syst., Jan. 2014, pp. 522–527. University of Technology, Delft, The Netherlands,
[149] M. P. Mattada, S. M. Magadum, and H. Guhilot, “Identification of and with the International Iberian Nanotechnology
hotspots on FPGA using time to digital converter and distributed tiny Laboratory (INL), Braga, Portugal. He is currently a Research Fellow with the
sensors,” in Proc. 2nd Int. Symp. Phys. Technol. Sensors (ISPTS), Nanodevices Research Group, Department of Nanoelectronics Engineering,
Mar. 2015, pp. 235–239. INL. His current research interests include the development of integrated
[150] N. Bulic, P. Dirnberger, and S. Silber, “New digital sensor design for interocular eye pressure monitoring systems, based on MEMS pressure
rotor displacement measurement based on the coupled oscillators,” in sensors, especially ranging from the design and modeling of MEMS sensors
Proc. 5th Eur. DSP Educ. Res. Conf., Sep. 2012, pp. 247–251. to the design of mixed-signal integrated circuits.

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