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Pankaj LT Spice

The document describes simulations of MOSFET characteristics, logic gates, combinational circuits, half/full adders, and an SR flip flop using CMOS technology in LTspice. Circuit diagrams and output waveforms are presented for each simulation.

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svashu172
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23 views14 pages

Pankaj LT Spice

The document describes simulations of MOSFET characteristics, logic gates, combinational circuits, half/full adders, and an SR flip flop using CMOS technology in LTspice. Circuit diagrams and output waveforms are presented for each simulation.

Uploaded by

svashu172
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Pankaj Kumawat(20EC41)

(Part:B)
Object: Design and simulate MOSFET characteristics using CMOS Technology.
Software used: LT-Spice.
Circuit Diagram:

Drain Characteristics:
Pankaj Kumawat(20EC41)

Transfer Characteristics:

Result : We designed and simulated MOSFET characteristics using LT-Spice.


Pankaj Kumawat(20EC41)

EXPERIMENT: 1

Object: Design and simulate all the logic gates (NOT, NAND and NOR) with 2 inputs in CMOS
Technology.

Software used: LT-Spice.


1. NOR GATE

OUTPUT:

2. NOT GATE
Pankaj Kumawat(20EC41)

OUTPUT:

3. NAND GATE:
Pankaj Kumawat(20EC41)

OUTPUT:
Pankaj Kumawat(20EC41)

EXPERIMENT: 2
OBJECT: Design and simulate Y = AB (C+D), Y = A+B(C+D) and 4X1 multiplexer using CMOS
Technology.

SOFTWARE USED: LT-Spice.


1. Y = AB (C+D)

Circuit Diagram:

Output waveform:
Pankaj Kumawat(20EC41)

2. Y = A+B(C+D)

Circuit Diagram:

Output Waveform:
Pankaj Kumawat(20EC41)

3. 4*1 Multiplexer

Y= [(S1’ S0’ I0) + (S1’ S0 I1) + (S1 S0’ I2) + (S1 S0 I3)] Circuit
diagram:
Pankaj Kumawat(20EC41)

Output Waveform:

RESULT – We are designed and simulated Y = [AB(C+D)], Y =[ A+B(C+D)] and 4X1


multiplexer in CMOS Technology on LTspice.
Pankaj Kumawat(20EC41)

Experiment: 3

Object: Design and simulate half adder and full adder using CMOS Technology.
Software used: LTspice.
1. Half Adder
Circuit Diagram:

Output waveform:
Pankaj Kumawat(20EC41)

2. Full Adder:
Pankaj Kumawat(20EC41)

Circuit Diagram :
Pankaj Kumawat(20EC41)

Output waveform:

Result: We designed and simulated half adder and full adder using CMOS Technology on LTspice.
Pankaj Kumawat(20EC41)

Experiment: 4
Object: Design and simulate SR flip flop using CMOS Technology.
Software used: LT-Spice.
Circuit Diagram:

Output Waveform:

Result: We designed and simulated SR flip flop using CMOS Technology on LTspice.

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