DATASHEET

ISL6269A FN9253
High-Performance Notebook PWM Controller Rev 3.00
November 18, 2014

The ISL6269A IC is a Single-phase Synchronous-Buck PWM

controller featuring Intersil's Robust Ripple Regulator R3™
Features
Technology that delivers truly superior dynamic response to • High performance R3™ Technology
input voltage and output load transients. Integrated MOSFET • Fast transient response
drivers and bootstrap diode result in fewer components and
• ±1% regulation accuracy: -10°C to +100°C and
smaller implementation area.
-40°C to +100°C
Intersil’s R3™ Technology combines the best features of • Wide input voltage range: +5.0V to +25.0V
fixed-frequency PWM and hysteretic PWM while eliminating
many of their shortcomings. R3™ Technology employs an • Output voltage range: +0.6V to +3.3V
innovative modulator that synthesizes an AC ripple voltage • Wide output load range: 0A to 25A
signal VR, analogous to the output inductor ripple current. The
• Selectable diode emulation mode for increased light load
AC signal VR enters a window comparator where the lower
efficiency
threshold is the error amplifier output VCOMP, and the upper
threshold is a programmable voltage reference VW, resulting in • Programmable PWM frequency: 200kHz to 600kHz
generation of the PWM signal. The voltage reference VW sets • Prebiased output start-up capability
the steady-state PWM frequency. Both edges of the PWM can
• Integrated MOSFET drivers and bootstrap diode
be modulated in response to input voltage transients and
output load transients, much faster than conventional • Internal digital soft-start
fixed-frequency PWM controllers. Unlike a conventional • Power good monitor
hysteretic converter, the ISL6269A has an error amplifier that
provides ±1% voltage regulation at the FB pin. • Fault protection
- Undervoltage protection
The ISL6269A has a 1.5ms digital soft-start and can be
- Soft crowbar overvoltage protection
started into a prebiased output voltage. A resistor divider is
used to program the output voltage setpoint. The ISL6269A - Low-side MOSFET rDS(ON) overcurrent protection
can be configured to operate in Continuous Conduction Mode - Over-temperature protection
(CCM) or Diode Emulation Mode (DEM), which improves - Fault identification by PGOOD pull down resistance
light-load efficiency. In CCM the controller always operates as a
• Pb-free (RoHS compliant)
synchronous rectifier, however when DEM is enabled, the
low-side MOSFET is permitted to stay off, blocking negative
current flow into the low-side MOSFET from the output
Applications
inductor. • PCI express graphical processing unit
• Auxiliary power rail
• VRM
• Network adapter

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November 18, 2014
ISL6269A

Pin Configuration
ISL6269A
(16 LD 4x4 QFN)
TOP VIEW

PGOOD

PHASE

BOOT
UG
16 15 14 13

VIN 1 12 PVCC

VCC 2 11 LG
GND
FCCM 3 10 PGND

EN 4 9 ISEN

5 6 7 8

FSET
FB
COMP

VO
Ordering Information
PART NUMBER TEMP RANGE PACKAGE
(Notes 1, 2, 3) PART MARKING (°C) (RoHS Compliant) PKG. DWG. #

ISL6269ACRZ 62 69ACRZ -10 to +100 16 Ld 4x4 QFN L16.4x4

ISL6269AIRZ 62 69AIRZ -40 to +100 16 Ld 4x4 QFN L16.4x4

NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6269A. For more information on MSL, please see tech brief TB363.

FN9253 Rev 3.00 Page 2 of 15

November 18, 2014
 Block Diagram
November 18, 2014
FN9253 Rev 3.00

ISL6269A
VIN
VO
GND
PACKAGE BOTTOM
PWM FREQUENCY
FSET
CONTROL
VCC

VREF
-
+
+
EN gmVIN VW
- -
+
R
- PWM
Q
OVP
+ VR S
-
+

gmVO
- - + VCOMP
CR +
UVP -
+

BOOT

EA DRIVER UG
FB
-
POR DIGITAL SOFT-START

PWM CONTROL
COMP PHASE
SHOOT THROUGH
ISEN - PROTECTION
OCP PVCC
IOC +

30W 90W 60W

DRIVER LG
Page 3 of 15

150°OT
PGOOD PGND

FCCM

FIGURE 1. SCHEMATIC BLOCK DIAGRAM

ISL6269A

Typical Application
ISL6269A
VIN
5V TO 25V
PGOOD VIN

CIN
RPGOOD

QHIGH_SIDE
5V
PVCC UG

RVCC

VCC BOOT

CPVCC CVCC
CBOOT LOUT VOUT
0.6V TO 3.3V
GND PHASE

RSEN COUT

FCCM ISEN

QLOW_SIDE

EN LG

RCOMP
COMP PGND

CCOMP1

FB FSET
VO
CCOMP2 RFSET CFSET

RBOTTOM RTOP

FIGURE 2. ISL6269A TYPICAL APPLICATION SCHEMATIC

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ISL6269A

Absolute Voltage Ratings Thermal Information

ISEN, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V Thermal Resistance (Typical, Notes 4, 5) JA (°C/W) JC (°C/W)
VCC, PGOOD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V QFN Package . . . . . . . . . . . . . . . . . . . . . . . . 48 11.5
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -55C to +150C
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Operating Temperature Range
EN, FCCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V ISL6269ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
VO, FB, COMP, FSET . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +0.3V ISL6269AIRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
PHASE to GND (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C
(<100ns Pulse Width, 10µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
BOOT to GND, or PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
UG (DC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PHASE, BOOT +0.3V Recommended Operating Conditions
(<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.0V Ambient Temperature Range
LG (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PGND, PVCC +0.3V ISL6269ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
(<100ns Pulse Width, 4µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V ISL6269AIRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 25V
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.

NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications These specifications apply for VIN = 15V, TA = -40°C to +100°C, unless otherwise stated. All typical
specifications TA = +25°C, VCC = 5V, PVCC = 5V, VIN = 15V
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VIN
VIN Input Bias Current IVIN EN = 5V, VIN = 5V - 6.5 10 µA
EN = 5V, VIN = 25V - 26 35 µA
VIN Shutdown Current IVIN_SHDN EN = GND, VIN = 25V - 0.1 1.0 µA
VCC and PVCC
VCC Input Bias Current IVCC EN = 5V, FCCM = GND, FB = 0.65V - 1.7 2.5 mA
VCC Shutdown Current IVCC_SHDN EN = GND, VCC = 5V - 0.1 1.0 µA
PVCC Shutdown Current IPVCC_SHDN EN = GND, PVCC = 5V - 0.1 1.0 µA
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage VVCC_THR TA = -10°C to +100°C 4.35 4.45 4.55 V
4.33 4.45 4.55 V
Falling VCC POR Threshold Voltage V TA = -10°C to +100°C 4.10 4.20 4.30 V
VCC_THF
4.08 4.20 4.30 V
REGULATION
Reference Voltage VREF - 0.6 - V
Regulation Accuracy FB connected to COMP -1 - +1 %
PWM
Frequency Range fSW FCCM = 5V 200 - 600 kHz
Frequency-set Accuracy fSW = 300kHz -12 - +12 %
VO Range VVO 0.60 - 3.30 V
IVO VO = 0.60V - 1.3 - µA
VO Input Leakage
VO = 3.30V - 7.0 - µA

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ISL6269A

Electrical Specifications These specifications apply for VIN = 15V, TA = -40°C to +100°C, unless otherwise stated. All typical
specifications TA = +25°C, VCC = 5V, PVCC = 5V, VIN = 15V (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
ERROR AMPLIFIER
FB Input Bias Current IFB FB = 0.60V -0.5 - +0.5 µA
COMP Source Current ICOMP_SRC FB = 0.40V, COMP = 3.20V - 2.5 - mA
COMP Sink Current ICOMP_SNK FB = 0.80V, COMP = 0.30V - 0.3 - mA
COMP High Clamp Voltage VCOMP_HC FB = 0.40V, Sink 50µA 3.10 3.40 3.65 V
COMP Low Clamp Voltage VCOMP_LC FB = 0.80V, Source 50µA 0.09 0.15 0.21 V
POWER GOOD
PGOOD Pull-down Impedance RPG_SS PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125 Ω
PGOOD = 5mA Sink 67 95 125 Ω
RPG_UV PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125 Ω
PGOOD = 5mA Sink 67 95 125 Ω
RPG_OV PGOOD = 5mA Sink, TA = -10°C to +100°C 50 63 85 Ω
PGOOD = 5mA Sink 45 63 85 Ω
RPG_OC PGOOD = 5mA Sink, TA = -10°C to +100°C 25 32 45 Ω
PGOOD = 5mA Sink 22 32 45 Ω
PGOOD Leakage Current IPGOOD PGOOD = 5V - 0.1 1.0 µA
PGOOD Maximum Sink Current (Note 6) - 5.0 - mA
PGOOD Soft-start Delay tSS EN High to PGOOD High, TA = -10°C to +100°C 2.20 2.75 3.30 ms
EN High to PGOOD High 2.20 2.75 3.50 ms
GATE DRIVER
UG Pull-Up Resistance RUGPU 200mA Source Current - 1.0 1.5 Ω
UG Source Current (Note 6) IUGSRC UG - PHASE = 2.5V - 2.0 - A
UG Sink Resistance RUGPD 250mA Sink Current - 1.0 1.5 Ω
UG Sink Current (Note 6) IUGSNK UG - PHASE = 2.5V - 2.0 - A
LG Pull-up Resistance RLGPU 250mA Source Current - 1.0 1.5 Ω
LG Source Current (Note 6) ILGSRC LG - PGND = 2.5V - 2.0 - A
LG Sink Resistance RLGPD 250mA Sink Current - 0.5 0.9 Ω
LG Sink Current (Note 6) ILGSNK LG - PGND = 2.5V - 4.0 - A
UG to LG Deadtime tUGFLGR UG falling to LG rising, no load - 21 - ns
LG to UG Deadtime tLGFUGR LG falling to UG rising, no load - 14 - ns
BOOTSTRAP DIODE
Forward Voltage VF PVCC = 5V, IF = 2mA - 0.58 - V
Reverse Leakage IR VR = 25V - 0.2 - µA
CONTROL INPUTS
EN High Threshold VENTHR 2.0 - - V
EN Low Threshold VENTHF - - 1.0 V
FCCM High Threshold VFCCMTHR 2.0 - - V
FCCM Low Threshold VFCCMTHF - - 1.0 V
EN Leakage IENL EN = 0V - 0.1 1.0 µA
IENH EN = 5.0V - 0.1 1.0 µA
FCCM Leakage IFCCML FCCM = 0V - 0.1 1.0 µA
IFCCMH FCCM = 5.0V - 2.0 - µA

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November 18, 2014
ISL6269A

Electrical Specifications These specifications apply for VIN = 15V, TA = -40°C to +100°C, unless otherwise stated. All typical
specifications TA = +25°C, VCC = 5V, PVCC = 5V, VIN = 15V (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
PROTECTION
ISEN OCP Threshold IOC ISEN sourcing, TA = -10°C to +100°C 19 26 33 µA
ISEN sourcing 17 26 33 µA
ISEN Short-circuit Threshold ISC ISEN sourcing - 50 - µA
UVP Threshold VUV 81 84 87 %
OVP Rising Threshold VOVR 113 116 119 %
OVP Falling Threshold VOVF 100 103 106 %
OTP Rising Threshold (Note 6) TOTR - 150 - °C
OTP Hysteresis (Note 6) TOTHYS - 25 - °C
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Functional Pin Descriptions the FB pin to the GND pin. Program the desired output voltage
with a resistor network connected across the VO, FB, and GND
GND (Bottom Pad) pins. Select the resistor values such that FB to GND is 600mV
when the converter output voltage is at the programmed
Signal common of the IC. Unless otherwise stated, signals are regulation value.
referenced to the GND pin, not the PGND pin.
FSET (Pin 7)
VIN (Pin 1)
The FSET pin programs the PWM switching frequency. Program
The VIN pin measures the converter input voltage which is a the desired PWM frequency with a resistor and a capacitor
required input to the R3™ PWM modulator. Connect across the connected across the FSET and GND pins.
drain of the high-side MOSFET to the GND pin.
VO (Pin 8)
VCC (Pin 2)
The VO pin measures the converter output voltage and is used
The VCC pin is the input bias voltage for the IC. Connect +5V from exclusively as an input to the R3™ PWM modulator. Connect at
the VCC pin to the GND pin. Decouple with at least 1µF of a MLCC the physical location where the best output voltage regulation is
capacitor from the VCC pin to the GND pin. desired.
FCCM (Pin 3) ISEN (Pin 9)
The FCCM pin configures the controller to operate in Forced The ISEN pin programs the threshold of the OCP overcurrent fault
Continuous Conduction Mode (FCCM) or Diode Emulation Mode protection. Program the desired OCP threshold with a resistor
(DEM.) DEM is disabled when the FCCM pin is pulled above the connected across the ISEN and PHASE pins. The OCP threshold is
rising threshold voltage VFCCMTHR, conversely DEM is enabled programmed to detect the peak current of the output inductor.
when the FCCM pin is pulled below the falling threshold voltage The peak current is the sum of the DC and AC components of the
VFCCMTHF. inductor current.
EN (Pin 4) PGND (Pin 10)
The EN pin is the on/off switch of the IC. The soft-start sequence The PGND pin conducts the turn-off transient current through the
begins when the EN pin is pulled above the rising threshold LG gate driver. The PGND pin must be connected to complete the
voltage VENTHR and VCC is above the power-on reset (POR) rising pull-down circuit of the LG gate driver. The PGND pin should be
threshold voltage VVCC_THR . When the EN pin is pulled below the connected to the source of the low-side MOSFET through a low
falling threshold voltage VENTHF PWM immediately stops. impedance path, preferably in parallel with the trace connecting
the LG pin to the gate of the low-side MOSFET. The adaptive
COMP (Pin 5) shoot-through protection circuit, measures the low-side MOSFET
The COMP pin is the output of the control-loop error amplifier. gate-source voltage from the LG pin to the PGND pin.
Compensation components for the control-loop connect across
the COMP and FB pins. LG (Pin 11)
The LG pin is the output of the low-side MOSFET gate driver.
FB (Pin 6) Connect to the gate of the low-side MOSFET.
The FB pin is the inverting input of the control-loop error
amplifier. The converter output voltage regulates to 600mV from

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ISL6269A

PVCC (Pin 12) threshold voltage. Figure 3 shows PWM pulses being generated
as VR traverses the VW and VCOMP thresholds. The PWM
The PVCC pin is the input voltage bias for the LG low-side
switching frequency is proportional to the slew rates of the
MOSFET gate driver. Connect +5V from the PVCC pin to the PGND
positive and negative slopes of VR; the PWM switching frequency
pin. Decouple with at least 1µF of an MLCC capacitor across the
is inversely proportional to the voltage between VW and VCOMP.
PVCC and PGND pins.

BOOT (Pin 13)

The BOOT pin stores the input voltage for the UG high-side
Ripple Capacitor Voltage CR Window Voltage VW
MOSFET gate driver. Connect an MLCC capacitor across the BOOT
and PHASE pins. The boot capacitor is charged through an
internal boot diode connected from the PVCC pin to the BOOT pin,
each time the PHASE pin drops below PVCC minus the voltage
dropped across the internal boot diode.

UG (Pin 14) Error Amplifier Voltage VCOMP

The UG pin is the output of the high-side MOSFET gate driver.

Connect to the gate of the high-side MOSFET.

PHASE (Pin 15) PWM

The PHASE pin detects the voltage polarity of the PHASE node
and is also the current return path for the UG high-side MOSFET
gate driver. Connect the PHASE pin to the node consisting of the FIGURE 3. MODULATOR WAVEFORMS DURING LOAD TRANSIENT
high-side MOSFET source, the low-side MOSFET drain and the
output inductor. Power-On Reset
The ISL6269A is disabled until the voltage VVCC has increased
PGOOD (Pin 16) above the rising power-on reset (POR) VVCC_THR threshold voltage.
The PGOOD pin is an open-drain output that indicates when the The controller will become once again disabled when the voltage
converter is able to supply regulated voltage. Connect the PGOOD VVCC decreases below the falling POR VVCC_THF threshold voltage.
pin to +5V through a pull-up resistor.
EN, Soft-Start and PGOOD
Theory of Operation The ISL6269A uses a digital soft-start circuit to ramp the output
voltage of the converter to the programmed regulation setpoint
Modulator at a predictable slew rate. The slew rate of the soft-start
The ISL6269A is a hybrid of fixed frequency PWM control, and sequence has been selected to limit the in-rush current through
variable frequency hysteretic control. Intersil’s R3™ Technology the output capacitors as they charge to the desired regulation
can simultaneously affect the PWM switching frequency and voltage. When the EN pin is pulled above the rising EN threshold
PWM duty cycle in response to input voltage and output load voltage VENTHR, the PGOOD soft-start delay tSS starts and the
transients. The term “Ripple” in the name “Robust Ripple output voltage begins to rise. The output voltage enters regulation
Regulator” refers to the converter output inductor ripple current, in approximately 1.5ms and the PGOOD pin goes to high
not the converter output ripple voltage. The R3™ Modulator impedance once tSS has elapsed.
synthesizes an AC signal VR, which is an ideal representation of
the output inductor ripple current. The duty-cycle of VR is the 1.5ms
VOUT
result of charge and discharge current through a ripple capacitor
CR. The current through CR is provided by a transconductance VCC and PVCC
amplifier gm that measures the VIN and VO pin voltages. The
positive slope of VR can be written as:
V RPOS =  g m    V IN – V OUT  (EQ. 1) EN

The negative slope of VR can be written as:

V RNEG = g m  V OUT (EQ. 2)

Where gm is the gain of the transconductance amplifier.

PGOOD
A window voltage VW is referenced with respect to the error
2.75ms
amplifier output voltage VCOMP, creating an envelope into which
the ripple voltage VR is compared. The amplitude of VW is set by
FIGURE 4. SOFT-START SEQUENCE
a resistor connected across the FSET and GND pins. The VR,
VCOMP and VW signals feed into a window comparator in which The PGOOD pin indicates when the converter is capable of
VCOMP is the lower threshold voltage and VW is the higher supplying regulated voltage. The PGOOD pin is an undefined

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ISL6269A

impedance if VVCC has not reached the rising POR threshold Diode Emulation
VVCC_THR, or if VVCC is below the falling POR threshold VVCC_THF.
The ISL6269A normally operates in Continuous Conduction
The ISL6269A features a unique fault-identification capability
Mode (CCM), minimizing conduction losses by forcing the
that can drastically reduce troubleshooting time and effort. The
low-side MOSFET to operate as a synchronous rectifier. An
pull-down resistance of the PGOOD pin corresponds to the fault
improvement in light-load efficiency is achieved by allowing the
status of the controller. During soft-start or if an undervoltage
converter to operate in Diode Emulation Mode (DEM), where the
fault occurs, the PGOOD pull-down resistance is 95Ω, or 30Ω for
low-side MOSFET behaves as a smart-diode, forcing the device to
an overcurrent fault, or 60Ω for an overvoltage fault.
block negative inductor current flow. The ISL6269A can be
TABLE 1. PGOOD PULL-DOWN RESISTANCE configured to operate in DEM by setting the FCCM pin low.
CONDITION PGOOD RESISTANCE Setting the FCCM pin high will disable DEM.
VCC Below POR Undefined Positive-going inductor current flows from either the source of
Soft Start or Undervoltage 95Ω the high-side MOSFET, or the drain of the low-side MOSFET.
Negative-going inductor current usually flows into the drain of the
Overvoltage 60Ω
low-side MOSFET. When the low-side MOSFET conducts positive
Overcurrent 30Ω inductor current, the phase voltage will be negative with respect
to the GND and PGND pins. Conversely, when the low-side
MOSFET Gate-Drive Outputs LG and UG MOSFET conducts negative inductor current, the phase voltage
will be positive with respect to the GND and PGND pins. Negative
The ISL6269A has internal gate drivers for the high-side and low-
inductor current occurs when the output load current is less than
side N-Channel MOSFETs. The LG gate driver is optimized for low
½ the inductor ripple current. Sinking negative inductor current
duty-cycle applications where the low-side MOSFET conduction
through the low-side MOSFET lowers efficiency through
losses are dominant, requiring a low rDS(ON) MOSFET. The LG
unnecessary conduction losses. Efficiency can be further
pull-down resistance is small in order to clamp the gate of the
improved with a reduction of unnecessary switching losses by
MOSFET below the VGS(th) at turnoff. The current transient
reducing the PWM frequency. It is characteristic of the R3™
through the gate at turnoff can be considerable because the
architecture for the PWM frequency to decrease while in diode
switching charge of a low rDS(ON) MOSFET can be large. Adaptive
emulation. The extent of the frequency reduction is proportional
shoot-through protection prevents a gate-driver output from
to the reduction of load current. Upon entering DEM, the PWM
turning on until the opposite gate-driver output has fallen below
frequency makes an initial step-reduction because of a 33%
approximately 1V. The dead-time shown in Figure 5 is extended
step-increase of the window voltage V W.
by the additional period that the falling gate voltage stays above
the 1V threshold. The high-side gate-driver output voltage is With FCCM pulled low, the converter will automatically enter DEM
measured across the UG and PHASE pins while the low-side after the PHASE pin has detected positive voltage, while the LG
gate-driver output voltage is measured across the LG and PGND gate-driver pin is high for eight consecutive PWM pulses. The
pins. The power for the LG gate driver is sourced directly from the converter will return to CCM on the following cycle after the
PVCC pin. The power for the UG gate driver is sourced from a PHASE pin detects negative voltage, indicating that the body
“boot” capacitor connected across the BOOT and PHASE pins. diode of the low-side MOSFET is conducting positive inductor
The boot capacitor is charged from a 5V bias supply through a current.
“boot diode” each time the low-side MOSFET turns on, pulling the
PHASE pin low. The ISL6269A has an integrated boot diode Overcurrent and Short-Circuit Protection
connected from the PVCC pin to the BOOT pin. The Overcurrent Protection (OCP) and short-circuit protection
(SCP) setpoint is programmed with resistor RSEN that is
connected across the ISEN and PHASE pins. The PHASE pin is
tLGFUGR tUGFLGR
connected to the drain terminal of the low-side MOSFET.
The SCP setpoint is internally set to twice the OCP setpoint. When
50% an OCP or SCP fault is detected, the PGOOD pin will pull down to
30Ωand latch off the converter. The fault will remain latched
UG until the EN pin has been pulled below the falling EN threshold
voltage VENTHF or if VVCC has decayed below the falling POR
threshold voltage VVCC_THF.
LG
The OCP circuit does not directly detect the DC load current
50%
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side MOSFET
drain current ID is assumed to be equal to the positive output
inductor current when the high-side MOSFET is off. The inductor
current develops a negative voltage across the rDS(ON) of the
FIGURE 5. LG AND UG DEAD-TIME low-side MOSFET that is measured shortly after the LG
gate-driver output goes high. The ISEN pin sources the OCP sense
current ISEN, through the OCP programming resistor RSEN,
forcing the ISEN pin to zero volts with respect to the GND pin. The

FN9253 Rev 3.00 Page 9 of 15

November 18, 2014
ISL6269A

negative voltage across the PHASE and GND pins is nulled by the state can be reset if the EN pin is pulled below the falling EN
voltage dropped across RSEN as ISEN conducts through it. An OCP threshold voltage VENTHF or if VVCC decays below the falling POR
fault occurs if ISEN rises above the OCP threshold current IOC threshold voltage VVCC_THF. All other protection circuits function
while attempting to null the negative voltage across the PHASE normally during OTP. It is likely that the IC will detect an UVP fault
and GND pins. ISEN must exceed IOC on all the PWM pulses that because in the absence of PWM, the output voltage immediately
occur within 20µs. If ISEN falls below IOC on a PWM pulse before decays below the undervoltage threshold VUV; the PGOOD pin will
20µs has elapsed, the timer will be reset. An SCP fault will occur pull down to 95Ωand latch-off the converter. The UVP fault will
within 10µs when ISEN exceeds twice IOC. The relationship remain latched until the EN pin has been pulled below the falling
between ID and ISEN is written as: EN threshold voltage VENTHF or if VVCC has decayed below the
falling POR threshold voltage VVCC_THF.
I SEN  R SEN = I D  r DS  ON  (EQ. 3)
Programming the Output Voltage
The value of RSEN is then written as:
When the converter is in regulation there will be 600mV from the
I P-P FB pin to the GND pin. Connect a two-resistor voltage divider
 I + --------- -  OC SP  r DS  ON 
 FL 2  across the VO pin and the GND pin with the output node
R SEN = ------------------------------------------------------------------------------ (EQ. 4)
I OC connected to the FB pin. Scale the voltage-divider network such
that the FB pin is 600mV with respect to the GND pin when the
Where: converter is regulating at the desired output voltage. The output
- RSEN (Ω) is the resistor used to program the overcurrent voltage can be programmed from 600mV to 3.3V.
setpoint Programming the output voltage is written as:
- ISEN is the current sense current that is sourced from the R BOTTOM
ISEN pin V REF = V OUT  --------------------------------------------------
- (EQ. 5)
R TOP + R BOTTOM
- IOC is the ISEN threshold current sourced from the ISEN pin
that will activate the OCP circuit Where:
- IFL is the maximum continuous DC load current - VOUT is the desired output voltage of the converter
- IP-P is the inductor peak-to-peak ripple current - VREF is the voltage that the converter regulates to between
- OCSP is the desired overcurrent setpoint expressed as a the FB pin and the GND pin
multiplier relative to IFL - RTOP is the voltage-programming resistor that connects
from the FB pin to the VO pin. In addition to setting the
Overvoltage Protection output voltage, this resistor is part of the loop compensation
network
When an OVP fault is detected, the PGOOD pin will pull down to
60Ωand latch-off the converter. The OVP fault will remain - RBOTTOM is the voltage-programming resistor that connects
latched until VVCC has decayed below the falling POR threshold from the FB pin to the GND pin
voltage VVCC_THF. Beginning with RTOP between 1kΩ to 5kΩcalculating RBOTTOM
The OVP fault detection circuit triggers after the voltage across is written as:
the FB and GND pins has increased above the rising overvoltage V REF  R
TOP
R BOTTOM = ------------------------------------- (EQ. 6)
threshold VOVR. Although the converter has latched-off in V OUT – V REF
response to an OVP fault, the LG gate-driver output will retain the
ability to toggle the low-side MOSFET on and off, in response to
Programming the PWM Switching Frequency
the output voltage transversing the VOVR and VOVF thresholds.
The ISL6269A does not use a clock signal to produce PWM. The
Undervoltage Protection PWM switching frequency fSW is programmed by the resistor
RFSET that is connected from the FSET pin to the GND pin. The
When a UVP fault is detected, the PGOOD pin will pull down to
approximate PWM switching frequency is written as:
95Ωand latch-off the converter. The fault will remain latched
1 (EQ. 7)
until the EN pin has been pulled below the falling EN threshold f SW = ---------------------------
K  R FSET
voltage VENTHF or if VVCC has decayed below the falling POR
threshold voltage VVCC_THF. The UVP fault detection circuit Estimating the value of RFSET is written as:
triggers after the voltage across the FB and GND pins has fallen 1 (EQ. 8)
R FSET = ------------------
below the undervoltage threshold VUV . K  f SW

Where:
Over-Temperature
- fSW is the PWM switching frequency
When the temperature of the ISL6269A increases above the
- RFSET is the fSW programming resistor
rising threshold temperature TOTR, the IC will enter an OTP state
that suspends the PWM , forcing the LG and UG gate-driver - K = 75 x 10-12
outputs low. The status of the PGOOD pin does not change nor It is recommended that whenever the control loop compensation
does the converter latch-off. The PWM remains suspended until network is modified, fSW should be checked for the correct
the IC temperature falls below the hysteresis temperature frequency and if necessary, adjust RFSET .
TOTHYS at which time normal PWM operation resumes. The OTP

FN9253 Rev 3.00 Page 10 of 15

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ISL6269A

Compensation Design General Application Design

The LC output filter has a double pole at its resonant frequency that
causes the phase to abruptly roll downward. The R3™ Modulator
Guide
used in the ISL6269A makes the LC output filter resemble a first This design guide is intended to provide a high-level explanation of
order system in which the closed loop stability can be achieved with the steps necessary to create a single-phase power converter. It is
a Type II compensation network. assumed that the reader is familiar with many of the basic skills
and techniques referenced. In addition to this guide, Intersil
provides complete reference designs that include schematics, bills
of materials, and example board layouts.
R2 C1
C2
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as:
COMP R1 V OUT
FB D = ---------------- (EQ. 9)
- V IN
EA The output inductor peak-to-peak ripple current is written as:
+ V OUT   1 – D 
I PP = -------------------------------------- (EQ. 10)
f SW  L OUT
REF
A typical step-down DC/DC converter will have an IP-P of 20% to
FSET 40% of the maximum DC output load current. The value of IP-P is
selected based upon several criteria such as MOSFET switching
loss, inductor core loss and the resistive loss of the inductor
RFSET CFSET
winding. The DC copper loss of the inductor can be estimated by:
2
R3™ MODULATOR P COPPER = I LOAD  DCR (EQ. 11)

Where ILOAD is the converter output DC current.

VO The copper loss can be significant so attention has to be given to
VOUT the DCR selection. Another factor to consider when choosing the
inductor is its saturation characteristics at elevated temperature.
VIN
A saturated inductor could cause destruction of circuit
VIN components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance COUT into
QHIGH_SIDE
which ripple current IP-P can flow. Current IP-P develops a
corresponding ripple voltage VP-P across COUT, which is the sum
UG of the voltage drop across the capacitor ESR and of the voltage
PHASE
change stemming from charge moved in and out of the
capacitor. These two voltages are written as:
LOUT DCR
V ESR = I P-P  E SR (EQ. 12)
GATE DRIVERS
QLOW_SIDE COUT and
LG I P-P
V C = ------------------------------------- (EQ. 13)
CESR 8  C OUT  f
GND SW

If the output of the converter has to support a load with high

ISL6269A pulsating current, several capacitors will need to be paralleled to
reduce the total ESR until the required VP-P is achieved. The
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
FIGURE 6. COMPENSATION REFERENCE CIRCUIT capacitors constructed with reverse package geometry are
Your local Intersil representative can provide a PC-based tool that available. A capacitor dissipates heat as a function of RMS current
can be used to calculate compensation network component and frequency. Be sure that IP-P is shared by a sufficient quantity
values and help simulate the loop frequency response. The of paralleled capacitors so that they operate below the maximum
compensation network consists of the internal error amplifier of the rated RMS current at fSW. Take into account that the rated value of
ISL6269A and the external components R1, R2, C1 and C2 as well a capacitor can fade as much as 50% as the DC voltage across it
as the frequency setting components RFSET and CFSET are increases.
identified in the schematic Figure 6.

FN9253 Rev 3.00 Page 11 of 15

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ISL6269A

Selection of the Input Capacitor There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
The important parameters for the bulk input capacitance are the
high-side MOSFET emphasizes low switch charge so that the
voltage rating and the RMS current rating. For reliable operation,
device spends the least amount of time dissipating power in the
select bulk capacitors with voltage and current ratings above the
linear region. Unlike the low-side MOSFET which has the
maximum input voltage and capable of supplying the RMS
drain-to-source voltage clamped by its body diode during turn off,
current required by the switching circuit. Their voltage rating
the high-side MOSFET turns off with VIN - VOUT - VLacross it. The
should be at least 1.25 times greater than the maximum input
preferred low-side MOSFET emphasizes low rDS(ON) when fully
voltage, while a voltage rating of 1.5 times is a preferred rating.
saturated to minimize conduction loss.
Figure 7 is a graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty cycle that is For the low-side MOSFET, (LS), the power loss can be assumed to
adjusted for converter efficiency. The ripple current calculation is be conductive only and is written as:
written as: 2
P CON_LS  I LOAD  r DS  ON _LS   1 – D  (EQ. 16)
2 2 2 D 
 I MAX   D – D   +  x  I MAX  ------
 12 
I IN_RMS = ----------------------------------------------------------------------------------------------------- (EQ. 14) For the high-side MOSFET, (HS), its conduction loss is written as:
I MAX
2
P CON_HS = I LOAD  r DS  ON _HS  D (EQ. 17)
Where:
- IMAX is the maximum continuous ILOAD of the converter For the high-side MOSFET, its switching loss is written as:
- x is a multiplier (0 to 1) corresponding to the inductor peak- V IN  I VALLEY  t ON  f V IN  I PEAK  t OFF  f
SW SW
to-peak ripple amplitude expressed as a percentage of IMAX P SW_HS = ----------------------------------------------------------------- + -------------------------------------------------------------
2 2
(0% to 100%)
(EQ. 18)
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter which is written as: Where:
V OUT - IVALLEY is the difference of the DC component of the
D = --------------------------
V IN  EFF (EQ. 15) inductor current minus 1/2 of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
In addition to the bulk capacitance, some low ESL ceramic
current plus 1/2 of the inductor ripple current
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET. - tON is the time required to drive the device into saturation
- tOFF is the time required to drive the device into cut-off
NORMALIZED INPUT RMS RIPPLE CURRENT

0.60
0.55 x=1 Selecting The Bootstrap Capacitor
x = 0.75
0.50 The selection of the bootstrap capacitor is written as:
0.45 Qg
x = 0.50 C BOOT = ------------------------ (EQ. 19)
0.40
x=0
V BOOT
0.35
Where:
0.30
0.25
- Qg is the total gate charge required to turn on the high-side
0.20
MOSFET
x = 0.25
0.15
- VBOOT, is the maximum allowed voltage decay across the
0.10
boot capacitor each time the high-side MOSFET is switched
on
0.05
0 As an example, suppose the high-side MOSFET has a total gate
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 charge Qg, of 25nC at VGS = 5V, and a VBOOT of 200mV. The
DUTY CYCLE calculated bootstrap capacitance is 0.125µF. For a comfortable
FIGURE 7. NORMALIZED RMS INPUT CURRENT FOR x = 0.8 margin select a capacitor that is double the calculated
capacitance, in this example 0.22µF will suffice. Use an X7R or
MOSFET Selection and Considerations X5R ceramic capacitor.
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain-to-source voltage rating. The MOSFETs used
in the power stage of the converter should have a maximum VDS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFET switches off.

FN9253 Rev 3.00 Page 12 of 15

November 18, 2014
ISL6269A

Layout Considerations FCCM (Pin 3), EN (Pin 4), PGOOD (Pin 16)
These are logic inputs that are referenced to the GND pin. Treat
As a general rule, power should be on the bottom layer of the
as a typical logic signal.
PCB and weak analog or logic signals are on the top layer of the
PCB. The ground-plane layer should be adjacent to the top layer to
COMP (Pin 5), FB (Pin 6), VO (Pin 8)
provide shielding. The ground plane layer should have an island
located under the IC, the compensation components and the FSET For best results, use an isolated sense line from the output load
components. The island should be connected to the rest of the to the VO pin. The input impedance of the FB pin is high, so place
ground plane layer at one point. the voltage programming and loop compensation components
close to the VO, FB, and GND pins keeping the high impedance
VIAS TO GND trace short.
GROUND OUTPUT
PLANE CAPACITORS
SCHOTTKY
FSET (Pin 7)
VOUT DIODE This pin requires a quiet environment. The resistor RFSET and
PHASE LOW-SIDE capacitor CFSET should be placed directly adjacent to this pin.
INDUCTOR NODE
MOSFETS Keep fast moving nodes away from this pin.
HIGH-SIDE
MOSFETS INPUT
CAPACITORS
ISEN (Pin 9)
VIN
Route the connection to the ISEN pin away from the traces and
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
components connected to the FB pin, COMP pin, and FSET pin.

Signal Ground and Power Ground LG (Pin 11)

The bottom of the ISL6269A QFN package is the signal ground The signal going through this trace is both high dv/dt and high
(GND) terminal for analog and logic signals of the IC. Connect the di/dt, with high peak charging and discharging current. Route
GND pad of the ISL6269A to the island of ground plane under the this trace in parallel with the trace from the PGND pin. These two
top layer using several vias, for a robust thermal and electrical traces should be short, wide, and away from other traces. There
conduction path. Connect the input capacitors, the output should be no other weak signal traces in proximity with these
capacitors, and the source of the lower MOSFETs to the power traces on any layer.
ground plane.
BOOT (Pin 13), UG (Pin 14), PHASE (Pin 15)
PGND (Pin 10)
The signals going through these traces are both high dv/dt and
This is the return path for the pull-down of the LG low-side high di/dt, with high peak charging and discharging current.
MOSFET gate driver. Ideally, PGND should be connected to the Route the UG and PHASE pins in parallel with short and wide
source of the low-side MOSFET with a low-resistance, low- traces. There should be no other weak signal traces in proximity
inductance path . with these traces on any layer.

VIN (Pin 1) Copper Size for the Phase Node

The VIN pin should be connected close to the drain of the high- The parasitic capacitance and parasitic inductance of the phase
side MOSFET, using a low resistance and low inductance path. node should be kept very low to minimize ringing. It is best to
limit the size of the PHASE node copper in strict accordance with
VCC (Pin 2) the current and thermal management of the application. An
For best performance, place the decoupling capacitor very close MLCC should be connected directly across the drain of the upper
to the VCC and GND pins. MOSFET and the source of the lower MOSFET to suppress the
turn-off voltage spike.
PVCC (Pin 12)
For best performance, place the decoupling capacitor very close
to the PVCC and PGND pins, preferably on the same side of the
PCB as the ISL6269A IC.

FN9253 Rev 3.00 Page 13 of 15

November 18, 2014
ISL6269A

Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure
that you have the latest revision.

DATE REVISION CHANGE

November 18, 2014 FN9253.3 -Updated entire datasheet to Intersil new standard.
-Updated Intersil Trademark statement at bottom of page 1 per directive from Legal.
-On page 2, updated Note 1 from “*Add”-T” suffix for tape and reel” to “Add “-T*” suffix for tape and reel. Please
refer to TB347 for details on reel specifications.” and added Note 3.
-On page 5, Updated Caution statement per legal's new verbiage.
-On page 7, updated Note 6 from “Guaranteed by characterization.” to “Compliance to datasheet limits is
assured by one or more methods: production test, characterization and/or design.”
Added revision history and about Intersil verbiage.
On page 15, updated L16.4x4 to new POD format by removing table listing dimensions and moving dimensions
onto drawing. Added Typical Recommended Land Pattern.

About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support

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Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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For information regarding Intersil Corporation and its products, see www.intersil.com

FN9253 Rev 3.00 Page 14 of 15

November 18, 2014
 ISL6269A

Package Outline Drawing

L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08

4X 1.95
4.00 A 12X 0.65
B 6
13 16 PIN #1 INDEX AREA

6
PIN 1
INDEX AREA 1
12

4.00
2 . 10 ± 0 . 15

9
4

(4X) 0.15
8 5
TOP VIEW +0.15 0.10 M C A B
16X 0 . 60
-0.10 4 0.28 +0.07 / -0.05
BOTTOM VIEW

SEE DETAIL "X"

0.10 C C
1.00 MAX
BASE PLANE

( 3 . 6 TYP ) SEATING PLANE

0.08 C
SIDE VIEW
( 2 . 10 ) ( 12X 0 . 65 )

( 16X 0 . 28 ) C 0 . 2 REF 5

( 16 X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

FN9253 Rev 3.00 Page 15 of 15

November 18, 2014